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authorJan Glauber <jglauber@cavium.com>2016-02-18 11:50:12 -0500
committerWill Deacon <will.deacon@arm.com>2016-02-18 13:43:32 -0500
commit94085fe570e7b87597d4695e6fa77d4256efd29e (patch)
tree4069ca2d4366f188a09fe0395604d2614bd133dd
parentc210ae80e4e7083e03bee13535d11fc2c991cf71 (diff)
arm64: dts: Add Cavium ThunderX specific PMU
Add a compatible string for the Cavium ThunderX PMU. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
-rw-r--r--Documentation/devicetree/bindings/arm/pmu.txt1
-rw-r--r--arch/arm64/boot/dts/cavium/thunder-88xx.dtsi5
2 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
index b6056d3bca06..6eb73be9433e 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -25,6 +25,7 @@ Required properties:
25 "qcom,scorpion-pmu" 25 "qcom,scorpion-pmu"
26 "qcom,scorpion-mp-pmu" 26 "qcom,scorpion-mp-pmu"
27 "qcom,krait-pmu" 27 "qcom,krait-pmu"
28 "cavium,thunder-pmu"
28- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu 29- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
29 interrupt (PPI) then 1 interrupt should be specified. 30 interrupt (PPI) then 1 interrupt should be specified.
30 31
diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
index 9cb7cf94284a..2eb9b225f0bc 100644
--- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
+++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
@@ -360,6 +360,11 @@
360 <1 10 0xff01>; 360 <1 10 0xff01>;
361 }; 361 };
362 362
363 pmu {
364 compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
365 interrupts = <1 7 4>;
366 };
367
363 soc { 368 soc {
364 compatible = "simple-bus"; 369 compatible = "simple-bus";
365 #address-cells = <2>; 370 #address-cells = <2>;