diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-10-22 06:58:23 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-10-22 06:58:23 -0400 |
commit | 936fd00549d26a19be723cf7cc1c0b1aa50f9fde (patch) | |
tree | ece248d2be77cce290560f9177bde6b4e4e76889 | |
parent | 9e415a8edce53fb0fed28e15bc06522d122e872e (diff) | |
parent | ce56a86e2ade45d052b3228cdfebe913a1ae7381 (diff) |
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Thomas Gleixner:
"A couple of fixes addressing the following issues:
- The last polishing for the TLB code, removing the last BUG_ON() and
the debug file along with tidying up the lazy TLB code.
- Prevent triple fault on 1st Gen. 486 caused by stupidly calling the
early IDT setup after the first function which causes a fault which
should be caught by the exception table.
- Limit the mmap of /dev/mem to valid addresses
- Prevent late microcode loading on Broadwell X
- Remove a redundant assignment in the cache info code"
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/mm: Limit mmap() of /dev/mem to valid physical addresses
x86/mm: Remove debug/x86/tlb_defer_switch_to_init_mm
x86/mm: Tidy up "x86/mm: Flush more aggressively in lazy TLB mode"
x86/mm/64: Remove the last VM_BUG_ON() from the TLB code
x86/microcode/intel: Disable late loading on model 79
x86/idt: Initialize early IDT before cr4_init_shadow()
x86/cpu/intel_cacheinfo: Remove redundant assignment to 'this_leaf'
-rw-r--r-- | arch/x86/include/asm/io.h | 4 | ||||
-rw-r--r-- | arch/x86/include/asm/tlbflush.h | 21 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/intel_cacheinfo.c | 1 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/microcode/intel.c | 19 | ||||
-rw-r--r-- | arch/x86/kernel/head32.c | 5 | ||||
-rw-r--r-- | arch/x86/mm/mmap.c | 12 | ||||
-rw-r--r-- | arch/x86/mm/tlb.c | 64 |
7 files changed, 59 insertions, 67 deletions
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index c40a95c33bb8..322d25ae23ab 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h | |||
@@ -110,6 +110,10 @@ build_mmio_write(__writeq, "q", unsigned long, "r", ) | |||
110 | 110 | ||
111 | #endif | 111 | #endif |
112 | 112 | ||
113 | #define ARCH_HAS_VALID_PHYS_ADDR_RANGE | ||
114 | extern int valid_phys_addr_range(phys_addr_t addr, size_t size); | ||
115 | extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); | ||
116 | |||
113 | /** | 117 | /** |
114 | * virt_to_phys - map virtual addresses to physical | 118 | * virt_to_phys - map virtual addresses to physical |
115 | * @address: address to remap | 119 | * @address: address to remap |
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index d362161d3291..c4aed0de565e 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h | |||
@@ -82,12 +82,21 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) | |||
82 | #define __flush_tlb_single(addr) __native_flush_tlb_single(addr) | 82 | #define __flush_tlb_single(addr) __native_flush_tlb_single(addr) |
83 | #endif | 83 | #endif |
84 | 84 | ||
85 | /* | 85 | static inline bool tlb_defer_switch_to_init_mm(void) |
86 | * If tlb_use_lazy_mode is true, then we try to avoid switching CR3 to point | 86 | { |
87 | * to init_mm when we switch to a kernel thread (e.g. the idle thread). If | 87 | /* |
88 | * it's false, then we immediately switch CR3 when entering a kernel thread. | 88 | * If we have PCID, then switching to init_mm is reasonably |
89 | */ | 89 | * fast. If we don't have PCID, then switching to init_mm is |
90 | DECLARE_STATIC_KEY_TRUE(tlb_use_lazy_mode); | 90 | * quite slow, so we try to defer it in the hopes that we can |
91 | * avoid it entirely. The latter approach runs the risk of | ||
92 | * receiving otherwise unnecessary IPIs. | ||
93 | * | ||
94 | * This choice is just a heuristic. The tlb code can handle this | ||
95 | * function returning true or false regardless of whether we have | ||
96 | * PCID. | ||
97 | */ | ||
98 | return !static_cpu_has(X86_FEATURE_PCID); | ||
99 | } | ||
91 | 100 | ||
92 | /* | 101 | /* |
93 | * 6 because 6 should be plenty and struct tlb_state will fit in | 102 | * 6 because 6 should be plenty and struct tlb_state will fit in |
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 24f749324c0f..9990a71e311f 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c | |||
@@ -831,7 +831,6 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, int index, | |||
831 | } else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { | 831 | } else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
832 | unsigned int apicid, nshared, first, last; | 832 | unsigned int apicid, nshared, first, last; |
833 | 833 | ||
834 | this_leaf = this_cpu_ci->info_list + index; | ||
835 | nshared = base->eax.split.num_threads_sharing + 1; | 834 | nshared = base->eax.split.num_threads_sharing + 1; |
836 | apicid = cpu_data(cpu).apicid; | 835 | apicid = cpu_data(cpu).apicid; |
837 | first = apicid - (apicid % nshared); | 836 | first = apicid - (apicid % nshared); |
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 8f7a9bbad514..7dbcb7adf797 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <linux/mm.h> | 34 | #include <linux/mm.h> |
35 | 35 | ||
36 | #include <asm/microcode_intel.h> | 36 | #include <asm/microcode_intel.h> |
37 | #include <asm/intel-family.h> | ||
37 | #include <asm/processor.h> | 38 | #include <asm/processor.h> |
38 | #include <asm/tlbflush.h> | 39 | #include <asm/tlbflush.h> |
39 | #include <asm/setup.h> | 40 | #include <asm/setup.h> |
@@ -918,6 +919,18 @@ static int get_ucode_fw(void *to, const void *from, size_t n) | |||
918 | return 0; | 919 | return 0; |
919 | } | 920 | } |
920 | 921 | ||
922 | static bool is_blacklisted(unsigned int cpu) | ||
923 | { | ||
924 | struct cpuinfo_x86 *c = &cpu_data(cpu); | ||
925 | |||
926 | if (c->x86 == 6 && c->x86_model == INTEL_FAM6_BROADWELL_X) { | ||
927 | pr_err_once("late loading on model 79 is disabled.\n"); | ||
928 | return true; | ||
929 | } | ||
930 | |||
931 | return false; | ||
932 | } | ||
933 | |||
921 | static enum ucode_state request_microcode_fw(int cpu, struct device *device, | 934 | static enum ucode_state request_microcode_fw(int cpu, struct device *device, |
922 | bool refresh_fw) | 935 | bool refresh_fw) |
923 | { | 936 | { |
@@ -926,6 +939,9 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device, | |||
926 | const struct firmware *firmware; | 939 | const struct firmware *firmware; |
927 | enum ucode_state ret; | 940 | enum ucode_state ret; |
928 | 941 | ||
942 | if (is_blacklisted(cpu)) | ||
943 | return UCODE_NFOUND; | ||
944 | |||
929 | sprintf(name, "intel-ucode/%02x-%02x-%02x", | 945 | sprintf(name, "intel-ucode/%02x-%02x-%02x", |
930 | c->x86, c->x86_model, c->x86_mask); | 946 | c->x86, c->x86_model, c->x86_mask); |
931 | 947 | ||
@@ -950,6 +966,9 @@ static int get_ucode_user(void *to, const void *from, size_t n) | |||
950 | static enum ucode_state | 966 | static enum ucode_state |
951 | request_microcode_user(int cpu, const void __user *buf, size_t size) | 967 | request_microcode_user(int cpu, const void __user *buf, size_t size) |
952 | { | 968 | { |
969 | if (is_blacklisted(cpu)) | ||
970 | return UCODE_NFOUND; | ||
971 | |||
953 | return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user); | 972 | return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user); |
954 | } | 973 | } |
955 | 974 | ||
diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c index cf2ce063f65a..2902ca4d5993 100644 --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c | |||
@@ -30,10 +30,11 @@ static void __init i386_default_early_setup(void) | |||
30 | 30 | ||
31 | asmlinkage __visible void __init i386_start_kernel(void) | 31 | asmlinkage __visible void __init i386_start_kernel(void) |
32 | { | 32 | { |
33 | cr4_init_shadow(); | 33 | /* Make sure IDT is set up before any exception happens */ |
34 | |||
35 | idt_setup_early_handler(); | 34 | idt_setup_early_handler(); |
36 | 35 | ||
36 | cr4_init_shadow(); | ||
37 | |||
37 | sanitize_boot_params(&boot_params); | 38 | sanitize_boot_params(&boot_params); |
38 | 39 | ||
39 | x86_early_init_platform_quirks(); | 40 | x86_early_init_platform_quirks(); |
diff --git a/arch/x86/mm/mmap.c b/arch/x86/mm/mmap.c index a99679826846..320c6237e1d1 100644 --- a/arch/x86/mm/mmap.c +++ b/arch/x86/mm/mmap.c | |||
@@ -174,3 +174,15 @@ const char *arch_vma_name(struct vm_area_struct *vma) | |||
174 | return "[mpx]"; | 174 | return "[mpx]"; |
175 | return NULL; | 175 | return NULL; |
176 | } | 176 | } |
177 | |||
178 | int valid_phys_addr_range(phys_addr_t addr, size_t count) | ||
179 | { | ||
180 | return addr + count <= __pa(high_memory); | ||
181 | } | ||
182 | |||
183 | int valid_mmap_phys_addr_range(unsigned long pfn, size_t count) | ||
184 | { | ||
185 | phys_addr_t addr = (phys_addr_t)pfn << PAGE_SHIFT; | ||
186 | |||
187 | return valid_phys_addr_range(addr, count); | ||
188 | } | ||
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 658bf0090565..0f3d0cea4d00 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c | |||
@@ -30,7 +30,6 @@ | |||
30 | 30 | ||
31 | atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1); | 31 | atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1); |
32 | 32 | ||
33 | DEFINE_STATIC_KEY_TRUE(tlb_use_lazy_mode); | ||
34 | 33 | ||
35 | static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen, | 34 | static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen, |
36 | u16 *new_asid, bool *need_flush) | 35 | u16 *new_asid, bool *need_flush) |
@@ -147,8 +146,8 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, | |||
147 | this_cpu_write(cpu_tlbstate.is_lazy, false); | 146 | this_cpu_write(cpu_tlbstate.is_lazy, false); |
148 | 147 | ||
149 | if (real_prev == next) { | 148 | if (real_prev == next) { |
150 | VM_BUG_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != | 149 | VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != |
151 | next->context.ctx_id); | 150 | next->context.ctx_id); |
152 | 151 | ||
153 | /* | 152 | /* |
154 | * We don't currently support having a real mm loaded without | 153 | * We don't currently support having a real mm loaded without |
@@ -213,6 +212,9 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, | |||
213 | } | 212 | } |
214 | 213 | ||
215 | /* | 214 | /* |
215 | * Please ignore the name of this function. It should be called | ||
216 | * switch_to_kernel_thread(). | ||
217 | * | ||
216 | * enter_lazy_tlb() is a hint from the scheduler that we are entering a | 218 | * enter_lazy_tlb() is a hint from the scheduler that we are entering a |
217 | * kernel thread or other context without an mm. Acceptable implementations | 219 | * kernel thread or other context without an mm. Acceptable implementations |
218 | * include doing nothing whatsoever, switching to init_mm, or various clever | 220 | * include doing nothing whatsoever, switching to init_mm, or various clever |
@@ -227,7 +229,7 @@ void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | |||
227 | if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm) | 229 | if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm) |
228 | return; | 230 | return; |
229 | 231 | ||
230 | if (static_branch_unlikely(&tlb_use_lazy_mode)) { | 232 | if (tlb_defer_switch_to_init_mm()) { |
231 | /* | 233 | /* |
232 | * There's a significant optimization that may be possible | 234 | * There's a significant optimization that may be possible |
233 | * here. We have accurate enough TLB flush tracking that we | 235 | * here. We have accurate enough TLB flush tracking that we |
@@ -626,57 +628,3 @@ static int __init create_tlb_single_page_flush_ceiling(void) | |||
626 | return 0; | 628 | return 0; |
627 | } | 629 | } |
628 | late_initcall(create_tlb_single_page_flush_ceiling); | 630 | late_initcall(create_tlb_single_page_flush_ceiling); |
629 | |||
630 | static ssize_t tlblazy_read_file(struct file *file, char __user *user_buf, | ||
631 | size_t count, loff_t *ppos) | ||
632 | { | ||
633 | char buf[2]; | ||
634 | |||
635 | buf[0] = static_branch_likely(&tlb_use_lazy_mode) ? '1' : '0'; | ||
636 | buf[1] = '\n'; | ||
637 | |||
638 | return simple_read_from_buffer(user_buf, count, ppos, buf, 2); | ||
639 | } | ||
640 | |||
641 | static ssize_t tlblazy_write_file(struct file *file, | ||
642 | const char __user *user_buf, size_t count, loff_t *ppos) | ||
643 | { | ||
644 | bool val; | ||
645 | |||
646 | if (kstrtobool_from_user(user_buf, count, &val)) | ||
647 | return -EINVAL; | ||
648 | |||
649 | if (val) | ||
650 | static_branch_enable(&tlb_use_lazy_mode); | ||
651 | else | ||
652 | static_branch_disable(&tlb_use_lazy_mode); | ||
653 | |||
654 | return count; | ||
655 | } | ||
656 | |||
657 | static const struct file_operations fops_tlblazy = { | ||
658 | .read = tlblazy_read_file, | ||
659 | .write = tlblazy_write_file, | ||
660 | .llseek = default_llseek, | ||
661 | }; | ||
662 | |||
663 | static int __init init_tlb_use_lazy_mode(void) | ||
664 | { | ||
665 | if (boot_cpu_has(X86_FEATURE_PCID)) { | ||
666 | /* | ||
667 | * Heuristic: with PCID on, switching to and from | ||
668 | * init_mm is reasonably fast, but remote flush IPIs | ||
669 | * as expensive as ever, so turn off lazy TLB mode. | ||
670 | * | ||
671 | * We can't do this in setup_pcid() because static keys | ||
672 | * haven't been initialized yet, and it would blow up | ||
673 | * badly. | ||
674 | */ | ||
675 | static_branch_disable(&tlb_use_lazy_mode); | ||
676 | } | ||
677 | |||
678 | debugfs_create_file("tlb_use_lazy_mode", S_IRUSR | S_IWUSR, | ||
679 | arch_debugfs_dir, NULL, &fops_tlblazy); | ||
680 | return 0; | ||
681 | } | ||
682 | late_initcall(init_tlb_use_lazy_mode); | ||