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authorLinus Walleij <linus.walleij@linaro.org>2018-08-08 08:38:55 -0400
committerDavid S. Miller <davem@davemloft.net>2018-08-09 17:15:00 -0400
commit933de7866b57b2fc8adc160642a81f07175f138d (patch)
tree426941763388190203f66173988ab92056d35f8e
parentcd16e5b233aadad5c4652f5466d1505a9f78bade (diff)
net: dsa: rtl8366rb: Support port 4 (WAN)
The totally undocumented IO mode needs to be set to enumerator 0 to enable port 4 also known as WAN in most configurations, for ordinary traffic. The 3 bits in the register come up as 010 after reset, but need to be set to 000. The Realtek source code contains a name for these bits, but no explanation of what the 8 different IO modes may be. Set it to zero for the time being and drop a comment so people know what is going on if they run into trouble. This "mode zero" works fine with the D-Link DIR-685 with RTL8366RB. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/dsa/rtl8366rb.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/net/dsa/rtl8366rb.c b/drivers/net/dsa/rtl8366rb.c
index 1e55b9bf8b56..a4d5049df692 100644
--- a/drivers/net/dsa/rtl8366rb.c
+++ b/drivers/net/dsa/rtl8366rb.c
@@ -48,6 +48,23 @@
48#define RTL8366RB_SSCR2 0x0004 48#define RTL8366RB_SSCR2 0x0004
49#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0) 49#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
50 50
51/* Port Mode Control registers */
52#define RTL8366RB_PMC0 0x0005
53#define RTL8366RB_PMC0_SPI BIT(0)
54#define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1)
55#define RTL8366RB_PMC0_PROBE BIT(2)
56#define RTL8366RB_PMC0_DIS_BISR BIT(3)
57#define RTL8366RB_PMC0_ADCTEST BIT(4)
58#define RTL8366RB_PMC0_SRAM_DIAG BIT(5)
59#define RTL8366RB_PMC0_EN_SCAN BIT(6)
60#define RTL8366RB_PMC0_P4_IOMODE_SHIFT 7
61#define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7)
62#define RTL8366RB_PMC0_P5_IOMODE_SHIFT 10
63#define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10)
64#define RTL8366RB_PMC0_SDSMODE_SHIFT 13
65#define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13)
66#define RTL8366RB_PMC1 0x0006
67
51/* Port Mirror Control Register */ 68/* Port Mirror Control Register */
52#define RTL8366RB_PMCR 0x0007 69#define RTL8366RB_PMCR 0x0007
53#define RTL8366RB_PMCR_SOURCE_PORT(a) (a) 70#define RTL8366RB_PMCR_SOURCE_PORT(a) (a)
@@ -860,6 +877,19 @@ static int rtl8366rb_setup(struct dsa_switch *ds)
860 if (ret) 877 if (ret)
861 return ret; 878 return ret;
862 879
880 /* Port 4 setup: this enables Port 4, usually the WAN port,
881 * common PHY IO mode is apparently mode 0, and this is not what
882 * the port is initialized to. There is no explanation of the
883 * IO modes in the Realtek source code, if your WAN port is
884 * connected to something exotic such as fiber, then this might
885 * be worth experimenting with.
886 */
887 ret = regmap_update_bits(smi->map, RTL8366RB_PMC0,
888 RTL8366RB_PMC0_P4_IOMODE_MASK,
889 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
890 if (ret)
891 return ret;
892
863 /* Discard VLAN tagged packets if the port is not a member of 893 /* Discard VLAN tagged packets if the port is not a member of
864 * the VLAN with which the packets is associated. 894 * the VLAN with which the packets is associated.
865 */ 895 */