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authorVinod Koul <vinod.koul@intel.com>2017-07-04 00:34:36 -0400
committerVinod Koul <vinod.koul@intel.com>2017-07-04 00:34:36 -0400
commit930a63485f858e2a12d25eb8204719a2d3157750 (patch)
tree9f0cd9091c76391c44443fcc5c628b016a6c6e97
parent1326fe64e70724b7c577db6c0837009f1e1fed23 (diff)
parent702fce05f5ad0e2af2c00d5ef41356ffdd4a3a56 (diff)
Merge branch 'topic/dw' into for-linus
Diffstat
-rw-r--r--drivers/dma/dw/Kconfig7
-rw-r--r--drivers/dma/dw/core.c332
-rw-r--r--drivers/dma/dw/platform.c6
-rw-r--r--drivers/dma/dw/regs.h50
-rw-r--r--include/linux/dma/dw.h21
-rw-r--r--sound/atmel/Kconfig13
-rw-r--r--sound/atmel/Makefile2
-rw-r--r--sound/atmel/abdac.c610
-rw-r--r--sound/atmel/ac97c.c447
9 files changed, 93 insertions, 1395 deletions
diff --git a/drivers/dma/dw/Kconfig b/drivers/dma/dw/Kconfig
index 5a37b9fcf40d..04b9728c1d26 100644
--- a/drivers/dma/dw/Kconfig
+++ b/drivers/dma/dw/Kconfig
@@ -6,17 +6,12 @@ config DW_DMAC_CORE
6 tristate 6 tristate
7 select DMA_ENGINE 7 select DMA_ENGINE
8 8
9config DW_DMAC_BIG_ENDIAN_IO
10 bool
11
12config DW_DMAC 9config DW_DMAC
13 tristate "Synopsys DesignWare AHB DMA platform driver" 10 tristate "Synopsys DesignWare AHB DMA platform driver"
14 select DW_DMAC_CORE 11 select DW_DMAC_CORE
15 select DW_DMAC_BIG_ENDIAN_IO if AVR32
16 default y if CPU_AT32AP7000
17 help 12 help
18 Support the Synopsys DesignWare AHB DMA controller. This 13 Support the Synopsys DesignWare AHB DMA controller. This
19 can be integrated in chips such as the Atmel AT32ap7000. 14 can be integrated in chips such as the Intel Cherrytrail.
20 15
21config DW_DMAC_PCI 16config DW_DMAC_PCI
22 tristate "Synopsys DesignWare AHB DMA PCI driver" 17 tristate "Synopsys DesignWare AHB DMA PCI driver"
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index e500950dad82..f43e6dafe446 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -561,92 +561,14 @@ static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
561 dwc_descriptor_complete(dwc, bad_desc, true); 561 dwc_descriptor_complete(dwc, bad_desc, true);
562} 562}
563 563
564/* --------------------- Cyclic DMA API extensions -------------------- */
565
566dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
567{
568 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
569 return channel_readl(dwc, SAR);
570}
571EXPORT_SYMBOL(dw_dma_get_src_addr);
572
573dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
574{
575 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
576 return channel_readl(dwc, DAR);
577}
578EXPORT_SYMBOL(dw_dma_get_dst_addr);
579
580/* Called with dwc->lock held and all DMAC interrupts disabled */
581static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
582 u32 status_block, u32 status_err, u32 status_xfer)
583{
584 unsigned long flags;
585
586 if (status_block & dwc->mask) {
587 void (*callback)(void *param);
588 void *callback_param;
589
590 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
591 channel_readl(dwc, LLP));
592 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
593
594 callback = dwc->cdesc->period_callback;
595 callback_param = dwc->cdesc->period_callback_param;
596
597 if (callback)
598 callback(callback_param);
599 }
600
601 /*
602 * Error and transfer complete are highly unlikely, and will most
603 * likely be due to a configuration error by the user.
604 */
605 if (unlikely(status_err & dwc->mask) ||
606 unlikely(status_xfer & dwc->mask)) {
607 unsigned int i;
608
609 dev_err(chan2dev(&dwc->chan),
610 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
611 status_xfer ? "xfer" : "error");
612
613 spin_lock_irqsave(&dwc->lock, flags);
614
615 dwc_dump_chan_regs(dwc);
616
617 dwc_chan_disable(dw, dwc);
618
619 /* Make sure DMA does not restart by loading a new list */
620 channel_writel(dwc, LLP, 0);
621 channel_writel(dwc, CTL_LO, 0);
622 channel_writel(dwc, CTL_HI, 0);
623
624 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
625 dma_writel(dw, CLEAR.ERROR, dwc->mask);
626 dma_writel(dw, CLEAR.XFER, dwc->mask);
627
628 for (i = 0; i < dwc->cdesc->periods; i++)
629 dwc_dump_lli(dwc, dwc->cdesc->desc[i]);
630
631 spin_unlock_irqrestore(&dwc->lock, flags);
632 }
633
634 /* Re-enable interrupts */
635 channel_set_bit(dw, MASK.BLOCK, dwc->mask);
636}
637
638/* ------------------------------------------------------------------------- */
639
640static void dw_dma_tasklet(unsigned long data) 564static void dw_dma_tasklet(unsigned long data)
641{ 565{
642 struct dw_dma *dw = (struct dw_dma *)data; 566 struct dw_dma *dw = (struct dw_dma *)data;
643 struct dw_dma_chan *dwc; 567 struct dw_dma_chan *dwc;
644 u32 status_block;
645 u32 status_xfer; 568 u32 status_xfer;
646 u32 status_err; 569 u32 status_err;
647 unsigned int i; 570 unsigned int i;
648 571
649 status_block = dma_readl(dw, RAW.BLOCK);
650 status_xfer = dma_readl(dw, RAW.XFER); 572 status_xfer = dma_readl(dw, RAW.XFER);
651 status_err = dma_readl(dw, RAW.ERROR); 573 status_err = dma_readl(dw, RAW.ERROR);
652 574
@@ -655,8 +577,7 @@ static void dw_dma_tasklet(unsigned long data)
655 for (i = 0; i < dw->dma.chancnt; i++) { 577 for (i = 0; i < dw->dma.chancnt; i++) {
656 dwc = &dw->chan[i]; 578 dwc = &dw->chan[i];
657 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) 579 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
658 dwc_handle_cyclic(dw, dwc, status_block, status_err, 580 dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n");
659 status_xfer);
660 else if (status_err & (1 << i)) 581 else if (status_err & (1 << i))
661 dwc_handle_error(dw, dwc); 582 dwc_handle_error(dw, dwc);
662 else if (status_xfer & (1 << i)) 583 else if (status_xfer & (1 << i))
@@ -1264,255 +1185,6 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
1264 dev_vdbg(chan2dev(chan), "%s: done\n", __func__); 1185 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1265} 1186}
1266 1187
1267/* --------------------- Cyclic DMA API extensions -------------------- */
1268
1269/**
1270 * dw_dma_cyclic_start - start the cyclic DMA transfer
1271 * @chan: the DMA channel to start
1272 *
1273 * Must be called with soft interrupts disabled. Returns zero on success or
1274 * -errno on failure.
1275 */
1276int dw_dma_cyclic_start(struct dma_chan *chan)
1277{
1278 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1279 struct dw_dma *dw = to_dw_dma(chan->device);
1280 unsigned long flags;
1281
1282 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1283 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1284 return -ENODEV;
1285 }
1286
1287 spin_lock_irqsave(&dwc->lock, flags);
1288
1289 /* Enable interrupts to perform cyclic transfer */
1290 channel_set_bit(dw, MASK.BLOCK, dwc->mask);
1291
1292 dwc_dostart(dwc, dwc->cdesc->desc[0]);
1293
1294 spin_unlock_irqrestore(&dwc->lock, flags);
1295
1296 return 0;
1297}
1298EXPORT_SYMBOL(dw_dma_cyclic_start);
1299
1300/**
1301 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1302 * @chan: the DMA channel to stop
1303 *
1304 * Must be called with soft interrupts disabled.
1305 */
1306void dw_dma_cyclic_stop(struct dma_chan *chan)
1307{
1308 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1309 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1310 unsigned long flags;
1311
1312 spin_lock_irqsave(&dwc->lock, flags);
1313
1314 dwc_chan_disable(dw, dwc);
1315
1316 spin_unlock_irqrestore(&dwc->lock, flags);
1317}
1318EXPORT_SYMBOL(dw_dma_cyclic_stop);
1319
1320/**
1321 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1322 * @chan: the DMA channel to prepare
1323 * @buf_addr: physical DMA address where the buffer starts
1324 * @buf_len: total number of bytes for the entire buffer
1325 * @period_len: number of bytes for each period
1326 * @direction: transfer direction, to or from device
1327 *
1328 * Must be called before trying to start the transfer. Returns a valid struct
1329 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1330 */
1331struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1332 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1333 enum dma_transfer_direction direction)
1334{
1335 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1336 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1337 struct dw_cyclic_desc *cdesc;
1338 struct dw_cyclic_desc *retval = NULL;
1339 struct dw_desc *desc;
1340 struct dw_desc *last = NULL;
1341 u8 lms = DWC_LLP_LMS(dwc->dws.m_master);
1342 unsigned long was_cyclic;
1343 unsigned int reg_width;
1344 unsigned int periods;
1345 unsigned int i;
1346 unsigned long flags;
1347
1348 spin_lock_irqsave(&dwc->lock, flags);
1349 if (dwc->nollp) {
1350 spin_unlock_irqrestore(&dwc->lock, flags);
1351 dev_dbg(chan2dev(&dwc->chan),
1352 "channel doesn't support LLP transfers\n");
1353 return ERR_PTR(-EINVAL);
1354 }
1355
1356 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1357 spin_unlock_irqrestore(&dwc->lock, flags);
1358 dev_dbg(chan2dev(&dwc->chan),
1359 "queue and/or active list are not empty\n");
1360 return ERR_PTR(-EBUSY);
1361 }
1362
1363 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1364 spin_unlock_irqrestore(&dwc->lock, flags);
1365 if (was_cyclic) {
1366 dev_dbg(chan2dev(&dwc->chan),
1367 "channel already prepared for cyclic DMA\n");
1368 return ERR_PTR(-EBUSY);
1369 }
1370
1371 retval = ERR_PTR(-EINVAL);
1372
1373 if (unlikely(!is_slave_direction(direction)))
1374 goto out_err;
1375
1376 dwc->direction = direction;
1377
1378 if (direction == DMA_MEM_TO_DEV)
1379 reg_width = __ffs(sconfig->dst_addr_width);
1380 else
1381 reg_width = __ffs(sconfig->src_addr_width);
1382
1383 periods = buf_len / period_len;
1384
1385 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1386 if (period_len > (dwc->block_size << reg_width))
1387 goto out_err;
1388 if (unlikely(period_len & ((1 << reg_width) - 1)))
1389 goto out_err;
1390 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1391 goto out_err;
1392
1393 retval = ERR_PTR(-ENOMEM);
1394
1395 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1396 if (!cdesc)
1397 goto out_err;
1398
1399 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1400 if (!cdesc->desc)
1401 goto out_err_alloc;
1402
1403 for (i = 0; i < periods; i++) {
1404 desc = dwc_desc_get(dwc);
1405 if (!desc)
1406 goto out_err_desc_get;
1407
1408 switch (direction) {
1409 case DMA_MEM_TO_DEV:
1410 lli_write(desc, dar, sconfig->dst_addr);
1411 lli_write(desc, sar, buf_addr + period_len * i);
1412 lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan)
1413 | DWC_CTLL_DST_WIDTH(reg_width)
1414 | DWC_CTLL_SRC_WIDTH(reg_width)
1415 | DWC_CTLL_DST_FIX
1416 | DWC_CTLL_SRC_INC
1417 | DWC_CTLL_INT_EN));
1418
1419 lli_set(desc, ctllo, sconfig->device_fc ?
1420 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1421 DWC_CTLL_FC(DW_DMA_FC_D_M2P));
1422
1423 break;
1424 case DMA_DEV_TO_MEM:
1425 lli_write(desc, dar, buf_addr + period_len * i);
1426 lli_write(desc, sar, sconfig->src_addr);
1427 lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan)
1428 | DWC_CTLL_SRC_WIDTH(reg_width)
1429 | DWC_CTLL_DST_WIDTH(reg_width)
1430 | DWC_CTLL_DST_INC
1431 | DWC_CTLL_SRC_FIX
1432 | DWC_CTLL_INT_EN));
1433
1434 lli_set(desc, ctllo, sconfig->device_fc ?
1435 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1436 DWC_CTLL_FC(DW_DMA_FC_D_P2M));
1437
1438 break;
1439 default:
1440 break;
1441 }
1442
1443 lli_write(desc, ctlhi, period_len >> reg_width);
1444 cdesc->desc[i] = desc;
1445
1446 if (last)
1447 lli_write(last, llp, desc->txd.phys | lms);
1448
1449 last = desc;
1450 }
1451
1452 /* Let's make a cyclic list */
1453 lli_write(last, llp, cdesc->desc[0]->txd.phys | lms);
1454
1455 dev_dbg(chan2dev(&dwc->chan),
1456 "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1457 &buf_addr, buf_len, period_len, periods);
1458
1459 cdesc->periods = periods;
1460 dwc->cdesc = cdesc;
1461
1462 return cdesc;
1463
1464out_err_desc_get:
1465 while (i--)
1466 dwc_desc_put(dwc, cdesc->desc[i]);
1467out_err_alloc:
1468 kfree(cdesc);
1469out_err:
1470 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1471 return (struct dw_cyclic_desc *)retval;
1472}
1473EXPORT_SYMBOL(dw_dma_cyclic_prep);
1474
1475/**
1476 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1477 * @chan: the DMA channel to free
1478 */
1479void dw_dma_cyclic_free(struct dma_chan *chan)
1480{
1481 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1482 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1483 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1484 unsigned int i;
1485 unsigned long flags;
1486
1487 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1488
1489 if (!cdesc)
1490 return;
1491
1492 spin_lock_irqsave(&dwc->lock, flags);
1493
1494 dwc_chan_disable(dw, dwc);
1495
1496 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1497 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1498 dma_writel(dw, CLEAR.XFER, dwc->mask);
1499
1500 spin_unlock_irqrestore(&dwc->lock, flags);
1501
1502 for (i = 0; i < cdesc->periods; i++)
1503 dwc_desc_put(dwc, cdesc->desc[i]);
1504
1505 kfree(cdesc->desc);
1506 kfree(cdesc);
1507
1508 dwc->cdesc = NULL;
1509
1510 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1511}
1512EXPORT_SYMBOL(dw_dma_cyclic_free);
1513
1514/*----------------------------------------------------------------------*/
1515
1516int dw_dma_probe(struct dw_dma_chip *chip) 1188int dw_dma_probe(struct dw_dma_chip *chip)
1517{ 1189{
1518 struct dw_dma_platform_data *pdata; 1190 struct dw_dma_platform_data *pdata;
@@ -1642,7 +1314,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)
1642 if (autocfg) { 1314 if (autocfg) {
1643 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; 1315 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1644 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r]; 1316 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r];
1645 unsigned int dwc_params = dma_readl_native(addr); 1317 unsigned int dwc_params = readl(addr);
1646 1318
1647 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, 1319 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1648 dwc_params); 1320 dwc_params);
diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index c639c60b825a..bc31fe802061 100644
--- a/drivers/dma/dw/platform.c
+++ b/drivers/dma/dw/platform.c
@@ -306,8 +306,12 @@ static int dw_resume_early(struct device *dev)
306{ 306{
307 struct platform_device *pdev = to_platform_device(dev); 307 struct platform_device *pdev = to_platform_device(dev);
308 struct dw_dma_chip *chip = platform_get_drvdata(pdev); 308 struct dw_dma_chip *chip = platform_get_drvdata(pdev);
309 int ret;
310
311 ret = clk_prepare_enable(chip->clk);
312 if (ret)
313 return ret;
309 314
310 clk_prepare_enable(chip->clk);
311 return dw_dma_enable(chip); 315 return dw_dma_enable(chip);
312} 316}
313 317
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 32a328721c88..09e7dfdbb790 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -116,20 +116,6 @@ struct dw_dma_regs {
116 DW_REG(GLOBAL_CFG); 116 DW_REG(GLOBAL_CFG);
117}; 117};
118 118
119/*
120 * Big endian I/O access when reading and writing to the DMA controller
121 * registers. This is needed on some platforms, like the Atmel AVR32
122 * architecture.
123 */
124
125#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
126#define dma_readl_native ioread32be
127#define dma_writel_native iowrite32be
128#else
129#define dma_readl_native readl
130#define dma_writel_native writel
131#endif
132
133/* Bitfields in DW_PARAMS */ 119/* Bitfields in DW_PARAMS */
134#define DW_PARAMS_NR_CHAN 8 /* number of channels */ 120#define DW_PARAMS_NR_CHAN 8 /* number of channels */
135#define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */ 121#define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */
@@ -280,7 +266,6 @@ struct dw_dma_chan {
280 unsigned long flags; 266 unsigned long flags;
281 struct list_head active_list; 267 struct list_head active_list;
282 struct list_head queue; 268 struct list_head queue;
283 struct dw_cyclic_desc *cdesc;
284 269
285 unsigned int descs_allocated; 270 unsigned int descs_allocated;
286 271
@@ -302,9 +287,9 @@ __dwc_regs(struct dw_dma_chan *dwc)
302} 287}
303 288
304#define channel_readl(dwc, name) \ 289#define channel_readl(dwc, name) \
305 dma_readl_native(&(__dwc_regs(dwc)->name)) 290 readl(&(__dwc_regs(dwc)->name))
306#define channel_writel(dwc, name, val) \ 291#define channel_writel(dwc, name, val) \
307 dma_writel_native((val), &(__dwc_regs(dwc)->name)) 292 writel((val), &(__dwc_regs(dwc)->name))
308 293
309static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) 294static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
310{ 295{
@@ -333,9 +318,9 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
333} 318}
334 319
335#define dma_readl(dw, name) \ 320#define dma_readl(dw, name) \
336 dma_readl_native(&(__dw_regs(dw)->name)) 321 readl(&(__dw_regs(dw)->name))
337#define dma_writel(dw, name, val) \ 322#define dma_writel(dw, name, val) \
338 dma_writel_native((val), &(__dw_regs(dw)->name)) 323 writel((val), &(__dw_regs(dw)->name))
339 324
340#define idma32_readq(dw, name) \ 325#define idma32_readq(dw, name) \
341 hi_lo_readq(&(__dw_regs(dw)->name)) 326 hi_lo_readq(&(__dw_regs(dw)->name))
@@ -352,43 +337,30 @@ static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
352 return container_of(ddev, struct dw_dma, dma); 337 return container_of(ddev, struct dw_dma, dma);
353} 338}
354 339
355#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
356typedef __be32 __dw32;
357#else
358typedef __le32 __dw32;
359#endif
360
361/* LLI == Linked List Item; a.k.a. DMA block descriptor */ 340/* LLI == Linked List Item; a.k.a. DMA block descriptor */
362struct dw_lli { 341struct dw_lli {
363 /* values that are not changed by hardware */ 342 /* values that are not changed by hardware */
364 __dw32 sar; 343 __le32 sar;
365 __dw32 dar; 344 __le32 dar;
366 __dw32 llp; /* chain to next lli */ 345 __le32 llp; /* chain to next lli */
367 __dw32 ctllo; 346 __le32 ctllo;
368 /* values that may get written back: */ 347 /* values that may get written back: */
369 __dw32 ctlhi; 348 __le32 ctlhi;
370 /* sstat and dstat can snapshot peripheral register state. 349 /* sstat and dstat can snapshot peripheral register state.
371 * silicon config may discard either or both... 350 * silicon config may discard either or both...
372 */ 351 */
373 __dw32 sstat; 352 __le32 sstat;
374 __dw32 dstat; 353 __le32 dstat;
375}; 354};
376 355
377struct dw_desc { 356struct dw_desc {
378 /* FIRST values the hardware uses */ 357 /* FIRST values the hardware uses */
379 struct dw_lli lli; 358 struct dw_lli lli;
380 359
381#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
382#define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_be32(v))
383#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_be32(v))
384#define lli_read(d, reg) be32_to_cpu((d)->lli.reg)
385#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_be32(v))
386#else
387#define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_le32(v)) 360#define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_le32(v))
388#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le32(v)) 361#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le32(v))
389#define lli_read(d, reg) le32_to_cpu((d)->lli.reg) 362#define lli_read(d, reg) le32_to_cpu((d)->lli.reg)
390#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le32(v)) 363#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le32(v))
391#endif
392 364
393 /* THEN values for driver housekeeping */ 365 /* THEN values for driver housekeeping */
394 struct list_head desc_node; 366 struct list_head desc_node;
diff --git a/include/linux/dma/dw.h b/include/linux/dma/dw.h
index b63b25814d77..e166cac8e870 100644
--- a/include/linux/dma/dw.h
+++ b/include/linux/dma/dw.h
@@ -50,25 +50,4 @@ static inline int dw_dma_probe(struct dw_dma_chip *chip) { return -ENODEV; }
50static inline int dw_dma_remove(struct dw_dma_chip *chip) { return 0; } 50static inline int dw_dma_remove(struct dw_dma_chip *chip) { return 0; }
51#endif /* CONFIG_DW_DMAC_CORE */ 51#endif /* CONFIG_DW_DMAC_CORE */
52 52
53/* DMA API extensions */
54struct dw_desc;
55
56struct dw_cyclic_desc {
57 struct dw_desc **desc;
58 unsigned long periods;
59 void (*period_callback)(void *param);
60 void *period_callback_param;
61};
62
63struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
64 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
65 enum dma_transfer_direction direction);
66void dw_dma_cyclic_free(struct dma_chan *chan);
67int dw_dma_cyclic_start(struct dma_chan *chan);
68void dw_dma_cyclic_stop(struct dma_chan *chan);
69
70dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
71
72dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
73
74#endif /* _DMA_DW_H */ 53#endif /* _DMA_DW_H */
diff --git a/sound/atmel/Kconfig b/sound/atmel/Kconfig
index 94de43a096f1..d789cbcb9106 100644
--- a/sound/atmel/Kconfig
+++ b/sound/atmel/Kconfig
@@ -1,18 +1,11 @@
1menu "Atmel devices (AVR32 and AT91)" 1menu "Atmel devices (AT91)"
2 depends on AVR32 || ARCH_AT91 2 depends on ARCH_AT91
3
4config SND_ATMEL_ABDAC
5 tristate "Atmel Audio Bitstream DAC (ABDAC) driver"
6 select SND_PCM
7 depends on DW_DMAC && AVR32
8 help
9 ALSA sound driver for the Atmel Audio Bitstream DAC (ABDAC).
10 3
11config SND_ATMEL_AC97C 4config SND_ATMEL_AC97C
12 tristate "Atmel AC97 Controller (AC97C) driver" 5 tristate "Atmel AC97 Controller (AC97C) driver"
13 select SND_PCM 6 select SND_PCM
14 select SND_AC97_CODEC 7 select SND_AC97_CODEC
15 depends on (DW_DMAC && AVR32) || ARCH_AT91 8 depends on ARCH_AT91
16 help 9 help
17 ALSA sound driver for the Atmel AC97 controller. 10 ALSA sound driver for the Atmel AC97 controller.
18 11
diff --git a/sound/atmel/Makefile b/sound/atmel/Makefile
index 219dcfac6086..d4009d1430ed 100644
--- a/sound/atmel/Makefile
+++ b/sound/atmel/Makefile
@@ -1,5 +1,3 @@
1snd-atmel-abdac-objs := abdac.o
2snd-atmel-ac97c-objs := ac97c.o 1snd-atmel-ac97c-objs := ac97c.o
3 2
4obj-$(CONFIG_SND_ATMEL_ABDAC) += snd-atmel-abdac.o
5obj-$(CONFIG_SND_ATMEL_AC97C) += snd-atmel-ac97c.o 3obj-$(CONFIG_SND_ATMEL_AC97C) += snd-atmel-ac97c.o
diff --git a/sound/atmel/abdac.c b/sound/atmel/abdac.c
deleted file mode 100644
index 558618802000..000000000000
--- a/sound/atmel/abdac.c
+++ /dev/null
@@ -1,610 +0,0 @@
1/*
2 * Driver for the Atmel on-chip Audio Bitstream DAC (ABDAC)
3 *
4 * Copyright (C) 2006-2009 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 */
10#include <linux/clk.h>
11#include <linux/bitmap.h>
12#include <linux/dmaengine.h>
13#include <linux/dma-mapping.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/types.h>
19#include <linux/io.h>
20
21#include <sound/core.h>
22#include <sound/initval.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/atmel-abdac.h>
26
27#include <linux/platform_data/dma-dw.h>
28#include <linux/dma/dw.h>
29
30/* DAC register offsets */
31#define DAC_DATA 0x0000
32#define DAC_CTRL 0x0008
33#define DAC_INT_MASK 0x000c
34#define DAC_INT_EN 0x0010
35#define DAC_INT_DIS 0x0014
36#define DAC_INT_CLR 0x0018
37#define DAC_INT_STATUS 0x001c
38
39/* Bitfields in CTRL */
40#define DAC_SWAP_OFFSET 30
41#define DAC_SWAP_SIZE 1
42#define DAC_EN_OFFSET 31
43#define DAC_EN_SIZE 1
44
45/* Bitfields in INT_MASK/INT_EN/INT_DIS/INT_STATUS/INT_CLR */
46#define DAC_UNDERRUN_OFFSET 28
47#define DAC_UNDERRUN_SIZE 1
48#define DAC_TX_READY_OFFSET 29
49#define DAC_TX_READY_SIZE 1
50
51/* Bit manipulation macros */
52#define DAC_BIT(name) \
53 (1 << DAC_##name##_OFFSET)
54#define DAC_BF(name, value) \
55 (((value) & ((1 << DAC_##name##_SIZE) - 1)) \
56 << DAC_##name##_OFFSET)
57#define DAC_BFEXT(name, value) \
58 (((value) >> DAC_##name##_OFFSET) \
59 & ((1 << DAC_##name##_SIZE) - 1))
60#define DAC_BFINS(name, value, old) \
61 (((old) & ~(((1 << DAC_##name##_SIZE) - 1) \
62 << DAC_##name##_OFFSET)) \
63 | DAC_BF(name, value))
64
65/* Register access macros */
66#define dac_readl(port, reg) \
67 __raw_readl((port)->regs + DAC_##reg)
68#define dac_writel(port, reg, value) \
69 __raw_writel((value), (port)->regs + DAC_##reg)
70
71/*
72 * ABDAC supports a maximum of 6 different rates from a generic clock. The
73 * generic clock has a power of two divider, which gives 6 steps from 192 kHz
74 * to 5112 Hz.
75 */
76#define MAX_NUM_RATES 6
77/* ALSA seems to use rates between 192000 Hz and 5112 Hz. */
78#define RATE_MAX 192000
79#define RATE_MIN 5112
80
81enum {
82 DMA_READY = 0,
83};
84
85struct atmel_abdac_dma {
86 struct dma_chan *chan;
87 struct dw_cyclic_desc *cdesc;
88};
89
90struct atmel_abdac {
91 struct clk *pclk;
92 struct clk *sample_clk;
93 struct platform_device *pdev;
94 struct atmel_abdac_dma dma;
95
96 struct snd_pcm_hw_constraint_list constraints_rates;
97 struct snd_pcm_substream *substream;
98 struct snd_card *card;
99 struct snd_pcm *pcm;
100
101 void __iomem *regs;
102 unsigned long flags;
103 unsigned int rates[MAX_NUM_RATES];
104 unsigned int rates_num;
105 int irq;
106};
107
108#define get_dac(card) ((struct atmel_abdac *)(card)->private_data)
109
110/* This function is called by the DMA driver. */
111static void atmel_abdac_dma_period_done(void *arg)
112{
113 struct atmel_abdac *dac = arg;
114 snd_pcm_period_elapsed(dac->substream);
115}
116
117static int atmel_abdac_prepare_dma(struct atmel_abdac *dac,
118 struct snd_pcm_substream *substream,
119 enum dma_data_direction direction)
120{
121 struct dma_chan *chan = dac->dma.chan;
122 struct dw_cyclic_desc *cdesc;
123 struct snd_pcm_runtime *runtime = substream->runtime;
124 unsigned long buffer_len, period_len;
125
126 /*
127 * We don't do DMA on "complex" transfers, i.e. with
128 * non-halfword-aligned buffers or lengths.
129 */
130 if (runtime->dma_addr & 1 || runtime->buffer_size & 1) {
131 dev_dbg(&dac->pdev->dev, "too complex transfer\n");
132 return -EINVAL;
133 }
134
135 buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
136 period_len = frames_to_bytes(runtime, runtime->period_size);
137
138 cdesc = dw_dma_cyclic_prep(chan, runtime->dma_addr, buffer_len,
139 period_len, DMA_MEM_TO_DEV);
140 if (IS_ERR(cdesc)) {
141 dev_dbg(&dac->pdev->dev, "could not prepare cyclic DMA\n");
142 return PTR_ERR(cdesc);
143 }
144
145 cdesc->period_callback = atmel_abdac_dma_period_done;
146 cdesc->period_callback_param = dac;
147
148 dac->dma.cdesc = cdesc;
149
150 set_bit(DMA_READY, &dac->flags);
151
152 return 0;
153}
154
155static struct snd_pcm_hardware atmel_abdac_hw = {
156 .info = (SNDRV_PCM_INFO_MMAP
157 | SNDRV_PCM_INFO_MMAP_VALID
158 | SNDRV_PCM_INFO_INTERLEAVED
159 | SNDRV_PCM_INFO_BLOCK_TRANSFER
160 | SNDRV_PCM_INFO_RESUME
161 | SNDRV_PCM_INFO_PAUSE),
162 .formats = (SNDRV_PCM_FMTBIT_S16_BE),
163 .rates = (SNDRV_PCM_RATE_KNOT),
164 .rate_min = RATE_MIN,
165 .rate_max = RATE_MAX,
166 .channels_min = 2,
167 .channels_max = 2,
168 .buffer_bytes_max = 64 * 4096,
169 .period_bytes_min = 4096,
170 .period_bytes_max = 4096,
171 .periods_min = 6,
172 .periods_max = 64,
173};
174
175static int atmel_abdac_open(struct snd_pcm_substream *substream)
176{
177 struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
178
179 dac->substream = substream;
180 atmel_abdac_hw.rate_max = dac->rates[dac->rates_num - 1];
181 atmel_abdac_hw.rate_min = dac->rates[0];
182 substream->runtime->hw = atmel_abdac_hw;
183
184 return snd_pcm_hw_constraint_list(substream->runtime, 0,
185 SNDRV_PCM_HW_PARAM_RATE, &dac->constraints_rates);
186}
187
188static int atmel_abdac_close(struct snd_pcm_substream *substream)
189{
190 struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
191 dac->substream = NULL;
192 return 0;
193}
194
195static int atmel_abdac_hw_params(struct snd_pcm_substream *substream,
196 struct snd_pcm_hw_params *hw_params)
197{
198 struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
199 int retval;
200
201 retval = snd_pcm_lib_malloc_pages(substream,
202 params_buffer_bytes(hw_params));
203 if (retval < 0)
204 return retval;
205 /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
206 if (retval == 1)
207 if (test_and_clear_bit(DMA_READY, &dac->flags))
208 dw_dma_cyclic_free(dac->dma.chan);
209
210 return retval;
211}
212
213static int atmel_abdac_hw_free(struct snd_pcm_substream *substream)
214{
215 struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
216 if (test_and_clear_bit(DMA_READY, &dac->flags))
217 dw_dma_cyclic_free(dac->dma.chan);
218 return snd_pcm_lib_free_pages(substream);
219}
220
221static int atmel_abdac_prepare(struct snd_pcm_substream *substream)
222{
223 struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
224 int retval;
225
226 retval = clk_set_rate(dac->sample_clk, 256 * substream->runtime->rate);
227 if (retval)
228 return retval;
229
230 if (!test_bit(DMA_READY, &dac->flags))
231 retval = atmel_abdac_prepare_dma(dac, substream, DMA_TO_DEVICE);
232
233 return retval;
234}
235
236static int atmel_abdac_trigger(struct snd_pcm_substream *substream, int cmd)
237{
238 struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
239 int retval = 0;
240
241 switch (cmd) {
242 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
243 case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
244 case SNDRV_PCM_TRIGGER_START:
245 clk_prepare_enable(dac->sample_clk);
246 retval = dw_dma_cyclic_start(dac->dma.chan);
247 if (retval)
248 goto out;
249 dac_writel(dac, CTRL, DAC_BIT(EN));
250 break;
251 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
252 case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
253 case SNDRV_PCM_TRIGGER_STOP:
254 dw_dma_cyclic_stop(dac->dma.chan);
255 dac_writel(dac, DATA, 0);
256 dac_writel(dac, CTRL, 0);
257 clk_disable_unprepare(dac->sample_clk);
258 break;
259 default:
260 retval = -EINVAL;
261 break;
262 }
263out:
264 return retval;
265}
266
267static snd_pcm_uframes_t
268atmel_abdac_pointer(struct snd_pcm_substream *substream)
269{
270 struct atmel_abdac *dac = snd_pcm_substream_chip(substream);
271 struct snd_pcm_runtime *runtime = substream->runtime;
272 snd_pcm_uframes_t frames;
273 unsigned long bytes;
274
275 bytes = dw_dma_get_src_addr(dac->dma.chan);
276 bytes -= runtime->dma_addr;
277
278 frames = bytes_to_frames(runtime, bytes);
279 if (frames >= runtime->buffer_size)
280 frames -= runtime->buffer_size;
281
282 return frames;
283}
284
285static irqreturn_t abdac_interrupt(int irq, void *dev_id)
286{
287 struct atmel_abdac *dac = dev_id;
288 u32 status;
289
290 status = dac_readl(dac, INT_STATUS);
291 if (status & DAC_BIT(UNDERRUN)) {
292 dev_err(&dac->pdev->dev, "underrun detected\n");
293 dac_writel(dac, INT_CLR, DAC_BIT(UNDERRUN));
294 } else {
295 dev_err(&dac->pdev->dev, "spurious interrupt (status=0x%x)\n",
296 status);
297 dac_writel(dac, INT_CLR, status);
298 }
299
300 return IRQ_HANDLED;
301}
302
303static struct snd_pcm_ops atmel_abdac_ops = {
304 .open = atmel_abdac_open,
305 .close = atmel_abdac_close,
306 .ioctl = snd_pcm_lib_ioctl,
307 .hw_params = atmel_abdac_hw_params,
308 .hw_free = atmel_abdac_hw_free,
309 .prepare = atmel_abdac_prepare,
310 .trigger = atmel_abdac_trigger,
311 .pointer = atmel_abdac_pointer,
312};
313
314static int atmel_abdac_pcm_new(struct atmel_abdac *dac)
315{
316 struct snd_pcm_hardware hw = atmel_abdac_hw;
317 struct snd_pcm *pcm;
318 int retval;
319
320 retval = snd_pcm_new(dac->card, dac->card->shortname,
321 dac->pdev->id, 1, 0, &pcm);
322 if (retval)
323 return retval;
324
325 strcpy(pcm->name, dac->card->shortname);
326 pcm->private_data = dac;
327 pcm->info_flags = 0;
328 dac->pcm = pcm;
329
330 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &atmel_abdac_ops);
331
332 retval = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
333 &dac->pdev->dev, hw.periods_min * hw.period_bytes_min,
334 hw.buffer_bytes_max);
335
336 return retval;
337}
338
339static bool filter(struct dma_chan *chan, void *slave)
340{
341 struct dw_dma_slave *dws = slave;
342
343 if (dws->dma_dev == chan->device->dev) {
344 chan->private = dws;
345 return true;
346 } else
347 return false;
348}
349
350static int set_sample_rates(struct atmel_abdac *dac)
351{
352 long new_rate = RATE_MAX;
353 int retval = -EINVAL;
354 int index = 0;
355
356 /* we start at 192 kHz and work our way down to 5112 Hz */
357 while (new_rate >= RATE_MIN && index < (MAX_NUM_RATES + 1)) {
358 new_rate = clk_round_rate(dac->sample_clk, 256 * new_rate);
359 if (new_rate <= 0)
360 break;
361 /* make sure we are below the ABDAC clock */
362 if (index < MAX_NUM_RATES &&
363 new_rate <= clk_get_rate(dac->pclk)) {
364 dac->rates[index] = new_rate / 256;
365 index++;
366 }
367 /* divide by 256 and then by two to get next rate */
368 new_rate /= 256 * 2;
369 }
370
371 if (index) {
372 int i;
373
374 /* reverse array, smallest go first */
375 for (i = 0; i < (index / 2); i++) {
376 unsigned int tmp = dac->rates[index - 1 - i];
377 dac->rates[index - 1 - i] = dac->rates[i];
378 dac->rates[i] = tmp;
379 }
380
381 dac->constraints_rates.count = index;
382 dac->constraints_rates.list = dac->rates;
383 dac->constraints_rates.mask = 0;
384 dac->rates_num = index;
385
386 retval = 0;
387 }
388
389 return retval;
390}
391
392static int atmel_abdac_probe(struct platform_device *pdev)
393{
394 struct snd_card *card;
395 struct atmel_abdac *dac;
396 struct resource *regs;
397 struct atmel_abdac_pdata *pdata;
398 struct clk *pclk;
399 struct clk *sample_clk;
400 int retval;
401 int irq;
402
403 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
404 if (!regs) {
405 dev_dbg(&pdev->dev, "no memory resource\n");
406 return -ENXIO;
407 }
408
409 irq = platform_get_irq(pdev, 0);
410 if (irq < 0) {
411 dev_dbg(&pdev->dev, "could not get IRQ number\n");
412 return irq;
413 }
414
415 pdata = pdev->dev.platform_data;
416 if (!pdata) {
417 dev_dbg(&pdev->dev, "no platform data\n");
418 return -ENXIO;
419 }
420
421 pclk = clk_get(&pdev->dev, "pclk");
422 if (IS_ERR(pclk)) {
423 dev_dbg(&pdev->dev, "no peripheral clock\n");
424 return PTR_ERR(pclk);
425 }
426 sample_clk = clk_get(&pdev->dev, "sample_clk");
427 if (IS_ERR(sample_clk)) {
428 dev_dbg(&pdev->dev, "no sample clock\n");
429 retval = PTR_ERR(sample_clk);
430 goto out_put_pclk;
431 }
432 clk_prepare_enable(pclk);
433
434 retval = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1,
435 SNDRV_DEFAULT_STR1, THIS_MODULE,
436 sizeof(struct atmel_abdac), &card);
437 if (retval) {
438 dev_dbg(&pdev->dev, "could not create sound card device\n");
439 goto out_put_sample_clk;
440 }
441
442 dac = get_dac(card);
443
444 dac->irq = irq;
445 dac->card = card;
446 dac->pclk = pclk;
447 dac->sample_clk = sample_clk;
448 dac->pdev = pdev;
449
450 retval = set_sample_rates(dac);
451 if (retval < 0) {
452 dev_dbg(&pdev->dev, "could not set supported rates\n");
453 goto out_free_card;
454 }
455
456 dac->regs = ioremap(regs->start, resource_size(regs));
457 if (!dac->regs) {
458 dev_dbg(&pdev->dev, "could not remap register memory\n");
459 retval = -ENOMEM;
460 goto out_free_card;
461 }
462
463 /* make sure the DAC is silent and disabled */
464 dac_writel(dac, DATA, 0);
465 dac_writel(dac, CTRL, 0);
466
467 retval = request_irq(irq, abdac_interrupt, 0, "abdac", dac);
468 if (retval) {
469 dev_dbg(&pdev->dev, "could not request irq\n");
470 goto out_unmap_regs;
471 }
472
473 if (pdata->dws.dma_dev) {
474 dma_cap_mask_t mask;
475
476 dma_cap_zero(mask);
477 dma_cap_set(DMA_SLAVE, mask);
478
479 dac->dma.chan = dma_request_channel(mask, filter, &pdata->dws);
480 if (dac->dma.chan) {
481 struct dma_slave_config dma_conf = {
482 .dst_addr = regs->start + DAC_DATA,
483 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
484 .src_maxburst = 1,
485 .dst_maxburst = 1,
486 .direction = DMA_MEM_TO_DEV,
487 .device_fc = false,
488 };
489
490 dmaengine_slave_config(dac->dma.chan, &dma_conf);
491 }
492 }
493 if (!pdata->dws.dma_dev || !dac->dma.chan) {
494 dev_dbg(&pdev->dev, "DMA not available\n");
495 retval = -ENODEV;
496 goto out_unmap_regs;
497 }
498
499 strcpy(card->driver, "Atmel ABDAC");
500 strcpy(card->shortname, "Atmel ABDAC");
501 sprintf(card->longname, "Atmel Audio Bitstream DAC");
502
503 retval = atmel_abdac_pcm_new(dac);
504 if (retval) {
505 dev_dbg(&pdev->dev, "could not register ABDAC pcm device\n");
506 goto out_release_dma;
507 }
508
509 retval = snd_card_register(card);
510 if (retval) {
511 dev_dbg(&pdev->dev, "could not register sound card\n");
512 goto out_release_dma;
513 }
514
515 platform_set_drvdata(pdev, card);
516
517 dev_info(&pdev->dev, "Atmel ABDAC at 0x%p using %s\n",
518 dac->regs, dev_name(&dac->dma.chan->dev->device));
519
520 return retval;
521
522out_release_dma:
523 dma_release_channel(dac->dma.chan);
524 dac->dma.chan = NULL;
525out_unmap_regs:
526 iounmap(dac->regs);
527out_free_card:
528 snd_card_free(card);
529out_put_sample_clk:
530 clk_put(sample_clk);
531 clk_disable_unprepare(pclk);
532out_put_pclk:
533 clk_put(pclk);
534 return retval;
535}
536
537#ifdef CONFIG_PM_SLEEP
538static int atmel_abdac_suspend(struct device *pdev)
539{
540 struct snd_card *card = dev_get_drvdata(pdev);
541 struct atmel_abdac *dac = card->private_data;
542
543 dw_dma_cyclic_stop(dac->dma.chan);
544 clk_disable_unprepare(dac->sample_clk);
545 clk_disable_unprepare(dac->pclk);
546
547 return 0;
548}
549
550static int atmel_abdac_resume(struct device *pdev)
551{
552 struct snd_card *card = dev_get_drvdata(pdev);
553 struct atmel_abdac *dac = card->private_data;
554
555 clk_prepare_enable(dac->pclk);
556 clk_prepare_enable(dac->sample_clk);
557 if (test_bit(DMA_READY, &dac->flags))
558 dw_dma_cyclic_start(dac->dma.chan);
559
560 return 0;
561}
562
563static SIMPLE_DEV_PM_OPS(atmel_abdac_pm, atmel_abdac_suspend, atmel_abdac_resume);
564#define ATMEL_ABDAC_PM_OPS &atmel_abdac_pm
565#else
566#define ATMEL_ABDAC_PM_OPS NULL
567#endif
568
569static int atmel_abdac_remove(struct platform_device *pdev)
570{
571 struct snd_card *card = platform_get_drvdata(pdev);
572 struct atmel_abdac *dac = get_dac(card);
573
574 clk_put(dac->sample_clk);
575 clk_disable_unprepare(dac->pclk);
576 clk_put(dac->pclk);
577
578 dma_release_channel(dac->dma.chan);
579 dac->dma.chan = NULL;
580 iounmap(dac->regs);
581 free_irq(dac->irq, dac);
582 snd_card_free(card);
583
584 return 0;
585}
586
587static struct platform_driver atmel_abdac_driver = {
588 .remove = atmel_abdac_remove,
589 .driver = {
590 .name = "atmel_abdac",
591 .pm = ATMEL_ABDAC_PM_OPS,
592 },
593};
594
595static int __init atmel_abdac_init(void)
596{
597 return platform_driver_probe(&atmel_abdac_driver,
598 atmel_abdac_probe);
599}
600module_init(atmel_abdac_init);
601
602static void __exit atmel_abdac_exit(void)
603{
604 platform_driver_unregister(&atmel_abdac_driver);
605}
606module_exit(atmel_abdac_exit);
607
608MODULE_LICENSE("GPL");
609MODULE_DESCRIPTION("Driver for Atmel Audio Bitstream DAC (ABDAC)");
610MODULE_AUTHOR("Hans-Christian Egtvedt <egtvedt@samfundet.no>");
diff --git a/sound/atmel/ac97c.c b/sound/atmel/ac97c.c
index 6dad042630d8..65e6948e3995 100644
--- a/sound/atmel/ac97c.c
+++ b/sound/atmel/ac97c.c
@@ -11,8 +11,6 @@
11#include <linux/delay.h> 11#include <linux/delay.h>
12#include <linux/bitmap.h> 12#include <linux/bitmap.h>
13#include <linux/device.h> 13#include <linux/device.h>
14#include <linux/dmaengine.h>
15#include <linux/dma-mapping.h>
16#include <linux/atmel_pdc.h> 14#include <linux/atmel_pdc.h>
17#include <linux/init.h> 15#include <linux/init.h>
18#include <linux/interrupt.h> 16#include <linux/interrupt.h>
@@ -34,36 +32,14 @@
34#include <sound/atmel-ac97c.h> 32#include <sound/atmel-ac97c.h>
35#include <sound/memalloc.h> 33#include <sound/memalloc.h>
36 34
37#include <linux/platform_data/dma-dw.h>
38#include <linux/dma/dw.h>
39
40#ifdef CONFIG_AVR32
41#include <mach/cpu.h>
42#else
43#define cpu_is_at32ap7000() 0
44#endif
45
46#include "ac97c.h" 35#include "ac97c.h"
47 36
48enum {
49 DMA_TX_READY = 0,
50 DMA_RX_READY,
51 DMA_TX_CHAN_PRESENT,
52 DMA_RX_CHAN_PRESENT,
53};
54
55/* Serialize access to opened variable */ 37/* Serialize access to opened variable */
56static DEFINE_MUTEX(opened_mutex); 38static DEFINE_MUTEX(opened_mutex);
57 39
58struct atmel_ac97c_dma {
59 struct dma_chan *rx_chan;
60 struct dma_chan *tx_chan;
61};
62
63struct atmel_ac97c { 40struct atmel_ac97c {
64 struct clk *pclk; 41 struct clk *pclk;
65 struct platform_device *pdev; 42 struct platform_device *pdev;
66 struct atmel_ac97c_dma dma;
67 43
68 struct snd_pcm_substream *playback_substream; 44 struct snd_pcm_substream *playback_substream;
69 struct snd_pcm_substream *capture_substream; 45 struct snd_pcm_substream *capture_substream;
@@ -74,7 +50,6 @@ struct atmel_ac97c {
74 50
75 u64 cur_format; 51 u64 cur_format;
76 unsigned int cur_rate; 52 unsigned int cur_rate;
77 unsigned long flags;
78 int playback_period, capture_period; 53 int playback_period, capture_period;
79 /* Serialize access to opened variable */ 54 /* Serialize access to opened variable */
80 spinlock_t lock; 55 spinlock_t lock;
@@ -91,65 +66,6 @@ struct atmel_ac97c {
91#define ac97c_readl(chip, reg) \ 66#define ac97c_readl(chip, reg) \
92 __raw_readl((chip)->regs + AC97C_##reg) 67 __raw_readl((chip)->regs + AC97C_##reg)
93 68
94/* This function is called by the DMA driver. */
95static void atmel_ac97c_dma_playback_period_done(void *arg)
96{
97 struct atmel_ac97c *chip = arg;
98 snd_pcm_period_elapsed(chip->playback_substream);
99}
100
101static void atmel_ac97c_dma_capture_period_done(void *arg)
102{
103 struct atmel_ac97c *chip = arg;
104 snd_pcm_period_elapsed(chip->capture_substream);
105}
106
107static int atmel_ac97c_prepare_dma(struct atmel_ac97c *chip,
108 struct snd_pcm_substream *substream,
109 enum dma_transfer_direction direction)
110{
111 struct dma_chan *chan;
112 struct dw_cyclic_desc *cdesc;
113 struct snd_pcm_runtime *runtime = substream->runtime;
114 unsigned long buffer_len, period_len;
115
116 /*
117 * We don't do DMA on "complex" transfers, i.e. with
118 * non-halfword-aligned buffers or lengths.
119 */
120 if (runtime->dma_addr & 1 || runtime->buffer_size & 1) {
121 dev_dbg(&chip->pdev->dev, "too complex transfer\n");
122 return -EINVAL;
123 }
124
125 if (direction == DMA_MEM_TO_DEV)
126 chan = chip->dma.tx_chan;
127 else
128 chan = chip->dma.rx_chan;
129
130 buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
131 period_len = frames_to_bytes(runtime, runtime->period_size);
132
133 cdesc = dw_dma_cyclic_prep(chan, runtime->dma_addr, buffer_len,
134 period_len, direction);
135 if (IS_ERR(cdesc)) {
136 dev_dbg(&chip->pdev->dev, "could not prepare cyclic DMA\n");
137 return PTR_ERR(cdesc);
138 }
139
140 if (direction == DMA_MEM_TO_DEV) {
141 cdesc->period_callback = atmel_ac97c_dma_playback_period_done;
142 set_bit(DMA_TX_READY, &chip->flags);
143 } else {
144 cdesc->period_callback = atmel_ac97c_dma_capture_period_done;
145 set_bit(DMA_RX_READY, &chip->flags);
146 }
147
148 cdesc->period_callback_param = chip;
149
150 return 0;
151}
152
153static struct snd_pcm_hardware atmel_ac97c_hw = { 69static struct snd_pcm_hardware atmel_ac97c_hw = {
154 .info = (SNDRV_PCM_INFO_MMAP 70 .info = (SNDRV_PCM_INFO_MMAP
155 | SNDRV_PCM_INFO_MMAP_VALID 71 | SNDRV_PCM_INFO_MMAP_VALID
@@ -254,13 +170,7 @@ static int atmel_ac97c_playback_hw_params(struct snd_pcm_substream *substream,
254 params_buffer_bytes(hw_params)); 170 params_buffer_bytes(hw_params));
255 if (retval < 0) 171 if (retval < 0)
256 return retval; 172 return retval;
257 /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */ 173
258 if (cpu_is_at32ap7000()) {
259 /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
260 if (retval == 1)
261 if (test_and_clear_bit(DMA_TX_READY, &chip->flags))
262 dw_dma_cyclic_free(chip->dma.tx_chan);
263 }
264 /* Set restrictions to params. */ 174 /* Set restrictions to params. */
265 mutex_lock(&opened_mutex); 175 mutex_lock(&opened_mutex);
266 chip->cur_rate = params_rate(hw_params); 176 chip->cur_rate = params_rate(hw_params);
@@ -280,10 +190,6 @@ static int atmel_ac97c_capture_hw_params(struct snd_pcm_substream *substream,
280 params_buffer_bytes(hw_params)); 190 params_buffer_bytes(hw_params));
281 if (retval < 0) 191 if (retval < 0)
282 return retval; 192 return retval;
283 /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
284 if (cpu_is_at32ap7000() && retval == 1)
285 if (test_and_clear_bit(DMA_RX_READY, &chip->flags))
286 dw_dma_cyclic_free(chip->dma.rx_chan);
287 193
288 /* Set restrictions to params. */ 194 /* Set restrictions to params. */
289 mutex_lock(&opened_mutex); 195 mutex_lock(&opened_mutex);
@@ -294,26 +200,6 @@ static int atmel_ac97c_capture_hw_params(struct snd_pcm_substream *substream,
294 return retval; 200 return retval;
295} 201}
296 202
297static int atmel_ac97c_playback_hw_free(struct snd_pcm_substream *substream)
298{
299 struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
300 if (cpu_is_at32ap7000()) {
301 if (test_and_clear_bit(DMA_TX_READY, &chip->flags))
302 dw_dma_cyclic_free(chip->dma.tx_chan);
303 }
304 return snd_pcm_lib_free_pages(substream);
305}
306
307static int atmel_ac97c_capture_hw_free(struct snd_pcm_substream *substream)
308{
309 struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
310 if (cpu_is_at32ap7000()) {
311 if (test_and_clear_bit(DMA_RX_READY, &chip->flags))
312 dw_dma_cyclic_free(chip->dma.rx_chan);
313 }
314 return snd_pcm_lib_free_pages(substream);
315}
316
317static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream) 203static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream)
318{ 204{
319 struct atmel_ac97c *chip = snd_pcm_substream_chip(substream); 205 struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
@@ -349,8 +235,6 @@ static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream)
349 235
350 switch (runtime->format) { 236 switch (runtime->format) {
351 case SNDRV_PCM_FORMAT_S16_LE: 237 case SNDRV_PCM_FORMAT_S16_LE:
352 if (cpu_is_at32ap7000())
353 word |= AC97C_CMR_CEM_LITTLE;
354 break; 238 break;
355 case SNDRV_PCM_FORMAT_S16_BE: /* fall through */ 239 case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
356 word &= ~(AC97C_CMR_CEM_LITTLE); 240 word &= ~(AC97C_CMR_CEM_LITTLE);
@@ -389,18 +273,11 @@ static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream)
389 dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n", 273 dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
390 runtime->rate); 274 runtime->rate);
391 275
392 if (cpu_is_at32ap7000()) { 276 /* Initialize and start the PDC */
393 if (!test_bit(DMA_TX_READY, &chip->flags)) 277 writel(runtime->dma_addr, chip->regs + ATMEL_PDC_TPR);
394 retval = atmel_ac97c_prepare_dma(chip, substream, 278 writel(block_size / 2, chip->regs + ATMEL_PDC_TCR);
395 DMA_MEM_TO_DEV); 279 writel(runtime->dma_addr + block_size, chip->regs + ATMEL_PDC_TNPR);
396 } else { 280 writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR);
397 /* Initialize and start the PDC */
398 writel(runtime->dma_addr, chip->regs + ATMEL_PDC_TPR);
399 writel(block_size / 2, chip->regs + ATMEL_PDC_TCR);
400 writel(runtime->dma_addr + block_size,
401 chip->regs + ATMEL_PDC_TNPR);
402 writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR);
403 }
404 281
405 return retval; 282 return retval;
406} 283}
@@ -440,8 +317,6 @@ static int atmel_ac97c_capture_prepare(struct snd_pcm_substream *substream)
440 317
441 switch (runtime->format) { 318 switch (runtime->format) {
442 case SNDRV_PCM_FORMAT_S16_LE: 319 case SNDRV_PCM_FORMAT_S16_LE:
443 if (cpu_is_at32ap7000())
444 word |= AC97C_CMR_CEM_LITTLE;
445 break; 320 break;
446 case SNDRV_PCM_FORMAT_S16_BE: /* fall through */ 321 case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
447 word &= ~(AC97C_CMR_CEM_LITTLE); 322 word &= ~(AC97C_CMR_CEM_LITTLE);
@@ -480,18 +355,11 @@ static int atmel_ac97c_capture_prepare(struct snd_pcm_substream *substream)
480 dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n", 355 dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
481 runtime->rate); 356 runtime->rate);
482 357
483 if (cpu_is_at32ap7000()) { 358 /* Initialize and start the PDC */
484 if (!test_bit(DMA_RX_READY, &chip->flags)) 359 writel(runtime->dma_addr, chip->regs + ATMEL_PDC_RPR);
485 retval = atmel_ac97c_prepare_dma(chip, substream, 360 writel(block_size / 2, chip->regs + ATMEL_PDC_RCR);
486 DMA_DEV_TO_MEM); 361 writel(runtime->dma_addr + block_size, chip->regs + ATMEL_PDC_RNPR);
487 } else { 362 writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR);
488 /* Initialize and start the PDC */
489 writel(runtime->dma_addr, chip->regs + ATMEL_PDC_RPR);
490 writel(block_size / 2, chip->regs + ATMEL_PDC_RCR);
491 writel(runtime->dma_addr + block_size,
492 chip->regs + ATMEL_PDC_RNPR);
493 writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR);
494 }
495 363
496 return retval; 364 return retval;
497} 365}
@@ -501,7 +369,6 @@ atmel_ac97c_playback_trigger(struct snd_pcm_substream *substream, int cmd)
501{ 369{
502 struct atmel_ac97c *chip = snd_pcm_substream_chip(substream); 370 struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
503 unsigned long camr, ptcr = 0; 371 unsigned long camr, ptcr = 0;
504 int retval = 0;
505 372
506 camr = ac97c_readl(chip, CAMR); 373 camr = ac97c_readl(chip, CAMR);
507 374
@@ -509,35 +376,23 @@ atmel_ac97c_playback_trigger(struct snd_pcm_substream *substream, int cmd)
509 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */ 376 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
510 case SNDRV_PCM_TRIGGER_RESUME: /* fall through */ 377 case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
511 case SNDRV_PCM_TRIGGER_START: 378 case SNDRV_PCM_TRIGGER_START:
512 if (cpu_is_at32ap7000()) { 379 ptcr = ATMEL_PDC_TXTEN;
513 retval = dw_dma_cyclic_start(chip->dma.tx_chan);
514 if (retval)
515 goto out;
516 } else {
517 ptcr = ATMEL_PDC_TXTEN;
518 }
519 camr |= AC97C_CMR_CENA | AC97C_CSR_ENDTX; 380 camr |= AC97C_CMR_CENA | AC97C_CSR_ENDTX;
520 break; 381 break;
521 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */ 382 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
522 case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */ 383 case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
523 case SNDRV_PCM_TRIGGER_STOP: 384 case SNDRV_PCM_TRIGGER_STOP:
524 if (cpu_is_at32ap7000()) 385 ptcr |= ATMEL_PDC_TXTDIS;
525 dw_dma_cyclic_stop(chip->dma.tx_chan);
526 else
527 ptcr |= ATMEL_PDC_TXTDIS;
528 if (chip->opened <= 1) 386 if (chip->opened <= 1)
529 camr &= ~AC97C_CMR_CENA; 387 camr &= ~AC97C_CMR_CENA;
530 break; 388 break;
531 default: 389 default:
532 retval = -EINVAL; 390 return -EINVAL;
533 goto out;
534 } 391 }
535 392
536 ac97c_writel(chip, CAMR, camr); 393 ac97c_writel(chip, CAMR, camr);
537 if (!cpu_is_at32ap7000()) 394 writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
538 writel(ptcr, chip->regs + ATMEL_PDC_PTCR); 395 return 0;
539out:
540 return retval;
541} 396}
542 397
543static int 398static int
@@ -545,7 +400,6 @@ atmel_ac97c_capture_trigger(struct snd_pcm_substream *substream, int cmd)
545{ 400{
546 struct atmel_ac97c *chip = snd_pcm_substream_chip(substream); 401 struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
547 unsigned long camr, ptcr = 0; 402 unsigned long camr, ptcr = 0;
548 int retval = 0;
549 403
550 camr = ac97c_readl(chip, CAMR); 404 camr = ac97c_readl(chip, CAMR);
551 ptcr = readl(chip->regs + ATMEL_PDC_PTSR); 405 ptcr = readl(chip->regs + ATMEL_PDC_PTSR);
@@ -554,35 +408,23 @@ atmel_ac97c_capture_trigger(struct snd_pcm_substream *substream, int cmd)
554 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */ 408 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
555 case SNDRV_PCM_TRIGGER_RESUME: /* fall through */ 409 case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
556 case SNDRV_PCM_TRIGGER_START: 410 case SNDRV_PCM_TRIGGER_START:
557 if (cpu_is_at32ap7000()) { 411 ptcr = ATMEL_PDC_RXTEN;
558 retval = dw_dma_cyclic_start(chip->dma.rx_chan);
559 if (retval)
560 goto out;
561 } else {
562 ptcr = ATMEL_PDC_RXTEN;
563 }
564 camr |= AC97C_CMR_CENA | AC97C_CSR_ENDRX; 412 camr |= AC97C_CMR_CENA | AC97C_CSR_ENDRX;
565 break; 413 break;
566 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */ 414 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
567 case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */ 415 case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
568 case SNDRV_PCM_TRIGGER_STOP: 416 case SNDRV_PCM_TRIGGER_STOP:
569 if (cpu_is_at32ap7000()) 417 ptcr |= ATMEL_PDC_RXTDIS;
570 dw_dma_cyclic_stop(chip->dma.rx_chan);
571 else
572 ptcr |= (ATMEL_PDC_RXTDIS);
573 if (chip->opened <= 1) 418 if (chip->opened <= 1)
574 camr &= ~AC97C_CMR_CENA; 419 camr &= ~AC97C_CMR_CENA;
575 break; 420 break;
576 default: 421 default:
577 retval = -EINVAL; 422 return -EINVAL;
578 break;
579 } 423 }
580 424
581 ac97c_writel(chip, CAMR, camr); 425 ac97c_writel(chip, CAMR, camr);
582 if (!cpu_is_at32ap7000()) 426 writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
583 writel(ptcr, chip->regs + ATMEL_PDC_PTCR); 427 return 0;
584out:
585 return retval;
586} 428}
587 429
588static snd_pcm_uframes_t 430static snd_pcm_uframes_t
@@ -593,10 +435,7 @@ atmel_ac97c_playback_pointer(struct snd_pcm_substream *substream)
593 snd_pcm_uframes_t frames; 435 snd_pcm_uframes_t frames;
594 unsigned long bytes; 436 unsigned long bytes;
595 437
596 if (cpu_is_at32ap7000()) 438 bytes = readl(chip->regs + ATMEL_PDC_TPR);
597 bytes = dw_dma_get_src_addr(chip->dma.tx_chan);
598 else
599 bytes = readl(chip->regs + ATMEL_PDC_TPR);
600 bytes -= runtime->dma_addr; 439 bytes -= runtime->dma_addr;
601 440
602 frames = bytes_to_frames(runtime, bytes); 441 frames = bytes_to_frames(runtime, bytes);
@@ -613,10 +452,7 @@ atmel_ac97c_capture_pointer(struct snd_pcm_substream *substream)
613 snd_pcm_uframes_t frames; 452 snd_pcm_uframes_t frames;
614 unsigned long bytes; 453 unsigned long bytes;
615 454
616 if (cpu_is_at32ap7000()) 455 bytes = readl(chip->regs + ATMEL_PDC_RPR);
617 bytes = dw_dma_get_dst_addr(chip->dma.rx_chan);
618 else
619 bytes = readl(chip->regs + ATMEL_PDC_RPR);
620 bytes -= runtime->dma_addr; 456 bytes -= runtime->dma_addr;
621 457
622 frames = bytes_to_frames(runtime, bytes); 458 frames = bytes_to_frames(runtime, bytes);
@@ -630,7 +466,7 @@ static struct snd_pcm_ops atmel_ac97_playback_ops = {
630 .close = atmel_ac97c_playback_close, 466 .close = atmel_ac97c_playback_close,
631 .ioctl = snd_pcm_lib_ioctl, 467 .ioctl = snd_pcm_lib_ioctl,
632 .hw_params = atmel_ac97c_playback_hw_params, 468 .hw_params = atmel_ac97c_playback_hw_params,
633 .hw_free = atmel_ac97c_playback_hw_free, 469 .hw_free = snd_pcm_lib_free_pages,
634 .prepare = atmel_ac97c_playback_prepare, 470 .prepare = atmel_ac97c_playback_prepare,
635 .trigger = atmel_ac97c_playback_trigger, 471 .trigger = atmel_ac97c_playback_trigger,
636 .pointer = atmel_ac97c_playback_pointer, 472 .pointer = atmel_ac97c_playback_pointer,
@@ -641,7 +477,7 @@ static struct snd_pcm_ops atmel_ac97_capture_ops = {
641 .close = atmel_ac97c_capture_close, 477 .close = atmel_ac97c_capture_close,
642 .ioctl = snd_pcm_lib_ioctl, 478 .ioctl = snd_pcm_lib_ioctl,
643 .hw_params = atmel_ac97c_capture_hw_params, 479 .hw_params = atmel_ac97c_capture_hw_params,
644 .hw_free = atmel_ac97c_capture_hw_free, 480 .hw_free = snd_pcm_lib_free_pages,
645 .prepare = atmel_ac97c_capture_prepare, 481 .prepare = atmel_ac97c_capture_prepare,
646 .trigger = atmel_ac97c_capture_trigger, 482 .trigger = atmel_ac97c_capture_trigger,
647 .pointer = atmel_ac97c_capture_pointer, 483 .pointer = atmel_ac97c_capture_pointer,
@@ -666,49 +502,40 @@ static irqreturn_t atmel_ac97c_interrupt(int irq, void *dev)
666 casr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "", 502 casr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "",
667 casr & AC97C_CSR_TXRDY ? " TXRDY" : "", 503 casr & AC97C_CSR_TXRDY ? " TXRDY" : "",
668 !casr ? " NONE" : ""); 504 !casr ? " NONE" : "");
669 if (!cpu_is_at32ap7000()) { 505 if ((casr & camr) & AC97C_CSR_ENDTX) {
670 if ((casr & camr) & AC97C_CSR_ENDTX) { 506 runtime = chip->playback_substream->runtime;
671 runtime = chip->playback_substream->runtime; 507 block_size = frames_to_bytes(runtime, runtime->period_size);
672 block_size = frames_to_bytes(runtime, 508 chip->playback_period++;
673 runtime->period_size); 509
674 chip->playback_period++; 510 if (chip->playback_period == runtime->periods)
675 511 chip->playback_period = 0;
676 if (chip->playback_period == runtime->periods) 512 next_period = chip->playback_period + 1;
677 chip->playback_period = 0; 513 if (next_period == runtime->periods)
678 next_period = chip->playback_period + 1; 514 next_period = 0;
679 if (next_period == runtime->periods) 515
680 next_period = 0; 516 offset = block_size * next_period;
681 517
682 offset = block_size * next_period; 518 writel(runtime->dma_addr + offset, chip->regs + ATMEL_PDC_TNPR);
683 519 writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR);
684 writel(runtime->dma_addr + offset, 520
685 chip->regs + ATMEL_PDC_TNPR); 521 snd_pcm_period_elapsed(chip->playback_substream);
686 writel(block_size / 2, 522 }
687 chip->regs + ATMEL_PDC_TNCR); 523 if ((casr & camr) & AC97C_CSR_ENDRX) {
688 524 runtime = chip->capture_substream->runtime;
689 snd_pcm_period_elapsed( 525 block_size = frames_to_bytes(runtime, runtime->period_size);
690 chip->playback_substream); 526 chip->capture_period++;
691 } 527
692 if ((casr & camr) & AC97C_CSR_ENDRX) { 528 if (chip->capture_period == runtime->periods)
693 runtime = chip->capture_substream->runtime; 529 chip->capture_period = 0;
694 block_size = frames_to_bytes(runtime, 530 next_period = chip->capture_period + 1;
695 runtime->period_size); 531 if (next_period == runtime->periods)
696 chip->capture_period++; 532 next_period = 0;
697 533
698 if (chip->capture_period == runtime->periods) 534 offset = block_size * next_period;
699 chip->capture_period = 0; 535
700 next_period = chip->capture_period + 1; 536 writel(runtime->dma_addr + offset, chip->regs + ATMEL_PDC_RNPR);
701 if (next_period == runtime->periods) 537 writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR);
702 next_period = 0; 538 snd_pcm_period_elapsed(chip->capture_substream);
703
704 offset = block_size * next_period;
705
706 writel(runtime->dma_addr + offset,
707 chip->regs + ATMEL_PDC_RNPR);
708 writel(block_size / 2,
709 chip->regs + ATMEL_PDC_RNCR);
710 snd_pcm_period_elapsed(chip->capture_substream);
711 }
712 } 539 }
713 retval = IRQ_HANDLED; 540 retval = IRQ_HANDLED;
714 } 541 }
@@ -763,29 +590,20 @@ static int atmel_ac97c_pcm_new(struct atmel_ac97c *chip)
763{ 590{
764 struct snd_pcm *pcm; 591 struct snd_pcm *pcm;
765 struct snd_pcm_hardware hw = atmel_ac97c_hw; 592 struct snd_pcm_hardware hw = atmel_ac97c_hw;
766 int capture, playback, retval, err; 593 int retval;
767 594
768 capture = test_bit(DMA_RX_CHAN_PRESENT, &chip->flags); 595 retval = snd_ac97_pcm_assign(chip->ac97_bus,
769 playback = test_bit(DMA_TX_CHAN_PRESENT, &chip->flags); 596 ARRAY_SIZE(at91_ac97_pcm_defs),
597 at91_ac97_pcm_defs);
598 if (retval)
599 return retval;
770 600
771 if (!cpu_is_at32ap7000()) { 601 retval = snd_pcm_new(chip->card, chip->card->shortname, 0, 1, 1, &pcm);
772 err = snd_ac97_pcm_assign(chip->ac97_bus,
773 ARRAY_SIZE(at91_ac97_pcm_defs),
774 at91_ac97_pcm_defs);
775 if (err)
776 return err;
777 }
778 retval = snd_pcm_new(chip->card, chip->card->shortname,
779 0, playback, capture, &pcm);
780 if (retval) 602 if (retval)
781 return retval; 603 return retval;
782 604
783 if (capture) 605 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &atmel_ac97_capture_ops);
784 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 606 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &atmel_ac97_playback_ops);
785 &atmel_ac97_capture_ops);
786 if (playback)
787 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
788 &atmel_ac97_playback_ops);
789 607
790 retval = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 608 retval = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
791 &chip->pdev->dev, hw.periods_min * hw.period_bytes_min, 609 &chip->pdev->dev, hw.periods_min * hw.period_bytes_min,
@@ -875,17 +693,6 @@ timed_out:
875 return 0xffff; 693 return 0xffff;
876} 694}
877 695
878static bool filter(struct dma_chan *chan, void *slave)
879{
880 struct dw_dma_slave *dws = slave;
881
882 if (dws->dma_dev == chan->device->dev) {
883 chan->private = dws;
884 return true;
885 } else
886 return false;
887}
888
889static void atmel_ac97c_reset(struct atmel_ac97c *chip) 696static void atmel_ac97c_reset(struct atmel_ac97c *chip)
890{ 697{
891 ac97c_writel(chip, MR, 0); 698 ac97c_writel(chip, MR, 0);
@@ -971,12 +778,7 @@ static int atmel_ac97c_probe(struct platform_device *pdev)
971 return -ENXIO; 778 return -ENXIO;
972 } 779 }
973 780
974 if (cpu_is_at32ap7000()) { 781 pclk = clk_get(&pdev->dev, "ac97_clk");
975 pclk = clk_get(&pdev->dev, "pclk");
976 } else {
977 pclk = clk_get(&pdev->dev, "ac97_clk");
978 }
979
980 if (IS_ERR(pclk)) { 782 if (IS_ERR(pclk)) {
981 dev_dbg(&pdev->dev, "no peripheral clock\n"); 783 dev_dbg(&pdev->dev, "no peripheral clock\n");
982 return PTR_ERR(pclk); 784 return PTR_ERR(pclk);
@@ -1047,88 +849,16 @@ static int atmel_ac97c_probe(struct platform_device *pdev)
1047 goto err_ac97_bus; 849 goto err_ac97_bus;
1048 } 850 }
1049 851
1050 if (cpu_is_at32ap7000()) {
1051 if (pdata->rx_dws.dma_dev) {
1052 dma_cap_mask_t mask;
1053
1054 dma_cap_zero(mask);
1055 dma_cap_set(DMA_SLAVE, mask);
1056
1057 chip->dma.rx_chan = dma_request_channel(mask, filter,
1058 &pdata->rx_dws);
1059 if (chip->dma.rx_chan) {
1060 struct dma_slave_config dma_conf = {
1061 .src_addr = regs->start + AC97C_CARHR +
1062 2,
1063 .src_addr_width =
1064 DMA_SLAVE_BUSWIDTH_2_BYTES,
1065 .src_maxburst = 1,
1066 .dst_maxburst = 1,
1067 .direction = DMA_DEV_TO_MEM,
1068 .device_fc = false,
1069 };
1070
1071 dmaengine_slave_config(chip->dma.rx_chan,
1072 &dma_conf);
1073 }
1074
1075 dev_info(&chip->pdev->dev, "using %s for DMA RX\n",
1076 dev_name(&chip->dma.rx_chan->dev->device));
1077 set_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
1078 }
1079
1080 if (pdata->tx_dws.dma_dev) {
1081 dma_cap_mask_t mask;
1082
1083 dma_cap_zero(mask);
1084 dma_cap_set(DMA_SLAVE, mask);
1085
1086 chip->dma.tx_chan = dma_request_channel(mask, filter,
1087 &pdata->tx_dws);
1088 if (chip->dma.tx_chan) {
1089 struct dma_slave_config dma_conf = {
1090 .dst_addr = regs->start + AC97C_CATHR +
1091 2,
1092 .dst_addr_width =
1093 DMA_SLAVE_BUSWIDTH_2_BYTES,
1094 .src_maxburst = 1,
1095 .dst_maxburst = 1,
1096 .direction = DMA_MEM_TO_DEV,
1097 .device_fc = false,
1098 };
1099
1100 dmaengine_slave_config(chip->dma.tx_chan,
1101 &dma_conf);
1102 }
1103
1104 dev_info(&chip->pdev->dev, "using %s for DMA TX\n",
1105 dev_name(&chip->dma.tx_chan->dev->device));
1106 set_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
1107 }
1108
1109 if (!test_bit(DMA_RX_CHAN_PRESENT, &chip->flags) &&
1110 !test_bit(DMA_TX_CHAN_PRESENT, &chip->flags)) {
1111 dev_dbg(&pdev->dev, "DMA not available\n");
1112 retval = -ENODEV;
1113 goto err_dma;
1114 }
1115 } else {
1116 /* Just pretend that we have DMA channel(for at91 i is actually
1117 * the PDC) */
1118 set_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
1119 set_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
1120 }
1121
1122 retval = atmel_ac97c_pcm_new(chip); 852 retval = atmel_ac97c_pcm_new(chip);
1123 if (retval) { 853 if (retval) {
1124 dev_dbg(&pdev->dev, "could not register ac97 pcm device\n"); 854 dev_dbg(&pdev->dev, "could not register ac97 pcm device\n");
1125 goto err_dma; 855 goto err_ac97_bus;
1126 } 856 }
1127 857
1128 retval = snd_card_register(card); 858 retval = snd_card_register(card);
1129 if (retval) { 859 if (retval) {
1130 dev_dbg(&pdev->dev, "could not register sound card\n"); 860 dev_dbg(&pdev->dev, "could not register sound card\n");
1131 goto err_dma; 861 goto err_ac97_bus;
1132 } 862 }
1133 863
1134 platform_set_drvdata(pdev, card); 864 platform_set_drvdata(pdev, card);
@@ -1138,17 +868,6 @@ static int atmel_ac97c_probe(struct platform_device *pdev)
1138 868
1139 return 0; 869 return 0;
1140 870
1141err_dma:
1142 if (cpu_is_at32ap7000()) {
1143 if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags))
1144 dma_release_channel(chip->dma.rx_chan);
1145 if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags))
1146 dma_release_channel(chip->dma.tx_chan);
1147 clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
1148 clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
1149 chip->dma.rx_chan = NULL;
1150 chip->dma.tx_chan = NULL;
1151 }
1152err_ac97_bus: 871err_ac97_bus:
1153 if (gpio_is_valid(chip->reset_pin)) 872 if (gpio_is_valid(chip->reset_pin))
1154 gpio_free(chip->reset_pin); 873 gpio_free(chip->reset_pin);
@@ -1170,14 +889,7 @@ static int atmel_ac97c_suspend(struct device *pdev)
1170 struct snd_card *card = dev_get_drvdata(pdev); 889 struct snd_card *card = dev_get_drvdata(pdev);
1171 struct atmel_ac97c *chip = card->private_data; 890 struct atmel_ac97c *chip = card->private_data;
1172 891
1173 if (cpu_is_at32ap7000()) {
1174 if (test_bit(DMA_RX_READY, &chip->flags))
1175 dw_dma_cyclic_stop(chip->dma.rx_chan);
1176 if (test_bit(DMA_TX_READY, &chip->flags))
1177 dw_dma_cyclic_stop(chip->dma.tx_chan);
1178 }
1179 clk_disable_unprepare(chip->pclk); 892 clk_disable_unprepare(chip->pclk);
1180
1181 return 0; 893 return 0;
1182} 894}
1183 895
@@ -1187,12 +899,6 @@ static int atmel_ac97c_resume(struct device *pdev)
1187 struct atmel_ac97c *chip = card->private_data; 899 struct atmel_ac97c *chip = card->private_data;
1188 900
1189 clk_prepare_enable(chip->pclk); 901 clk_prepare_enable(chip->pclk);
1190 if (cpu_is_at32ap7000()) {
1191 if (test_bit(DMA_RX_READY, &chip->flags))
1192 dw_dma_cyclic_start(chip->dma.rx_chan);
1193 if (test_bit(DMA_TX_READY, &chip->flags))
1194 dw_dma_cyclic_start(chip->dma.tx_chan);
1195 }
1196 return 0; 902 return 0;
1197} 903}
1198 904
@@ -1219,17 +925,6 @@ static int atmel_ac97c_remove(struct platform_device *pdev)
1219 iounmap(chip->regs); 925 iounmap(chip->regs);
1220 free_irq(chip->irq, chip); 926 free_irq(chip->irq, chip);
1221 927
1222 if (cpu_is_at32ap7000()) {
1223 if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags))
1224 dma_release_channel(chip->dma.rx_chan);
1225 if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags))
1226 dma_release_channel(chip->dma.tx_chan);
1227 clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
1228 clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
1229 chip->dma.rx_chan = NULL;
1230 chip->dma.tx_chan = NULL;
1231 }
1232
1233 snd_card_free(card); 928 snd_card_free(card);
1234 929
1235 return 0; 930 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-01 12:08:54 -0400