Merge tag 'pinctrl-v4.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "A bunch of pin control fixes for v4.10 that didn't get sent off until
  now, sorry for the delay.

  It's only driver fixes:

   - A bunch of fixes to the Intel drivers: broxton, baytrail. Bugs
     related to register offsets, IRQ, debounce functionality.

   - Fix a conflict amongst UART settings on the meson.

   - Fix the ethernet setting on the Uniphier.

   - A compilation warning squelched"

* tag 'pinctrl-v4.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: uniphier: fix Ethernet (RMII) pin-mux setting for LD20
  pinctrl: meson: fix uart_ao_b for GXBB and GXL/GXM
  pinctrl: amd: avoid maybe-uninitalized warning
  pinctrl: baytrail: Do not add all GPIOs to IRQ domain
  pinctrl: baytrail: Rectify debounce support
  pinctrl: intel: Set pin direction properly
  pinctrl: broxton: Use correct PADCFGLOCK offset

7 files changed, 54 insertions, 35 deletions

diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index 37300634b7d2..c123488266ce 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -1092,6 +1092,7 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
         enum pin_config_param param = pinconf_to_config_param(*config);
         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
+        void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
         unsigned long flags;
         u32 conf, pull, val, debounce;
         u16 arg = 0;
@@ -1128,7 +1129,7 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
                         return -EINVAL;
 
                 raw_spin_lock_irqsave(&vg->lock, flags);
-                debounce = readl(byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG));
+                debounce = readl(db_reg);
                 raw_spin_unlock_irqrestore(&vg->lock, flags);
 
                 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
@@ -1176,6 +1177,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
         unsigned int param, arg;
         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
+        void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
         unsigned long flags;
         u32 conf, val, debounce;
         int i, ret = 0;
@@ -1238,36 +1240,40 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
 
                         break;
                 case PIN_CONFIG_INPUT_DEBOUNCE:
-                        debounce = readl(byt_gpio_reg(vg, offset,
-                                                      BYT_DEBOUNCE_REG));
-                        conf &= ~BYT_DEBOUNCE_PULSE_MASK;
+                        debounce = readl(db_reg);
+                        debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
 
                         switch (arg) {
+                        case 0:
+                                conf &= BYT_DEBOUNCE_EN;
+                                break;
                         case 375:
-                                conf |= BYT_DEBOUNCE_PULSE_375US;
+                                debounce |= BYT_DEBOUNCE_PULSE_375US;
                                 break;
                         case 750:
-                                conf |= BYT_DEBOUNCE_PULSE_750US;
+                                debounce |= BYT_DEBOUNCE_PULSE_750US;
                                 break;
                         case 1500:
-                                conf |= BYT_DEBOUNCE_PULSE_1500US;
+                                debounce |= BYT_DEBOUNCE_PULSE_1500US;
                                 break;
                         case 3000:
-                                conf |= BYT_DEBOUNCE_PULSE_3MS;
+                                debounce |= BYT_DEBOUNCE_PULSE_3MS;
                                 break;
                         case 6000:
-                                conf |= BYT_DEBOUNCE_PULSE_6MS;
+                                debounce |= BYT_DEBOUNCE_PULSE_6MS;
                                 break;
                         case 12000:
-                                conf |= BYT_DEBOUNCE_PULSE_12MS;
+                                debounce |= BYT_DEBOUNCE_PULSE_12MS;
                                 break;
                         case 24000:
-                                conf |= BYT_DEBOUNCE_PULSE_24MS;
+                                debounce |= BYT_DEBOUNCE_PULSE_24MS;
                                 break;
                         default:
                                 ret = -EINVAL;
                         }
 
+                        if (!ret)
+                                writel(debounce, db_reg);
                         break;
                 default:
                         ret = -ENOTSUPP;
@@ -1617,6 +1623,8 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
 
 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
 {
+        struct gpio_chip *gc = &vg->chip;
+        struct device *dev = &vg->pdev->dev;
         void __iomem *reg;
         u32 base, value;
         int i;
@@ -1638,10 +1646,12 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
                 }
 
                 value = readl(reg);
-                if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
-                    !(value & BYT_DIRECT_IRQ_EN)) {
+                if (value & BYT_DIRECT_IRQ_EN) {
+                        clear_bit(i, gc->irq_valid_mask);
+                        dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
+                } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
                         byt_gpio_clear_triggering(vg, i);
-                        dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
+                        dev_dbg(dev, "disabling GPIO %d\n", i);
                 }
         }
 
@@ -1680,6 +1690,7 @@ static int byt_gpio_probe(struct byt_gpio *vg)
         gc->can_sleep   = false;
         gc->parent      = &vg->pdev->dev;
         gc->ngpio       = vg->soc_data->npins;
+        gc->irq_need_valid_mask = true;
 
 #ifdef CONFIG_PM_SLEEP
         vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c
index 59cb7a6fc5be..901b356b09d7 100644
--- a/drivers/pinctrl/intel/pinctrl-broxton.c
+++ b/drivers/pinctrl/intel/pinctrl-broxton.c
@@ -19,7 +19,7 @@
 
 #define BXT_PAD_OWN     0x020
 #define BXT_HOSTSW_OWN  0x080
-#define BXT_PADCFGLOCK  0x090
+#define BXT_PADCFGLOCK  0x060
 #define BXT_GPI_IE      0x110
 
 #define BXT_COMMUNITY(s, e)                             \
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 1e139672f1af..6df35dcb29ae 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -353,6 +353,21 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
         return 0;
 }
 
+static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
+{
+        u32 value;
+
+        value = readl(padcfg0);
+        if (input) {
+                value &= ~PADCFG0_GPIORXDIS;
+                value |= PADCFG0_GPIOTXDIS;
+        } else {
+                value &= ~PADCFG0_GPIOTXDIS;
+                value |= PADCFG0_GPIORXDIS;
+        }
+        writel(value, padcfg0);
+}
+
 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
                                      struct pinctrl_gpio_range *range,
                                      unsigned pin)
@@ -375,11 +390,11 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
         /* Disable SCI/SMI/NMI generation */
         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
-        /* Disable TX buffer and enable RX (this will be input) */
-        value &= ~PADCFG0_GPIORXDIS;
-        value |= PADCFG0_GPIOTXDIS;
         writel(value, padcfg0);
 
+        /* Disable TX buffer and enable RX (this will be input) */
+        __intel_gpio_set_direction(padcfg0, true);
+
         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 
         return 0;
@@ -392,18 +407,11 @@ static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
         void __iomem *padcfg0;
         unsigned long flags;
-        u32 value;
 
         raw_spin_lock_irqsave(&pctrl->lock, flags);
 
         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
-
-        value = readl(padcfg0);
-        if (input)
-                value |= PADCFG0_GPIOTXDIS;
-        else
-                value &= ~PADCFG0_GPIOTXDIS;
-        writel(value, padcfg0);
+        __intel_gpio_set_direction(padcfg0, input);
 
         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index c3928aa3fefa..e0bca4df2a2f 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -253,9 +253,8 @@ static const unsigned int uart_tx_ao_a_pins[]	= { PIN(GPIOAO_0, 0) };
 static const unsigned int uart_rx_ao_a_pins[]   = { PIN(GPIOAO_1, 0) };
 static const unsigned int uart_cts_ao_a_pins[]  = { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_a_pins[]  = { PIN(GPIOAO_3, 0) };
-static const unsigned int uart_tx_ao_b_pins[]   = { PIN(GPIOAO_0, 0) };
-static const unsigned int uart_rx_ao_b_pins[]   = { PIN(GPIOAO_1, 0),
-                                                    PIN(GPIOAO_5, 0) };
+static const unsigned int uart_tx_ao_b_pins[]   = { PIN(GPIOAO_4, 0) };
+static const unsigned int uart_rx_ao_b_pins[]   = { PIN(GPIOAO_5, 0) };
 static const unsigned int uart_cts_ao_b_pins[]  = { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_b_pins[]  = { PIN(GPIOAO_3, 0) };
 
@@ -498,7 +497,7 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
         GPIO_GROUP(GPIOAO_13, 0),
 
         /* bank AO */
-        GROUP(uart_tx_ao_b,     0,      26),
+        GROUP(uart_tx_ao_b,     0,      24),
         GROUP(uart_rx_ao_b,     0,      25),
         GROUP(uart_tx_ao_a,     0,      12),
         GROUP(uart_rx_ao_a,     0,      11),
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index 25694f7094c7..b69743b07a1d 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -214,9 +214,8 @@ static const unsigned int uart_tx_ao_a_pins[]	= { PIN(GPIOAO_0, 0) };
 static const unsigned int uart_rx_ao_a_pins[]   = { PIN(GPIOAO_1, 0) };
 static const unsigned int uart_cts_ao_a_pins[]  = { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_a_pins[]  = { PIN(GPIOAO_3, 0) };
-static const unsigned int uart_tx_ao_b_pins[]   = { PIN(GPIOAO_0, 0) };
-static const unsigned int uart_rx_ao_b_pins[]   = { PIN(GPIOAO_1, 0),
-                                                    PIN(GPIOAO_5, 0) };
+static const unsigned int uart_tx_ao_b_pins[]   = { PIN(GPIOAO_4, 0) };
+static const unsigned int uart_rx_ao_b_pins[]   = { PIN(GPIOAO_5, 0) };
 static const unsigned int uart_cts_ao_b_pins[]  = { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_b_pins[]  = { PIN(GPIOAO_3, 0) };
 
@@ -409,7 +408,7 @@ static struct meson_pmx_group meson_gxl_aobus_groups[] = {
         GPIO_GROUP(GPIOAO_9, 0),
 
         /* bank AO */
-        GROUP(uart_tx_ao_b,     0,      26),
+        GROUP(uart_tx_ao_b,     0,      24),
         GROUP(uart_rx_ao_b,     0,      25),
         GROUP(uart_tx_ao_a,     0,      12),
         GROUP(uart_rx_ao_a,     0,      11),
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index c9a146948192..537b52055756 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -202,6 +202,8 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
                         i = 128;
                         pin_num = AMD_GPIO_PINS_BANK2 + i;
                         break;
+                default:
+                        return;
                 }
 
                 for (; i < pin_num; i++) {
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index aa8bd9794683..96686336e3a3 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -561,7 +561,7 @@ static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                                           0, 0, 0, 0};
 static const unsigned ether_rmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 39,
                                            41, 42, 45};
-static const int ether_rmii_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
 static const unsigned i2c0_pins[] = {63, 64};
 static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {65, 66};