Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
 "Here are the latest bug fixes for ARM SoCs, mostly addressing recent
  regressions.  Changes are across several platforms, so I'm listing
  every change separately here.

  Regressions since 4.5:

   - A correction of the psci firmware DT binding, to prevent users from
     relying on unintended semantics

   - Actually getting the newly merged clock driver for some OMAP
     platforms to work

   - A revert of patches for the Qualcomm BAM, these need to be reworked
     for 4.7 to avoid breaking boards other than the one they were
     intended for

   - A correction for the I2C device nodes on the Socionext Uniphier
     platform

   - i.MX SDHCI was broken for non-DT platforms due to a change with the
     setting of the DMA mask

   - A revert of a patch that accidentally added a nonexisting clock on
     the Rensas "Porter" board

   - A couple of OMAP fixes that are all related to suspend after the
     power domain changes for dra7

   - On Mediatek, revert part of the power domain initialization changes
     that broke mt8173-evb

  Fixes for older bugs:

   - Workaround for an "external abort" in the omap34xx suspend/resume
     code.

   - The USB1/eSATA should not be listed as an excon device on
     am57xx-beagle-x15 (broken since v4.0)

   - A v4.5 regression in the TI AM33xx and AM43XX DT specifying
     incorrect DMA request lines for the GPMC

   - The jiffies calibration on Renesas platforms was incorrect for some
     modern CPU cores.

   - A hardware errata woraround for clockdomains on TI DRA7"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  drivers: firmware: psci: unify enable-method binding on ARM {64,32}-bit systems
  arm64: dts: uniphier: fix I2C nodes of PH1-LD20
  ARM: shmobile: timer: Fix preset_lpj leading to too short delays
  Revert "ARM: dts: porter: Enable SCIF_CLK frequency and pins"
  ARM: dts: r8a7791: Don't disable referenced optional clocks
  Revert "ARM: OMAP: Catch callers of revision information prior to it being populated"
  ARM: OMAP3: Fix external abort on 36xx waking from off mode idle
  ARM: dts: am57xx-beagle-x15: remove extcon_usb1
  ARM: dts: am437x: Fix GPMC dma properties
  ARM: dts: am33xx: Fix GPMC dma properties
  Revert "soc: mediatek: SCPSYS: Fix double enabling of regulators"
  ARM: mach-imx: sdhci-esdhc-imx: initialize DMA mask
  ARM: DRA7: clockdomain: Implement timer workaround for errata i874
  ARM: OMAP: Catch callers of revision information prior to it being populated
  ARM: dts: dra7: Correct clock tree for sys_32k_ck
  ARM: OMAP: DRA7: Provide proper class to omap2_set_globals_tap
  ARM: OMAP: DRA7: wakeupgen: Skip SAR save for wakeupgen
  Revert "dts: msm8974: Add dma channels for blsp2_i2c1 node"
  Revert "dts: msm8974: Add blsp2_bam dma node"
  ARM: dts: Add clocks for dm814x ADPLL

21 files changed, 310 insertions, 135 deletions

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index ccc62f145306..3f0cbbb8395f 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -192,7 +192,6 @@ nodes to be present and contain the properties described below.
                           can be one of:
                             "allwinner,sun6i-a31"
                             "allwinner,sun8i-a23"
-                            "arm,psci"
                             "arm,realview-smp"
                             "brcm,bcm-nsp-smp"
                             "brcm,brahma-b15"
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 55ca9c7dcf6a..0467846b4cc3 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -860,7 +860,7 @@
                         ti,no-idle-on-init;
                         reg = <0x50000000 0x2000>;
                         interrupts = <100>;
-                        dmas = <&edma 52>;
+                        dmas = <&edma 52 0>;
                         dma-names = "rxtx";
                         gpmc,num-cs = <7>;
                         gpmc,num-waitpins = <2>;
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 344b861a55a5..ba580a9da390 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -884,7 +884,7 @@
                 gpmc: gpmc@50000000 {
                         compatible = "ti,am3352-gpmc";
                         ti,hwmods = "gpmc";
-                        dmas = <&edma 52>;
+                        dmas = <&edma 52 0>;
                         dma-names = "rxtx";
                         clocks = <&l3s_gclk>;
                         clock-names = "fck";
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 0a5fc5d02ce2..4168eb9dd369 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -99,13 +99,6 @@
                 #cooling-cells = <2>;
         };
 
-        extcon_usb1: extcon_usb1 {
-                compatible = "linux,extcon-usb-gpio";
-                id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&extcon_usb1_pins>;
-        };
-
         hdmi0: connector {
                 compatible = "hdmi-connector";
                 label = "hdmi";
@@ -349,12 +342,6 @@
                 >;
         };
 
-        extcon_usb1_pins: extcon_usb1_pins {
-                pinctrl-single,pins = <
-                        DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
-                >;
-        };
-
         tpd12s015_pins: pinmux_tpd12s015_pins {
                 pinctrl-single,pins = <
                         DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14)              /* gpio7_10 CT_CP_HPD */
@@ -706,10 +693,6 @@
         pinctrl-0 = <&usb1_pins>;
 };
 
-&omap_dwc3_1 {
-        extcon = <&extcon_usb1>;
-};
-
 &omap_dwc3_2 {
         extcon = <&extcon_usb2>;
 };
diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi
index e0ea6a93a22e..792a64ee0df7 100644
--- a/arch/arm/boot/dts/dm814x-clocks.dtsi
+++ b/arch/arm/boot/dts/dm814x-clocks.dtsi
@@ -4,6 +4,157 @@
  * published by the Free Software Foundation.
  */
 
+&pllss {
+        /*
+         * See TRM "2.6.10 Connected outputso DPLLS" and
+         * "2.6.11 Connected Outputs of DPLLJ". Only clkout is
+         * connected except for hdmi and usb.
+         */
+        adpll_mpu_ck: adpll@40 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-s-clock";
+                reg = <0x40 0x40>;
+                clocks = <&devosc_ck &devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow", "clkinphif";
+                clock-output-names = "481c5040.adpll.dcoclkldo",
+                                     "481c5040.adpll.clkout",
+                                     "481c5040.adpll.clkoutx2",
+                                     "481c5040.adpll.clkouthif";
+        };
+
+        adpll_dsp_ck: adpll@80 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0x80 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c5080.adpll.dcoclkldo",
+                                     "481c5080.adpll.clkout",
+                                     "481c5080.adpll.clkoutldo";
+        };
+
+        adpll_sgx_ck: adpll@b0 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0xb0 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c50b0.adpll.dcoclkldo",
+                                     "481c50b0.adpll.clkout",
+                                     "481c50b0.adpll.clkoutldo";
+        };
+
+        adpll_hdvic_ck: adpll@e0 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0xe0 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c50e0.adpll.dcoclkldo",
+                                     "481c50e0.adpll.clkout",
+                                     "481c50e0.adpll.clkoutldo";
+        };
+
+        adpll_l3_ck: adpll@110 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0x110 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c5110.adpll.dcoclkldo",
+                                     "481c5110.adpll.clkout",
+                                     "481c5110.adpll.clkoutldo";
+        };
+
+        adpll_isp_ck: adpll@140 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0x140 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c5140.adpll.dcoclkldo",
+                                     "481c5140.adpll.clkout",
+                                     "481c5140.adpll.clkoutldo";
+        };
+
+        adpll_dss_ck: adpll@170 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0x170 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c5170.adpll.dcoclkldo",
+                                     "481c5170.adpll.clkout",
+                                     "481c5170.adpll.clkoutldo";
+        };
+
+        adpll_video0_ck: adpll@1a0 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0x1a0 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c51a0.adpll.dcoclkldo",
+                                     "481c51a0.adpll.clkout",
+                                     "481c51a0.adpll.clkoutldo";
+        };
+
+        adpll_video1_ck: adpll@1d0 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0x1d0 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c51d0.adpll.dcoclkldo",
+                                     "481c51d0.adpll.clkout",
+                                     "481c51d0.adpll.clkoutldo";
+        };
+
+        adpll_hdmi_ck: adpll@200 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0x200 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c5200.adpll.dcoclkldo",
+                                     "481c5200.adpll.clkout",
+                                     "481c5200.adpll.clkoutldo";
+        };
+
+        adpll_audio_ck: adpll@230 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0x230 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c5230.adpll.dcoclkldo",
+                                     "481c5230.adpll.clkout",
+                                     "481c5230.adpll.clkoutldo";
+        };
+
+        adpll_usb_ck: adpll@260 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0x260 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c5260.adpll.dcoclkldo",
+                                     "481c5260.adpll.clkout",
+                                     "481c5260.adpll.clkoutldo";
+        };
+
+        adpll_ddr_ck: adpll@290 {
+                #clock-cells = <1>;
+                compatible = "ti,dm814-adpll-lj-clock";
+                reg = <0x290 0x30>;
+                clocks = <&devosc_ck &devosc_ck>;
+                clock-names = "clkinp", "clkinpulow";
+                clock-output-names = "481c5290.adpll.dcoclkldo",
+                                     "481c5290.adpll.clkout",
+                                     "481c5290.adpll.clkoutldo";
+        };
+};
+
 &pllss_clocks {
         timer1_fck: timer1_fck {
                 #clock-cells = <0>;
@@ -23,6 +174,24 @@
                 reg = <0x2e0>;
         };
 
+        /* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
+        cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&adpll_video0_ck 1
+                          &adpll_video1_ck 1
+                          &adpll_audio_ck 1>;
+                ti,bit-shift = <1>;
+                reg = <0x2e8>;
+        };
+
+        /* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
+        cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <125000000>;
+        };
+
         sysclk18_ck: sysclk18_ck {
                 #clock-cells = <0>;
                 compatible = "ti,mux-clock";
@@ -79,37 +248,6 @@
                 compatible = "fixed-clock";
                 clock-frequency = <1000000000>;
         };
-
-        sysclk4_ck: sysclk4_ck {
-                #clock-cells = <0>;
-                compatible = "fixed-clock";
-                clock-frequency = <222000000>;
-        };
-
-        sysclk6_ck: sysclk6_ck {
-                #clock-cells = <0>;
-                compatible = "fixed-clock";
-                clock-frequency = <100000000>;
-        };
-
-        sysclk10_ck: sysclk10_ck {
-                #clock-cells = <0>;
-                compatible = "fixed-clock";
-                clock-frequency = <48000000>;
-        };
-
-        cpsw_125mhz_gclk: cpsw_125mhz_gclk {
-                #clock-cells = <0>;
-                compatible = "fixed-clock";
-                clock-frequency = <125000000>;
-        };
-
-        cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
-                #clock-cells = <0>;
-                compatible = "fixed-clock";
-                clock-frequency = <250000000>;
-        };
-
 };
 
 &prcm_clocks {
@@ -138,6 +276,49 @@
                 clock-div = <78125>;
         };
 
+        /* L4_HS 220 MHz*/
+        sysclk4_ck: sysclk4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,fixed-factor-clock";
+                clocks = <&adpll_l3_ck 1>;
+                ti,clock-mult = <1>;
+                ti,clock-div = <1>;
+        };
+
+        /* L4_FWCFG */
+        sysclk5_ck: sysclk5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,fixed-factor-clock";
+                clocks = <&adpll_l3_ck 1>;
+                ti,clock-mult = <1>;
+                ti,clock-div = <2>;
+        };
+
+        /* L4_LS 110 MHz */
+        sysclk6_ck: sysclk6_ck {
+                #clock-cells = <0>;
+                compatible = "ti,fixed-factor-clock";
+                clocks = <&adpll_l3_ck 1>;
+                ti,clock-mult = <1>;
+                ti,clock-div = <2>;
+        };
+
+        sysclk8_ck: sysclk8_ck {
+                #clock-cells = <0>;
+                compatible = "ti,fixed-factor-clock";
+                clocks = <&adpll_usb_ck 1>;
+                ti,clock-mult = <1>;
+                ti,clock-div = <1>;
+        };
+
+        sysclk10_ck: sysclk10_ck {
+                compatible = "ti,divider-clock";
+                reg = <0x324>;
+                ti,max-div = <7>;
+                #clock-cells = <0>;
+                clocks = <&adpll_usb_ck 1>;
+        };
+
         aud_clkin0_ck: aud_clkin0_ck {
                 #clock-cells = <0>;
                 compatible = "fixed-clock";
diff --git a/arch/arm/boot/dts/dra62x-clocks.dtsi b/arch/arm/boot/dts/dra62x-clocks.dtsi
index 6f98dc8df9dd..0e49741747ef 100644
--- a/arch/arm/boot/dts/dra62x-clocks.dtsi
+++ b/arch/arm/boot/dts/dra62x-clocks.dtsi
@@ -6,6 +6,32 @@
 
 #include "dm814x-clocks.dtsi"
 
+/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
+&adpll_hdvic_ck {
+        status = "disabled";
+};
+
+&adpll_l3_ck {
+        status = "disabled";
+};
+
+&adpll_dss_ck {
+        status = "disabled";
+};
+
+/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
+&sysclk4_ck {
+        clocks = <&adpll_isp_ck 1>;
+};
+
+&sysclk5_ck {
+        clocks = <&adpll_isp_ck 1>;
+};
+
+&sysclk6_ck {
+        clocks = <&adpll_isp_ck 1>;
+};
+
 /*
  * Compared to dm814x, dra62x has different shifts and more mux options.
  * Please add the extra options for ysclk_14 and 16 if really needed.
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d0bae06b7eb7..ef2164a99d0f 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -98,12 +98,20 @@
                 clock-frequency = <32768>;
         };
 
-        sys_32k_ck: sys_32k_ck {
+        sys_clk32_crystal_ck: sys_clk32_crystal_ck {
                 #clock-cells = <0>;
                 compatible = "fixed-clock";
                 clock-frequency = <32768>;
         };
 
+        sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin1>;
+                clock-mult = <1>;
+                clock-div = <610>;
+        };
+
         virt_12000000_ck: virt_12000000_ck {
                 #clock-cells = <0>;
                 compatible = "fixed-clock";
@@ -2170,4 +2178,12 @@
                 ti,bit-shift = <22>;
                 reg = <0x0558>;
         };
+
+        sys_32k_ck: sys_32k_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x6c4>;
+        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index ef5330578431..8193139d0d87 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
 #include "skeleton.dtsi"
 
@@ -460,8 +460,6 @@
                         clock-names = "core", "iface";
                         #address-cells = <1>;
                         #size-cells = <0>;
-                        dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
-                        dma-names = "tx", "rx";
                 };
 
                 spmi_bus: spmi@fc4cf000 {
@@ -479,16 +477,6 @@
                         interrupt-controller;
                         #interrupt-cells = <4>;
                 };
-
-                blsp2_dma: dma-controller@f9944000 {
-                        compatible = "qcom,bam-v1.4.0";
-                        reg = <0xf9944000 0x19000>;
-                        interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&gcc GCC_BLSP2_AHB_CLK>;
-                        clock-names = "bam_clk";
-                        #dma-cells = <1>;
-                        qcom,ee = <0>;
-                };
         };
 
         smd {
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 0ad71b81d3a2..cc6e28f81fe4 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -661,6 +661,7 @@
 };
 
 &pcie_bus_clk {
+        clock-frequency = <100000000>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index 6c08314427d6..a9285d9a57cd 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -143,19 +143,11 @@
 };
 
 &pfc {
-        pinctrl-0 = <&scif_clk_pins>;
-        pinctrl-names = "default";
-
         scif0_pins: serial0 {
                 renesas,groups = "scif0_data_d";
                 renesas,function = "scif0";
         };
 
-        scif_clk_pins: scif_clk {
-                renesas,groups = "scif_clk";
-                renesas,function = "scif_clk";
-        };
-
         ether_pins: ether {
                 renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
                 renesas,function = "eth";
@@ -229,11 +221,6 @@
         status = "okay";
 };
 
-&scif_clk {
-        clock-frequency = <14745600>;
-        status = "okay";
-};
-
 &ether {
         pinctrl-0 = <&ether_pins &phy1_pins>;
         pinctrl-names = "default";
@@ -414,6 +401,7 @@
 };
 
 &pcie_bus_clk {
+        clock-frequency = <100000000>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 6439f0569fe2..1cd1b6a3a72a 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1083,9 +1083,8 @@
                 pcie_bus_clk: pcie_bus_clk {
                         compatible = "fixed-clock";
                         #clock-cells = <0>;
-                        clock-frequency = <100000000>;
+                        clock-frequency = <0>;
                         clock-output-names = "pcie_bus";
-                        status = "disabled";
                 };
 
                 /* External SCIF clock */
@@ -1094,7 +1093,6 @@
                         #clock-cells = <0>;
                         /* This value must be overridden by the board. */
                         clock-frequency = <0>;
-                        status = "disabled";
                 };
 
                 /* External USB clock - can be overridden by the board */
@@ -1112,7 +1110,6 @@
                         /* This value must be overridden by the board. */
                         clock-frequency = <0>;
                         clock-output-names = "can_clk";
-                        status = "disabled";
                 };
 
                 /* Special CPG clocks */
diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
index a5edd7d60266..3d039ef021e0 100644
--- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
+++ b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
@@ -71,6 +71,7 @@ struct platform_device *__init imx_add_sdhci_esdhc_imx(
         if (!pdata)
                 pdata = &default_esdhc_pdata;
 
-        return imx_add_platform_device(data->devid, data->id, res,
-                        ARRAY_SIZE(res), pdata, sizeof(*pdata));
+        return imx_add_platform_device_dmamask(data->devid, data->id, res,
+                        ARRAY_SIZE(res), pdata, sizeof(*pdata),
+                        DMA_BIT_MASK(32));
 }
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
index 7581e036bda6..ef9ed36e8a61 100644
--- a/arch/arm/mach-omap2/clockdomains7xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -461,7 +461,7 @@ static struct clockdomain ipu_7xx_clkdm = {
         .cm_inst          = DRA7XX_CM_CORE_AON_IPU_INST,
         .clkdm_offs       = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
         .dep_bit          = DRA7XX_IPU_STATDEP_SHIFT,
-        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .flags            = CLKDM_CAN_SWSUP,
 };
 
 static struct clockdomain mpu1_7xx_clkdm = {
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 9821be6dfd5e..49de4dd227be 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -737,7 +737,8 @@ void __init omap5_init_late(void)
 #ifdef CONFIG_SOC_DRA7XX
 void __init dra7xx_init_early(void)
 {
-        omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
+        omap2_set_globals_tap(DRA7XX_CLASS,
+                              OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
         omap2_control_base_init();
         omap4_pm_init_early();
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index f397bd6bd6e3..2c04f2741476 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -274,6 +274,10 @@ static inline void omap5_irq_save_context(void)
  */
 static void irq_save_context(void)
 {
+        /* DRA7 has no SAR to save */
+        if (soc_is_dra7xx())
+                return;
+
         if (!sar_base)
                 sar_base = omap4_get_sar_ram_base();
 
@@ -290,6 +294,9 @@ static void irq_sar_clear(void)
 {
         u32 val;
         u32 offset = SAR_BACKUP_STATUS_OFFSET;
+        /* DRA7 has no SAR to save */
+        if (soc_is_dra7xx())
+                return;
 
         if (soc_is_omap54xx())
                 offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2dbd3785ee6f..d44e0e2f1106 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -198,7 +198,6 @@ void omap_sram_idle(void)
         int per_next_state = PWRDM_POWER_ON;
         int core_next_state = PWRDM_POWER_ON;
         int per_going_off;
-        int core_prev_state;
         u32 sdrc_pwr = 0;
 
         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
@@ -278,16 +277,20 @@ void omap_sram_idle(void)
                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 
         /* CORE */
-        if (core_next_state < PWRDM_POWER_ON) {
-                core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
-                if (core_prev_state == PWRDM_POWER_OFF) {
-                        omap3_core_restore_context();
-                        omap3_cm_restore_context();
-                        omap3_sram_restore_context();
-                        omap2_sms_restore_context();
-                }
+        if (core_next_state < PWRDM_POWER_ON &&
+            pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
+                omap3_core_restore_context();
+                omap3_cm_restore_context();
+                omap3_sram_restore_context();
+                omap2_sms_restore_context();
+        } else {
+                /*
+                 * In off-mode resume path above, omap3_core_restore_context
+                 * also handles the INTC autoidle restore done here so limit
+                 * this to non-off mode resume paths so we don't do it twice.
+                 */
+                omap3_intc_resume_idle();
         }
-        omap3_intc_resume_idle();
 
         pwrdm_post_transition(NULL);
 
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index ad008e4b0c49..67d79f9c6bad 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -40,8 +40,7 @@ static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
 void __init shmobile_init_delay(void)
 {
         struct device_node *np, *cpus;
-        bool is_a7_a8_a9 = false;
-        bool is_a15 = false;
+        unsigned int div = 0;
         bool has_arch_timer = false;
         u32 max_freq = 0;
 
@@ -55,27 +54,22 @@ void __init shmobile_init_delay(void)
                 if (!of_property_read_u32(np, "clock-frequency", &freq))
                         max_freq = max(max_freq, freq);
 
-                if (of_device_is_compatible(np, "arm,cortex-a8") ||
-                    of_device_is_compatible(np, "arm,cortex-a9")) {
-                        is_a7_a8_a9 = true;
-                } else if (of_device_is_compatible(np, "arm,cortex-a7")) {
-                        is_a7_a8_a9 = true;
-                        has_arch_timer = true;
-                } else if (of_device_is_compatible(np, "arm,cortex-a15")) {
-                        is_a15 = true;
+                if (of_device_is_compatible(np, "arm,cortex-a8")) {
+                        div = 2;
+                } else if (of_device_is_compatible(np, "arm,cortex-a9")) {
+                        div = 1;
+                } else if (of_device_is_compatible(np, "arm,cortex-a7") ||
+                         of_device_is_compatible(np, "arm,cortex-a15")) {
+                        div = 1;
                         has_arch_timer = true;
                 }
         }
 
         of_node_put(cpus);
 
-        if (!max_freq)
+        if (!max_freq || !div)
                 return;
 
-        if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
-                if (is_a7_a8_a9)
-                        shmobile_setup_delay_hz(max_freq, 1, 3);
-                else if (is_a15)
-                        shmobile_setup_delay_hz(max_freq, 2, 4);
-        }
+        if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
+                shmobile_setup_delay_hz(max_freq, 1, div);
 }
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20-ref.dts
index 727ae5f8c4e7..b0ed44313a5b 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20-ref.dts
@@ -70,7 +70,6 @@
                 i2c3 = &i2c3;
                 i2c4 = &i2c4;
                 i2c5 = &i2c5;
-                i2c6 = &i2c6;
         };
 };
 
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
index e682a3f52791..651c9d9d2d54 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
@@ -201,15 +201,12 @@
 
                 i2c2: i2c@58782000 {
                         compatible = "socionext,uniphier-fi2c";
-                        status = "disabled";
                         reg = <0x58782000 0x80>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         interrupts = <0 43 4>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_i2c2>;
                         clocks = <&i2c_clk>;
-                        clock-frequency = <100000>;
+                        clock-frequency = <400000>;
                 };
 
                 i2c3: i2c@58783000 {
@@ -227,12 +224,15 @@
 
                 i2c4: i2c@58784000 {
                         compatible = "socionext,uniphier-fi2c";
+                        status = "disabled";
                         reg = <0x58784000 0x80>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         interrupts = <0 45 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_i2c4>;
                         clocks = <&i2c_clk>;
-                        clock-frequency = <400000>;
+                        clock-frequency = <100000>;
                 };
 
                 i2c5: i2c@58785000 {
@@ -245,16 +245,6 @@
                         clock-frequency = <400000>;
                 };
 
-                i2c6: i2c@58786000 {
-                        compatible = "socionext,uniphier-fi2c";
-                        reg = <0x58786000 0x80>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        interrupts = <0 26 4>;
-                        clocks = <&i2c_clk>;
-                        clock-frequency = <400000>;
-                };
-
                 system_bus: system-bus@58c00000 {
                         compatible = "socionext,uniphier-system-bus";
                         status = "disabled";
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index 11bfee8b79a9..b5d05807e6ec 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -360,7 +360,7 @@ static struct cpuidle_ops psci_cpuidle_ops __initdata = {
         .init = psci_dt_cpu_init_idle,
 };
 
-CPUIDLE_METHOD_OF_DECLARE(psci, "arm,psci", &psci_cpuidle_ops);
+CPUIDLE_METHOD_OF_DECLARE(psci, "psci", &psci_cpuidle_ops);
 #endif
 #endif
 
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 57e781c71e67..837effe19907 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -491,13 +491,14 @@ static int scpsys_probe(struct platform_device *pdev)
                 genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
 
                 /*
-                 * With CONFIG_PM disabled turn on all domains to make the
-                 * hardware usable.
+                 * Initially turn on all domains to make the domains usable
+                 * with !CONFIG_PM and to get the hardware in sync with the
+                 * software.  The unused domains will be switched off during
+                 * late_init time.
                  */
-                if (!IS_ENABLED(CONFIG_PM))
-                        genpd->power_on(genpd);
+                genpd->power_on(genpd);
 
-                pm_genpd_init(genpd, NULL, true);
+                pm_genpd_init(genpd, NULL, false);
         }
 
         /*