Merge tag 'drm-intel-next-fixes-2015-09-10' of git://anongit.freedesktop.org/drm-intel into drm-next

Fixes headed for v4.3-rc1, including Maarten's DP MST state checker fix
you requested.

* tag 'drm-intel-next-fixes-2015-09-10' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Allow DSI dual link to be configured on any pipe
  drm/i915: Don't try to use DDR DVFS on CHV when disabled in the BIOS
  drm/i915: Fix CSR MMIO address check
  drm/i915: Limit the number of loops for reading a split 64bit register
  drm/i915: Fix broken mst get_hw_state.
  drm/i915: Pass hpd_status_i915[] to intel_get_hpd_pins() in pre-g4x
  uapi/drm/i915_drm.h: fix userspace compilation.
  drm/i915: Always mark the object as dirty when used by the GPU

9 files changed, 54 insertions, 32 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e304d4e5ae0c..b06e03080771 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1928,6 +1928,8 @@ struct drm_i915_private {
                         struct skl_wm_values skl_hw;
                         struct vlv_wm_values vlv;
                 };
+
+                uint8_t max_level;
         } wm;
 
         struct i915_runtime_pm pm;
@@ -3383,13 +3385,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
 
 #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
-        u32 upper, lower, tmp;                                          \
-        tmp = I915_READ(upper_reg);                                     \
+        u32 upper, lower, old_upper, loop = 0;                          \
+        upper = I915_READ(upper_reg);                                   \
         do {                                                            \
-                upper = tmp;                                            \
+                old_upper = upper;                                      \
                 lower = I915_READ(lower_reg);                           \
-                tmp = I915_READ(upper_reg);                             \
-        } while (upper != tmp);                                         \
+                upper = I915_READ(upper_reg);                           \
+        } while (upper != old_upper && loop++ < 2);                     \
         (u64)upper << 32 | lower; })
 
 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 923a3c4bf0b7..a953d4975b8c 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1032,6 +1032,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
                 u32 old_read = obj->base.read_domains;
                 u32 old_write = obj->base.write_domain;
 
+                obj->dirty = 1; /* be paranoid  */
                 obj->base.write_domain = obj->base.pending_write_domain;
                 if (obj->base.write_domain == 0)
                         obj->base.pending_read_domains |= obj->base.read_domains;
@@ -1039,7 +1040,6 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
 
                 i915_vma_move_to_active(vma, req);
                 if (obj->base.write_domain) {
-                        obj->dirty = 1;
                         i915_gem_request_assign(&obj->last_write_req, req);
 
                         intel_fb_obj_invalidate(obj, ORIGIN_CS);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d94c92d842fb..a2bceb70a3fd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1558,7 +1558,7 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev)
                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
 
                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
-                                   hotplug_trigger, hpd_status_g4x,
+                                   hotplug_trigger, hpd_status_i915,
                                    i9xx_port_hotplug_long_detect);
                 intel_hpd_irq_handler(dev, pin_mask, long_mask);
         }
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index ba1ae031e6fd..d0f1b8d833cd 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -350,7 +350,7 @@ static void finish_csr_load(const struct firmware *fw, void *context)
         }
         csr->mmio_count = dmc_header->mmio_count;
         for (i = 0; i < dmc_header->mmio_count; i++) {
-                if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE &&
+                if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
                         dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
                                                 dmc_header->mmioaddr[i]);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ca9278be49f7..8cc9264f7809 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6305,7 +6305,7 @@ static void intel_connector_check_state(struct intel_connector *connector)
                       connector->base.name);
 
         if (connector->get_hw_state(connector)) {
-                struct drm_encoder *encoder = &connector->encoder->base;
+                struct intel_encoder *encoder = connector->encoder;
                 struct drm_connector_state *conn_state = connector->base.state;
 
                 I915_STATE_WARN(!crtc,
@@ -6317,13 +6317,13 @@ static void intel_connector_check_state(struct intel_connector *connector)
                 I915_STATE_WARN(!crtc->state->active,
                       "connector is active, but attached crtc isn't\n");
 
-                if (!encoder)
+                if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
                         return;
 
-                I915_STATE_WARN(conn_state->best_encoder != encoder,
+                I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
                         "atomic encoder doesn't match attached encoder\n");
 
-                I915_STATE_WARN(conn_state->crtc != encoder->crtc,
+                I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
                         "attached encoder crtc differs from connector crtc\n");
         } else {
                 I915_STATE_WARN(crtc && crtc->state->active,
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 983553cf8b74..3e4be5a3becd 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -173,6 +173,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
                 return;
         }
 
+        /* MST encoders are bound to a crtc, not to a connector,
+         * force the mapping here for get_hw_state.
+         */
+        found->encoder = encoder;
+
         DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
         intel_mst->port = found->port;
 
@@ -400,7 +405,7 @@ static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
 
 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
 {
-        if (connector->encoder) {
+        if (connector->encoder && connector->base.state->crtc) {
                 enum pipe pipe;
                 if (!connector->encoder->get_hw_state(connector->encoder, &pipe))
                         return false;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4a601cf90f16..32a6c7184ca4 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1048,11 +1048,7 @@ void intel_dsi_init(struct drm_device *dev)
         intel_connector->unregister = intel_connector_unregister;
 
         /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
-        if (dev_priv->vbt.dsi.config->dual_link) {
-                /* XXX: does dual link work on either pipe? */
-                intel_encoder->crtc_mask = (1 << PIPE_A);
-                intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
-        } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
+        if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
                 intel_encoder->crtc_mask = (1 << PIPE_A);
                 intel_dsi->ports = (1 << PORT_A);
         } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
@@ -1060,6 +1056,9 @@ void intel_dsi_init(struct drm_device *dev)
                 intel_dsi->ports = (1 << PORT_C);
         }
 
+        if (dev_priv->vbt.dsi.config->dual_link)
+                intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
+
         /* Create a DSI host (and a device) for each port. */
         for_each_dsi_port(port, intel_dsi->ports) {
                 struct intel_dsi_host *host;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fff0c22682ee..ddbb7ed0a193 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -955,8 +955,6 @@ enum vlv_wm_level {
         VLV_WM_LEVEL_PM2,
         VLV_WM_LEVEL_PM5,
         VLV_WM_LEVEL_DDR_DVFS,
-        CHV_WM_NUM_LEVELS,
-        VLV_WM_NUM_LEVELS = 1,
 };
 
 /* latency must be in 0.1us units. */
@@ -982,9 +980,13 @@ static void vlv_setup_wm_latency(struct drm_device *dev)
         /* all latencies in usec */
         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 
+        dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
+
         if (IS_CHERRYVIEW(dev_priv)) {
                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
+
+                dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
         }
 }
 
@@ -1137,10 +1139,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
         memset(wm_state, 0, sizeof(*wm_state));
 
         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
-        if (IS_CHERRYVIEW(dev))
-                wm_state->num_levels = CHV_WM_NUM_LEVELS;
-        else
-                wm_state->num_levels = VLV_WM_NUM_LEVELS;
+        wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
 
         wm_state->num_active_planes = 0;
 
@@ -1220,7 +1219,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
         }
 
         /* clear any (partially) filled invalid levels */
-        for (level = wm_state->num_levels; level < CHV_WM_NUM_LEVELS; level++) {
+        for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
         }
@@ -1324,10 +1323,7 @@ static void vlv_merge_wm(struct drm_device *dev,
         struct intel_crtc *crtc;
         int num_active_crtcs = 0;
 
-        if (IS_CHERRYVIEW(dev))
-                wm->level = VLV_WM_LEVEL_DDR_DVFS;
-        else
-                wm->level = VLV_WM_LEVEL_PM2;
+        wm->level = to_i915(dev)->wm.max_level;
         wm->cxsr = true;
 
         for_each_intel_crtc(dev, crtc) {
@@ -4083,9 +4079,29 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
                 if (val & DSP_MAXFIFO_PM5_ENABLE)
                         wm->level = VLV_WM_LEVEL_PM5;
 
+                /*
+                 * If DDR DVFS is disabled in the BIOS, Punit
+                 * will never ack the request. So if that happens
+                 * assume we don't have to enable/disable DDR DVFS
+                 * dynamically. To test that just set the REQ_ACK
+                 * bit to poke the Punit, but don't change the
+                 * HIGH/LOW bits so that we don't actually change
+                 * the current state.
+                 */
                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
-                if ((val & FORCE_DDR_HIGH_FREQ) == 0)
-                        wm->level = VLV_WM_LEVEL_DDR_DVFS;
+                val |= FORCE_DDR_FREQ_REQ_ACK;
+                vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
+
+                if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
+                              FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
+                        DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
+                                      "assuming DDR DVFS is disabled\n");
+                        dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
+                } else {
+                        val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
+                        if ((val & FORCE_DDR_HIGH_FREQ) == 0)
+                                wm->level = VLV_WM_LEVEL_DDR_DVFS;
+                }
 
                 mutex_unlock(&dev_priv->rps.hw_lock);
         }
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index dbd16a2d37db..fd5aa47bd689 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -358,7 +358,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
 
 typedef struct drm_i915_getparam {
-        s32 param;
+        __s32 param;
         /*
          * WARNING: Using pointers instead of fixed-size u64 means we need to write
          * compat32 code. Don't repeat this mistake.