diff options
| author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2018-05-11 00:31:20 -0400 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-05-16 04:47:18 -0400 |
| commit | 913a78b575c313b8bee8384a542e637049232e40 (patch) | |
| tree | 9190f7860d92f5e56f2a11570dd119bd9c3a9399 | |
| parent | 0d292de1ebe0cfc599d7eeccdff4aa0d77a03f55 (diff) | |
arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes
This patch adds EthernetAVB node for r8a77990 (R-Car E3).
Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77990.dtsi | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index bbc3db50bc01..be4f519711a1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi | |||
| @@ -191,6 +191,51 @@ | |||
| 191 | #power-domain-cells = <1>; | 191 | #power-domain-cells = <1>; |
| 192 | }; | 192 | }; |
| 193 | 193 | ||
| 194 | avb: ethernet@e6800000 { | ||
| 195 | compatible = "renesas,etheravb-r8a77990", | ||
| 196 | "renesas,etheravb-rcar-gen3"; | ||
| 197 | reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; | ||
| 198 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | ||
| 199 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | ||
| 200 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | ||
| 201 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | ||
| 202 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | ||
| 203 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | ||
| 204 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | ||
| 205 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | ||
| 206 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | ||
| 207 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | ||
| 208 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | ||
| 209 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | ||
| 210 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | ||
| 211 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | ||
| 212 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | ||
| 213 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | ||
| 214 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | ||
| 215 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | ||
| 216 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | ||
| 217 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | ||
| 218 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | ||
| 219 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | ||
| 220 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | ||
| 221 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | ||
| 222 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | ||
| 223 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | ||
| 224 | "ch4", "ch5", "ch6", "ch7", | ||
| 225 | "ch8", "ch9", "ch10", "ch11", | ||
| 226 | "ch12", "ch13", "ch14", "ch15", | ||
| 227 | "ch16", "ch17", "ch18", "ch19", | ||
| 228 | "ch20", "ch21", "ch22", "ch23", | ||
| 229 | "ch24"; | ||
| 230 | clocks = <&cpg CPG_MOD 812>; | ||
| 231 | power-domains = <&sysc 32>; | ||
| 232 | resets = <&cpg 812>; | ||
| 233 | phy-mode = "rgmii"; | ||
| 234 | #address-cells = <1>; | ||
| 235 | #size-cells = <0>; | ||
| 236 | status = "disabled"; | ||
| 237 | }; | ||
| 238 | |||
| 194 | scif2: serial@e6e88000 { | 239 | scif2: serial@e6e88000 { |
| 195 | compatible = "renesas,scif-r8a77990", | 240 | compatible = "renesas,scif-r8a77990", |
| 196 | "renesas,rcar-gen3-scif", "renesas,scif"; | 241 | "renesas,rcar-gen3-scif", "renesas,scif"; |
