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authorMoritz Fischer <moritz.fischer@ettus.com>2015-10-16 18:42:28 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2015-10-18 00:57:16 -0400
commit908ca2dbc819f47ab3ef4d38f83e9e81c218b10d (patch)
tree0b9941c18f8f3d9618a2a11c6029f458fb6e1ef4
parent1920c298e74b1b9982247bcc33f2a206271ec835 (diff)
ARM: dt: fpga: Added binding docs for Xilinx Zynq FPGA manager.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt19
1 files changed, 19 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
new file mode 100644
index 000000000000..7018aa896835
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
@@ -0,0 +1,19 @@
1Xilinx Zynq FPGA Manager
2
3Required properties:
4- compatible: should contain "xlnx,zynq-devcfg-1.0"
5- reg: base address and size for memory mapped io
6- interrupts: interrupt for the FPGA manager device
7- clocks: phandle for clocks required operation
8- clock-names: name for the clock, should be "ref_clk"
9- syscon: phandle for access to SLCR registers
10
11Example:
12 devcfg: devcfg@f8007000 {
13 compatible = "xlnx,zynq-devcfg-1.0";
14 reg = <0xf8007000 0x100>;
15 interrupts = <0 8 4>;
16 clocks = <&clkc 12>;
17 clock-names = "ref_clk";
18 syscon = <&slcr>;
19 };