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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-09-16 17:43:45 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-09-17 03:25:07 -0400
commit9084e7d27671bc463c09ae6f0d6dfeea5f74f041 (patch)
tree12608ec4a716ba15e6d12b962997860fed747614
parent37327abdfbb4e2d7c9033f450de5e36e401d6efc (diff)
drm/i915: re-layout intel_panel.c to obey 80 char limit
Especially intel_gmch_panel_fitting was shifting way too much over the right edge and also was way too long. So extract two helpers, one for gen4+ and one for gen2/3. Now the entire thing is again almost readable ... Spurred by checkpatch freaking out about a Ville's pipeconfig rework in intel_panel.c Otherwise just two lines that needed appropriate breaking. Not functional change in this patch. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c152
1 files changed, 88 insertions, 64 deletions
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index c9dba46f52af..e36149d578fa 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -73,8 +73,10 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
73 case DRM_MODE_SCALE_ASPECT: 73 case DRM_MODE_SCALE_ASPECT:
74 /* Scale but preserve the aspect ratio */ 74 /* Scale but preserve the aspect ratio */
75 { 75 {
76 u32 scaled_width = adjusted_mode->hdisplay * pipe_config->pipe_src_h; 76 u32 scaled_width = adjusted_mode->hdisplay
77 u32 scaled_height = pipe_config->pipe_src_w * adjusted_mode->vdisplay; 77 * pipe_config->pipe_src_h;
78 u32 scaled_height = pipe_config->pipe_src_w
79 * adjusted_mode->vdisplay;
78 if (scaled_width > scaled_height) { /* pillar */ 80 if (scaled_width > scaled_height) { /* pillar */
79 width = scaled_height / pipe_config->pipe_src_h; 81 width = scaled_height / pipe_config->pipe_src_h;
80 if (width & 1) 82 if (width & 1)
@@ -169,6 +171,83 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
169 return (FACTOR * ratio + FACTOR/2) / FACTOR; 171 return (FACTOR * ratio + FACTOR/2) / FACTOR;
170} 172}
171 173
174static void i965_scale_aspect(struct intel_crtc_config *pipe_config,
175 u32 *pfit_control)
176{
177 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
178 u32 scaled_width = adjusted_mode->hdisplay *
179 pipe_config->pipe_src_h;
180 u32 scaled_height = pipe_config->pipe_src_w *
181 adjusted_mode->vdisplay;
182
183 /* 965+ is easy, it does everything in hw */
184 if (scaled_width > scaled_height)
185 *pfit_control |= PFIT_ENABLE |
186 PFIT_SCALING_PILLAR;
187 else if (scaled_width < scaled_height)
188 *pfit_control |= PFIT_ENABLE |
189 PFIT_SCALING_LETTER;
190 else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w)
191 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
192}
193
194static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config,
195 u32 *pfit_control, u32 *pfit_pgm_ratios,
196 u32 *border)
197{
198 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
199 u32 scaled_width = adjusted_mode->hdisplay *
200 pipe_config->pipe_src_h;
201 u32 scaled_height = pipe_config->pipe_src_w *
202 adjusted_mode->vdisplay;
203 u32 bits;
204
205 /*
206 * For earlier chips we have to calculate the scaling
207 * ratio by hand and program it into the
208 * PFIT_PGM_RATIO register
209 */
210 if (scaled_width > scaled_height) { /* pillar */
211 centre_horizontally(adjusted_mode,
212 scaled_height /
213 pipe_config->pipe_src_h);
214
215 *border = LVDS_BORDER_ENABLE;
216 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) {
217 bits = panel_fitter_scaling(pipe_config->pipe_src_h,
218 adjusted_mode->vdisplay);
219
220 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
221 bits << PFIT_VERT_SCALE_SHIFT);
222 *pfit_control |= (PFIT_ENABLE |
223 VERT_INTERP_BILINEAR |
224 HORIZ_INTERP_BILINEAR);
225 }
226 } else if (scaled_width < scaled_height) { /* letter */
227 centre_vertically(adjusted_mode,
228 scaled_width /
229 pipe_config->pipe_src_w);
230
231 *border = LVDS_BORDER_ENABLE;
232 if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
233 bits = panel_fitter_scaling(pipe_config->pipe_src_w,
234 adjusted_mode->hdisplay);
235
236 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
237 bits << PFIT_VERT_SCALE_SHIFT);
238 *pfit_control |= (PFIT_ENABLE |
239 VERT_INTERP_BILINEAR |
240 HORIZ_INTERP_BILINEAR);
241 }
242 } else {
243 /* Aspects match, Let hw scale both directions */
244 *pfit_control |= (PFIT_ENABLE |
245 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
246 VERT_INTERP_BILINEAR |
247 HORIZ_INTERP_BILINEAR);
248 }
249}
250
172void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, 251void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
173 struct intel_crtc_config *pipe_config, 252 struct intel_crtc_config *pipe_config,
174 int fitting_mode) 253 int fitting_mode)
@@ -196,67 +275,11 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
196 break; 275 break;
197 case DRM_MODE_SCALE_ASPECT: 276 case DRM_MODE_SCALE_ASPECT:
198 /* Scale but preserve the aspect ratio */ 277 /* Scale but preserve the aspect ratio */
199 if (INTEL_INFO(dev)->gen >= 4) { 278 if (INTEL_INFO(dev)->gen >= 4)
200 u32 scaled_width = adjusted_mode->hdisplay * 279 i965_scale_aspect(pipe_config, &pfit_control);
201 pipe_config->pipe_src_h; 280 else
202 u32 scaled_height = pipe_config->pipe_src_w * 281 i9xx_scale_aspect(pipe_config, &pfit_control,
203 adjusted_mode->vdisplay; 282 &pfit_pgm_ratios, &border);
204
205 /* 965+ is easy, it does everything in hw */
206 if (scaled_width > scaled_height)
207 pfit_control |= PFIT_ENABLE |
208 PFIT_SCALING_PILLAR;
209 else if (scaled_width < scaled_height)
210 pfit_control |= PFIT_ENABLE |
211 PFIT_SCALING_LETTER;
212 else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w)
213 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
214 } else {
215 u32 scaled_width = adjusted_mode->hdisplay *
216 pipe_config->pipe_src_h;
217 u32 scaled_height = pipe_config->pipe_src_w *
218 adjusted_mode->vdisplay;
219 /*
220 * For earlier chips we have to calculate the scaling
221 * ratio by hand and program it into the
222 * PFIT_PGM_RATIO register
223 */
224 if (scaled_width > scaled_height) { /* pillar */
225 centre_horizontally(adjusted_mode,
226 scaled_height /
227 pipe_config->pipe_src_h);
228
229 border = LVDS_BORDER_ENABLE;
230 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) {
231 u32 bits = panel_fitter_scaling(pipe_config->pipe_src_h, adjusted_mode->vdisplay);
232 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
233 bits << PFIT_VERT_SCALE_SHIFT);
234 pfit_control |= (PFIT_ENABLE |
235 VERT_INTERP_BILINEAR |
236 HORIZ_INTERP_BILINEAR);
237 }
238 } else if (scaled_width < scaled_height) { /* letter */
239 centre_vertically(adjusted_mode,
240 scaled_width /
241 pipe_config->pipe_src_w);
242
243 border = LVDS_BORDER_ENABLE;
244 if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
245 u32 bits = panel_fitter_scaling(pipe_config->pipe_src_w, adjusted_mode->hdisplay);
246 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
247 bits << PFIT_VERT_SCALE_SHIFT);
248 pfit_control |= (PFIT_ENABLE |
249 VERT_INTERP_BILINEAR |
250 HORIZ_INTERP_BILINEAR);
251 }
252 } else {
253 /* Aspects match, Let hw scale both directions */
254 pfit_control |= (PFIT_ENABLE |
255 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
256 VERT_INTERP_BILINEAR |
257 HORIZ_INTERP_BILINEAR);
258 }
259 }
260 break; 283 break;
261 case DRM_MODE_SCALE_FULLSCREEN: 284 case DRM_MODE_SCALE_FULLSCREEN:
262 /* 285 /*
@@ -438,7 +461,8 @@ static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
438 I915_WRITE(BLC_PWM_CPU_CTL, val | level); 461 I915_WRITE(BLC_PWM_CPU_CTL, val | level);
439} 462}
440 463
441static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level) 464static void intel_panel_actually_set_backlight(struct drm_device *dev,
465 u32 level)
442{ 466{
443 struct drm_i915_private *dev_priv = dev->dev_private; 467 struct drm_i915_private *dev_priv = dev->dev_private;
444 u32 tmp; 468 u32 tmp;