aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorStephen Boyd <sboyd@codeaurora.org>2017-12-07 02:09:59 -0500
committerStephen Boyd <sboyd@codeaurora.org>2017-12-07 02:09:59 -0500
commit90552a6f9312861ff2481fc9802c4cf6be02e338 (patch)
treef3f9493dc2410d8608feeac33dda59251bac5b96
parentcf251161553039a0e8c22c678712ead444a34338 (diff)
parentfe7020e64f042db4b5ca50c358b232e866523447 (diff)
Merge branch '4.15-rc1-clkctrl-driver' of https://github.com/t-kristo/linux-pm into clk-next
* '4.15-rc1-clkctrl-driver' of https://github.com/t-kristo/linux-pm: (28 commits) clk: ti: omap4: clkctrl data fixes for opt-clocks clk: ti: dm816: add clkctrl clock data dt-bindings: clk: add dm816 clkctrl definitions clk: ti: dm814: add clkctrl clock data dt-bindings: clk: add dm814 clkctrl definitions clk: ti: am43xx: add clkctrl clock data dt-bindings: clk: add am43xx clkctrl definitions clk: ti: am33xx: add clkctrl clock data dt-bindings: clk: add am33xx clkctrl definitions clk: ti: dra7: add clkctrl clock data dt-bindings: clk: add dra7 clkctrl definitions clk: ti: omap5: add clkctrl clock data dt-bindings: clk: add omap5 clkctrl definitions clk: ti: omap3: cleanup unnecessary clock aliases clk: ti: am43xx: cleanup unnecessary clock aliases clk: ti: am33xx: cleanup unnecessary clock aliases clk: ti: dm816x: cleanup unnecessary clock aliases clk: ti: dm814x: cleanup unnecessary clock aliases clk: ti: omap5: cleanup unnecessary clock aliases clk: ti: dra7: drop unnecessary clock aliases ...
Diffstat
-rw-r--r--drivers/clk/ti/apll.c3
-rw-r--r--drivers/clk/ti/clk-33xx.c279
-rw-r--r--drivers/clk/ti/clk-3xxx.c263
-rw-r--r--drivers/clk/ti/clk-43xx.c295
-rw-r--r--drivers/clk/ti/clk-44xx.c200
-rw-r--r--drivers/clk/ti/clk-54xx.c697
-rw-r--r--drivers/clk/ti/clk-7xx.c1076
-rw-r--r--drivers/clk/ti/clk-814x.c50
-rw-r--r--drivers/clk/ti/clk-816x.c62
-rw-r--r--drivers/clk/ti/clk.c70
-rw-r--r--drivers/clk/ti/clkctrl.c91
-rw-r--r--drivers/clk/ti/clock.h13
-rw-r--r--drivers/clk/ti/composite.c3
-rw-r--r--drivers/clk/ti/dpll.c3
-rw-r--r--include/dt-bindings/clock/am3.h108
-rw-r--r--include/dt-bindings/clock/am4.h113
-rw-r--r--include/dt-bindings/clock/dm814.h45
-rw-r--r--include/dt-bindings/clock/dm816.h53
-rw-r--r--include/dt-bindings/clock/dra7.h172
-rw-r--r--include/dt-bindings/clock/omap5.h118
20 files changed, 2662 insertions, 1052 deletions
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 83b148f8037c..9498e9363b57 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -133,9 +133,10 @@ static const struct clk_ops apll_ck_ops = {
133 .get_parent = &dra7_init_apll_parent, 133 .get_parent = &dra7_init_apll_parent,
134}; 134};
135 135
136static void __init omap_clk_register_apll(struct clk_hw *hw, 136static void __init omap_clk_register_apll(void *user,
137 struct device_node *node) 137 struct device_node *node)
138{ 138{
139 struct clk_hw *hw = user;
139 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 140 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
140 struct dpll_data *ad = clk_hw->dpll_data; 141 struct dpll_data *ad = clk_hw->dpll_data;
141 struct clk *clk; 142 struct clk *clk;
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index 0e47d95faf49..612491a26070 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -19,98 +19,201 @@
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/clk-provider.h> 20#include <linux/clk-provider.h>
21#include <linux/clk/ti.h> 21#include <linux/clk/ti.h>
22#include <dt-bindings/clock/am3.h>
22 23
23#include "clock.h" 24#include "clock.h"
24 25
26static const char * const am3_gpio1_dbclk_parents[] __initconst = {
27 "l4_per_cm:clk:0138:0",
28 NULL,
29};
30
31static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
32 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
33 { 0 },
34};
35
36static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
37 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
38 { 0 },
39};
40
41static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
42 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
43 { 0 },
44};
45
46static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
47 { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
48 { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP, "lcd_gclk", "lcdc_clkdm" },
49 { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
50 { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
51 { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
52 { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
53 { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
54 { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
55 { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
56 { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
57 { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
58 { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
59 { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
60 { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
61 { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
62 { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
63 { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
64 { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
65 { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
66 { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
67 { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
68 { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
69 { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
70 { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
71 { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
72 { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
73 { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
74 { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
75 { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
76 { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
77 { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
78 { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
79 { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
80 { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
81 { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
82 { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
83 { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
84 { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
85 { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
86 { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
87 { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
88 { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
89 { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
90 { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
91 { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
92 { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
93 { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
94 { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
95 { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
96 { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
97 { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
98 { 0 },
99};
100
101static const char * const am3_gpio0_dbclk_parents[] __initconst = {
102 "gpio0_dbclk_mux_ck",
103 NULL,
104};
105
106static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
107 { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
108 { 0 },
109};
110
111static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
112 "sys_clkin_ck",
113 NULL,
114};
115
116static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
117 "l4_wkup_cm:clk:0010:19",
118 "l4_wkup_cm:clk:0010:30",
119 NULL,
120};
121
122static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
123 "l4_wkup_cm:clk:0010:20",
124 NULL,
125};
126
127static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
128 .max_div = 64,
129 .flags = CLK_DIVIDER_POWER_OF_TWO,
130};
131
132static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
133 "l4_wkup_cm:clk:0010:22",
134 NULL,
135};
136
137static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
138 .max_div = 64,
139 .flags = CLK_DIVIDER_POWER_OF_TWO,
140};
141
142static const char * const am3_dbg_clka_ck_parents[] __initconst = {
143 "dpll_core_m4_ck",
144 NULL,
145};
146
147static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
148 { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
149 { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
150 { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
151 { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
152 { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
153 { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
154 { 0 },
155};
156
157static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
158 { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
159 { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
160 { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
161 { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
162 { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
163 { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
164 { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
165 { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
166 { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
167 { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
168 { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
169 { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
170 { 0 },
171};
172
173static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
174 { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
175 { 0 },
176};
177
178static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
179 { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
180 { 0 },
181};
182
183static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
184 { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
185 { 0 },
186};
187
188static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
189 { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
190 { 0 },
191};
192
193const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
194 { 0x44e00014, am3_l4_per_clkctrl_regs },
195 { 0x44e00404, am3_l4_wkup_clkctrl_regs },
196 { 0x44e00604, am3_mpu_clkctrl_regs },
197 { 0x44e00800, am3_l4_rtc_clkctrl_regs },
198 { 0x44e00904, am3_gfx_l3_clkctrl_regs },
199 { 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
200 { 0 },
201};
202
25static struct ti_dt_clk am33xx_clks[] = { 203static struct ti_dt_clk am33xx_clks[] = {
26 DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), 204 DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
27 DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
28 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
29 DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
30 DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
31 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
32 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
33 DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
34 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
35 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
36 DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
37 DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
38 DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
39 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
40 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
41 DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
42 DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
43 DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
44 DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
45 DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
46 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
47 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
48 DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
49 DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
50 DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
51 DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
52 DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
53 DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
54 DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
55 DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
56 DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
57 DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
58 DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
59 DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
60 DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
61 DT_CLK(NULL, "mmu_fck", "mmu_fck"),
62 DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
63 DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
64 DT_CLK(NULL, "sha0_fck", "sha0_fck"),
65 DT_CLK(NULL, "aes0_fck", "aes0_fck"),
66 DT_CLK(NULL, "rng_fck", "rng_fck"),
67 DT_CLK(NULL, "timer1_fck", "timer1_fck"),
68 DT_CLK(NULL, "timer2_fck", "timer2_fck"),
69 DT_CLK(NULL, "timer3_fck", "timer3_fck"),
70 DT_CLK(NULL, "timer4_fck", "timer4_fck"),
71 DT_CLK(NULL, "timer5_fck", "timer5_fck"),
72 DT_CLK(NULL, "timer6_fck", "timer6_fck"),
73 DT_CLK(NULL, "timer7_fck", "timer7_fck"),
74 DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
75 DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
76 DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
77 DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
78 DT_CLK(NULL, "l3_gclk", "l3_gclk"),
79 DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
80 DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
81 DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
82 DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
83 DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
84 DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
85 DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
86 DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
87 DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
88 DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
89 DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
90 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
91 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
92 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
93 DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
94 DT_CLK(NULL, "mmc_clk", "mmc_clk"),
95 DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
96 DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
97 DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
98 DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
99 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
100 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 205 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
101 DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"), 206 DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
102 DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"), 207 DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
103 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"), 208 DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
104 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"), 209 DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
105 DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"), 210 DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
106 DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"), 211 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
107 DT_CLK(NULL, "clkout2_ck", "clkout2_ck"), 212 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
108 DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), 213 DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
109 DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), 214 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
110 DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"), 215 DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
111 DT_CLK("48300200.pwm", "tbclk", "ehrpwm0_tbclk"), 216 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
112 DT_CLK("48302200.pwm", "tbclk", "ehrpwm1_tbclk"),
113 DT_CLK("48304200.pwm", "tbclk", "ehrpwm2_tbclk"),
114 { .node_name = NULL }, 217 { .node_name = NULL },
115}; 218};
116 219
@@ -133,6 +236,8 @@ int __init am33xx_dt_clk_init(void)
133 236
134 omap2_clk_disable_autoidle_all(); 237 omap2_clk_disable_autoidle_all();
135 238
239 ti_clk_add_aliases();
240
136 omap2_clk_enable_init_clocks(enable_init_clks, 241 omap2_clk_enable_init_clocks(enable_init_clks,
137 ARRAY_SIZE(enable_init_clks)); 242 ARRAY_SIZE(enable_init_clks));
138 243
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index b1251cae98b8..8aa5f5793835 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -224,296 +224,43 @@ const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
224}; 224};
225 225
226static struct ti_dt_clk omap3xxx_clks[] = { 226static struct ti_dt_clk omap3xxx_clks[] = {
227 DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
228 DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
229 DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
230 DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
231 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
232 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
233 DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
234 DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
235 DT_CLK("twl", "fck", "osc_sys_ck"),
236 DT_CLK(NULL, "sys_ck", "sys_ck"),
237 DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
238 DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
239 DT_CLK(NULL, "sys_altclk", "sys_altclk"),
240 DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
241 DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
242 DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
243 DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
244 DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
245 DT_CLK(NULL, "core_ck", "core_ck"),
246 DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
247 DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
248 DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
249 DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
250 DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
251 DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
252 DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
253 DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
254 DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
255 DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
256 DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
257 DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
258 DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
259 DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
260 DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
261 DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
262 DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
263 DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
264 DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
265 DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
266 DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
267 DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
268 DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
269 DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
270 DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
271 DT_CLK(NULL, "corex2_fck", "corex2_fck"),
272 DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
273 DT_CLK(NULL, "mpu_ck", "mpu_ck"),
274 DT_CLK(NULL, "arm_fck", "arm_fck"),
275 DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
276 DT_CLK(NULL, "l3_ick", "l3_ick"),
277 DT_CLK(NULL, "l4_ick", "l4_ick"),
278 DT_CLK(NULL, "rm_ick", "rm_ick"),
279 DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
280 DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
281 DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
282 DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
283 DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
284 DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
285 DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
286 DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
287 DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
288 DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
289 DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
290 DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
291 DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
292 DT_CLK(NULL, "uart2_fck", "uart2_fck"),
293 DT_CLK(NULL, "uart1_fck", "uart1_fck"),
294 DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
295 DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
296 DT_CLK(NULL, "hdq_fck", "hdq_fck"),
297 DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
298 DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
299 DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
300 DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
301 DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
302 DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
303 DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
304 DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
305 DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
306 DT_CLK(NULL, "hdq_ick", "hdq_ick"),
307 DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
308 DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
309 DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
310 DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
311 DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
312 DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
313 DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
314 DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
315 DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
316 DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
317 DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
318 DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
319 DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
320 DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
321 DT_CLK(NULL, "uart2_ick", "uart2_ick"),
322 DT_CLK(NULL, "uart1_ick", "uart1_ick"),
323 DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
324 DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
325 DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
326 DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
327 DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
328 DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
329 DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
330 DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
331 DT_CLK(NULL, "aes2_ick", "aes2_ick"),
332 DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
333 DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
334 DT_CLK(NULL, "sha12_ick", "sha12_ick"),
335 DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
336 DT_CLK("omap_wdt", "ick", "wdt2_ick"),
337 DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
338 DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
339 DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
340 DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
341 DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
342 DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
343 DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
344 DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
345 DT_CLK(NULL, "uart3_fck", "uart3_fck"),
346 DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
347 DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
348 DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
349 DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
350 DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
351 DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
352 DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
353 DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
354 DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
355 DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
356 DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
357 DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
358 DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
359 DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
360 DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
361 DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
362 DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
363 DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
364 DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
365 DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
366 DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
367 DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
368 DT_CLK(NULL, "uart3_ick", "uart3_ick"),
369 DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
370 DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
371 DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
372 DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
373 DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
374 DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
375 DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
376 DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
377 DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
378 DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
379 DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
380 DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
381 DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
382 DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
383 DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
384 DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
385 DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
386 DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
387 DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
388 DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
389 DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
390 DT_CLK(NULL, "pclk_fck", "pclk_fck"),
391 DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
392 DT_CLK(NULL, "atclk_fck", "atclk_fck"),
393 DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
394 DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
395 DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
396 DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
397 DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
398 DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"), 227 DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
399 DT_CLK(NULL, "timer_sys_ck", "sys_ck"), 228 DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
400 DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
401 { .node_name = NULL },
402};
403
404static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
405 DT_CLK(NULL, "aes1_ick", "aes1_ick"),
406 DT_CLK("omap_rng", "ick", "rng_ick"),
407 DT_CLK("omap3-rom-rng", "ick", "rng_ick"),
408 DT_CLK(NULL, "sha11_ick", "sha11_ick"),
409 DT_CLK(NULL, "des1_ick", "des1_ick"),
410 DT_CLK(NULL, "cam_mclk", "cam_mclk"),
411 DT_CLK(NULL, "cam_ick", "cam_ick"),
412 DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
413 DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
414 DT_CLK(NULL, "pka_ick", "pka_ick"),
415 DT_CLK(NULL, "icr_ick", "icr_ick"),
416 DT_CLK("omap-aes", "ick", "aes2_ick"),
417 DT_CLK("omap-sham", "ick", "sha12_ick"),
418 DT_CLK(NULL, "des2_ick", "des2_ick"),
419 DT_CLK(NULL, "mspro_ick", "mspro_ick"),
420 DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
421 DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
422 DT_CLK(NULL, "sr1_fck", "sr1_fck"),
423 DT_CLK(NULL, "sr2_fck", "sr2_fck"),
424 DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
425 DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
426 DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
427 DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
428 DT_CLK(NULL, "iva2_ck", "iva2_ck"),
429 DT_CLK(NULL, "modem_fck", "modem_fck"),
430 DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
431 DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
432 DT_CLK(NULL, "mspro_fck", "mspro_fck"),
433 DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
434 DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
435 { .node_name = NULL }, 229 { .node_name = NULL },
436}; 230};
437 231
438static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = { 232static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
439 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"), 233 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
440 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"), 234 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
441 DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
442 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"), 235 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
443 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"), 236 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
444 DT_CLK(NULL, "usim_fck", "usim_fck"),
445 DT_CLK(NULL, "usim_ick", "usim_ick"),
446 { .node_name = NULL }, 237 { .node_name = NULL },
447}; 238};
448 239
449static struct ti_dt_clk omap3430es1_clks[] = { 240static struct ti_dt_clk omap3430es1_clks[] = {
450 DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
451 DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
452 DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
453 DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
454 DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
455 DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
456 DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
457 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"), 241 DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
458 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"), 242 DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
459 DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
460 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"), 243 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
461 DT_CLK(NULL, "fac_ick", "fac_ick"),
462 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"), 244 DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
463 DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
464 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"), 245 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
465 DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
466 DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"), 246 DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
467 { .node_name = NULL }, 247 { .node_name = NULL },
468}; 248};
469 249
470static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = { 250static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
471 DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
472 DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
473 DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
474 DT_CLK(NULL, "sgx_fck", "sgx_fck"),
475 DT_CLK(NULL, "sgx_ick", "sgx_ick"),
476 DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
477 DT_CLK(NULL, "ts_fck", "ts_fck"),
478 DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
479 DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
480 DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
481 DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
482 DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
483 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"), 251 DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
484 DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
485 DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"), 252 DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
486 DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
487 DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
488 DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
489 { .node_name = NULL }, 253 { .node_name = NULL },
490}; 254};
491 255
492static struct ti_dt_clk am35xx_clks[] = { 256static struct ti_dt_clk am35xx_clks[] = {
493 DT_CLK(NULL, "ipss_ick", "ipss_ick"),
494 DT_CLK(NULL, "rmii_ck", "rmii_ck"),
495 DT_CLK(NULL, "pclk_ck", "pclk_ck"),
496 DT_CLK(NULL, "emac_ick", "emac_ick"),
497 DT_CLK(NULL, "emac_fck", "emac_fck"),
498 DT_CLK("davinci_emac.0", NULL, "emac_ick"),
499 DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
500 DT_CLK("vpfe-capture", "master", "vpfe_ick"),
501 DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
502 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"), 257 DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
503 DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"), 258 DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
504 DT_CLK(NULL, "hecc_ck", "hecc_ck"),
505 DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"), 259 DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
506 DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"), 260 DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
507 { .node_name = NULL }, 261 { .node_name = NULL },
508}; 262};
509 263
510static struct ti_dt_clk omap36xx_clks[] = {
511 DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
512 DT_CLK(NULL, "uart4_fck", "uart4_fck"),
513 DT_CLK(NULL, "uart4_ick", "uart4_ick"),
514 { .node_name = NULL },
515};
516
517static const char *enable_init_clks[] = { 264static const char *enable_init_clks[] = {
518 "sdrc_ick", 265 "sdrc_ick",
519 "gpmc_fck", 266 "gpmc_fck",
@@ -579,16 +326,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type)
579 soc_type == OMAP3_SOC_OMAP3630) 326 soc_type == OMAP3_SOC_OMAP3630)
580 ti_dt_clocks_register(omap36xx_omap3430es2plus_clks); 327 ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
581 328
582 if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
583 soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
584 soc_type == OMAP3_SOC_OMAP3630)
585 ti_dt_clocks_register(omap34xx_omap36xx_clks);
586
587 if (soc_type == OMAP3_SOC_OMAP3630)
588 ti_dt_clocks_register(omap36xx_clks);
589
590 omap2_clk_disable_autoidle_all(); 329 omap2_clk_disable_autoidle_all();
591 330
331 ti_clk_add_aliases();
332
592 omap2_clk_enable_init_clocks(enable_init_clks, 333 omap2_clk_enable_init_clocks(enable_init_clks,
593 ARRAY_SIZE(enable_init_clks)); 334 ARRAY_SIZE(enable_init_clks));
594 335
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index e816a7500e43..2b7c2e017665 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -19,109 +19,208 @@
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/clk-provider.h> 20#include <linux/clk-provider.h>
21#include <linux/clk/ti.h> 21#include <linux/clk/ti.h>
22#include <dt-bindings/clock/am4.h>
22 23
23#include "clock.h" 24#include "clock.h"
24 25
26static const char * const am4_synctimer_32kclk_parents[] __initconst = {
27 "mux_synctimer32k_ck",
28 NULL,
29};
30
31static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
32 { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
33 { 0 },
34};
35
36static const char * const am4_gpio0_dbclk_parents[] __initconst = {
37 "gpio0_dbclk_mux_ck",
38 NULL,
39};
40
41static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
42 { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
43 { 0 },
44};
45
46static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
47 { AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },
48 { AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
49 { AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },
50 { AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },
51 { AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },
52 { AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },
53 { AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
54 { AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
55 { AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },
56 { AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
57 { AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
58 { AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
59 { 0 },
60};
61
62static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
63 { AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
64 { 0 },
65};
66
67static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
68 { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
69 { 0 },
70};
71
72static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
73 { AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
74 { 0 },
75};
76
77static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
78 "dpll_per_clkdcoldo",
79 NULL,
80};
81
82static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
83 { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
84 { 0 },
85};
86
87static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
88 { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
89 { 0 },
90};
91
92static const char * const am4_gpio1_dbclk_parents[] __initconst = {
93 "clkdiv32k_ick",
94 NULL,
95};
96
97static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
98 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
99 { 0 },
100};
101
102static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
103 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
104 { 0 },
105};
106
107static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
108 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
109 { 0 },
110};
111
112static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
113 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
114 { 0 },
115};
116
117static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
118 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
119 { 0 },
120};
121
122static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {
123 { AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
124 { AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
125 { AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
126 { AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
127 { AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
128 { AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
129 { AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
130 { AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
131 { AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
132 { AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
133 { AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
134 { AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
135 { AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },
136 { AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
137 { AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
138 { AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
139 { AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
140 { AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
141 { AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
142 { AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
143 { AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
144 { AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
145 { AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
146 { AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
147 { AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
148 { AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
149 { AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
150 { AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
151 { AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
152 { AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
153 { AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
154 { AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
155 { AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
156 { AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
157 { AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
158 { AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
159 { AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
160 { AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
161 { AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
162 { AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
163 { AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
164 { AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
165 { AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
166 { AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
167 { AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
168 { AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
169 { AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
170 { AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
171 { AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
172 { AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
173 { AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
174 { AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
175 { AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
176 { AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
177 { AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
178 { AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
179 { AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
180 { AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
181 { AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
182 { AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
183 { AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
184 { AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
185 { AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
186 { AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
187 { AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
188 { AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
189 { AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
190 { AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "disp_clk", "dss_clkdm" },
191 { AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
192 { 0 },
193};
194
195const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
196 { 0x44df2820, am4_l4_wkup_clkctrl_regs },
197 { 0x44df8320, am4_mpu_clkctrl_regs },
198 { 0x44df8420, am4_gfx_l3_clkctrl_regs },
199 { 0x44df8520, am4_l4_rtc_clkctrl_regs },
200 { 0x44df8820, am4_l4_per_clkctrl_regs },
201 { 0 },
202};
203
204const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
205 { 0x44df2820, am4_l4_wkup_clkctrl_regs },
206 { 0x44df8320, am4_mpu_clkctrl_regs },
207 { 0x44df8420, am4_gfx_l3_clkctrl_regs },
208 { 0x44df8820, am4_l4_per_clkctrl_regs },
209 { 0 },
210};
211
25static struct ti_dt_clk am43xx_clks[] = { 212static struct ti_dt_clk am43xx_clks[] = {
26 DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
27 DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
28 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
29 DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
30 DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
31 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
32 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
33 DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
34 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
35 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
36 DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
37 DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
38 DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
39 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
40 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
41 DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
42 DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
43 DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
44 DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
45 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
46 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
47 DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
48 DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
49 DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
50 DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
51 DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
52 DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
53 DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
54 DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
55 DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
56 DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
57 DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
58 DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
59 DT_CLK(NULL, "sha0_fck", "sha0_fck"),
60 DT_CLK(NULL, "aes0_fck", "aes0_fck"),
61 DT_CLK(NULL, "rng_fck", "rng_fck"),
62 DT_CLK(NULL, "timer1_fck", "timer1_fck"),
63 DT_CLK(NULL, "timer2_fck", "timer2_fck"),
64 DT_CLK(NULL, "timer3_fck", "timer3_fck"),
65 DT_CLK(NULL, "timer4_fck", "timer4_fck"),
66 DT_CLK(NULL, "timer5_fck", "timer5_fck"),
67 DT_CLK(NULL, "timer6_fck", "timer6_fck"),
68 DT_CLK(NULL, "timer7_fck", "timer7_fck"),
69 DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
70 DT_CLK(NULL, "l3_gclk", "l3_gclk"),
71 DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
72 DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
73 DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
74 DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
75 DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
76 DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
77 DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
78 DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"),
79 DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
80 DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
81 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
82 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
83 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
84 DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
85 DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
86 DT_CLK(NULL, "mmc_clk", "mmc_clk"),
87 DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
88 DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
89 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), 213 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
90 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 214 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
91 DT_CLK(NULL, "sysclk_div", "sysclk_div"), 215 DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),
92 DT_CLK(NULL, "disp_clk", "disp_clk"), 216 DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),
93 DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"), 217 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),
94 DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"), 218 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),
95 DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"), 219 DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),
96 DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"), 220 DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),
97 DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"), 221 DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),
98 DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"), 222 DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),
99 DT_CLK(NULL, "timer8_fck", "timer8_fck"), 223 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),
100 DT_CLK(NULL, "timer9_fck", "timer9_fck"),
101 DT_CLK(NULL, "timer10_fck", "timer10_fck"),
102 DT_CLK(NULL, "timer11_fck", "timer11_fck"),
103 DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
104 DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
105 DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
106 DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
107 DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
108 DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
109 DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
110 DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
111 DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
112 DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
113 DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
114 DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
115 DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
116 DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"),
117 DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"),
118 DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"),
119 DT_CLK("48300200.pwm", "tbclk", "ehrpwm0_tbclk"),
120 DT_CLK("48302200.pwm", "tbclk", "ehrpwm1_tbclk"),
121 DT_CLK("48304200.pwm", "tbclk", "ehrpwm2_tbclk"),
122 DT_CLK("48306200.pwm", "tbclk", "ehrpwm3_tbclk"),
123 DT_CLK("48308200.pwm", "tbclk", "ehrpwm4_tbclk"),
124 DT_CLK("4830a200.pwm", "tbclk", "ehrpwm5_tbclk"),
125 { .node_name = NULL }, 224 { .node_name = NULL },
126}; 225};
127 226
@@ -133,6 +232,8 @@ int __init am43xx_dt_clk_init(void)
133 232
134 omap2_clk_disable_autoidle_all(); 233 omap2_clk_disable_autoidle_all();
135 234
235 ti_clk_add_aliases();
236
136 /* 237 /*
137 * cpsw_cpts_rft_clk has got the choice of 3 clocksources 238 * cpsw_cpts_rft_clk has got the choice of 3 clocksources
138 * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck. 239 * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 2005f032c02f..339d30d64ebb 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -35,7 +35,7 @@
35#define OMAP4_DPLL_USB_DEFFREQ 960000000 35#define OMAP4_DPLL_USB_DEFFREQ 960000000
36 36
37static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = { 37static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
38 { OMAP4_MPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_mpu_m2_ck" }, 38 { OMAP4_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
39 { 0 }, 39 { 0 },
40}; 40};
41 41
@@ -59,7 +59,7 @@ static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
59}; 59};
60 60
61static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = { 61static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
62 "dmic_sync_mux_ck", 62 "abe_cm:clk:0018:26",
63 "pad_clks_ck", 63 "pad_clks_ck",
64 "slimbus_clk", 64 "slimbus_clk",
65 NULL, 65 NULL,
@@ -79,7 +79,7 @@ static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
79}; 79};
80 80
81static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = { 81static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
82 "mcasp_sync_mux_ck", 82 "abe_cm:clk:0020:26",
83 "pad_clks_ck", 83 "pad_clks_ck",
84 "slimbus_clk", 84 "slimbus_clk",
85 NULL, 85 NULL,
@@ -92,7 +92,7 @@ static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
92}; 92};
93 93
94static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = { 94static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
95 "mcbsp1_sync_mux_ck", 95 "abe_cm:clk:0028:26",
96 "pad_clks_ck", 96 "pad_clks_ck",
97 "slimbus_clk", 97 "slimbus_clk",
98 NULL, 98 NULL,
@@ -105,7 +105,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst =
105}; 105};
106 106
107static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = { 107static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
108 "mcbsp2_sync_mux_ck", 108 "abe_cm:clk:0030:26",
109 "pad_clks_ck", 109 "pad_clks_ck",
110 "slimbus_clk", 110 "slimbus_clk",
111 NULL, 111 NULL,
@@ -118,7 +118,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst =
118}; 118};
119 119
120static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = { 120static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
121 "mcbsp3_sync_mux_ck", 121 "abe_cm:clk:0038:26",
122 "pad_clks_ck", 122 "pad_clks_ck",
123 "slimbus_clk", 123 "slimbus_clk",
124 NULL, 124 NULL,
@@ -186,18 +186,18 @@ static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst =
186 186
187static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = { 187static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
188 { OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" }, 188 { OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
189 { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "aess_fclk" }, 189 { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
190 { OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, 190 { OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
191 { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "func_dmic_abe_gfclk" }, 191 { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
192 { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "func_mcasp_abe_gfclk" }, 192 { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" },
193 { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "func_mcbsp1_gfclk" }, 193 { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
194 { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "func_mcbsp2_gfclk" }, 194 { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
195 { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "func_mcbsp3_gfclk" }, 195 { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
196 { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "slimbus1_fclk_0" }, 196 { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" },
197 { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "timer5_sync_mux" }, 197 { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
198 { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "timer6_sync_mux" }, 198 { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
199 { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "timer7_sync_mux" }, 199 { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
200 { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "timer8_sync_mux" }, 200 { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
201 { OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 201 { OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
202 { 0 }, 202 { 0 },
203}; 203};
@@ -280,6 +280,7 @@ static const char * const omap4_fdif_fck_parents[] __initconst = {
280 280
281static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = { 281static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = {
282 .max_div = 4, 282 .max_div = 4,
283 .flags = CLK_DIVIDER_POWER_OF_TWO,
283}; 284};
284 285
285static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = { 286static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
@@ -289,7 +290,7 @@ static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
289 290
290static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = { 291static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
291 { OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" }, 292 { OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
292 { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "fdif_fck" }, 293 { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" },
293 { 0 }, 294 { 0 },
294}; 295};
295 296
@@ -322,7 +323,7 @@ static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst
322}; 323};
323 324
324static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = { 325static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
325 { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "dss_dss_clk" }, 326 { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" },
326 { 0 }, 327 { 0 },
327}; 328};
328 329
@@ -338,7 +339,7 @@ static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
338}; 339};
339 340
340static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = { 341static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
341 { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "sgx_clk_mux" }, 342 { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" },
342 { 0 }, 343 { 0 },
343}; 344};
344 345
@@ -365,6 +366,7 @@ static const char * const omap4_hsi_fck_parents[] __initconst = {
365 366
366static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = { 367static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = {
367 .max_div = 4, 368 .max_div = 4,
369 .flags = CLK_DIVIDER_POWER_OF_TWO,
368}; 370};
369 371
370static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = { 372static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
@@ -373,12 +375,12 @@ static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
373}; 375};
374 376
375static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = { 377static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
376 "utmi_p1_gfclk", 378 "l3_init_cm:clk:0038:24",
377 NULL, 379 NULL,
378}; 380};
379 381
380static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = { 382static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
381 "utmi_p2_gfclk", 383 "l3_init_cm:clk:0038:25",
382 NULL, 384 NULL,
383}; 385};
384 386
@@ -419,7 +421,7 @@ static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initcon
419}; 421};
420 422
421static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = { 423static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
422 "otg_60m_gfclk", 424 "l3_init_cm:clk:0040:24",
423 NULL, 425 NULL,
424}; 426};
425 427
@@ -453,14 +455,14 @@ static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __ini
453}; 455};
454 456
455static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = { 457static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
456 { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "hsmmc1_fclk" }, 458 { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" },
457 { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "hsmmc2_fclk" }, 459 { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" },
458 { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "hsi_fck" }, 460 { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" },
459 { OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" }, 461 { OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
460 { OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" }, 462 { OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
461 { OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" }, 463 { OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
462 { OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" }, 464 { OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
463 { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "ocp2scp_usb_phy_phy_48m" }, 465 { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" },
464 { 0 }, 466 { 0 },
465}; 467};
466 468
@@ -531,7 +533,7 @@ static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
531}; 533};
532 534
533static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = { 535static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
534 "mcbsp4_sync_mux_ck", 536 "l4_per_cm:clk:00c0:26",
535 "pad_clks_ck", 537 "pad_clks_ck",
536 NULL, 538 NULL,
537}; 539};
@@ -544,7 +546,7 @@ static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = {
544 546
545static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = { 547static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = {
546 { 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL }, 548 { 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
547 { 25, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL }, 549 { 26, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
548 { 0 }, 550 { 0 },
549}; 551};
550 552
@@ -571,12 +573,12 @@ static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst
571}; 573};
572 574
573static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = { 575static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
574 { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "cm2_dm10_mux" }, 576 { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" },
575 { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "cm2_dm11_mux" }, 577 { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" },
576 { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "cm2_dm2_mux" }, 578 { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" },
577 { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "cm2_dm3_mux" }, 579 { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" },
578 { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "cm2_dm4_mux" }, 580 { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" },
579 { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "cm2_dm9_mux" }, 581 { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" },
580 { OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" }, 582 { OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
581 { OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" }, 583 { OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
582 { OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" }, 584 { OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
@@ -589,14 +591,14 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
589 { OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 591 { OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
590 { OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 592 { OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
591 { OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" }, 593 { OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
592 { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "per_mcbsp4_gfclk" }, 594 { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" },
593 { OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 595 { OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
594 { OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 596 { OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
595 { OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 597 { OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
596 { OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 598 { OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
597 { OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 599 { OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
598 { OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 600 { OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
599 { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "slimbus2_fclk_0" }, 601 { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" },
600 { OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 602 { OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
601 { OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 603 { OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
602 { OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 604 { OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
@@ -619,7 +621,7 @@ static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initcon
619 { OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" }, 621 { OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
620 { OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 622 { OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
621 { OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" }, 623 { OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
622 { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "dmt1_clk_mux" }, 624 { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" },
623 { OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" }, 625 { OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
624 { OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 626 { OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
625 { 0 }, 627 { 0 },
@@ -633,7 +635,7 @@ static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
633}; 635};
634 636
635static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = { 637static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
636 "pmd_trace_clk_mux_ck", 638 "emu_sys_cm:clk:0000:22",
637 NULL, 639 NULL,
638}; 640};
639 641
@@ -651,12 +653,13 @@ static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __init
651}; 653};
652 654
653static const char * const omap4_stm_clk_div_ck_parents[] __initconst = { 655static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
654 "pmd_stm_clock_mux_ck", 656 "emu_sys_cm:clk:0000:20",
655 NULL, 657 NULL,
656}; 658};
657 659
658static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = { 660static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = {
659 .max_div = 64, 661 .max_div = 64,
662 .flags = CLK_DIVIDER_POWER_OF_TWO,
660}; 663};
661 664
662static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = { 665static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = {
@@ -697,52 +700,79 @@ const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
697}; 700};
698 701
699static struct ti_dt_clk omap44xx_clks[] = { 702static struct ti_dt_clk omap44xx_clks[] = {
700 DT_CLK("smp_twd", NULL, "mpu_periphclk"),
701 DT_CLK("omapdss_dss", "ick", "dss_fck"),
702 DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
703 DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
704 DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
705 DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
706 DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
707 DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
708 DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
709 DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
710 DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
711 DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
712 DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
713 DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
714 DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
715 DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
716 DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
717 DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
718 DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
719 DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
720 DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
721 DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
722 DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
723 DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
724 DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
725 DT_CLK(NULL, "uart1_ick", "dummy_ck"),
726 DT_CLK(NULL, "uart2_ick", "dummy_ck"),
727 DT_CLK(NULL, "uart3_ick", "dummy_ck"),
728 DT_CLK(NULL, "uart4_ick", "dummy_ck"),
729 DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
730 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
731 DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"),
732 DT_CLK("omap_wdt", "ick", "dummy_ck"),
733 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 703 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
734 DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"), 704 /*
735 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"), 705 * XXX: All the clock aliases below are only needed for legacy
736 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"), 706 * hwmod support. Once hwmod is removed, these can be removed
737 DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"), 707 * also.
738 DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"), 708 */
739 DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"), 709 DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"),
740 DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"), 710 DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"),
741 DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"), 711 DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"),
742 DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"), 712 DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"),
743 DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"), 713 DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"),
744 DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"), 714 DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"),
745 DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"), 715 DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"),
716 DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
717 DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"),
718 DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),
719 DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"),
720 DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"),
721 DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"),
722 DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"),
723 DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"),
724 DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"),
725 DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"),
726 DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"),
727 DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"),
728 DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"),
729 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"),
730 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"),
731 DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"),
732 DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"),
733 DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"),
734 DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"),
735 DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"),
736 DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"),
737 DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"),
738 DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"),
739 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
740 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
741 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
742 DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"),
743 DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"),
744 DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"),
745 DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"),
746 DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"),
747 DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"),
748 DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"),
749 DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"),
750 DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"),
751 DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"),
752 DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"),
753 DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"),
754 DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"),
755 DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"),
756 DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"),
757 DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"),
758 DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"),
759 DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"),
760 DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"),
761 DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"),
762 DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"),
763 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"),
764 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"),
765 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"),
766 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"),
767 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"),
768 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"),
769 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"),
770 DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"),
771 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"),
772 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"),
773 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"),
774 DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"),
775 DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"),
746 { .node_name = NULL }, 776 { .node_name = NULL },
747}; 777};
748 778
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index 294bc03ec067..a17b0c4646a1 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -16,6 +16,7 @@
16#include <linux/clkdev.h> 16#include <linux/clkdev.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/clk/ti.h> 18#include <linux/clk/ti.h>
19#include <dt-bindings/clock/omap5.h>
19 20
20#include "clock.h" 21#include "clock.h"
21 22
@@ -27,201 +28,511 @@
27 */ 28 */
28#define OMAP5_DPLL_USB_DEFFREQ 960000000 29#define OMAP5_DPLL_USB_DEFFREQ 960000000
29 30
31static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
32 { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
33 { 0 },
34};
35
36static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
37 { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h11x2_ck" },
38 { 0 },
39};
40
41static const char * const omap5_dmic_gfclk_parents[] __initconst = {
42 "abe_cm:clk:0018:26",
43 "pad_clks_ck",
44 "slimbus_clk",
45 NULL,
46};
47
48static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
49 "abe_24m_fclk",
50 "dss_syc_gfclk_div",
51 "func_24m_clk",
52 NULL,
53};
54
55static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
56 { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
57 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
58 { 0 },
59};
60
61static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
62 "abe_cm:clk:0028:26",
63 "pad_clks_ck",
64 "slimbus_clk",
65 NULL,
66};
67
68static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
69 { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
70 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
71 { 0 },
72};
73
74static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
75 "abe_cm:clk:0030:26",
76 "pad_clks_ck",
77 "slimbus_clk",
78 NULL,
79};
80
81static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
82 { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
83 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
84 { 0 },
85};
86
87static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
88 "abe_cm:clk:0038:26",
89 "pad_clks_ck",
90 "slimbus_clk",
91 NULL,
92};
93
94static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
95 { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
96 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
97 { 0 },
98};
99
100static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
101 "dss_syc_gfclk_div",
102 "sys_32k_ck",
103 NULL,
104};
105
106static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
107 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
108 { 0 },
109};
110
111static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
112 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
113 { 0 },
114};
115
116static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
117 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
118 { 0 },
119};
120
121static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
122 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
123 { 0 },
124};
125
126static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
127 { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
128 { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
129 { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
130 { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
131 { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
132 { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
133 { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
134 { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
135 { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
136 { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
137 { 0 },
138};
139
140static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
141 { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
142 { 0 },
143};
144
145static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
146 { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
147 { 0 },
148};
149
150static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
151 { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" },
152 { 0 },
153};
154
155static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
156 { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
157 { 0 },
158};
159
160static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
161 { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
162 { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
163 { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
164 { 0 },
165};
166
167static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
168 { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
169 { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
170 { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
171 { 0 },
172};
173
174static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
175 { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
176 { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
177 { 0 },
178};
179
180static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
181 "sys_clkin",
182 "sys_32k_ck",
183 NULL,
184};
185
186static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
187 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
188 { 0 },
189};
190
191static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
192 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
193 { 0 },
194};
195
196static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
197 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
198 { 0 },
199};
200
201static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
202 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
203 { 0 },
204};
205
206static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
207 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
208 { 0 },
209};
210
211static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
212 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
213 { 0 },
214};
215
216static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
217 "sys_32k_ck",
218 NULL,
219};
220
221static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
222 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
223 { 0 },
224};
225
226static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
227 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
228 { 0 },
229};
230
231static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
232 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
233 { 0 },
234};
235
236static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
237 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
238 { 0 },
239};
240
241static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
242 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
243 { 0 },
244};
245
246static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
247 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
248 { 0 },
249};
250
251static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
252 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
253 { 0 },
254};
255
256static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
257 { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
258 { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
259 { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
260 { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
261 { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
262 { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
263 { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
264 { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
265 { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
266 { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
267 { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
268 { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
269 { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
270 { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
271 { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
272 { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
273 { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
274 { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
275 { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
276 { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
277 { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
278 { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
279 { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
280 { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
281 { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
282 { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
283 { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
284 { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
285 { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
286 { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
287 { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
288 { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
289 { 0 },
290};
291
292static const char * const omap5_dss_dss_clk_parents[] __initconst = {
293 "dpll_per_h12x2_ck",
294 NULL,
295};
296
297static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
298 "func_48m_fclk",
299 NULL,
300};
301
302static const char * const omap5_dss_sys_clk_parents[] __initconst = {
303 "dss_syc_gfclk_div",
304 NULL,
305};
306
307static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
308 { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
309 { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
310 { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
311 { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
312 { 0 },
313};
314
315static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
316 { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
317 { 0 },
318};
319
320static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
321 "func_128m_clk",
322 "dpll_per_m2x2_ck",
323 NULL,
324};
325
326static const char * const omap5_mmc1_fclk_parents[] __initconst = {
327 "l3init_cm:clk:0008:24",
328 NULL,
329};
330
331static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
332 .max_div = 2,
333};
334
335static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
336 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
337 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
338 { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
339 { 0 },
340};
341
342static const char * const omap5_mmc2_fclk_parents[] __initconst = {
343 "l3init_cm:clk:0010:24",
344 NULL,
345};
346
347static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
348 .max_div = 2,
349};
350
351static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
352 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
353 { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
354 { 0 },
355};
356
357static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
358 "l3init_60m_fclk",
359 NULL,
360};
361
362static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
363 "dpll_usb_m2_ck",
364 NULL,
365};
366
367static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
368 "l3init_cm:clk:0038:24",
369 NULL,
370};
371
372static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
373 "l3init_cm:clk:0038:25",
374 NULL,
375};
376
377static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
378 "l3init_60m_fclk",
379 "xclk60mhsp1_ck",
380 NULL,
381};
382
383static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
384 "l3init_60m_fclk",
385 "xclk60mhsp2_ck",
386 NULL,
387};
388
389static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
390 { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
391 { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
392 { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
393 { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
394 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
395 { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
396 { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
397 { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
398 { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
399 { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
400 { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
401 { 0 },
402};
403
404static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
405 { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
406 { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
407 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
408 { 0 },
409};
410
411static const char * const omap5_sata_ref_clk_parents[] __initconst = {
412 "sys_clkin",
413 NULL,
414};
415
416static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
417 { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
418 { 0 },
419};
420
421static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
422 "dpll_usb_clkdcoldo",
423 NULL,
424};
425
426static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
427 { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
428 { 0 },
429};
430
431static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
432 { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
433 { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
434 { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
435 { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
436 { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
437 { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
438 { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
439 { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
440 { 0 },
441};
442
443static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
444 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
445 { 0 },
446};
447
448static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
449 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
450 { 0 },
451};
452
453static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
454 { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
455 { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
456 { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
457 { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
458 { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
459 { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
460 { 0 },
461};
462
463const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
464 { 0x4a004320, omap5_mpu_clkctrl_regs },
465 { 0x4a004420, omap5_dsp_clkctrl_regs },
466 { 0x4a004520, omap5_abe_clkctrl_regs },
467 { 0x4a008720, omap5_l3main1_clkctrl_regs },
468 { 0x4a008820, omap5_l3main2_clkctrl_regs },
469 { 0x4a008920, omap5_ipu_clkctrl_regs },
470 { 0x4a008a20, omap5_dma_clkctrl_regs },
471 { 0x4a008b20, omap5_emif_clkctrl_regs },
472 { 0x4a008d20, omap5_l4cfg_clkctrl_regs },
473 { 0x4a008e20, omap5_l3instr_clkctrl_regs },
474 { 0x4a009020, omap5_l4per_clkctrl_regs },
475 { 0x4a009420, omap5_dss_clkctrl_regs },
476 { 0x4a009620, omap5_l3init_clkctrl_regs },
477 { 0x4ae07920, omap5_wkupaon_clkctrl_regs },
478 { 0 },
479};
480
30static struct ti_dt_clk omap54xx_clks[] = { 481static struct ti_dt_clk omap54xx_clks[] = {
31 DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
32 DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
33 DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
34 DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
35 DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
36 DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
37 DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
38 DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
39 DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
40 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
41 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
42 DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
43 DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
44 DT_CLK(NULL, "sys_clkin", "sys_clkin"),
45 DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
46 DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
47 DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
48 DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
49 DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
50 DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
51 DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
52 DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
53 DT_CLK(NULL, "abe_clk", "abe_clk"),
54 DT_CLK(NULL, "abe_iclk", "abe_iclk"),
55 DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
56 DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
57 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
58 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
59 DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"),
60 DT_CLK(NULL, "c2c_fclk", "c2c_fclk"),
61 DT_CLK(NULL, "c2c_iclk", "c2c_iclk"),
62 DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
63 DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"),
64 DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
65 DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
66 DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
67 DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
68 DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
69 DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
70 DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
71 DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
72 DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
73 DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
74 DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
75 DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"),
76 DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"),
77 DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
78 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
79 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
80 DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
81 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
82 DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
83 DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
84 DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
85 DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
86 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
87 DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
88 DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
89 DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"),
90 DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"),
91 DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"),
92 DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"),
93 DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"),
94 DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"),
95 DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
96 DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
97 DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
98 DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
99 DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"),
100 DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
101 DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
102 DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
103 DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
104 DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
105 DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
106 DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"),
107 DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
108 DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
109 DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
110 DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
111 DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
112 DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
113 DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
114 DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
115 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
116 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
117 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
118 DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
119 DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
120 DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
121 DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
122 DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
123 DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
124 DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"),
125 DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"),
126 DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"),
127 DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
128 DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
129 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
130 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
131 DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"),
132 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
133 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
134 DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"),
135 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
136 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
137 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
138 DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"),
139 DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
140 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
141 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
142 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
143 DT_CLK(NULL, "aess_fclk", "aess_fclk"),
144 DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
145 DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"),
146 DT_CLK(NULL, "fdif_fclk", "fdif_fclk"),
147 DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
148 DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
149 DT_CLK(NULL, "hsi_fclk", "hsi_fclk"),
150 DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
151 DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"),
152 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
153 DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"),
154 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
155 DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"),
156 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
157 DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"),
158 DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
159 DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"),
160 DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
161 DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"),
162 DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
163 DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
164 DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
165 DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
166 DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
167 DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
168 DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
169 DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
170 DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
171 DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
172 DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
173 DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
174 DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
175 DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
176 DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
177 DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
178 DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
179 DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
180 DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
181 DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
182 DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
183 DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
184 DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
185 DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
186 DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
187 DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
188 DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
189 DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
190 DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
191 DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
192 DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
193 DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
194 DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
195 DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
196 DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
197 DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
198 DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
199 DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
200 DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
201 DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
202 DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
203 DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
204 DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
205 DT_CLK(NULL, "uart1_ick", "dummy_ck"),
206 DT_CLK(NULL, "uart2_ick", "dummy_ck"),
207 DT_CLK(NULL, "uart3_ick", "dummy_ck"),
208 DT_CLK(NULL, "uart4_ick", "dummy_ck"),
209 DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
210 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
211 DT_CLK("omap_wdt", "ick", "dummy_ck"),
212 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 482 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
213 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"), 483 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
214 DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin"), 484 DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
215 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin"), 485 DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
216 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin"), 486 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
217 DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin"), 487 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
218 DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin"), 488 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
219 DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin"), 489 DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
220 DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin"), 490 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
221 DT_CLK("40138000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), 491 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
222 DT_CLK("4013a000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), 492 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
223 DT_CLK("4013c000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), 493 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
224 DT_CLK("4013e000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), 494 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
495 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
496 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
497 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
498 DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
499 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
500 DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
501 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
502 DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
503 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
504 DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
505 DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
506 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
507 DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
508 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
509 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
510 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
511 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
512 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
513 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
514 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
515 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
516 DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
517 DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
518 DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
519 DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
520 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
521 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
522 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
523 DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
524 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
525 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
526 DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
527 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
528 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
529 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
530 DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
531 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
532 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
533 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
534 DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
535 DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
225 { .node_name = NULL }, 536 { .node_name = NULL },
226}; 537};
227 538
@@ -234,6 +545,8 @@ int __init omap5xxx_dt_clk_init(void)
234 545
235 omap2_clk_disable_autoidle_all(); 546 omap2_clk_disable_autoidle_all();
236 547
548 ti_clk_add_aliases();
549
237 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); 550 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
238 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); 551 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
239 rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); 552 rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 9fd6043314eb..fb249a1637a5 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -15,297 +15,809 @@
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/clkdev.h> 16#include <linux/clkdev.h>
17#include <linux/clk/ti.h> 17#include <linux/clk/ti.h>
18#include <dt-bindings/clock/dra7.h>
18 19
19#include "clock.h" 20#include "clock.h"
20 21
21#define DRA7_DPLL_GMAC_DEFFREQ 1000000000 22#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
22#define DRA7_DPLL_USB_DEFFREQ 960000000 23#define DRA7_DPLL_USB_DEFFREQ 960000000
23 24
25static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
26 { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
27 { 0 },
28};
29
30static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
31 "per_abe_x1_gfclk2_div",
32 "video1_clk2_div",
33 "video2_clk2_div",
34 "hdmi_clk2_div",
35 NULL,
36};
37
38static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
39 "abe_24m_fclk",
40 "abe_sys_clk_div",
41 "func_24m_clk",
42 "atl_clkin3_ck",
43 "atl_clkin2_ck",
44 "atl_clkin1_ck",
45 "atl_clkin0_ck",
46 "sys_clkin2",
47 "ref_clkin0_ck",
48 "ref_clkin1_ck",
49 "ref_clkin2_ck",
50 "ref_clkin3_ck",
51 "mlb_clk",
52 "mlbp_clk",
53 NULL,
54};
55
56static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
57 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
58 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
59 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
60 { 0 },
61};
62
63static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
64 "timer_sys_clk_div",
65 "sys_32k_ck",
66 "sys_clkin2",
67 "ref_clkin0_ck",
68 "ref_clkin1_ck",
69 "ref_clkin2_ck",
70 "ref_clkin3_ck",
71 "abe_giclk_div",
72 "video1_div_clk",
73 "video2_div_clk",
74 "hdmi_div_clk",
75 "clkoutmux0_clk_mux",
76 NULL,
77};
78
79static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
80 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
81 { 0 },
82};
83
84static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
85 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
86 { 0 },
87};
88
89static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
90 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
91 { 0 },
92};
93
94static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
95 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
96 { 0 },
97};
98
99static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
100 "func_48m_fclk",
101 "dpll_per_m2x2_ck",
102 NULL,
103};
104
105static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
106 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
107 { 0 },
108};
109
110static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
111 { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
112 { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
113 { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
114 { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
115 { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
116 { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
117 { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
118 { 0 },
119};
120
121static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
122 { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
123 { 0 },
124};
125
126static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
127 { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
128 { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
129 { 0 },
130};
131
132static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
133 { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
134 { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
135 { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
136 { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
137 { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
138 { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
139 { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
140 { 0 },
141};
142
143static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
144 { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
145 { 0 },
146};
147
148static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
149 { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
150 { 0 },
151};
152
153static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
154 "sys_32k_ck",
155 "video1_clkin_ck",
156 "video2_clkin_ck",
157 "hdmi_clkin_ck",
158 NULL,
159};
160
161static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
162 "l3_iclk_div",
163 "dpll_abe_m2_ck",
164 "atl_cm:clk:0000:24",
165 NULL,
166};
167
168static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
169 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
170 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
171 { 0 },
172};
173
174static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
175 { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
176 { 0 },
177};
178
179static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
180 { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
181 { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
182 { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
183 { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
184 { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
185 { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
186 { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
187 { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
188 { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
189 { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
190 { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
191 { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
192 { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
193 { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
194 { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
195 { 0 },
196};
197
198static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
199 { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
200 { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
201 { 0 },
202};
203
204static const char * const dra7_dss_dss_clk_parents[] __initconst = {
205 "dpll_per_h12x2_ck",
206 NULL,
207};
208
209static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
210 "func_48m_fclk",
211 NULL,
212};
213
214static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
215 "hdmi_dpll_clk_mux",
216 NULL,
217};
218
219static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
220 "sys_32k_ck",
221 NULL,
222};
223
224static const char * const dra7_dss_video1_clk_parents[] __initconst = {
225 "video1_dpll_clk_mux",
226 NULL,
227};
228
229static const char * const dra7_dss_video2_clk_parents[] __initconst = {
230 "video2_dpll_clk_mux",
231 NULL,
232};
233
234static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
235 { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
236 { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
237 { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
238 { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
239 { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
240 { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
241 { 0 },
242};
243
244static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
245 { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
246 { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
247 { 0 },
248};
249
250static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
251 "func_128m_clk",
252 "dpll_per_m2x2_ck",
253 NULL,
254};
255
256static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
257 "l3init_cm:clk:0008:24",
258 NULL,
259};
260
261static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
262 .max_div = 4,
263 .flags = CLK_DIVIDER_POWER_OF_TWO,
264};
265
266static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
267 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
268 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
269 { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
270 { 0 },
271};
272
273static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
274 "l3init_cm:clk:0010:24",
275 NULL,
276};
277
278static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
279 .max_div = 4,
280 .flags = CLK_DIVIDER_POWER_OF_TWO,
281};
282
283static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
284 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
285 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
286 { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
287 { 0 },
288};
289
290static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
291 "l3init_960m_gfclk",
292 NULL,
293};
294
295static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
296 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
297 { 0 },
298};
299
300static const char * const dra7_sata_ref_clk_parents[] __initconst = {
301 "sys_clkin1",
302 NULL,
303};
304
305static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
306 { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
307 { 0 },
308};
309
310static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
311 "apll_pcie_ck",
312 NULL,
313};
314
315static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
316 "optfclk_pciephy_div",
317 NULL,
318};
319
320static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
321 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
322 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
323 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
324 { 0 },
325};
326
327static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
328 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
329 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
330 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
331 { 0 },
332};
333
334static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
335 "dpll_gmac_h11x2_ck",
336 "rmii_clk_ck",
337 NULL,
338};
339
340static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
341 "video1_clkin_ck",
342 "video2_clkin_ck",
343 "dpll_abe_m2_ck",
344 "hdmi_clkin_ck",
345 "l3_iclk_div",
346 NULL,
347};
348
349static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
350 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
351 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
352 { 0 },
353};
354
355static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
356 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
357 { 0 },
358};
359
360static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
361 { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
362 { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
363 { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
364 { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
365 { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
366 { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
367 { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
368 { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
369 { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
370 { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
371 { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
372 { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
373 { 0 },
374};
375
376static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
377 "timer_sys_clk_div",
378 "sys_32k_ck",
379 "sys_clkin2",
380 "ref_clkin0_ck",
381 "ref_clkin1_ck",
382 "ref_clkin2_ck",
383 "ref_clkin3_ck",
384 "abe_giclk_div",
385 "video1_div_clk",
386 "video2_div_clk",
387 "hdmi_div_clk",
388 NULL,
389};
390
391static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
392 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
393 { 0 },
394};
395
396static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
397 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
398 { 0 },
399};
400
401static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
402 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
403 { 0 },
404};
405
406static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
407 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
408 { 0 },
409};
410
411static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
412 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
413 { 0 },
414};
415
416static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
417 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
418 { 0 },
419};
420
421static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
422 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
423 { 0 },
424};
425
426static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
427 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
428 { 0 },
429};
430
431static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
432 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
433 { 0 },
434};
435
436static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
437 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
438 { 0 },
439};
440
441static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
442 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
443 { 0 },
444};
445
446static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
447 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
448 { 0 },
449};
450
451static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
452 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
453 { 0 },
454};
455
456static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
457 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
458 { 0 },
459};
460
461static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
462 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
463 { 0 },
464};
465
466static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
467 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
468 { 0 },
469};
470
471static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
472 "l4per_cm:clk:0120:24",
473 NULL,
474};
475
476static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
477 .max_div = 4,
478 .flags = CLK_DIVIDER_POWER_OF_TWO,
479};
480
481static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
482 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
483 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
484 { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
485 { 0 },
486};
487
488static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
489 "l4per_cm:clk:0128:24",
490 NULL,
491};
492
493static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
494 .max_div = 4,
495 .flags = CLK_DIVIDER_POWER_OF_TWO,
496};
497
498static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
499 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
500 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
501 { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
502 { 0 },
503};
504
505static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
506 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
507 { 0 },
508};
509
510static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
511 "func_128m_clk",
512 "dpll_per_h13x2_ck",
513 NULL,
514};
515
516static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
517 "l4per_cm:clk:0138:24",
518 NULL,
519};
520
521static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
522 .max_div = 4,
523 .flags = CLK_DIVIDER_POWER_OF_TWO,
524};
525
526static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
527 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
528 { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
529 { 0 },
530};
531
532static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
533 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
534 { 0 },
535};
536
537static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
538 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
539 { 0 },
540};
541
542static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
543 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
544 { 0 },
545};
546
547static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
548 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
549 { 0 },
550};
551
552static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
553 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
554 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
555 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
556 { 0 },
557};
558
559static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
560 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
561 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
562 { 0 },
563};
564
565static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
566 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
567 { 0 },
568};
569
570static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
571 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
572 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
573 { 0 },
574};
575
576static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
577 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
578 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
579 { 0 },
580};
581
582static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
583 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
584 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
585 { 0 },
586};
587
588static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
589 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
590 { 0 },
591};
592
593static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
594 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
595 { 0 },
596};
597
598static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
599 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
600 { 0 },
601};
602
603static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
604 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
605 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
606 { 0 },
607};
608
609static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
610 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
611 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
612 { 0 },
613};
614
615static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
616 { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
617 { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
618 { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
619 { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
620 { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
621 { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
622 { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
623 { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
624 { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
625 { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
626 { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
627 { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
628 { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
629 { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
630 { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
631 { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
632 { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
633 { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
634 { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
635 { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
636 { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
637 { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
638 { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
639 { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
640 { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
641 { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
642 { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
643 { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
644 { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
645 { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
646 { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
647 { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
648 { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
649 { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
650 { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
651 { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
652 { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
653 { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
654 { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
655 { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
656 { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
657 { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
658 { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
659 { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
660 { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
661 { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
662 { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
663 { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
664 { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
665 { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
666 { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
667 { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
668 { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
669 { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
670 { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
671 { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
672 { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
673 { 0 },
674};
675
676static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
677 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
678 { 0 },
679};
680
681static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
682 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
683 { 0 },
684};
685
686static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
687 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
688 { 0 },
689};
690
691static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
692 "sys_clkin1",
693 "sys_clkin2",
694 NULL,
695};
696
697static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
698 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
699 { 0 },
700};
701
702static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
703 { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
704 { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
705 { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
706 { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
707 { DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
708 { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
709 { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
710 { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
711 { 0 },
712};
713
714const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
715 { 0x4a005320, dra7_mpu_clkctrl_regs },
716 { 0x4a005540, dra7_ipu_clkctrl_regs },
717 { 0x4a005740, dra7_rtc_clkctrl_regs },
718 { 0x4a008620, dra7_coreaon_clkctrl_regs },
719 { 0x4a008720, dra7_l3main1_clkctrl_regs },
720 { 0x4a008a20, dra7_dma_clkctrl_regs },
721 { 0x4a008b20, dra7_emif_clkctrl_regs },
722 { 0x4a008c00, dra7_atl_clkctrl_regs },
723 { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
724 { 0x4a008e20, dra7_l3instr_clkctrl_regs },
725 { 0x4a009120, dra7_dss_clkctrl_regs },
726 { 0x4a009320, dra7_l3init_clkctrl_regs },
727 { 0x4a009700, dra7_l4per_clkctrl_regs },
728 { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
729 { 0 },
730};
731
24static struct ti_dt_clk dra7xx_clks[] = { 732static struct ti_dt_clk dra7xx_clks[] = {
25 DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
26 DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"),
27 DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"),
28 DT_CLK(NULL, "atl_clkin3_ck", "atl_clkin3_ck"),
29 DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"),
30 DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"),
31 DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"),
32 DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"),
33 DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"),
34 DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"),
35 DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"),
36 DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"),
37 DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"),
38 DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"),
39 DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
40 DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
41 DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
42 DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
43 DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
44 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
45 DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"),
46 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
47 DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
48 DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
49 DT_CLK(NULL, "sys_clkin1", "sys_clkin1"),
50 DT_CLK(NULL, "sys_clkin2", "sys_clkin2"),
51 DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"),
52 DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"),
53 DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"),
54 DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"),
55 DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"),
56 DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"),
57 DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
58 DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
59 DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
60 DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
61 DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
62 DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
63 DT_CLK(NULL, "abe_clk", "abe_clk"),
64 DT_CLK(NULL, "aess_fclk", "aess_fclk"),
65 DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"),
66 DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
67 DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"),
68 DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"),
69 DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"),
70 DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"),
71 DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"),
72 DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"),
73 DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"),
74 DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"),
75 DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"),
76 DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"),
77 DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
78 DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"),
79 DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
80 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
81 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
82 DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
83 DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
84 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
85 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
86 DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"),
87 DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"),
88 DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"),
89 DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"),
90 DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"),
91 DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
92 DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
93 DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"),
94 DT_CLK(NULL, "iva_dclk", "iva_dclk"),
95 DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"),
96 DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"),
97 DT_CLK(NULL, "gpu_dclk", "gpu_dclk"),
98 DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
99 DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"),
100 DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
101 DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
102 DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"),
103 DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"),
104 DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"),
105 DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"),
106 DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"),
107 DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"),
108 DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"),
109 DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
110 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
111 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
112 DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"),
113 DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
114 DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
115 DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
116 DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"),
117 DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"),
118 DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"),
119 DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"),
120 DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"),
121 DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"),
122 DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"),
123 DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"),
124 DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"),
125 DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"),
126 DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"),
127 DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"),
128 DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"),
129 DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"),
130 DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"),
131 DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
132 DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
133 DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
134 DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
135 DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
136 DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
137 DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
138 DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"),
139 DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"),
140 DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"),
141 DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"),
142 DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"),
143 DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"),
144 DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"),
145 DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"),
146 DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
147 DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
148 DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
149 DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"),
150 DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
151 DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
152 DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
153 DT_CLK(NULL, "eve_clk", "eve_clk"),
154 DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
155 DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
156 DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
157 DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
158 DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
159 DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"),
160 DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"),
161 DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"),
162 DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"),
163 DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
164 DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
165 DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
166 DT_CLK(NULL, "mlb_clk", "mlb_clk"),
167 DT_CLK(NULL, "mlbp_clk", "mlbp_clk"),
168 DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"),
169 DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"),
170 DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"),
171 DT_CLK(NULL, "video1_div_clk", "video1_div_clk"),
172 DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"),
173 DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"),
174 DT_CLK(NULL, "video2_div_clk", "video2_div_clk"),
175 DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"),
176 DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
177 DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
178 DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
179 DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
180 DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"),
181 DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"),
182 DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"),
183 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
184 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
185 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
186 DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
187 DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
188 DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
189 DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
190 DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
191 DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"),
192 DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"),
193 DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"),
194 DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"),
195 DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
196 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"),
197 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"),
198 DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"),
199 DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"),
200 DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"),
201 DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"),
202 DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"),
203 DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"),
204 DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"),
205 DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
206 DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
207 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"),
208 DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
209 DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"),
210 DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"),
211 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"),
212 DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"),
213 DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"),
214 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"),
215 DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"),
216 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"),
217 DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"),
218 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"),
219 DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"),
220 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"),
221 DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"),
222 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
223 DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
224 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
225 DT_CLK(NULL, "mcasp8_ahclkx_mux", "mcasp8_ahclkx_mux"),
226 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
227 DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
228 DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
229 DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
230 DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"),
231 DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"),
232 DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"),
233 DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"),
234 DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"),
235 DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"),
236 DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"),
237 DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
238 DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
239 DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"),
240 DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"),
241 DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"),
242 DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"),
243 DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
244 DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
245 DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
246 DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
247 DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
248 DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
249 DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
250 DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
251 DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
252 DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"),
253 DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"),
254 DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"),
255 DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"),
256 DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"),
257 DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"),
258 DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"),
259 DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"),
260 DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"),
261 DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"),
262 DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"),
263 DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"),
264 DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"),
265 DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
266 DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
267 DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
268 DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
269 DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
270 DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
271 DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
272 DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
273 DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
274 DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
275 DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
276 DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
277 DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
278 DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
279 DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
280 DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
281 DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
282 DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
283 DT_CLK(NULL, "uart1_ick", "dummy_ck"),
284 DT_CLK(NULL, "uart2_ick", "dummy_ck"),
285 DT_CLK(NULL, "uart3_ick", "dummy_ck"),
286 DT_CLK(NULL, "uart4_ick", "dummy_ck"),
287 DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
288 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
289 DT_CLK("omap_wdt", "ick", "dummy_ck"),
290 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 733 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
291 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"), 734 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
292 DT_CLK("4ae18000.timer", "timer_sys_ck", "timer_sys_clk_div"),
293 DT_CLK("48032000.timer", "timer_sys_ck", "timer_sys_clk_div"),
294 DT_CLK("48034000.timer", "timer_sys_ck", "timer_sys_clk_div"),
295 DT_CLK("48036000.timer", "timer_sys_ck", "timer_sys_clk_div"),
296 DT_CLK("4803e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
297 DT_CLK("48086000.timer", "timer_sys_ck", "timer_sys_clk_div"),
298 DT_CLK("48088000.timer", "timer_sys_ck", "timer_sys_clk_div"),
299 DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
300 DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
301 DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
302 DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
303 DT_CLK("48828000.timer", "timer_sys_ck", "timer_sys_clk_div"),
304 DT_CLK("4882a000.timer", "timer_sys_ck", "timer_sys_clk_div"),
305 DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),
306 DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
307 DT_CLK(NULL, "sys_clkin", "sys_clkin1"), 735 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
308 DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"), 736 DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
737 DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
738 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
739 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
740 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
741 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
742 DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
743 DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
744 DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
745 DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
746 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
747 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
748 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
749 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
750 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
751 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
752 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
753 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
754 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
755 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
756 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
757 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
758 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
759 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
760 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
761 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
762 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
763 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
764 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
765 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
766 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
767 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
768 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
769 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
770 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
771 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
772 DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
773 DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
774 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
775 DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
776 DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
777 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
778 DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
779 DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
780 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
781 DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
782 DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
783 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
784 DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
785 DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
786 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
787 DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
788 DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
789 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
790 DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
791 DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
792 DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
793 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
794 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
795 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
796 DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
797 DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
798 DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
799 DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
800 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
801 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
802 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
803 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
804 DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
805 DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
806 DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
807 DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
808 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
809 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
810 DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
811 DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
812 DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
813 DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
814 DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
815 DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
816 DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
817 DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
818 DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
819 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
820 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
309 { .node_name = NULL }, 821 { .node_name = NULL },
310}; 822};
311 823
@@ -318,6 +830,8 @@ int __init dra7xx_dt_clk_init(void)
318 830
319 omap2_clk_disable_autoidle_all(); 831 omap2_clk_disable_autoidle_all();
320 832
833 ti_clk_add_aliases();
834
321 dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); 835 dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
322 rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); 836 rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
323 if (rc) 837 if (rc)
diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c
index 52c6efc53731..f688fdd2cb59 100644
--- a/drivers/clk/ti/clk-814x.c
+++ b/drivers/clk/ti/clk-814x.c
@@ -9,23 +9,48 @@
9#include <linux/clk-provider.h> 9#include <linux/clk-provider.h>
10#include <linux/clk/ti.h> 10#include <linux/clk/ti.h>
11#include <linux/of_platform.h> 11#include <linux/of_platform.h>
12#include <dt-bindings/clock/dm814.h>
12 13
13#include "clock.h" 14#include "clock.h"
14 15
16static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = {
17 { DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" },
18 { 0 },
19};
20
21static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = {
22 { DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
23 { DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
24 { DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
25 { DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
26 { DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
27 { DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
28 { DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
29 { DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
30 { DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
31 { DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
32 { DM814_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
33 { DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
34 { DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
35 { DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
36 { DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
37 { DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
38 { DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
39 { DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
40 { DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
41 { DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
42 { DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
43 { 0 },
44};
45
46const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
47 { 0x48180500, dm814_default_clkctrl_regs },
48 { 0x48181400, dm814_alwon_clkctrl_regs },
49 { 0 },
50};
51
15static struct ti_dt_clk dm814_clks[] = { 52static struct ti_dt_clk dm814_clks[] = {
16 DT_CLK(NULL, "devosc_ck", "devosc_ck"),
17 DT_CLK(NULL, "mpu_ck", "mpu_ck"),
18 DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
19 DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
20 DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
21 DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"),
22 DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
23 DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
24 DT_CLK(NULL, "timer_sys_ck", "devosc_ck"), 53 DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
25 DT_CLK(NULL, "timer1_fck", "timer1_fck"),
26 DT_CLK(NULL, "timer2_fck", "timer2_fck"),
27 DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
28 DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
29 { .node_name = NULL }, 54 { .node_name = NULL },
30}; 55};
31 56
@@ -83,6 +108,7 @@ int __init dm814x_dt_clk_init(void)
83{ 108{
84 ti_dt_clocks_register(dm814_clks); 109 ti_dt_clocks_register(dm814_clks);
85 omap2_clk_disable_autoidle_all(); 110 omap2_clk_disable_autoidle_all();
111 ti_clk_add_aliases();
86 omap2_clk_enable_init_clocks(NULL, 0); 112 omap2_clk_enable_init_clocks(NULL, 0);
87 timer_clocks_initialized = true; 113 timer_clocks_initialized = true;
88 114
diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c
index 2a5d84fdddc5..7d215cdf9dda 100644
--- a/drivers/clk/ti/clk-816x.c
+++ b/drivers/clk/ti/clk-816x.c
@@ -13,30 +13,59 @@
13#include <linux/list.h> 13#include <linux/list.h>
14#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
15#include <linux/clk/ti.h> 15#include <linux/clk/ti.h>
16#include <dt-bindings/clock/dm816.h>
16 17
17#include "clock.h" 18#include "clock.h"
18 19
20static const struct omap_clkctrl_reg_data dm816_default_clkctrl_regs[] __initconst = {
21 { DM816_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
22 { 0 },
23};
24
25static const struct omap_clkctrl_reg_data dm816_alwon_clkctrl_regs[] __initconst = {
26 { DM816_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
27 { DM816_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
28 { DM816_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
29 { DM816_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
30 { DM816_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
31 { DM816_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
32 { DM816_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
33 { DM816_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
34 { DM816_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
35 { DM816_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
36 { DM816_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
37 { DM816_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
38 { DM816_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
39 { DM816_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
40 { DM816_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
41 { DM816_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
42 { DM816_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
43 { DM816_SPINBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
44 { DM816_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
45 { DM816_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
46 { DM816_DAVINCI_MDIO_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
47 { DM816_EMAC1_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
48 { DM816_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk2_ck" },
49 { DM816_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
50 { DM816_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
51 { DM816_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
52 { DM816_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
53 { DM816_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
54 { DM816_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
55 { 0 },
56};
57
58const struct omap_clkctrl_data dm816_clkctrl_data[] __initconst = {
59 { 0x48180500, dm816_default_clkctrl_regs },
60 { 0x48181400, dm816_alwon_clkctrl_regs },
61 { 0 },
62};
63
19static struct ti_dt_clk dm816x_clks[] = { 64static struct ti_dt_clk dm816x_clks[] = {
20 DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), 65 DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),
21 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 66 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
22 DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
23 DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"), 67 DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
24 DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"), 68 DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
25 DT_CLK(NULL, "mpu_ck", "mpu_ck"),
26 DT_CLK(NULL, "timer1_fck", "timer1_fck"),
27 DT_CLK(NULL, "timer2_fck", "timer2_fck"),
28 DT_CLK(NULL, "timer3_fck", "timer3_fck"),
29 DT_CLK(NULL, "timer4_fck", "timer4_fck"),
30 DT_CLK(NULL, "timer5_fck", "timer5_fck"),
31 DT_CLK(NULL, "timer6_fck", "timer6_fck"),
32 DT_CLK(NULL, "timer7_fck", "timer7_fck"),
33 DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
34 DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
35 DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
36 DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
37 DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
38 DT_CLK(NULL, "sysclk24_ck", "sysclk24_ck"),
39 DT_CLK("4a100000.ethernet", "sysclk24_ck", "sysclk24_ck"),
40 { .node_name = NULL }, 69 { .node_name = NULL },
41}; 70};
42 71
@@ -50,6 +79,7 @@ int __init dm816x_dt_clk_init(void)
50{ 79{
51 ti_dt_clocks_register(dm816x_clks); 80 ti_dt_clocks_register(dm816x_clks);
52 omap2_clk_disable_autoidle_all(); 81 omap2_clk_disable_autoidle_all();
82 ti_clk_add_aliases();
53 omap2_clk_enable_init_clocks(enable_init_clks, 83 omap2_clk_enable_init_clocks(enable_init_clks,
54 ARRAY_SIZE(enable_init_clks)); 84 ARRAY_SIZE(enable_init_clks));
55 85
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index e5a1c8297a1d..302c9e64e5fa 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -108,25 +108,77 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
108 struct device_node *node; 108 struct device_node *node;
109 struct clk *clk; 109 struct clk *clk;
110 struct of_phandle_args clkspec; 110 struct of_phandle_args clkspec;
111 char buf[64];
112 char *ptr;
113 char *tags[2];
114 int i;
115 int num_args;
116 int ret;
117 static bool clkctrl_nodes_missing;
118 static bool has_clkctrl_data;
111 119
112 for (c = oclks; c->node_name != NULL; c++) { 120 for (c = oclks; c->node_name != NULL; c++) {
113 node = of_find_node_by_name(NULL, c->node_name); 121 strcpy(buf, c->node_name);
122 ptr = buf;
123 for (i = 0; i < 2; i++)
124 tags[i] = NULL;
125 num_args = 0;
126 while (*ptr) {
127 if (*ptr == ':') {
128 if (num_args >= 2) {
129 pr_warn("Bad number of tags on %s\n",
130 c->node_name);
131 return;
132 }
133 tags[num_args++] = ptr + 1;
134 *ptr = 0;
135 }
136 ptr++;
137 }
138
139 if (num_args && clkctrl_nodes_missing)
140 continue;
141
142 node = of_find_node_by_name(NULL, buf);
143 if (num_args)
144 node = of_find_node_by_name(node, "clk");
114 clkspec.np = node; 145 clkspec.np = node;
146 clkspec.args_count = num_args;
147 for (i = 0; i < num_args; i++) {
148 ret = kstrtoint(tags[i], i ? 10 : 16, clkspec.args + i);
149 if (ret) {
150 pr_warn("Bad tag in %s at %d: %s\n",
151 c->node_name, i, tags[i]);
152 return;
153 }
154 }
115 clk = of_clk_get_from_provider(&clkspec); 155 clk = of_clk_get_from_provider(&clkspec);
116 156
117 if (!IS_ERR(clk)) { 157 if (!IS_ERR(clk)) {
118 c->lk.clk = clk; 158 c->lk.clk = clk;
119 clkdev_add(&c->lk); 159 clkdev_add(&c->lk);
120 } else { 160 } else {
121 pr_warn("failed to lookup clock node %s\n", 161 if (num_args && !has_clkctrl_data) {
122 c->node_name); 162 if (of_find_compatible_node(NULL, NULL,
163 "ti,clkctrl")) {
164 has_clkctrl_data = true;
165 } else {
166 clkctrl_nodes_missing = true;
167
168 pr_warn("missing clkctrl nodes, please update your dts.\n");
169 continue;
170 }
171 }
172
173 pr_warn("failed to lookup clock node %s, ret=%ld\n",
174 c->node_name, PTR_ERR(clk));
123 } 175 }
124 } 176 }
125} 177}
126 178
127struct clk_init_item { 179struct clk_init_item {
128 struct device_node *node; 180 struct device_node *node;
129 struct clk_hw *hw; 181 void *user;
130 ti_of_clk_init_cb_t func; 182 ti_of_clk_init_cb_t func;
131 struct list_head link; 183 struct list_head link;
132}; 184};
@@ -136,14 +188,14 @@ static LIST_HEAD(retry_list);
136/** 188/**
137 * ti_clk_retry_init - retries a failed clock init at later phase 189 * ti_clk_retry_init - retries a failed clock init at later phase
138 * @node: device not for the clock 190 * @node: device not for the clock
139 * @hw: partially initialized clk_hw struct for the clock 191 * @user: user data pointer
140 * @func: init function to be called for the clock 192 * @func: init function to be called for the clock
141 * 193 *
142 * Adds a failed clock init to the retry list. The retry list is parsed 194 * Adds a failed clock init to the retry list. The retry list is parsed
143 * once all the other clocks have been initialized. 195 * once all the other clocks have been initialized.
144 */ 196 */
145int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, 197int __init ti_clk_retry_init(struct device_node *node, void *user,
146 ti_of_clk_init_cb_t func) 198 ti_of_clk_init_cb_t func)
147{ 199{
148 struct clk_init_item *retry; 200 struct clk_init_item *retry;
149 201
@@ -154,7 +206,7 @@ int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
154 206
155 retry->node = node; 207 retry->node = node;
156 retry->func = func; 208 retry->func = func;
157 retry->hw = hw; 209 retry->user = user;
158 list_add(&retry->link, &retry_list); 210 list_add(&retry->link, &retry_list);
159 211
160 return 0; 212 return 0;
@@ -276,7 +328,7 @@ void ti_dt_clk_init_retry_clks(void)
276 while (!list_empty(&retry_list) && retries) { 328 while (!list_empty(&retry_list) && retries) {
277 list_for_each_entry_safe(retry, tmp, &retry_list, link) { 329 list_for_each_entry_safe(retry, tmp, &retry_list, link) {
278 pr_debug("retry-init: %s\n", retry->node->name); 330 pr_debug("retry-init: %s\n", retry->node->name);
279 retry->func(retry->hw, retry->node); 331 retry->func(retry->user, retry->node);
280 list_del(&retry->link); 332 list_del(&retry->link);
281 kfree(retry); 333 kfree(retry);
282 } 334 }
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 53e71d0503ec..afa0d6bfc5c1 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -21,6 +21,7 @@
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/clk/ti.h> 22#include <linux/clk/ti.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/timekeeping.h>
24#include "clock.h" 25#include "clock.h"
25 26
26#define NO_IDLEST 0x1 27#define NO_IDLEST 0x1
@@ -46,6 +47,7 @@ static bool _early_timeout = true;
46struct omap_clkctrl_provider { 47struct omap_clkctrl_provider {
47 void __iomem *base; 48 void __iomem *base;
48 struct list_head clocks; 49 struct list_head clocks;
50 char *clkdm_name;
49}; 51};
50 52
51struct omap_clkctrl_clk { 53struct omap_clkctrl_clk {
@@ -89,7 +91,18 @@ static bool _omap4_is_ready(u32 val)
89 91
90static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout) 92static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
91{ 93{
92 if (unlikely(_early_timeout)) { 94 /*
95 * There are two special cases where ktime_to_ns() can't be
96 * used to track the timeouts. First one is during early boot
97 * when the timers haven't been initialized yet. The second
98 * one is during suspend-resume cycle while timekeeping is
99 * being suspended / resumed. Clocksource for the system
100 * can be from a timer that requires pm_runtime access, which
101 * will eventually bring us here with timekeeping_suspended,
102 * during both suspend entry and resume paths. This happens
103 * at least on am43xx platform.
104 */
105 if (unlikely(_early_timeout || timekeeping_suspended)) {
93 if (time->cycles++ < timeout) { 106 if (time->cycles++ < timeout) {
94 udelay(1); 107 udelay(1);
95 return false; 108 return false;
@@ -208,6 +221,7 @@ static const struct clk_ops omap4_clkctrl_clk_ops = {
208 .enable = _omap4_clkctrl_clk_enable, 221 .enable = _omap4_clkctrl_clk_enable,
209 .disable = _omap4_clkctrl_clk_disable, 222 .disable = _omap4_clkctrl_clk_disable,
210 .is_enabled = _omap4_clkctrl_clk_is_enabled, 223 .is_enabled = _omap4_clkctrl_clk_is_enabled,
224 .init = omap2_init_clk_clkdm,
211}; 225};
212 226
213static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec, 227static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
@@ -321,6 +335,9 @@ _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
321 } 335 }
322 336
323 mux->mask = num_parents; 337 mux->mask = num_parents;
338 if (!(mux->flags & CLK_MUX_INDEX_ONE))
339 mux->mask--;
340
324 mux->mask = (1 << fls(mux->mask)) - 1; 341 mux->mask = (1 << fls(mux->mask)) - 1;
325 342
326 mux->shift = data->bit; 343 mux->shift = data->bit;
@@ -340,6 +357,7 @@ _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
340{ 357{
341 struct clk_omap_divider *div; 358 struct clk_omap_divider *div;
342 const struct omap_clkctrl_div_data *div_data = data->data; 359 const struct omap_clkctrl_div_data *div_data = data->data;
360 u8 div_flags = 0;
343 361
344 div = kzalloc(sizeof(*div), GFP_KERNEL); 362 div = kzalloc(sizeof(*div), GFP_KERNEL);
345 if (!div) 363 if (!div)
@@ -347,12 +365,16 @@ _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
347 365
348 div->reg.ptr = reg; 366 div->reg.ptr = reg;
349 div->shift = data->bit; 367 div->shift = data->bit;
368 div->flags = div_data->flags;
369
370 if (div->flags & CLK_DIVIDER_POWER_OF_TWO)
371 div_flags |= CLKF_INDEX_POWER_OF_TWO;
350 372
351 if (ti_clk_parse_divider_data((int *)div_data->dividers, 373 if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,
352 div_data->max_div, 0, 0, 374 div_data->max_div, div_flags,
353 &div->width, &div->table)) { 375 &div->width, &div->table)) {
354 pr_err("%s: Data parsing for %s:%04x:%d failed\n", __func__, 376 pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__,
355 node->name, offset, data->bit); 377 node, offset, data->bit);
356 kfree(div); 378 kfree(div);
357 return; 379 return;
358 } 380 }
@@ -400,6 +422,12 @@ _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
400 } 422 }
401} 423}
402 424
425static void __init _clkctrl_add_provider(void *data,
426 struct device_node *np)
427{
428 of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data);
429}
430
403static void __init _ti_omap4_clkctrl_setup(struct device_node *node) 431static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
404{ 432{
405 struct omap_clkctrl_provider *provider; 433 struct omap_clkctrl_provider *provider;
@@ -411,6 +439,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
411 struct omap_clkctrl_clk *clkctrl_clk; 439 struct omap_clkctrl_clk *clkctrl_clk;
412 const __be32 *addrp; 440 const __be32 *addrp;
413 u32 addr; 441 u32 addr;
442 int ret;
414 443
415 addrp = of_get_address(node, 0, NULL, NULL); 444 addrp = of_get_address(node, 0, NULL, NULL);
416 addr = (u32)of_translate_address(node, addrp); 445 addr = (u32)of_translate_address(node, addrp);
@@ -419,6 +448,31 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
419 if (of_machine_is_compatible("ti,omap4")) 448 if (of_machine_is_compatible("ti,omap4"))
420 data = omap4_clkctrl_data; 449 data = omap4_clkctrl_data;
421#endif 450#endif
451#ifdef CONFIG_SOC_OMAP5
452 if (of_machine_is_compatible("ti,omap5"))
453 data = omap5_clkctrl_data;
454#endif
455#ifdef CONFIG_SOC_DRA7XX
456 if (of_machine_is_compatible("ti,dra7"))
457 data = dra7_clkctrl_data;
458#endif
459#ifdef CONFIG_SOC_AM33XX
460 if (of_machine_is_compatible("ti,am33xx"))
461 data = am3_clkctrl_data;
462#endif
463#ifdef CONFIG_SOC_AM43XX
464 if (of_machine_is_compatible("ti,am4372"))
465 data = am4_clkctrl_data;
466 if (of_machine_is_compatible("ti,am438x"))
467 data = am438x_clkctrl_data;
468#endif
469#ifdef CONFIG_SOC_TI81XX
470 if (of_machine_is_compatible("ti,dm814"))
471 data = dm814_clkctrl_data;
472
473 if (of_machine_is_compatible("ti,dm816"))
474 data = dm816_clkctrl_data;
475#endif
422 476
423 while (data->addr) { 477 while (data->addr) {
424 if (addr == data->addr) 478 if (addr == data->addr)
@@ -428,7 +482,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
428 } 482 }
429 483
430 if (!data->addr) { 484 if (!data->addr) {
431 pr_err("%s not found from clkctrl data.\n", node->name); 485 pr_err("%pOF not found from clkctrl data.\n", node);
432 return; 486 return;
433 } 487 }
434 488
@@ -438,6 +492,21 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
438 492
439 provider->base = of_iomap(node, 0); 493 provider->base = of_iomap(node, 0);
440 494
495 provider->clkdm_name = kmalloc(strlen(node->parent->name) + 3,
496 GFP_KERNEL);
497 if (!provider->clkdm_name) {
498 kfree(provider);
499 return;
500 }
501
502 /*
503 * Create default clkdm name, replace _cm from end of parent node
504 * name with _clkdm
505 */
506 strcpy(provider->clkdm_name, node->parent->name);
507 provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
508 strcat(provider->clkdm_name, "clkdm");
509
441 INIT_LIST_HEAD(&provider->clocks); 510 INIT_LIST_HEAD(&provider->clocks);
442 511
443 /* Generate clocks */ 512 /* Generate clocks */
@@ -460,6 +529,11 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
460 if (reg_data->flags & CLKF_NO_IDLEST) 529 if (reg_data->flags & CLKF_NO_IDLEST)
461 hw->flags |= NO_IDLEST; 530 hw->flags |= NO_IDLEST;
462 531
532 if (reg_data->clkdm_name)
533 hw->clkdm_name = reg_data->clkdm_name;
534 else
535 hw->clkdm_name = provider->clkdm_name;
536
463 init.parent_names = &reg_data->parent; 537 init.parent_names = &reg_data->parent;
464 init.num_parents = 1; 538 init.num_parents = 1;
465 init.flags = 0; 539 init.flags = 0;
@@ -485,7 +559,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
485 reg_data++; 559 reg_data++;
486 } 560 }
487 561
488 of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider); 562 ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
563 if (ret == -EPROBE_DEFER)
564 ti_clk_retry_init(node, provider, _clkctrl_add_provider);
565
489 return; 566 return;
490 567
491cleanup: 568cleanup:
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 561dbe99ced7..883e39e5d3ec 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -207,6 +207,7 @@ struct ti_dt_clk {
207struct omap_clkctrl_div_data { 207struct omap_clkctrl_div_data {
208 const int *dividers; 208 const int *dividers;
209 int max_div; 209 int max_div;
210 u32 flags;
210}; 211};
211 212
212struct omap_clkctrl_bit_data { 213struct omap_clkctrl_bit_data {
@@ -221,6 +222,7 @@ struct omap_clkctrl_reg_data {
221 const struct omap_clkctrl_bit_data *bit_data; 222 const struct omap_clkctrl_bit_data *bit_data;
222 u16 flags; 223 u16 flags;
223 const char *parent; 224 const char *parent;
225 const char *clkdm_name;
224}; 226};
225 227
226struct omap_clkctrl_data { 228struct omap_clkctrl_data {
@@ -229,12 +231,19 @@ struct omap_clkctrl_data {
229}; 231};
230 232
231extern const struct omap_clkctrl_data omap4_clkctrl_data[]; 233extern const struct omap_clkctrl_data omap4_clkctrl_data[];
234extern const struct omap_clkctrl_data omap5_clkctrl_data[];
235extern const struct omap_clkctrl_data dra7_clkctrl_data[];
236extern const struct omap_clkctrl_data am3_clkctrl_data[];
237extern const struct omap_clkctrl_data am4_clkctrl_data[];
238extern const struct omap_clkctrl_data am438x_clkctrl_data[];
239extern const struct omap_clkctrl_data dm814_clkctrl_data[];
240extern const struct omap_clkctrl_data dm816_clkctrl_data[];
232 241
233#define CLKF_SW_SUP BIT(0) 242#define CLKF_SW_SUP BIT(0)
234#define CLKF_HW_SUP BIT(1) 243#define CLKF_HW_SUP BIT(1)
235#define CLKF_NO_IDLEST BIT(2) 244#define CLKF_NO_IDLEST BIT(2)
236 245
237typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); 246typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
238 247
239struct clk *ti_clk_register_gate(struct ti_clk *setup); 248struct clk *ti_clk_register_gate(struct ti_clk *setup);
240struct clk *ti_clk_register_interface(struct ti_clk *setup); 249struct clk *ti_clk_register_interface(struct ti_clk *setup);
@@ -262,7 +271,7 @@ int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
262int ti_clk_get_reg_addr(struct device_node *node, int index, 271int ti_clk_get_reg_addr(struct device_node *node, int index,
263 struct clk_omap_reg *reg); 272 struct clk_omap_reg *reg);
264void ti_dt_clocks_register(struct ti_dt_clk *oclks); 273void ti_dt_clocks_register(struct ti_dt_clk *oclks);
265int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, 274int ti_clk_retry_init(struct device_node *node, void *user,
266 ti_of_clk_init_cb_t func); 275 ti_of_clk_init_cb_t func);
267int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); 276int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
268 277
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index beea89463ca2..3eaba2d16ce4 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -161,9 +161,10 @@ struct clk *ti_clk_register_composite(struct ti_clk *setup)
161} 161}
162#endif 162#endif
163 163
164static void __init _register_composite(struct clk_hw *hw, 164static void __init _register_composite(void *user,
165 struct device_node *node) 165 struct device_node *node)
166{ 166{
167 struct clk_hw *hw = user;
167 struct clk *clk; 168 struct clk *clk;
168 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); 169 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
169 struct component_clk *comp; 170 struct component_clk *comp;
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index d4e4444bc5ca..d246598c5016 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -152,9 +152,10 @@ static const struct clk_ops dpll_x2_ck_ops = {
152 * clk-bypass is missing), the clock is added to retry list and 152 * clk-bypass is missing), the clock is added to retry list and
153 * the initialization is retried on later stage. 153 * the initialization is retried on later stage.
154 */ 154 */
155static void __init _register_dpll(struct clk_hw *hw, 155static void __init _register_dpll(void *user,
156 struct device_node *node) 156 struct device_node *node)
157{ 157{
158 struct clk_hw *hw = user;
158 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 159 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
159 struct dpll_data *dd = clk_hw->dpll_data; 160 struct dpll_data *dd = clk_hw->dpll_data;
160 struct clk *clk; 161 struct clk *clk;
diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h
new file mode 100644
index 000000000000..b396f00e481d
--- /dev/null
+++ b/include/dt-bindings/clock/am3.h
@@ -0,0 +1,108 @@
1/*
2 * Copyright 2017 Texas Instruments, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __DT_BINDINGS_CLK_AM3_H
14#define __DT_BINDINGS_CLK_AM3_H
15
16#define AM3_CLKCTRL_OFFSET 0x0
17#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
18
19/* l4_per clocks */
20#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
21#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
22#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
23#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
24#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
25#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
26#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
27#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
28#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
29#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
30#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38)
31#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c)
32#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40)
33#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44)
34#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48)
35#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c)
36#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50)
37#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60)
38#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68)
39#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c)
40#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70)
41#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74)
42#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78)
43#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c)
44#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80)
45#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84)
46#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88)
47#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90)
48#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94)
49#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0)
50#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac)
51#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0)
52#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4)
53#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc)
54#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0)
55#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4)
56#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc)
57#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4)
58#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8)
59#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc)
60#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0)
61#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8)
62#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec)
63#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0)
64#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4)
65#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8)
66#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc)
67#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100)
68#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c)
69#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110)
70#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120)
71#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130)
72#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c)
73
74/* l4_wkup clocks */
75#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4
76#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
77#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
78#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
79#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
80#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
81#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
82#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
83#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
84#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
85#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
86#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
87#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
88#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
89
90/* mpu clocks */
91#define AM3_MPU_CLKCTRL_OFFSET 0x4
92#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET)
93#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4)
94
95/* l4_rtc clocks */
96#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
97
98/* gfx_l3 clocks */
99#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4
100#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
101#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4)
102
103/* l4_cefuse clocks */
104#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20
105#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
106#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
107
108#endif
diff --git a/include/dt-bindings/clock/am4.h b/include/dt-bindings/clock/am4.h
new file mode 100644
index 000000000000..d21df00b3270
--- /dev/null
+++ b/include/dt-bindings/clock/am4.h
@@ -0,0 +1,113 @@
1/*
2 * Copyright 2017 Texas Instruments, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __DT_BINDINGS_CLK_AM4_H
14#define __DT_BINDINGS_CLK_AM4_H
15
16#define AM4_CLKCTRL_OFFSET 0x20
17#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
18
19/* l4_wkup clocks */
20#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
21#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
22#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
23#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
24#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
25#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
26#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
27#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
28#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
29#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358)
30#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360)
31#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368)
32
33/* mpu clocks */
34#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
35
36/* gfx_l3 clocks */
37#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
38
39/* l4_rtc clocks */
40#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
41
42/* l4_per clocks */
43#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
44#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
45#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
46#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
47#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
48#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
49#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68)
50#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70)
51#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
52#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
53#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
54#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
55#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
56#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
57#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238)
58#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240)
59#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248)
60#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258)
61#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260)
62#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268)
63#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320)
64#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420)
65#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428)
66#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430)
67#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438)
68#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440)
69#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448)
70#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450)
71#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458)
72#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460)
73#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468)
74#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478)
75#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480)
76#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488)
77#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490)
78#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498)
79#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0)
80#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8)
81#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0)
82#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8)
83#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0)
84#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8)
85#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0)
86#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500)
87#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508)
88#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510)
89#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518)
90#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520)
91#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528)
92#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530)
93#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538)
94#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540)
95#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548)
96#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550)
97#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558)
98#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560)
99#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568)
100#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570)
101#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578)
102#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580)
103#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588)
104#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590)
105#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598)
106#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0)
107#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8)
108#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0)
109#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720)
110#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
111#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
112
113#endif
diff --git a/include/dt-bindings/clock/dm814.h b/include/dt-bindings/clock/dm814.h
new file mode 100644
index 000000000000..0e7099a344e1
--- /dev/null
+++ b/include/dt-bindings/clock/dm814.h
@@ -0,0 +1,45 @@
1/*
2 * Copyright 2017 Texas Instruments, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __DT_BINDINGS_CLK_DM814_H
14#define __DT_BINDINGS_CLK_DM814_H
15
16#define DM814_CLKCTRL_OFFSET 0x0
17#define DM814_CLKCTRL_INDEX(offset) ((offset) - DM814_CLKCTRL_OFFSET)
18
19/* default clocks */
20#define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
21
22/* alwon clocks */
23#define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
24#define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
25#define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
26#define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
27#define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
28#define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
29#define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
30#define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
31#define DM814_MCSPI1_CLKCTRL DM814_CLKCTRL_INDEX(0x190)
32#define DM814_GPMC_CLKCTRL DM814_CLKCTRL_INDEX(0x1d0)
33#define DM814_CPGMAC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1d4)
34#define DM814_MPU_CLKCTRL DM814_CLKCTRL_INDEX(0x1dc)
35#define DM814_RTC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f0)
36#define DM814_TPCC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f4)
37#define DM814_TPTC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1f8)
38#define DM814_TPTC1_CLKCTRL DM814_CLKCTRL_INDEX(0x1fc)
39#define DM814_TPTC2_CLKCTRL DM814_CLKCTRL_INDEX(0x200)
40#define DM814_TPTC3_CLKCTRL DM814_CLKCTRL_INDEX(0x204)
41#define DM814_MMC1_CLKCTRL DM814_CLKCTRL_INDEX(0x21c)
42#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220)
43#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224)
44
45#endif
diff --git a/include/dt-bindings/clock/dm816.h b/include/dt-bindings/clock/dm816.h
new file mode 100644
index 000000000000..69e8a36d783e
--- /dev/null
+++ b/include/dt-bindings/clock/dm816.h
@@ -0,0 +1,53 @@
1/*
2 * Copyright 2017 Texas Instruments, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __DT_BINDINGS_CLK_DM816_H
14#define __DT_BINDINGS_CLK_DM816_H
15
16#define DM816_CLKCTRL_OFFSET 0x0
17#define DM816_CLKCTRL_INDEX(offset) ((offset) - DM816_CLKCTRL_OFFSET)
18
19/* default clocks */
20#define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
21
22/* alwon clocks */
23#define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
24#define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
25#define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
26#define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
27#define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
28#define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
29#define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
30#define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
31#define DM816_TIMER2_CLKCTRL DM816_CLKCTRL_INDEX(0x174)
32#define DM816_TIMER3_CLKCTRL DM816_CLKCTRL_INDEX(0x178)
33#define DM816_TIMER4_CLKCTRL DM816_CLKCTRL_INDEX(0x17c)
34#define DM816_TIMER5_CLKCTRL DM816_CLKCTRL_INDEX(0x180)
35#define DM816_TIMER6_CLKCTRL DM816_CLKCTRL_INDEX(0x184)
36#define DM816_TIMER7_CLKCTRL DM816_CLKCTRL_INDEX(0x188)
37#define DM816_WD_TIMER_CLKCTRL DM816_CLKCTRL_INDEX(0x18c)
38#define DM816_MCSPI1_CLKCTRL DM816_CLKCTRL_INDEX(0x190)
39#define DM816_MAILBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x194)
40#define DM816_SPINBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x198)
41#define DM816_MMC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1b0)
42#define DM816_GPMC_CLKCTRL DM816_CLKCTRL_INDEX(0x1d0)
43#define DM816_DAVINCI_MDIO_CLKCTRL DM816_CLKCTRL_INDEX(0x1d4)
44#define DM816_EMAC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1d8)
45#define DM816_MPU_CLKCTRL DM816_CLKCTRL_INDEX(0x1dc)
46#define DM816_RTC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f0)
47#define DM816_TPCC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f4)
48#define DM816_TPTC0_CLKCTRL DM816_CLKCTRL_INDEX(0x1f8)
49#define DM816_TPTC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1fc)
50#define DM816_TPTC2_CLKCTRL DM816_CLKCTRL_INDEX(0x200)
51#define DM816_TPTC3_CLKCTRL DM816_CLKCTRL_INDEX(0x204)
52
53#endif
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h
new file mode 100644
index 000000000000..5e1061b15aed
--- /dev/null
+++ b/include/dt-bindings/clock/dra7.h
@@ -0,0 +1,172 @@
1/*
2 * Copyright 2017 Texas Instruments, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __DT_BINDINGS_CLK_DRA7_H
14#define __DT_BINDINGS_CLK_DRA7_H
15
16#define DRA7_CLKCTRL_OFFSET 0x20
17#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
18
19/* mpu clocks */
20#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
21
22/* ipu clocks */
23#define DRA7_IPU_CLKCTRL_OFFSET 0x40
24#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
25#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
26#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
27#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
28#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
29#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
30#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
31#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
32
33/* rtc clocks */
34#define DRA7_RTC_CLKCTRL_OFFSET 0x40
35#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
36#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
37
38/* coreaon clocks */
39#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
40#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
41
42/* l3main1 clocks */
43#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
44#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
45#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
46#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
47#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
48#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
49#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
50
51/* dma clocks */
52#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
53
54/* emif clocks */
55#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
56
57/* atl clocks */
58#define DRA7_ATL_CLKCTRL_OFFSET 0x0
59#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
60#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
61
62/* l4cfg clocks */
63#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
64#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
65#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
66#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
67#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
68#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
69#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
70#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
71#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
72#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
73#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
74#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
75#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
76#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
77#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
78
79/* l3instr clocks */
80#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
81#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
82
83/* dss clocks */
84#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
85#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
86
87/* l3init clocks */
88#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
89#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
90#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
91#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
92#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
93#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
94#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0)
95#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8)
96#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0)
97#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
98#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
99#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
100
101/* l4per clocks */
102#define DRA7_L4PER_CLKCTRL_OFFSET 0x0
103#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
104#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc)
105#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14)
106#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
107#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
108#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
109#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
110#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
111#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
112#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
113#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
114#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
115#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
116#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
117#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
118#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
119#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90)
120#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98)
121#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
122#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
123#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
124#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
125#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
126#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4)
127#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8)
128#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0)
129#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8)
130#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
131#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
132#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
133#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
134#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
135#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
136#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
137#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
138#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130)
139#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138)
140#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
141#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
142#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
143#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
144#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160)
145#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168)
146#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
147#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178)
148#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190)
149#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198)
150#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
151#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
152#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
153#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
154#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
155#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
156#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
157#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
158#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
159#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204)
160#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208)
161
162/* wkupaon clocks */
163#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
164#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
165#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
166#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
167#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
168#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
169#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
170#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
171
172#endif
diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h
new file mode 100644
index 000000000000..f51821a91216
--- /dev/null
+++ b/include/dt-bindings/clock/omap5.h
@@ -0,0 +1,118 @@
1/*
2 * Copyright 2017 Texas Instruments, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __DT_BINDINGS_CLK_OMAP5_H
14#define __DT_BINDINGS_CLK_OMAP5_H
15
16#define OMAP5_CLKCTRL_OFFSET 0x20
17#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET)
18
19/* mpu clocks */
20#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
21
22/* dsp clocks */
23#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
24
25/* abe clocks */
26#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
27#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
28#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
29#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
30#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
31#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
32#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
33#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
34#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
35#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
36
37/* l3main1 clocks */
38#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
39
40/* l3main2 clocks */
41#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
42
43/* ipu clocks */
44#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
45
46/* dma clocks */
47#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
48
49/* emif clocks */
50#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
51#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
52#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
53
54/* l4cfg clocks */
55#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
56#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
57#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
58
59/* l3instr clocks */
60#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
61#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
62
63/* l4per clocks */
64#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
65#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
66#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
67#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
68#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
69#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
70#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60)
71#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
72#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
73#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
74#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
75#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0)
76#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8)
77#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0)
78#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8)
79#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0)
80#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
81#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8)
82#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100)
83#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108)
84#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
85#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
86#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
87#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
88#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140)
89#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
90#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150)
91#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158)
92#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160)
93#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
94#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
95#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
96
97/* dss clocks */
98#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
99
100/* l3init clocks */
101#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
102#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
103#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
104#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
105#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88)
106#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0)
107#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8)
108#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
109
110/* wkupaon clocks */
111#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
112#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
113#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
114#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
115#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
116#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
117
118#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 21:26:21 -0400