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authorKishon Vijay Abraham I <kishon@ti.com>2016-01-14 09:11:10 -0500
committerPaul Walmsley <paul@pwsan.com>2016-02-09 04:18:52 -0500
commit8fe097a3d99e22355fb8e3bcee59542bf3f46b2d (patch)
treef05bb6a2b368270f857685d3440a1a5ebf91447c
parent4965be1fc8dbb3dfc8bf401c78cb78c35d5d0d4d (diff)
ARM: DRA7: hwmod: Add reset data for PCIe
Add PCIe reset data to PCIe hwmods on DRA7x. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c15
-rw-r--r--arch/arm/mach-omap2/prm7xx.h1
2 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 84c2699e551b..b61355e2a771 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1531,14 +1531,21 @@ static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1531}; 1531};
1532 1532
1533/* pcie1 */ 1533/* pcie1 */
1534static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1535 { .name = "pcie", .rst_shift = 0 },
1536};
1537
1534static struct omap_hwmod dra7xx_pciess1_hwmod = { 1538static struct omap_hwmod dra7xx_pciess1_hwmod = {
1535 .name = "pcie1", 1539 .name = "pcie1",
1536 .class = &dra7xx_pciess_hwmod_class, 1540 .class = &dra7xx_pciess_hwmod_class,
1537 .clkdm_name = "pcie_clkdm", 1541 .clkdm_name = "pcie_clkdm",
1542 .rst_lines = dra7xx_pciess1_resets,
1543 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
1538 .main_clk = "l4_root_clk_div", 1544 .main_clk = "l4_root_clk_div",
1539 .prcm = { 1545 .prcm = {
1540 .omap4 = { 1546 .omap4 = {
1541 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, 1547 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1548 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1542 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, 1549 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1543 .modulemode = MODULEMODE_SWCTRL, 1550 .modulemode = MODULEMODE_SWCTRL,
1544 }, 1551 },
@@ -1546,14 +1553,22 @@ static struct omap_hwmod dra7xx_pciess1_hwmod = {
1546}; 1553};
1547 1554
1548/* pcie2 */ 1555/* pcie2 */
1556static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1557 { .name = "pcie", .rst_shift = 1 },
1558};
1559
1560/* pcie2 */
1549static struct omap_hwmod dra7xx_pciess2_hwmod = { 1561static struct omap_hwmod dra7xx_pciess2_hwmod = {
1550 .name = "pcie2", 1562 .name = "pcie2",
1551 .class = &dra7xx_pciess_hwmod_class, 1563 .class = &dra7xx_pciess_hwmod_class,
1552 .clkdm_name = "pcie_clkdm", 1564 .clkdm_name = "pcie_clkdm",
1565 .rst_lines = dra7xx_pciess2_resets,
1566 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
1553 .main_clk = "l4_root_clk_div", 1567 .main_clk = "l4_root_clk_div",
1554 .prcm = { 1568 .prcm = {
1555 .omap4 = { 1569 .omap4 = {
1556 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET, 1570 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1571 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1557 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET, 1572 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1558 .modulemode = MODULEMODE_SWCTRL, 1573 .modulemode = MODULEMODE_SWCTRL,
1559 }, 1574 },
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index cc1e6a2b97f6..294deed956f3 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -360,6 +360,7 @@
360/* PRM.L3INIT_PRM register offsets */ 360/* PRM.L3INIT_PRM register offsets */
361#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 361#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
362#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 362#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
363#define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010
363#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 364#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
364#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 365#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
365#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 366#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030