perf/x86/intel: Fix PEBSv3 record drain

Alexander hit the WARN_ON_ONCE(!event) on his Skylake while running
the perf fuzzer.

This means the PEBSv3 record included a status bit for an inactive
event, something that _should_ not happen.

Move the code that filters the status bits against our known PEBS
events up a spot to guarantee we only deal with events we know about.

Further add "continue" statements to the WARN_ON_ONCE()s such that
we'll not die nor generate silly events in case we ever do hit them
again.

Reported-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Tested-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vince@deater.net>
Cc: stable@vger.kernel.org
Fixes: a3d86542de88 ("perf/x86/intel/pebs: Add PEBSv3 decoding")
Signed-off-by: Ingo Molnar <mingo@kernel.org>

1 files changed, 11 insertions, 8 deletions

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 7ce9f3f669e6..9b983a474253 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1274,18 +1274,18 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
                 struct pebs_record_nhm *p = at;
                 u64 pebs_status;
 
-                /* PEBS v3 has accurate status bits */
+                pebs_status = p->status & cpuc->pebs_enabled;
+                pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
+
+                /* PEBS v3 has more accurate status bits */
                 if (x86_pmu.intel_cap.pebs_format >= 3) {
-                        for_each_set_bit(bit, (unsigned long *)&p->status,
-                                         MAX_PEBS_EVENTS)
+                        for_each_set_bit(bit, (unsigned long *)&pebs_status,
+                                         x86_pmu.max_pebs_events)
                                 counts[bit]++;
 
                         continue;
                 }
 
-                pebs_status = p->status & cpuc->pebs_enabled;
-                pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
-
                 /*
                  * On some CPUs the PEBS status can be zero when PEBS is
                  * racing with clearing of GLOBAL_STATUS.
@@ -1333,8 +1333,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
                         continue;
 
                 event = cpuc->events[bit];
-                WARN_ON_ONCE(!event);
-                WARN_ON_ONCE(!event->attr.precise_ip);
+                if (WARN_ON_ONCE(!event))
+                        continue;
+
+                if (WARN_ON_ONCE(!event->attr.precise_ip))
+                        continue;
 
                 /* log dropped samples number */
                 if (error[bit])