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authorAlexander Shishkin <alexander.shishkin@linux.intel.com>2016-09-16 09:48:19 -0400
committerThomas Gleixner <tglx@linutronix.de>2016-09-19 19:18:28 -0400
commit8ee83b2ab3d1987cbd80c9f2c6f2b12fed87b51e (patch)
treea8561379f6733c47eeb6eababc8d0c9154ff0fbf
parentcd34cd97b7b4336aa2c623c37daffab264c7c6ce (diff)
perf/x86/intel/pt: Add support for PTWRITE and power event tracing
The Intel PT facility grew some new functionality: * PTWRITE packet carries the payload of the new PTWRITE instruction that can be used to instrument Intel PT traces with user-supplied data. Packets of this type are only generated if 'ptwrite' capability is set and PTWEn bit is set in the event attribute's config. Flow update packets (FUP) can be generated on PTWRITE packets if FUPonPTW config bit is set. Setting these bits is not allowed if 'ptwrite' capability is not set. * PWRE, PWRX, MWAIT, EXSTOP packets communicate core power management events. These depend on 'power_event_tracing' capability and are enabled by setting PwrEvtEn bit in the event attribute. Extend the driver capabilities and provide the proper sanity checks in the event validation function. [ tglx: Massaged changelog ] Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@infradead.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: vince@deater.net Cc: eranian@google.com Cc: Adrian Hunter <adrian.hunter@intel.com> Link: http://lkml.kernel.org/r/20160916134819.1978-1-alexander.shishkin@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-rw-r--r--arch/x86/events/intel/pt.c24
-rw-r--r--arch/x86/events/intel/pt.h5
2 files changed, 28 insertions, 1 deletions
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index 04bb5fb5a8d7..18d18fdda93d 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -69,6 +69,8 @@ static struct pt_cap_desc {
69 PT_CAP(psb_cyc, 0, CR_EBX, BIT(1)), 69 PT_CAP(psb_cyc, 0, CR_EBX, BIT(1)),
70 PT_CAP(ip_filtering, 0, CR_EBX, BIT(2)), 70 PT_CAP(ip_filtering, 0, CR_EBX, BIT(2)),
71 PT_CAP(mtc, 0, CR_EBX, BIT(3)), 71 PT_CAP(mtc, 0, CR_EBX, BIT(3)),
72 PT_CAP(ptwrite, 0, CR_EBX, BIT(4)),
73 PT_CAP(power_event_trace, 0, CR_EBX, BIT(5)),
72 PT_CAP(topa_output, 0, CR_ECX, BIT(0)), 74 PT_CAP(topa_output, 0, CR_ECX, BIT(0)),
73 PT_CAP(topa_multiple_entries, 0, CR_ECX, BIT(1)), 75 PT_CAP(topa_multiple_entries, 0, CR_ECX, BIT(1)),
74 PT_CAP(single_range_output, 0, CR_ECX, BIT(2)), 76 PT_CAP(single_range_output, 0, CR_ECX, BIT(2)),
@@ -259,10 +261,16 @@ fail:
259#define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \ 261#define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \
260 RTIT_CTL_MTC_RANGE) 262 RTIT_CTL_MTC_RANGE)
261 263
264#define RTIT_CTL_PTW (RTIT_CTL_PTW_EN | \
265 RTIT_CTL_FUP_ON_PTW)
266
262#define PT_CONFIG_MASK (RTIT_CTL_TSC_EN | \ 267#define PT_CONFIG_MASK (RTIT_CTL_TSC_EN | \
263 RTIT_CTL_DISRETC | \ 268 RTIT_CTL_DISRETC | \
264 RTIT_CTL_CYC_PSB | \ 269 RTIT_CTL_CYC_PSB | \
265 RTIT_CTL_MTC) 270 RTIT_CTL_MTC | \
271 RTIT_CTL_PWR_EVT_EN | \
272 RTIT_CTL_FUP_ON_PTW | \
273 RTIT_CTL_PTW_EN)
266 274
267static bool pt_event_valid(struct perf_event *event) 275static bool pt_event_valid(struct perf_event *event)
268{ 276{
@@ -311,6 +319,20 @@ static bool pt_event_valid(struct perf_event *event)
311 return false; 319 return false;
312 } 320 }
313 321
322 if (config & RTIT_CTL_PWR_EVT_EN &&
323 !pt_cap_get(PT_CAP_power_event_trace))
324 return false;
325
326 if (config & RTIT_CTL_PTW) {
327 if (!pt_cap_get(PT_CAP_ptwrite))
328 return false;
329
330 /* FUPonPTW without PTW doesn't make sense */
331 if ((config & RTIT_CTL_FUP_ON_PTW) &&
332 !(config & RTIT_CTL_PTW_EN))
333 return false;
334 }
335
314 return true; 336 return true;
315} 337}
316 338
diff --git a/arch/x86/events/intel/pt.h b/arch/x86/events/intel/pt.h
index efffa4a09f68..53473c21b554 100644
--- a/arch/x86/events/intel/pt.h
+++ b/arch/x86/events/intel/pt.h
@@ -26,11 +26,14 @@
26#define RTIT_CTL_CYCLEACC BIT(1) 26#define RTIT_CTL_CYCLEACC BIT(1)
27#define RTIT_CTL_OS BIT(2) 27#define RTIT_CTL_OS BIT(2)
28#define RTIT_CTL_USR BIT(3) 28#define RTIT_CTL_USR BIT(3)
29#define RTIT_CTL_PWR_EVT_EN BIT(4)
30#define RTIT_CTL_FUP_ON_PTW BIT(5)
29#define RTIT_CTL_CR3EN BIT(7) 31#define RTIT_CTL_CR3EN BIT(7)
30#define RTIT_CTL_TOPA BIT(8) 32#define RTIT_CTL_TOPA BIT(8)
31#define RTIT_CTL_MTC_EN BIT(9) 33#define RTIT_CTL_MTC_EN BIT(9)
32#define RTIT_CTL_TSC_EN BIT(10) 34#define RTIT_CTL_TSC_EN BIT(10)
33#define RTIT_CTL_DISRETC BIT(11) 35#define RTIT_CTL_DISRETC BIT(11)
36#define RTIT_CTL_PTW_EN BIT(12)
34#define RTIT_CTL_BRANCH_EN BIT(13) 37#define RTIT_CTL_BRANCH_EN BIT(13)
35#define RTIT_CTL_MTC_RANGE_OFFSET 14 38#define RTIT_CTL_MTC_RANGE_OFFSET 14
36#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 39#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
@@ -91,6 +94,8 @@ enum pt_capabilities {
91 PT_CAP_psb_cyc, 94 PT_CAP_psb_cyc,
92 PT_CAP_ip_filtering, 95 PT_CAP_ip_filtering,
93 PT_CAP_mtc, 96 PT_CAP_mtc,
97 PT_CAP_ptwrite,
98 PT_CAP_power_event_trace,
94 PT_CAP_topa_output, 99 PT_CAP_topa_output,
95 PT_CAP_topa_multiple_entries, 100 PT_CAP_topa_multiple_entries,
96 PT_CAP_single_range_output, 101 PT_CAP_single_range_output,