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authorRex Zhu <Rex.Zhu@amd.com>2018-03-21 06:36:50 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-03-22 15:43:29 -0400
commit8ebde09b16919b8cd6aa0af186d300faf5a145fc (patch)
treeb8f3549c281bf319b752cd4036d179d050107577
parentbbfcc8af37577c7f8950a1442c398da64de5e5b7 (diff)
drm/amd/pp: Add new asic support in pp_psm.c
In new asics(vega12), no power state management in driver, So no need to implement related callback functions. and add some ps checks in pp_psm.c Revert "drm/amd/powerplay: add new pp_psm infrastructure for vega12 (v2)" This reverts commit 7d1a63f3aa331b853e41f92d0e7890ed31de8c13. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/Makefile4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c270
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_legacy.c262
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_legacy.h40
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_new.c76
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_new.h40
6 files changed, 239 insertions, 453 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index 9446dbc47551..faf9c880e4f7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -31,9 +31,9 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
31 smu7_clockpowergating.o \ 31 smu7_clockpowergating.o \
32 vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \ 32 vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \
33 vega10_thermal.o smu10_hwmgr.o pp_psm.o\ 33 vega10_thermal.o smu10_hwmgr.o pp_psm.o\
34 pp_overdriver.o smu_helper.o pp_psm_legacy.o pp_psm_new.o \
35 vega12_processpptables.o vega12_hwmgr.o \ 34 vega12_processpptables.o vega12_hwmgr.o \
36 vega12_powertune.o vega12_thermal.o 35 vega12_powertune.o vega12_thermal.o \
36 pp_overdriver.o smu_helper.o
37 37
38AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) 38AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
39 39
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
index 295ab9fed3f0..0f2851b5b368 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
@@ -21,65 +21,269 @@
21 * 21 *
22 */ 22 */
23 23
24#include <linux/types.h>
25#include <linux/kernel.h>
26#include <linux/slab.h>
24#include "pp_psm.h" 27#include "pp_psm.h"
25#include "pp_psm_legacy.h"
26#include "pp_psm_new.h"
27 28
28int psm_init_power_state_table(struct pp_hwmgr *hwmgr) 29int psm_init_power_state_table(struct pp_hwmgr *hwmgr)
29{ 30{
30 if (hwmgr->chip_id != CHIP_VEGA12) 31 int result;
31 return psm_legacy_init_power_state_table(hwmgr); 32 unsigned int i;
32 else 33 unsigned int table_entries;
33 return psm_new_init_power_state_table(hwmgr); 34 struct pp_power_state *state;
35 int size;
36
37 if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
38 return 0;
39
40 if (hwmgr->hwmgr_func->get_power_state_size == NULL)
41 return 0;
42
43 hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
44
45 hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
46 sizeof(struct pp_power_state);
47
48 if (table_entries == 0 || size == 0) {
49 pr_warn("Please check whether power state management is suppported on this asic\n");
50 return 0;
51 }
52
53 hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
54 if (hwmgr->ps == NULL)
55 return -ENOMEM;
56
57 hwmgr->request_ps = kzalloc(size, GFP_KERNEL);
58 if (hwmgr->request_ps == NULL) {
59 kfree(hwmgr->ps);
60 hwmgr->ps = NULL;
61 return -ENOMEM;
62 }
63
64 hwmgr->current_ps = kzalloc(size, GFP_KERNEL);
65 if (hwmgr->current_ps == NULL) {
66 kfree(hwmgr->request_ps);
67 kfree(hwmgr->ps);
68 hwmgr->request_ps = NULL;
69 hwmgr->ps = NULL;
70 return -ENOMEM;
71 }
72
73 state = hwmgr->ps;
74
75 for (i = 0; i < table_entries; i++) {
76 result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
77
78 if (state->classification.flags & PP_StateClassificationFlag_Boot) {
79 hwmgr->boot_ps = state;
80 memcpy(hwmgr->current_ps, state, size);
81 memcpy(hwmgr->request_ps, state, size);
82 }
83
84 state->id = i + 1; /* assigned unique num for every power state id */
85
86 if (state->classification.flags & PP_StateClassificationFlag_Uvd)
87 hwmgr->uvd_ps = state;
88 state = (struct pp_power_state *)((unsigned long)state + size);
89 }
90
91 return 0;
34} 92}
35 93
36int psm_fini_power_state_table(struct pp_hwmgr *hwmgr) 94int psm_fini_power_state_table(struct pp_hwmgr *hwmgr)
37{ 95{
38 if (hwmgr->chip_id != CHIP_VEGA12) 96 if (hwmgr == NULL)
39 return psm_legacy_fini_power_state_table(hwmgr); 97 return -EINVAL;
40 else 98
41 return psm_new_fini_power_state_table(hwmgr); 99 if (!hwmgr->ps)
100 return 0;
101
102 kfree(hwmgr->current_ps);
103 kfree(hwmgr->request_ps);
104 kfree(hwmgr->ps);
105 hwmgr->request_ps = NULL;
106 hwmgr->ps = NULL;
107 hwmgr->current_ps = NULL;
108 return 0;
109}
110
111static int psm_get_ui_state(struct pp_hwmgr *hwmgr,
112 enum PP_StateUILabel ui_label,
113 unsigned long *state_id)
114{
115 struct pp_power_state *state;
116 int table_entries;
117 int i;
118
119 table_entries = hwmgr->num_ps;
120 state = hwmgr->ps;
121
122 for (i = 0; i < table_entries; i++) {
123 if (state->classification.ui_label & ui_label) {
124 *state_id = state->id;
125 return 0;
126 }
127 state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
128 }
129 return -EINVAL;
130}
131
132static int psm_get_state_by_classification(struct pp_hwmgr *hwmgr,
133 enum PP_StateClassificationFlag flag,
134 unsigned long *state_id)
135{
136 struct pp_power_state *state;
137 int table_entries;
138 int i;
139
140 table_entries = hwmgr->num_ps;
141 state = hwmgr->ps;
142
143 for (i = 0; i < table_entries; i++) {
144 if (state->classification.flags & flag) {
145 *state_id = state->id;
146 return 0;
147 }
148 state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
149 }
150 return -EINVAL;
151}
152
153static int psm_set_states(struct pp_hwmgr *hwmgr, unsigned long state_id)
154{
155 struct pp_power_state *state;
156 int table_entries;
157 int i;
158
159 table_entries = hwmgr->num_ps;
160
161 state = hwmgr->ps;
162
163 for (i = 0; i < table_entries; i++) {
164 if (state->id == state_id) {
165 memcpy(hwmgr->request_ps, state, hwmgr->ps_size);
166 return 0;
167 }
168 state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
169 }
170 return -EINVAL;
42} 171}
43 172
44int psm_set_boot_states(struct pp_hwmgr *hwmgr) 173int psm_set_boot_states(struct pp_hwmgr *hwmgr)
45{ 174{
46 if (hwmgr->chip_id != CHIP_VEGA12) 175 unsigned long state_id;
47 return psm_legacy_set_boot_states(hwmgr); 176 int ret = -EINVAL;
48 else 177
49 return psm_new_set_boot_states(hwmgr); 178 if (!hwmgr->ps)
179 return 0;
180
181 if (!psm_get_state_by_classification(hwmgr, PP_StateClassificationFlag_Boot,
182 &state_id))
183 ret = psm_set_states(hwmgr, state_id);
184
185 return ret;
50} 186}
51 187
52int psm_set_performance_states(struct pp_hwmgr *hwmgr) 188int psm_set_performance_states(struct pp_hwmgr *hwmgr)
53{ 189{
54 if (hwmgr->chip_id != CHIP_VEGA12) 190 unsigned long state_id;
55 return psm_legacy_set_performance_states(hwmgr); 191 int ret = -EINVAL;
56 else 192
57 return psm_new_set_performance_states(hwmgr); 193 if (!hwmgr->ps)
194 return 0;
195
196 if (!psm_get_ui_state(hwmgr, PP_StateUILabel_Performance,
197 &state_id))
198 ret = psm_set_states(hwmgr, state_id);
199
200 return ret;
58} 201}
59 202
60int psm_set_user_performance_state(struct pp_hwmgr *hwmgr, 203int psm_set_user_performance_state(struct pp_hwmgr *hwmgr,
61 enum PP_StateUILabel label_id, 204 enum PP_StateUILabel label_id,
62 struct pp_power_state **state) 205 struct pp_power_state **state)
63{ 206{
64 if (hwmgr->chip_id != CHIP_VEGA12) 207 int table_entries;
65 return psm_legacy_set_user_performance_state(hwmgr, 208 int i;
66 label_id, 209
67 state); 210 if (!hwmgr->ps)
211 return 0;
212
213 table_entries = hwmgr->num_ps;
214 *state = hwmgr->ps;
215
216restart_search:
217 for (i = 0; i < table_entries; i++) {
218 if ((*state)->classification.ui_label & label_id)
219 return 0;
220 *state = (struct pp_power_state *)((uintptr_t)*state + hwmgr->ps_size);
221 }
222
223 switch (label_id) {
224 case PP_StateUILabel_Battery:
225 case PP_StateUILabel_Balanced:
226 label_id = PP_StateUILabel_Performance;
227 goto restart_search;
228 default:
229 break;
230 }
231 return -EINVAL;
232}
233
234static void power_state_management(struct pp_hwmgr *hwmgr,
235 struct pp_power_state *new_ps)
236{
237 struct pp_power_state *pcurrent;
238 struct pp_power_state *requested;
239 bool equal;
240
241 if (new_ps != NULL)
242 requested = new_ps;
68 else 243 else
69 return psm_new_set_user_performance_state(hwmgr, 244 requested = hwmgr->request_ps;
70 label_id, 245
71 state); 246 pcurrent = hwmgr->current_ps;
247
248 phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
249 if (pcurrent == NULL || (0 != phm_check_states_equal(hwmgr,
250 &pcurrent->hardware, &requested->hardware, &equal)))
251 equal = false;
252
253 if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) {
254 phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
255 memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr->ps_size);
256 }
72} 257}
73 258
74int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip, 259int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
75 struct pp_power_state *new_ps) 260 struct pp_power_state *new_ps)
76{ 261{
77 if (hwmgr->chip_id != CHIP_VEGA12) 262 uint32_t index;
78 return psm_legacy_adjust_power_state_dynamic(hwmgr, 263 long workload;
79 skip, 264
80 new_ps); 265 if (skip)
81 else 266 return 0;
82 return psm_new_adjust_power_state_dynamic(hwmgr, 267
83 skip, 268 phm_display_configuration_changed(hwmgr);
84 new_ps); 269
270 if (hwmgr->ps)
271 power_state_management(hwmgr, new_ps);
272
273 phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
274
275 if (!phm_force_dpm_levels(hwmgr, hwmgr->request_dpm_level))
276 hwmgr->dpm_level = hwmgr->request_dpm_level;
277
278 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
279 index = fls(hwmgr->workload_mask);
280 index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
281 workload = hwmgr->workload_setting[index];
282
283 if (hwmgr->power_profile_mode != workload && hwmgr->hwmgr_func->set_power_profile_mode)
284 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
285 }
286
287 return 0;
85} 288}
289
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_legacy.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_legacy.c
deleted file mode 100644
index e3ac52820641..000000000000
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_legacy.c
+++ /dev/null
@@ -1,262 +0,0 @@
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/types.h>
25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include "pp_psm_legacy.h"
28
29int psm_legacy_init_power_state_table(struct pp_hwmgr *hwmgr)
30{
31 int result;
32 unsigned int i;
33 unsigned int table_entries;
34 struct pp_power_state *state;
35 int size;
36
37 if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
38 return -EINVAL;
39
40 if (hwmgr->hwmgr_func->get_power_state_size == NULL)
41 return -EINVAL;
42
43 hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
44
45 hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
46 sizeof(struct pp_power_state);
47
48 hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
49 if (hwmgr->ps == NULL)
50 return -ENOMEM;
51
52 hwmgr->request_ps = kzalloc(size, GFP_KERNEL);
53 if (hwmgr->request_ps == NULL) {
54 kfree(hwmgr->ps);
55 hwmgr->ps = NULL;
56 return -ENOMEM;
57 }
58
59 hwmgr->current_ps = kzalloc(size, GFP_KERNEL);
60 if (hwmgr->current_ps == NULL) {
61 kfree(hwmgr->request_ps);
62 kfree(hwmgr->ps);
63 hwmgr->request_ps = NULL;
64 hwmgr->ps = NULL;
65 return -ENOMEM;
66 }
67
68 state = hwmgr->ps;
69
70 for (i = 0; i < table_entries; i++) {
71 result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
72
73 if (state->classification.flags & PP_StateClassificationFlag_Boot) {
74 hwmgr->boot_ps = state;
75 memcpy(hwmgr->current_ps, state, size);
76 memcpy(hwmgr->request_ps, state, size);
77 }
78
79 state->id = i + 1; /* assigned unique num for every power state id */
80
81 if (state->classification.flags & PP_StateClassificationFlag_Uvd)
82 hwmgr->uvd_ps = state;
83 state = (struct pp_power_state *)((unsigned long)state + size);
84 }
85
86 return 0;
87}
88
89int psm_legacy_fini_power_state_table(struct pp_hwmgr *hwmgr)
90{
91 if (hwmgr == NULL)
92 return -EINVAL;
93
94 kfree(hwmgr->current_ps);
95 kfree(hwmgr->request_ps);
96 kfree(hwmgr->ps);
97 hwmgr->request_ps = NULL;
98 hwmgr->ps = NULL;
99 hwmgr->current_ps = NULL;
100 return 0;
101}
102
103static int get_ui_state(struct pp_hwmgr *hwmgr,
104 enum PP_StateUILabel ui_label,
105 unsigned long *state_id)
106{
107 struct pp_power_state *state;
108 int table_entries;
109 int i;
110
111 table_entries = hwmgr->num_ps;
112 state = hwmgr->ps;
113
114 for (i = 0; i < table_entries; i++) {
115 if (state->classification.ui_label & ui_label) {
116 *state_id = state->id;
117 return 0;
118 }
119 state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
120 }
121 return -EINVAL;
122}
123
124static int get_state_by_classification(struct pp_hwmgr *hwmgr,
125 enum PP_StateClassificationFlag flag,
126 unsigned long *state_id)
127{
128 struct pp_power_state *state;
129 int table_entries;
130 int i;
131
132 table_entries = hwmgr->num_ps;
133 state = hwmgr->ps;
134
135 for (i = 0; i < table_entries; i++) {
136 if (state->classification.flags & flag) {
137 *state_id = state->id;
138 return 0;
139 }
140 state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
141 }
142 return -EINVAL;
143}
144
145static int set_states(struct pp_hwmgr *hwmgr, unsigned long state_id)
146{
147 struct pp_power_state *state;
148 int table_entries;
149 int i;
150
151 table_entries = hwmgr->num_ps;
152
153 state = hwmgr->ps;
154
155 for (i = 0; i < table_entries; i++) {
156 if (state->id == state_id) {
157 memcpy(hwmgr->request_ps, state, hwmgr->ps_size);
158 return 0;
159 }
160 state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
161 }
162 return -EINVAL;
163}
164
165int psm_legacy_set_boot_states(struct pp_hwmgr *hwmgr)
166{
167 unsigned long state_id;
168 int ret = -EINVAL;
169
170 if (!get_state_by_classification(hwmgr, PP_StateClassificationFlag_Boot,
171 &state_id))
172 ret = set_states(hwmgr, state_id);
173
174 return ret;
175}
176
177int psm_legacy_set_performance_states(struct pp_hwmgr *hwmgr)
178{
179 unsigned long state_id;
180 int ret = -EINVAL;
181
182 if (!get_ui_state(hwmgr, PP_StateUILabel_Performance,
183 &state_id))
184 ret = set_states(hwmgr, state_id);
185
186 return ret;
187}
188
189int psm_legacy_set_user_performance_state(struct pp_hwmgr *hwmgr,
190 enum PP_StateUILabel label_id,
191 struct pp_power_state **state)
192{
193 int table_entries;
194 int i;
195
196 table_entries = hwmgr->num_ps;
197 *state = hwmgr->ps;
198
199restart_search:
200 for (i = 0; i < table_entries; i++) {
201 if ((*state)->classification.ui_label & label_id)
202 return 0;
203 *state = (struct pp_power_state *)((uintptr_t)*state + hwmgr->ps_size);
204 }
205
206 switch (label_id) {
207 case PP_StateUILabel_Battery:
208 case PP_StateUILabel_Balanced:
209 label_id = PP_StateUILabel_Performance;
210 goto restart_search;
211 default:
212 break;
213 }
214 return -EINVAL;
215}
216
217int psm_legacy_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
218 struct pp_power_state *new_ps)
219{
220 struct pp_power_state *pcurrent;
221 struct pp_power_state *requested;
222 bool equal;
223 uint32_t index;
224 long workload;
225
226 if (skip)
227 return 0;
228
229 phm_display_configuration_changed(hwmgr);
230
231 if (new_ps != NULL)
232 requested = new_ps;
233 else
234 requested = hwmgr->request_ps;
235
236 pcurrent = hwmgr->current_ps;
237
238 phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
239 if (pcurrent == NULL || (0 != phm_check_states_equal(hwmgr,
240 &pcurrent->hardware, &requested->hardware, &equal)))
241 equal = false;
242
243 if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) {
244 phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
245 memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr->ps_size);
246 }
247
248 phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
249 if (!phm_force_dpm_levels(hwmgr, hwmgr->request_dpm_level))
250 hwmgr->dpm_level = hwmgr->request_dpm_level;
251
252 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
253 index = fls(hwmgr->workload_mask);
254 index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
255 workload = hwmgr->workload_setting[index];
256
257 if (hwmgr->power_profile_mode != workload && hwmgr->hwmgr_func->set_power_profile_mode)
258 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
259 }
260
261 return 0;
262}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_legacy.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_legacy.h
deleted file mode 100644
index bc99411c1a46..000000000000
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_legacy.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef PP_PSM_LEGACY_H
25#define PP_PSM_LEGACY_H
26
27#include "hwmgr.h"
28
29int psm_legacy_init_power_state_table(struct pp_hwmgr *hwmgr);
30int psm_legacy_fini_power_state_table(struct pp_hwmgr *hwmgr);
31int psm_legacy_set_boot_states(struct pp_hwmgr *hwmgr);
32int psm_legacy_set_performance_states(struct pp_hwmgr *hwmgr);
33int psm_legacy_set_user_performance_state(struct pp_hwmgr *hwmgr,
34 enum PP_StateUILabel label_id,
35 struct pp_power_state **state);
36int psm_legacy_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr,
37 bool skip,
38 struct pp_power_state *new_ps);
39
40#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_new.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_new.c
deleted file mode 100644
index 9eba8a1f2855..000000000000
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_new.c
+++ /dev/null
@@ -1,76 +0,0 @@
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/types.h>
25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include "pp_psm_new.h"
28
29int psm_new_init_power_state_table(struct pp_hwmgr *hwmgr)
30{
31 hwmgr->ps_size = 0;
32 hwmgr->num_ps = 0;
33 hwmgr->ps = NULL;
34 hwmgr->request_ps = NULL;
35 hwmgr->current_ps = NULL;
36 hwmgr->boot_ps = NULL;
37 hwmgr->uvd_ps = NULL;
38
39 return 0;
40}
41
42int psm_new_fini_power_state_table(struct pp_hwmgr *hwmgr)
43{
44 return 0;
45}
46
47int psm_new_set_boot_states(struct pp_hwmgr *hwmgr)
48{
49 return 0;
50}
51
52int psm_new_set_performance_states(struct pp_hwmgr *hwmgr)
53{
54 return 0;
55}
56
57int psm_new_set_user_performance_state(struct pp_hwmgr *hwmgr,
58 enum PP_StateUILabel label_id,
59 struct pp_power_state **state)
60{
61 return 0;
62}
63
64int psm_new_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr,
65 bool skip,
66 struct pp_power_state *new_ps)
67{
68 if (skip)
69 return 0;
70
71 phm_display_configuration_changed(hwmgr);
72
73 phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
74
75 return 0;
76}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_new.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_new.h
deleted file mode 100644
index 5c4fabcd8a15..000000000000
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm_new.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef PP_PSM_NEW_H
25#define PP_PSM_NEW_H
26
27#include "hwmgr.h"
28
29int psm_new_init_power_state_table(struct pp_hwmgr *hwmgr);
30int psm_new_fini_power_state_table(struct pp_hwmgr *hwmgr);
31int psm_new_set_boot_states(struct pp_hwmgr *hwmgr);
32int psm_new_set_performance_states(struct pp_hwmgr *hwmgr);
33int psm_new_set_user_performance_state(struct pp_hwmgr *hwmgr,
34 enum PP_StateUILabel label_id,
35 struct pp_power_state **state);
36int psm_new_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr,
37 bool skip,
38 struct pp_power_state *new_ps);
39
40#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 01:39:29 -0400