diff options
author | Dave Airlie <airlied@redhat.com> | 2018-04-25 21:08:26 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2018-04-25 21:08:26 -0400 |
commit | 8eb8ad52fbc99aa87f1c56db378ee910833ed780 (patch) | |
tree | 94d441bce1af28fa8e027b9a0bfb6329ef825e33 | |
parent | d736aa62c291623b4cf71ea57daa6e63047c640e (diff) | |
parent | 7ad35721e7d5a5b56a4eddcdd9920c3c1e51ae4c (diff) |
Merge branch 'drm-fixes-4.17' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
- Fix a hang on CZ boards with EDC enabled
- Fix hangs related to DP MST handling
- Fix a deadlock in irq handling in DC
* 'drm-fixes-4.17' of git://people.freedesktop.org/~agd5f/linux:
drm/amd/display: Check dc_sink every time in MST hotplug
drm/amd/display: Update MST edid property every time
drm/amd/display: Don't read EDID in atomic_check
drm/amd/display: Disallow enabling CRTC without primary plane with FB
drm/amd/display: Fix deadlock when flushing irq
drm/amdgpu: set COMPUTE_PGM_RSRC1 for SGPR/VGPR clearing shaders
4 files changed, 39 insertions, 37 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index b0e591eaa71a..e14263fca1c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | |||
@@ -1459,10 +1459,11 @@ static const u32 sgpr_init_compute_shader[] = | |||
1459 | static const u32 vgpr_init_regs[] = | 1459 | static const u32 vgpr_init_regs[] = |
1460 | { | 1460 | { |
1461 | mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff, | 1461 | mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff, |
1462 | mmCOMPUTE_RESOURCE_LIMITS, 0, | 1462 | mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */ |
1463 | mmCOMPUTE_NUM_THREAD_X, 256*4, | 1463 | mmCOMPUTE_NUM_THREAD_X, 256*4, |
1464 | mmCOMPUTE_NUM_THREAD_Y, 1, | 1464 | mmCOMPUTE_NUM_THREAD_Y, 1, |
1465 | mmCOMPUTE_NUM_THREAD_Z, 1, | 1465 | mmCOMPUTE_NUM_THREAD_Z, 1, |
1466 | mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */ | ||
1466 | mmCOMPUTE_PGM_RSRC2, 20, | 1467 | mmCOMPUTE_PGM_RSRC2, 20, |
1467 | mmCOMPUTE_USER_DATA_0, 0xedcedc00, | 1468 | mmCOMPUTE_USER_DATA_0, 0xedcedc00, |
1468 | mmCOMPUTE_USER_DATA_1, 0xedcedc01, | 1469 | mmCOMPUTE_USER_DATA_1, 0xedcedc01, |
@@ -1479,10 +1480,11 @@ static const u32 vgpr_init_regs[] = | |||
1479 | static const u32 sgpr1_init_regs[] = | 1480 | static const u32 sgpr1_init_regs[] = |
1480 | { | 1481 | { |
1481 | mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f, | 1482 | mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f, |
1482 | mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, | 1483 | mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */ |
1483 | mmCOMPUTE_NUM_THREAD_X, 256*5, | 1484 | mmCOMPUTE_NUM_THREAD_X, 256*5, |
1484 | mmCOMPUTE_NUM_THREAD_Y, 1, | 1485 | mmCOMPUTE_NUM_THREAD_Y, 1, |
1485 | mmCOMPUTE_NUM_THREAD_Z, 1, | 1486 | mmCOMPUTE_NUM_THREAD_Z, 1, |
1487 | mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */ | ||
1486 | mmCOMPUTE_PGM_RSRC2, 20, | 1488 | mmCOMPUTE_PGM_RSRC2, 20, |
1487 | mmCOMPUTE_USER_DATA_0, 0xedcedc00, | 1489 | mmCOMPUTE_USER_DATA_0, 0xedcedc00, |
1488 | mmCOMPUTE_USER_DATA_1, 0xedcedc01, | 1490 | mmCOMPUTE_USER_DATA_1, 0xedcedc01, |
@@ -1503,6 +1505,7 @@ static const u32 sgpr2_init_regs[] = | |||
1503 | mmCOMPUTE_NUM_THREAD_X, 256*5, | 1505 | mmCOMPUTE_NUM_THREAD_X, 256*5, |
1504 | mmCOMPUTE_NUM_THREAD_Y, 1, | 1506 | mmCOMPUTE_NUM_THREAD_Y, 1, |
1505 | mmCOMPUTE_NUM_THREAD_Z, 1, | 1507 | mmCOMPUTE_NUM_THREAD_Z, 1, |
1508 | mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */ | ||
1506 | mmCOMPUTE_PGM_RSRC2, 20, | 1509 | mmCOMPUTE_PGM_RSRC2, 20, |
1507 | mmCOMPUTE_USER_DATA_0, 0xedcedc00, | 1510 | mmCOMPUTE_USER_DATA_0, 0xedcedc00, |
1508 | mmCOMPUTE_USER_DATA_1, 0xedcedc01, | 1511 | mmCOMPUTE_USER_DATA_1, 0xedcedc01, |
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4e2f379ce217..1dd1142246c2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | |||
@@ -4557,6 +4557,7 @@ static int dm_update_crtcs_state(struct dc *dc, | |||
4557 | struct amdgpu_dm_connector *aconnector = NULL; | 4557 | struct amdgpu_dm_connector *aconnector = NULL; |
4558 | struct drm_connector_state *new_con_state = NULL; | 4558 | struct drm_connector_state *new_con_state = NULL; |
4559 | struct dm_connector_state *dm_conn_state = NULL; | 4559 | struct dm_connector_state *dm_conn_state = NULL; |
4560 | struct drm_plane_state *new_plane_state = NULL; | ||
4560 | 4561 | ||
4561 | new_stream = NULL; | 4562 | new_stream = NULL; |
4562 | 4563 | ||
@@ -4564,6 +4565,13 @@ static int dm_update_crtcs_state(struct dc *dc, | |||
4564 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | 4565 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
4565 | acrtc = to_amdgpu_crtc(crtc); | 4566 | acrtc = to_amdgpu_crtc(crtc); |
4566 | 4567 | ||
4568 | new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary); | ||
4569 | |||
4570 | if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) { | ||
4571 | ret = -EINVAL; | ||
4572 | goto fail; | ||
4573 | } | ||
4574 | |||
4567 | aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); | 4575 | aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); |
4568 | 4576 | ||
4569 | /* TODO This hack should go away */ | 4577 | /* TODO This hack should go away */ |
@@ -4760,7 +4768,7 @@ static int dm_update_planes_state(struct dc *dc, | |||
4760 | if (!dm_old_crtc_state->stream) | 4768 | if (!dm_old_crtc_state->stream) |
4761 | continue; | 4769 | continue; |
4762 | 4770 | ||
4763 | DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n", | 4771 | DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", |
4764 | plane->base.id, old_plane_crtc->base.id); | 4772 | plane->base.id, old_plane_crtc->base.id); |
4765 | 4773 | ||
4766 | if (!dc_remove_plane_from_context( | 4774 | if (!dc_remove_plane_from_context( |
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index 490017df371d..4be21bf54749 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | |||
@@ -329,14 +329,15 @@ void amdgpu_dm_irq_fini(struct amdgpu_device *adev) | |||
329 | { | 329 | { |
330 | int src; | 330 | int src; |
331 | struct irq_list_head *lh; | 331 | struct irq_list_head *lh; |
332 | unsigned long irq_table_flags; | ||
332 | DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n"); | 333 | DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n"); |
333 | |||
334 | for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) { | 334 | for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) { |
335 | 335 | DM_IRQ_TABLE_LOCK(adev, irq_table_flags); | |
336 | /* The handler was removed from the table, | 336 | /* The handler was removed from the table, |
337 | * it means it is safe to flush all the 'work' | 337 | * it means it is safe to flush all the 'work' |
338 | * (because no code can schedule a new one). */ | 338 | * (because no code can schedule a new one). */ |
339 | lh = &adev->dm.irq_handler_list_low_tab[src]; | 339 | lh = &adev->dm.irq_handler_list_low_tab[src]; |
340 | DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags); | ||
340 | flush_work(&lh->work); | 341 | flush_work(&lh->work); |
341 | } | 342 | } |
342 | } | 343 | } |
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 8291d74f26bc..ace9ad578ca0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | |||
@@ -161,6 +161,11 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) | |||
161 | struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); | 161 | struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); |
162 | struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder; | 162 | struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder; |
163 | 163 | ||
164 | if (amdgpu_dm_connector->edid) { | ||
165 | kfree(amdgpu_dm_connector->edid); | ||
166 | amdgpu_dm_connector->edid = NULL; | ||
167 | } | ||
168 | |||
164 | drm_encoder_cleanup(&amdgpu_encoder->base); | 169 | drm_encoder_cleanup(&amdgpu_encoder->base); |
165 | kfree(amdgpu_encoder); | 170 | kfree(amdgpu_encoder); |
166 | drm_connector_cleanup(connector); | 171 | drm_connector_cleanup(connector); |
@@ -181,28 +186,22 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { | |||
181 | void dm_dp_mst_dc_sink_create(struct drm_connector *connector) | 186 | void dm_dp_mst_dc_sink_create(struct drm_connector *connector) |
182 | { | 187 | { |
183 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); | 188 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
184 | struct edid *edid; | ||
185 | struct dc_sink *dc_sink; | 189 | struct dc_sink *dc_sink; |
186 | struct dc_sink_init_data init_params = { | 190 | struct dc_sink_init_data init_params = { |
187 | .link = aconnector->dc_link, | 191 | .link = aconnector->dc_link, |
188 | .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; | 192 | .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; |
189 | 193 | ||
194 | /* FIXME none of this is safe. we shouldn't touch aconnector here in | ||
195 | * atomic_check | ||
196 | */ | ||
197 | |||
190 | /* | 198 | /* |
191 | * TODO: Need to further figure out why ddc.algo is NULL while MST port exists | 199 | * TODO: Need to further figure out why ddc.algo is NULL while MST port exists |
192 | */ | 200 | */ |
193 | if (!aconnector->port || !aconnector->port->aux.ddc.algo) | 201 | if (!aconnector->port || !aconnector->port->aux.ddc.algo) |
194 | return; | 202 | return; |
195 | 203 | ||
196 | edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port); | 204 | ASSERT(aconnector->edid); |
197 | |||
198 | if (!edid) { | ||
199 | drm_mode_connector_update_edid_property( | ||
200 | &aconnector->base, | ||
201 | NULL); | ||
202 | return; | ||
203 | } | ||
204 | |||
205 | aconnector->edid = edid; | ||
206 | 205 | ||
207 | dc_sink = dc_link_add_remote_sink( | 206 | dc_sink = dc_link_add_remote_sink( |
208 | aconnector->dc_link, | 207 | aconnector->dc_link, |
@@ -215,9 +214,6 @@ void dm_dp_mst_dc_sink_create(struct drm_connector *connector) | |||
215 | 214 | ||
216 | amdgpu_dm_add_sink_to_freesync_module( | 215 | amdgpu_dm_add_sink_to_freesync_module( |
217 | connector, aconnector->edid); | 216 | connector, aconnector->edid); |
218 | |||
219 | drm_mode_connector_update_edid_property( | ||
220 | &aconnector->base, aconnector->edid); | ||
221 | } | 217 | } |
222 | 218 | ||
223 | static int dm_dp_mst_get_modes(struct drm_connector *connector) | 219 | static int dm_dp_mst_get_modes(struct drm_connector *connector) |
@@ -230,10 +226,6 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) | |||
230 | 226 | ||
231 | if (!aconnector->edid) { | 227 | if (!aconnector->edid) { |
232 | struct edid *edid; | 228 | struct edid *edid; |
233 | struct dc_sink *dc_sink; | ||
234 | struct dc_sink_init_data init_params = { | ||
235 | .link = aconnector->dc_link, | ||
236 | .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; | ||
237 | edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port); | 229 | edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port); |
238 | 230 | ||
239 | if (!edid) { | 231 | if (!edid) { |
@@ -244,11 +236,17 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) | |||
244 | } | 236 | } |
245 | 237 | ||
246 | aconnector->edid = edid; | 238 | aconnector->edid = edid; |
239 | } | ||
247 | 240 | ||
241 | if (!aconnector->dc_sink) { | ||
242 | struct dc_sink *dc_sink; | ||
243 | struct dc_sink_init_data init_params = { | ||
244 | .link = aconnector->dc_link, | ||
245 | .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; | ||
248 | dc_sink = dc_link_add_remote_sink( | 246 | dc_sink = dc_link_add_remote_sink( |
249 | aconnector->dc_link, | 247 | aconnector->dc_link, |
250 | (uint8_t *)edid, | 248 | (uint8_t *)aconnector->edid, |
251 | (edid->extensions + 1) * EDID_LENGTH, | 249 | (aconnector->edid->extensions + 1) * EDID_LENGTH, |
252 | &init_params); | 250 | &init_params); |
253 | 251 | ||
254 | dc_sink->priv = aconnector; | 252 | dc_sink->priv = aconnector; |
@@ -256,12 +254,12 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) | |||
256 | 254 | ||
257 | if (aconnector->dc_sink) | 255 | if (aconnector->dc_sink) |
258 | amdgpu_dm_add_sink_to_freesync_module( | 256 | amdgpu_dm_add_sink_to_freesync_module( |
259 | connector, edid); | 257 | connector, aconnector->edid); |
260 | |||
261 | drm_mode_connector_update_edid_property( | ||
262 | &aconnector->base, edid); | ||
263 | } | 258 | } |
264 | 259 | ||
260 | drm_mode_connector_update_edid_property( | ||
261 | &aconnector->base, aconnector->edid); | ||
262 | |||
265 | ret = drm_add_edid_modes(connector, aconnector->edid); | 263 | ret = drm_add_edid_modes(connector, aconnector->edid); |
266 | 264 | ||
267 | return ret; | 265 | return ret; |
@@ -424,14 +422,6 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, | |||
424 | dc_sink_release(aconnector->dc_sink); | 422 | dc_sink_release(aconnector->dc_sink); |
425 | aconnector->dc_sink = NULL; | 423 | aconnector->dc_sink = NULL; |
426 | } | 424 | } |
427 | if (aconnector->edid) { | ||
428 | kfree(aconnector->edid); | ||
429 | aconnector->edid = NULL; | ||
430 | } | ||
431 | |||
432 | drm_mode_connector_update_edid_property( | ||
433 | &aconnector->base, | ||
434 | NULL); | ||
435 | 425 | ||
436 | aconnector->mst_connected = false; | 426 | aconnector->mst_connected = false; |
437 | } | 427 | } |