diff options
| author | Tiffany Lin <tiffany.lin@mediatek.com> | 2016-05-03 06:11:27 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@s-opensource.com> | 2016-07-08 13:13:55 -0400 |
| commit | 8eb80252424375de3cdcf16c199d68894b9561f1 (patch) | |
| tree | 039f013b4ef631bea0dc8fcf338e5d0b67cda7bd | |
| parent | 2cc93862d4840fd50c287a17d99a4fe78ae4844b (diff) | |
[media] arm64: dts: mediatek: Add Video Encoder for MT8173
Add video encoder node for MT8173
Signed-off-by: Tiffany Lin <tiffany.lin@mediatek.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173.dtsi | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 72a230f81042..77b8c4e388ca 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi | |||
| @@ -777,6 +777,45 @@ | |||
| 777 | clock-names = "apb", "smi"; | 777 | clock-names = "apb", "smi"; |
| 778 | }; | 778 | }; |
| 779 | 779 | ||
| 780 | vcodec_enc: vcodec@18002000 { | ||
| 781 | compatible = "mediatek,mt8173-vcodec-enc"; | ||
| 782 | reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ | ||
| 783 | <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ | ||
| 784 | interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, | ||
| 785 | <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; | ||
| 786 | mediatek,larb = <&larb3>, | ||
| 787 | <&larb5>; | ||
| 788 | iommus = <&iommu M4U_PORT_VENC_RCPU>, | ||
| 789 | <&iommu M4U_PORT_VENC_REC>, | ||
| 790 | <&iommu M4U_PORT_VENC_BSDMA>, | ||
| 791 | <&iommu M4U_PORT_VENC_SV_COMV>, | ||
| 792 | <&iommu M4U_PORT_VENC_RD_COMV>, | ||
| 793 | <&iommu M4U_PORT_VENC_CUR_LUMA>, | ||
| 794 | <&iommu M4U_PORT_VENC_CUR_CHROMA>, | ||
| 795 | <&iommu M4U_PORT_VENC_REF_LUMA>, | ||
| 796 | <&iommu M4U_PORT_VENC_REF_CHROMA>, | ||
| 797 | <&iommu M4U_PORT_VENC_NBM_RDMA>, | ||
| 798 | <&iommu M4U_PORT_VENC_NBM_WDMA>, | ||
| 799 | <&iommu M4U_PORT_VENC_RCPU_SET2>, | ||
| 800 | <&iommu M4U_PORT_VENC_REC_FRM_SET2>, | ||
| 801 | <&iommu M4U_PORT_VENC_BSDMA_SET2>, | ||
| 802 | <&iommu M4U_PORT_VENC_SV_COMA_SET2>, | ||
| 803 | <&iommu M4U_PORT_VENC_RD_COMA_SET2>, | ||
| 804 | <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, | ||
| 805 | <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, | ||
| 806 | <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, | ||
| 807 | <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; | ||
| 808 | mediatek,vpu = <&vpu>; | ||
| 809 | clocks = <&topckgen CLK_TOP_VENCPLL_D2>, | ||
| 810 | <&topckgen CLK_TOP_VENC_SEL>, | ||
| 811 | <&topckgen CLK_TOP_UNIVPLL1_D2>, | ||
| 812 | <&topckgen CLK_TOP_VENC_LT_SEL>; | ||
| 813 | clock-names = "venc_sel_src", | ||
| 814 | "venc_sel", | ||
| 815 | "venc_lt_sel_src", | ||
| 816 | "venc_lt_sel"; | ||
| 817 | }; | ||
| 818 | |||
| 780 | vencltsys: clock-controller@19000000 { | 819 | vencltsys: clock-controller@19000000 { |
| 781 | compatible = "mediatek,mt8173-vencltsys", "syscon"; | 820 | compatible = "mediatek,mt8173-vencltsys", "syscon"; |
| 782 | reg = <0 0x19000000 0 0x1000>; | 821 | reg = <0 0x19000000 0 0x1000>; |