clk: samsung: exynos5433: Add clocks for CMU_ISP domain

This patch adds the mux/divider/gate clocks for CMU_ISP domain which generates the clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
author: Chanwoo Choi <cw00.choi@samsung.com> 2015-02-02 19:13:54 -0500
committer: Sylwester Nawrocki <s.nawrocki@samsung.com> 2015-02-05 13:31:06 -0500
commit: 8e46c4b84faf317773d5a4ec6d807ceae2d0eb41 (patch)
tree: cdb7af210fdb36a90034e3b48f8dc1629d2e1ecf
parent: 45e58aa5f751fd861d46f7b6d438c1be147458c6 (diff)
3 files changed, 375 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index acc1d8aac95c..4f3bfcd366a3 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -43,6 +43,8 @@ Required Properties:
    which generates clocks for MFC(Multi-Format Codec) IP.
  - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
    which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
+  - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
+    which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
 - reg: physical base address of the controller and length of memory mapped
  region.
@@ -137,6 +139,11 @@ Required Properties:
                - oscclk
                - aclk_hevc_400
+        Input clocks for isp clock controller:
+                - oscclk
+                - aclk_isp_dis_400
+                - aclk_isp_400
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume.
@@ -370,6 +377,19 @@ Example 2: Examples of clock controller nodes are listed below.
                clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
        };
+        cmu_isp: clock-controller@146d0000 {
+                compatible = "samsung,exynos5433-cmu-isp";
+                reg = <0x146d0000 0x0b0c>;
+                #clock-cells = <1>;
+                clock-names = "oscclk",
+                        "aclk_isp_dis_400",
+                        "aclk_isp_400";
+                clocks = <&xxti>,
+                       <&cmu_top CLK_ACLK_ISP_DIS_400>,
+                       <&cmu_top CLK_ACLK_ISP_400>;
+        };
 Example 3: UART controller node that consumes the clock generated by the clock
           controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 482a603c7e6b..a8ea6e1fbffc 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -404,6 +404,12 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
 };
 static struct samsung_div_clock top_div_clks[] __initdata = {
+        /* DIV_TOP0 */
+        DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
+                        "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
+        DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
+                        "mout_aclk_isp_400", DIV_TOP0, 0, 4),
        /* DIV_TOP1 */
        DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
                        DIV_TOP1, 28, 3),
@@ -560,6 +566,12 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
        GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
                        ENABLE_ACLK_TOP, 14,
                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
+                        ENABLE_ACLK_TOP, 7,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
+                        ENABLE_ACLK_TOP, 6,
+                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
                        ENABLE_ACLK_TOP, 5,
                        CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
@@ -4218,3 +4230,258 @@ static void __init exynos5433_cmu_hevc_init(struct device_node *np)
 }
 CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
                exynos5433_cmu_hevc_init);
+/*
+ * Register offset definitions for CMU_ISP
+ */
+#define MUX_SEL_ISP                     0x0200
+#define MUX_ENABLE_ISP                  0x0300
+#define MUX_STAT_ISP                    0x0400
+#define DIV_ISP                         0x0600
+#define DIV_STAT_ISP                    0x0700
+#define ENABLE_ACLK_ISP0                0x0800
+#define ENABLE_ACLK_ISP1                0x0804
+#define ENABLE_ACLK_ISP2                0x0808
+#define ENABLE_PCLK_ISP                 0x0900
+#define ENABLE_SCLK_ISP                 0x0a00
+#define ENABLE_IP_ISP0                  0x0b00
+#define ENABLE_IP_ISP1                  0x0b04
+#define ENABLE_IP_ISP2                  0x0b08
+#define ENABLE_IP_ISP3                  0x0b0c
+static unsigned long isp_clk_regs[] __initdata = {
+        MUX_SEL_ISP,
+        MUX_ENABLE_ISP,
+        MUX_STAT_ISP,
+        DIV_ISP,
+        DIV_STAT_ISP,
+        ENABLE_ACLK_ISP0,
+        ENABLE_ACLK_ISP1,
+        ENABLE_ACLK_ISP2,
+        ENABLE_PCLK_ISP,
+        ENABLE_SCLK_ISP,
+        ENABLE_IP_ISP0,
+        ENABLE_IP_ISP1,
+        ENABLE_IP_ISP2,
+        ENABLE_IP_ISP3,
+};
+PNAME(mout_aclk_isp_dis_400_user_p)     = { "oscclk", "aclk_isp_dis_400", };
+PNAME(mout_aclk_isp_400_user_p)         = { "oscclk", "aclk_isp_400", };
+static struct samsung_mux_clock isp_mux_clks[] __initdata = {
+        /* MUX_SEL_ISP */
+        MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
+                        mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
+        MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
+                        mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
+};
+static struct samsung_div_clock isp_div_clks[] __initdata = {
+        /* DIV_ISP */
+        DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
+                        "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
+        DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
+                        DIV_ISP, 8, 3),
+        DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
+                        "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
+        DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
+                        "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
+};
+static struct samsung_gate_clock isp_gate_clks[] __initdata = {
+        /* ENABLE_ACLK_ISP0 */
+        GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 5, 0, 0),
+        GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 4, 0, 0),
+        GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
+                        ENABLE_ACLK_ISP0, 3, 0, 0),
+        GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 2, 0, 0),
+        GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 1, 0, 0),
+        GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP0, 0, 0, 0),
+        /* ENABLE_ACLK_ISP1 */
+        GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+                        17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+                        16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+                        15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
+                        "div_pclk_isp", ENABLE_ACLK_ISP1,
+                        14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
+                        "div_pclk_isp", ENABLE_ACLK_ISP1,
+                        13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
+                        "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
+                        12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
+                        "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
+                        11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+                        10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
+                        9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
+                        "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
+                        8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
+                        "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
+                        7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
+                        ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
+                        ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
+                        "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
+                        4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
+                        "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
+                        3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
+        /* ENABLE_ACLK_ISP2 */
+        GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+                        13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+                        9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+                        6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
+                        "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
+                        2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
+                        ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
+        /* ENABLE_PCLK_ISP */
+        GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
+                        ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
+                        "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
+                        7, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
+                        ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
+                        ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
+                        ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
+        /* ENABLE_SCLK_ISP */
+        GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
+                        "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
+                        5, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
+                        "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
+                        4, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
+                        "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+                        3, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
+                        "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+                        2, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
+                        "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+                        1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
+                        "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
+                        0, CLK_IGNORE_UNUSED, 0),
+};
+static struct samsung_cmu_info isp_cmu_info __initdata = {
+        .mux_clks               = isp_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(isp_mux_clks),
+        .div_clks               = isp_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(isp_div_clks),
+        .gate_clks              = isp_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(isp_gate_clks),
+        .nr_clk_ids             = ISP_NR_CLK,
+        .clk_regs               = isp_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(isp_clk_regs),
+};
+static void __init exynos5433_cmu_isp_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &isp_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
+                exynos5433_cmu_isp_init);
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 1b2d333c1786..fbc81e3424a6 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -116,6 +116,8 @@
 #define CLK_DIV_SCLK_USBDRD30           143
 #define CLK_DIV_SCLK_JPEG               144
 #define CLK_DIV_ACLK_MSCL_400           145
+#define CLK_DIV_ACLK_ISP_DIS_400        146
+#define CLK_DIV_ACLK_ISP_400            147
 #define CLK_ACLK_PERIC_66               200
 #define CLK_ACLK_PERIS_66               201
@@ -155,8 +157,10 @@
 #define CLK_ACLK_MSCL_400               235
 #define CLK_ACLK_MFC_400                236
 #define CLK_ACLK_HEVC_400               237
+#define CLK_ACLK_ISP_DIS_400            238
+#define CLK_ACLK_ISP_400                239
-#define TOP_NR_CLK                      238
+#define TOP_NR_CLK                      240
 /* CMU_CPIF */
 #define CLK_FOUT_MPHY_PLL               1
@@ -1026,4 +1030,87 @@
 #define HEVC_NR_CLK                                     19
+/* CMU_ISP */
+#define CLK_MOUT_ACLK_ISP_DIS_400_USER                  1
+#define CLK_MOUT_ACLK_ISP_400_USER                      2
+#define CLK_DIV_PCLK_ISP_DIS                            3
+#define CLK_DIV_PCLK_ISP                                4
+#define CLK_DIV_ACLK_ISP_D_200                          5
+#define CLK_DIV_ACLK_ISP_C_200                          6
+#define CLK_ACLK_ISP_D_GLUE                             7
+#define CLK_ACLK_SCALERP                                8
+#define CLK_ACLK_3DNR                                   9
+#define CLK_ACLK_DIS                                    10
+#define CLK_ACLK_SCALERC                                11
+#define CLK_ACLK_DRC                                    12
+#define CLK_ACLK_ISP                                    13
+#define CLK_ACLK_AXIUS_SCALERP                          14
+#define CLK_ACLK_AXIUS_SCALERC                          15
+#define CLK_ACLK_AXIUS_DRC                              16
+#define CLK_ACLK_ASYNCAHBM_ISP2P                        17
+#define CLK_ACLK_ASYNCAHBM_ISP1P                        18
+#define CLK_ACLK_ASYNCAXIS_DIS1                         19
+#define CLK_ACLK_ASYNCAXIS_DIS0                         20
+#define CLK_ACLK_ASYNCAXIM_DIS1                         21
+#define CLK_ACLK_ASYNCAXIM_DIS0                         22
+#define CLK_ACLK_ASYNCAXIM_ISP2P                        23
+#define CLK_ACLK_ASYNCAXIM_ISP1P                        24
+#define CLK_ACLK_AHB2APB_ISP2P                          25
+#define CLK_ACLK_AHB2APB_ISP1P                          26
+#define CLK_ACLK_AXI2APB_ISP2P                          27
+#define CLK_ACLK_AXI2APB_ISP1P                          28
+#define CLK_ACLK_XIU_ISPEX1                             29
+#define CLK_ACLK_XIU_ISPEX0                             30
+#define CLK_ACLK_ISPND_400                              31
+#define CLK_ACLK_SMMU_SCALERP                           32
+#define CLK_ACLK_SMMU_3DNR                              33
+#define CLK_ACLK_SMMU_DIS1                              34
+#define CLK_ACLK_SMMU_DIS0                              35
+#define CLK_ACLK_SMMU_SCALERC                           36
+#define CLK_ACLK_SMMU_DRC                               37
+#define CLK_ACLK_SMMU_ISP                               38
+#define CLK_ACLK_BTS_SCALERP                            39
+#define CLK_ACLK_BTS_3DR                                40
+#define CLK_ACLK_BTS_DIS1                               41
+#define CLK_ACLK_BTS_DIS0                               42
+#define CLK_ACLK_BTS_SCALERC                            43
+#define CLK_ACLK_BTS_DRC                                44
+#define CLK_ACLK_BTS_ISP                                45
+#define CLK_PCLK_SMMU_SCALERP                           46
+#define CLK_PCLK_SMMU_3DNR                              47
+#define CLK_PCLK_SMMU_DIS1                              48
+#define CLK_PCLK_SMMU_DIS0                              49
+#define CLK_PCLK_SMMU_SCALERC                           50
+#define CLK_PCLK_SMMU_DRC                               51
+#define CLK_PCLK_SMMU_ISP                               52
+#define CLK_PCLK_BTS_SCALERP                            53
+#define CLK_PCLK_BTS_3DNR                               54
+#define CLK_PCLK_BTS_DIS1                               55
+#define CLK_PCLK_BTS_DIS0                               56
+#define CLK_PCLK_BTS_SCALERC                            57
+#define CLK_PCLK_BTS_DRC                                58
+#define CLK_PCLK_BTS_ISP                                59
+#define CLK_PCLK_ASYNCAXI_DIS1                          60
+#define CLK_PCLK_ASYNCAXI_DIS0                          61
+#define CLK_PCLK_PMU_ISP                                62
+#define CLK_PCLK_SYSREG_ISP                             63
+#define CLK_PCLK_CMU_ISP_LOCAL                          64
+#define CLK_PCLK_SCALERP                                65
+#define CLK_PCLK_3DNR                                   66
+#define CLK_PCLK_DIS_CORE                               67
+#define CLK_PCLK_DIS                                    68
+#define CLK_PCLK_SCALERC                                69
+#define CLK_PCLK_DRC                                    70
+#define CLK_PCLK_ISP                                    71
+#define CLK_SCLK_PIXELASYNCS_DIS                        72
+#define CLK_SCLK_PIXELASYNCM_DIS                        73
+#define CLK_SCLK_PIXELASYNCS_SCALERP                    74
+#define CLK_SCLK_PIXELASYNCM_ISPD                       75
+#define CLK_SCLK_PIXELASYNCS_ISPC                       76
+#define CLK_SCLK_PIXELASYNCM_ISPC                       77
+#define ISP_NR_CLK                                      78
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
author	Chanwoo Choi <cw00.choi@samsung.com>	2015-02-02 19:13:54 -0500
committer	Sylwester Nawrocki <s.nawrocki@samsung.com>	2015-02-05 13:31:06 -0500
commit	8e46c4b84faf317773d5a4ec6d807ceae2d0eb41 (patch)
tree	cdb7af210fdb36a90034e3b48f8dc1629d2e1ecf
parent	45e58aa5f751fd861d46f7b6d438c1be147458c6 (diff)

diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt index acc1d8aac95c..4f3bfcd366a3 100644 --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -43,6 +43,8 @@ Required Properties:
43	which generates clocks for MFC(Multi-Format Codec) IP.	43	which generates clocks for MFC(Multi-Format Codec) IP.
44	- "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC	44	- "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
45	which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.	45	which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
		46	- "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
		47	which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
46		48
47	- reg: physical base address of the controller and length of memory mapped	49	- reg: physical base address of the controller and length of memory mapped
48	region.	50	region.
@@ -137,6 +139,11 @@ Required Properties:
137	- oscclk	139	- oscclk
138	- aclk_hevc_400	140	- aclk_hevc_400
139		141
		142	Input clocks for isp clock controller:
		143	- oscclk
		144	- aclk_isp_dis_400
		145	- aclk_isp_400
		146
140	Each clock is assigned an identifier and client nodes can use this identifier	147	Each clock is assigned an identifier and client nodes can use this identifier
141	to specify the clock which they consume.	148	to specify the clock which they consume.
142		149
@@ -370,6 +377,19 @@ Example 2: Examples of clock controller nodes are listed below.
370	clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;	377	clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
371	};	378	};
372		379
		380	cmu_isp: clock-controller@146d0000 {
		381	compatible = "samsung,exynos5433-cmu-isp";
		382	reg = <0x146d0000 0x0b0c>;
		383	#clock-cells = <1>;
		384
		385	clock-names = "oscclk",
		386	"aclk_isp_dis_400",
		387	"aclk_isp_400";
		388	clocks = <&xxti>,
		389	<&cmu_top CLK_ACLK_ISP_DIS_400>,
		390	<&cmu_top CLK_ACLK_ISP_400>;
		391	};
		392
373	Example 3: UART controller node that consumes the clock generated by the clock	393	Example 3: UART controller node that consumes the clock generated by the clock
374	controller.	394	controller.
375		395


diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 482a603c7e6b..a8ea6e1fbffc 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -404,6 +404,12 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = {
404	};	404	};
405		405
406	static struct samsung_div_clock top_div_clks[] __initdata = {	406	static struct samsung_div_clock top_div_clks[] __initdata = {
		407	/* DIV_TOP0 */
		408	DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
		409	"mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
		410	DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
		411	"mout_aclk_isp_400", DIV_TOP0, 0, 4),
		412
407	/* DIV_TOP1 */	413	/* DIV_TOP1 */
408	DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",	414	DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
409	DIV_TOP1, 28, 3),	415	DIV_TOP1, 28, 3),
@@ -560,6 +566,12 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
560	GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",	566	GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
561	ENABLE_ACLK_TOP, 14,	567	ENABLE_ACLK_TOP, 14,
562	CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED, 0),	568	CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED, 0),
		569	GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
		570	ENABLE_ACLK_TOP, 7,
		571	CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED, 0),
		572	GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
		573	ENABLE_ACLK_TOP, 6,
		574	CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED, 0),
563	GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",	575	GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
564	ENABLE_ACLK_TOP, 5,	576	ENABLE_ACLK_TOP, 5,
565	CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED, 0),	577	CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED, 0),
@@ -4218,3 +4230,258 @@ static void __init exynos5433_cmu_hevc_init(struct device_node *np)
4218	}	4230	}
4219	CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",	4231	CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4220	exynos5433_cmu_hevc_init);	4232	exynos5433_cmu_hevc_init);
		4233
		4234	/*
		4235	* Register offset definitions for CMU_ISP
		4236	*/
		4237	#define MUX_SEL_ISP 0x0200
		4238	#define MUX_ENABLE_ISP 0x0300
		4239	#define MUX_STAT_ISP 0x0400
		4240	#define DIV_ISP 0x0600
		4241	#define DIV_STAT_ISP 0x0700
		4242	#define ENABLE_ACLK_ISP0 0x0800
		4243	#define ENABLE_ACLK_ISP1 0x0804
		4244	#define ENABLE_ACLK_ISP2 0x0808
		4245	#define ENABLE_PCLK_ISP 0x0900
		4246	#define ENABLE_SCLK_ISP 0x0a00
		4247	#define ENABLE_IP_ISP0 0x0b00
		4248	#define ENABLE_IP_ISP1 0x0b04
		4249	#define ENABLE_IP_ISP2 0x0b08
		4250	#define ENABLE_IP_ISP3 0x0b0c
		4251
		4252	static unsigned long isp_clk_regs[] __initdata = {
		4253	MUX_SEL_ISP,
		4254	MUX_ENABLE_ISP,
		4255	MUX_STAT_ISP,
		4256	DIV_ISP,
		4257	DIV_STAT_ISP,
		4258	ENABLE_ACLK_ISP0,
		4259	ENABLE_ACLK_ISP1,
		4260	ENABLE_ACLK_ISP2,
		4261	ENABLE_PCLK_ISP,
		4262	ENABLE_SCLK_ISP,
		4263	ENABLE_IP_ISP0,
		4264	ENABLE_IP_ISP1,
		4265	ENABLE_IP_ISP2,
		4266	ENABLE_IP_ISP3,
		4267	};
		4268
		4269	PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
		4270	PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
		4271
		4272	static struct samsung_mux_clock isp_mux_clks[] __initdata = {
		4273	/* MUX_SEL_ISP */
		4274	MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
		4275	mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
		4276	MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
		4277	mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
		4278	};
		4279
		4280	static struct samsung_div_clock isp_div_clks[] __initdata = {
		4281	/* DIV_ISP */
		4282	DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
		4283	"mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
		4284	DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
		4285	DIV_ISP, 8, 3),
		4286	DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
		4287	"mout_aclk_isp_400_user", DIV_ISP, 4, 3),
		4288	DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
		4289	"mout_aclk_isp_400_user", DIV_ISP, 0, 3),
		4290	};
		4291
		4292	static struct samsung_gate_clock isp_gate_clks[] __initdata = {
		4293	/* ENABLE_ACLK_ISP0 */
		4294	GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
		4295	ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
		4296	GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
		4297	ENABLE_ACLK_ISP0, 5, 0, 0),
		4298	GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
		4299	ENABLE_ACLK_ISP0, 4, 0, 0),
		4300	GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
		4301	ENABLE_ACLK_ISP0, 3, 0, 0),
		4302	GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
		4303	ENABLE_ACLK_ISP0, 2, 0, 0),
		4304	GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
		4305	ENABLE_ACLK_ISP0, 1, 0, 0),
		4306	GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
		4307	ENABLE_ACLK_ISP0, 0, 0, 0),
		4308
		4309	/* ENABLE_ACLK_ISP1 */
		4310	GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
		4311	"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
		4312	17, CLK_IGNORE_UNUSED, 0),
		4313	GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
		4314	"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
		4315	16, CLK_IGNORE_UNUSED, 0),
		4316	GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
		4317	"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
		4318	15, CLK_IGNORE_UNUSED, 0),
		4319	GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
		4320	"div_pclk_isp", ENABLE_ACLK_ISP1,
		4321	14, CLK_IGNORE_UNUSED, 0),
		4322	GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
		4323	"div_pclk_isp", ENABLE_ACLK_ISP1,
		4324	13, CLK_IGNORE_UNUSED, 0),
		4325	GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
		4326	"mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
		4327	12, CLK_IGNORE_UNUSED, 0),
		4328	GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
		4329	"mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
		4330	11, CLK_IGNORE_UNUSED, 0),
		4331	GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
		4332	"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
		4333	10, CLK_IGNORE_UNUSED, 0),
		4334	GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
		4335	"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
		4336	9, CLK_IGNORE_UNUSED, 0),
		4337	GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
		4338	"div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
		4339	8, CLK_IGNORE_UNUSED, 0),
		4340	GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
		4341	"div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
		4342	7, CLK_IGNORE_UNUSED, 0),
		4343	GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
		4344	ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
		4345	GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
		4346	ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
		4347	GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
		4348	"div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
		4349	4, CLK_IGNORE_UNUSED, 0),
		4350	GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
		4351	"div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
		4352	3, CLK_IGNORE_UNUSED, 0),
		4353	GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
		4354	ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
		4355	GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
		4356	ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
		4357	GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
		4358	ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
		4359
		4360	/* ENABLE_ACLK_ISP2 */
		4361	GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
		4362	"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
		4363	13, CLK_IGNORE_UNUSED, 0),
		4364	GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
		4365	ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
		4366	GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
		4367	ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
		4368	GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
		4369	ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
		4370	GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
		4371	"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
		4372	9, CLK_IGNORE_UNUSED, 0),
		4373	GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
		4374	ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
		4375	GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
		4376	ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
		4377	GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
		4378	"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
		4379	6, CLK_IGNORE_UNUSED, 0),
		4380	GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
		4381	ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
		4382	GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
		4383	ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
		4384	GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
		4385	ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
		4386	GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
		4387	"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
		4388	2, CLK_IGNORE_UNUSED, 0),
		4389	GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
		4390	ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
		4391	GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
		4392	ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
		4393
		4394	/* ENABLE_PCLK_ISP */
		4395	GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
		4396	ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
		4397	GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
		4398	ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
		4399	GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
		4400	ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
		4401	GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
		4402	ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
		4403	GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
		4404	ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
		4405	GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
		4406	ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
		4407	GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
		4408	ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
		4409	GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
		4410	ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
		4411	GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
		4412	ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
		4413	GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
		4414	ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
		4415	GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
		4416	ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
		4417	GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
		4418	ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
		4419	GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
		4420	ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
		4421	GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
		4422	ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
		4423	GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
		4424	ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
		4425	GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
		4426	ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
		4427	GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
		4428	ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
		4429	GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
		4430	ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
		4431	GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
		4432	"div_aclk_isp_c_200", ENABLE_PCLK_ISP,
		4433	7, CLK_IGNORE_UNUSED, 0),
		4434	GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
		4435	ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
		4436	GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
		4437	ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
		4438	GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
		4439	ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
		4440	GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
		4441	ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
		4442	GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
		4443	ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
		4444	GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
		4445	ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
		4446	GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
		4447	ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
		4448
		4449	/* ENABLE_SCLK_ISP */
		4450	GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
		4451	"mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
		4452	5, CLK_IGNORE_UNUSED, 0),
		4453	GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
		4454	"mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
		4455	4, CLK_IGNORE_UNUSED, 0),
		4456	GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
		4457	"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
		4458	3, CLK_IGNORE_UNUSED, 0),
		4459	GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
		4460	"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
		4461	2, CLK_IGNORE_UNUSED, 0),
		4462	GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
		4463	"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
		4464	1, CLK_IGNORE_UNUSED, 0),
		4465	GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
		4466	"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
		4467	0, CLK_IGNORE_UNUSED, 0),
		4468	};
		4469
		4470	static struct samsung_cmu_info isp_cmu_info __initdata = {
		4471	.mux_clks = isp_mux_clks,
		4472	.nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
		4473	.div_clks = isp_div_clks,
		4474	.nr_div_clks = ARRAY_SIZE(isp_div_clks),
		4475	.gate_clks = isp_gate_clks,
		4476	.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
		4477	.nr_clk_ids = ISP_NR_CLK,
		4478	.clk_regs = isp_clk_regs,
		4479	.nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
		4480	};
		4481
		4482	static void __init exynos5433_cmu_isp_init(struct device_node *np)
		4483	{
		4484	samsung_cmu_register_one(np, &isp_cmu_info);
		4485	}
		4486	CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
		4487	exynos5433_cmu_isp_init);


diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 1b2d333c1786..fbc81e3424a6 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h
@@ -116,6 +116,8 @@
116	#define CLK_DIV_SCLK_USBDRD30 143	116	#define CLK_DIV_SCLK_USBDRD30 143
117	#define CLK_DIV_SCLK_JPEG 144	117	#define CLK_DIV_SCLK_JPEG 144
118	#define CLK_DIV_ACLK_MSCL_400 145	118	#define CLK_DIV_ACLK_MSCL_400 145
		119	#define CLK_DIV_ACLK_ISP_DIS_400 146
		120	#define CLK_DIV_ACLK_ISP_400 147
119		121
120	#define CLK_ACLK_PERIC_66 200	122	#define CLK_ACLK_PERIC_66 200
121	#define CLK_ACLK_PERIS_66 201	123	#define CLK_ACLK_PERIS_66 201
@@ -155,8 +157,10 @@
155	#define CLK_ACLK_MSCL_400 235	157	#define CLK_ACLK_MSCL_400 235
156	#define CLK_ACLK_MFC_400 236	158	#define CLK_ACLK_MFC_400 236
157	#define CLK_ACLK_HEVC_400 237	159	#define CLK_ACLK_HEVC_400 237
		160	#define CLK_ACLK_ISP_DIS_400 238
		161	#define CLK_ACLK_ISP_400 239
158		162
159	#define TOP_NR_CLK 238	163	#define TOP_NR_CLK 240
160		164
161	/* CMU_CPIF */	165	/* CMU_CPIF */
162	#define CLK_FOUT_MPHY_PLL 1	166	#define CLK_FOUT_MPHY_PLL 1
@@ -1026,4 +1030,87 @@
1026		1030
1027	#define HEVC_NR_CLK 19	1031	#define HEVC_NR_CLK 19
1028		1032
		1033	/* CMU_ISP */
		1034	#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1
		1035	#define CLK_MOUT_ACLK_ISP_400_USER 2
		1036
		1037	#define CLK_DIV_PCLK_ISP_DIS 3
		1038	#define CLK_DIV_PCLK_ISP 4
		1039	#define CLK_DIV_ACLK_ISP_D_200 5
		1040	#define CLK_DIV_ACLK_ISP_C_200 6
		1041
		1042	#define CLK_ACLK_ISP_D_GLUE 7
		1043	#define CLK_ACLK_SCALERP 8
		1044	#define CLK_ACLK_3DNR 9
		1045	#define CLK_ACLK_DIS 10
		1046	#define CLK_ACLK_SCALERC 11
		1047	#define CLK_ACLK_DRC 12
		1048	#define CLK_ACLK_ISP 13
		1049	#define CLK_ACLK_AXIUS_SCALERP 14
		1050	#define CLK_ACLK_AXIUS_SCALERC 15
		1051	#define CLK_ACLK_AXIUS_DRC 16
		1052	#define CLK_ACLK_ASYNCAHBM_ISP2P 17
		1053	#define CLK_ACLK_ASYNCAHBM_ISP1P 18
		1054	#define CLK_ACLK_ASYNCAXIS_DIS1 19
		1055	#define CLK_ACLK_ASYNCAXIS_DIS0 20
		1056	#define CLK_ACLK_ASYNCAXIM_DIS1 21
		1057	#define CLK_ACLK_ASYNCAXIM_DIS0 22
		1058	#define CLK_ACLK_ASYNCAXIM_ISP2P 23
		1059	#define CLK_ACLK_ASYNCAXIM_ISP1P 24
		1060	#define CLK_ACLK_AHB2APB_ISP2P 25
		1061	#define CLK_ACLK_AHB2APB_ISP1P 26
		1062	#define CLK_ACLK_AXI2APB_ISP2P 27
		1063	#define CLK_ACLK_AXI2APB_ISP1P 28
		1064	#define CLK_ACLK_XIU_ISPEX1 29
		1065	#define CLK_ACLK_XIU_ISPEX0 30
		1066	#define CLK_ACLK_ISPND_400 31
		1067	#define CLK_ACLK_SMMU_SCALERP 32
		1068	#define CLK_ACLK_SMMU_3DNR 33
		1069	#define CLK_ACLK_SMMU_DIS1 34
		1070	#define CLK_ACLK_SMMU_DIS0 35
		1071	#define CLK_ACLK_SMMU_SCALERC 36
		1072	#define CLK_ACLK_SMMU_DRC 37
		1073	#define CLK_ACLK_SMMU_ISP 38
		1074	#define CLK_ACLK_BTS_SCALERP 39
		1075	#define CLK_ACLK_BTS_3DR 40
		1076	#define CLK_ACLK_BTS_DIS1 41
		1077	#define CLK_ACLK_BTS_DIS0 42
		1078	#define CLK_ACLK_BTS_SCALERC 43
		1079	#define CLK_ACLK_BTS_DRC 44
		1080	#define CLK_ACLK_BTS_ISP 45
		1081	#define CLK_PCLK_SMMU_SCALERP 46
		1082	#define CLK_PCLK_SMMU_3DNR 47
		1083	#define CLK_PCLK_SMMU_DIS1 48
		1084	#define CLK_PCLK_SMMU_DIS0 49
		1085	#define CLK_PCLK_SMMU_SCALERC 50
		1086	#define CLK_PCLK_SMMU_DRC 51
		1087	#define CLK_PCLK_SMMU_ISP 52
		1088	#define CLK_PCLK_BTS_SCALERP 53
		1089	#define CLK_PCLK_BTS_3DNR 54
		1090	#define CLK_PCLK_BTS_DIS1 55
		1091	#define CLK_PCLK_BTS_DIS0 56
		1092	#define CLK_PCLK_BTS_SCALERC 57
		1093	#define CLK_PCLK_BTS_DRC 58
		1094	#define CLK_PCLK_BTS_ISP 59
		1095	#define CLK_PCLK_ASYNCAXI_DIS1 60
		1096	#define CLK_PCLK_ASYNCAXI_DIS0 61
		1097	#define CLK_PCLK_PMU_ISP 62
		1098	#define CLK_PCLK_SYSREG_ISP 63
		1099	#define CLK_PCLK_CMU_ISP_LOCAL 64
		1100	#define CLK_PCLK_SCALERP 65
		1101	#define CLK_PCLK_3DNR 66
		1102	#define CLK_PCLK_DIS_CORE 67
		1103	#define CLK_PCLK_DIS 68
		1104	#define CLK_PCLK_SCALERC 69
		1105	#define CLK_PCLK_DRC 70
		1106	#define CLK_PCLK_ISP 71
		1107	#define CLK_SCLK_PIXELASYNCS_DIS 72
		1108	#define CLK_SCLK_PIXELASYNCM_DIS 73
		1109	#define CLK_SCLK_PIXELASYNCS_SCALERP 74
		1110	#define CLK_SCLK_PIXELASYNCM_ISPD 75
		1111	#define CLK_SCLK_PIXELASYNCS_ISPC 76
		1112	#define CLK_SCLK_PIXELASYNCM_ISPC 77
		1113
		1114	#define ISP_NR_CLK 78
		1115
1029	#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */	1116	#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */