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authorKevin Hilman <khilman@linaro.org>2015-06-25 00:32:10 -0400
committerKevin Hilman <khilman@linaro.org>2015-06-25 00:32:10 -0400
commit8d2977bf36bf6fc66d0c8e64263711cc2f0c1e4b (patch)
treeec7ba9c8506ed60509ace9fcd66d38e70d0be562
parentb953c0d234bc72e8489d3bf51a276c5c4ec85345 (diff)
parente75ea4569d6d1d10935d74ff80bad52dc09bd062 (diff)
Merge tag 'armsoc-cleanup' into test-merge
ARM: SoC cleanups for v4.2 A relatively small setup of cleanups this time around, and similar to last time the bulk of it is removal of legacy board support: - OMAP: removal of legacy (non-DT) booting for several platforms - i.MX: remove some legacy board files Conflicts: None # gpg: Signature made Wed Jun 24 21:32:09 2015 PDT using RSA key ID D3FBC665 # gpg: Good signature from "Kevin Hilman <khilman@deeprootsystems.com>" # gpg: aka "Kevin Hilman <khilman@linaro.org>" # gpg: aka "Kevin Hilman <khilman@kernel.org>"
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/atmel-at91.txt2
-rw-r--r--Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt2
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5260-xyref5260.dts2
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3517.dts2
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi2
-rw-r--r--arch/arm/include/asm/suspend.h1
-rw-r--r--arch/arm/kernel/sleep.S14
-rw-r--r--arch/arm/mach-at91/Makefile5
-rw-r--r--arch/arm/mach-at91/Makefile.boot8
-rw-r--r--arch/arm/mach-at91/include/mach/at91_ramc.h28
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_mc.h116
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_smc.h98
-rw-r--r--arch/arm/mach-at91/pm.c8
-rw-r--r--arch/arm/mach-at91/pm.h14
-rw-r--r--arch/arm/mach-at91/pm_suspend.S3
-rw-r--r--arch/arm/mach-at91/sam9_smc.c136
-rw-r--r--arch/arm/mach-at91/sam9_smc.h11
-rw-r--r--arch/arm/mach-bcm/Makefile2
-rw-r--r--arch/arm/mach-bcm/brcmstb.h19
-rw-r--r--arch/arm/mach-bcm/headsmp-brcmstb.S33
-rw-r--r--arch/arm/mach-bcm/platsmp-brcmstb.c4
-rw-r--r--arch/arm/mach-berlin/headsmp.S6
-rw-r--r--arch/arm/mach-berlin/platsmp.c3
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h2
-rw-r--r--arch/arm/mach-hisi/Makefile2
-rw-r--r--arch/arm/mach-hisi/core.h1
-rw-r--r--arch/arm/mach-hisi/headsmp.S16
-rw-r--r--arch/arm/mach-hisi/platsmp.c4
-rw-r--r--arch/arm/mach-imx/Kconfig34
-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/clk-imx6sx.c4
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c318
-rw-r--r--arch/arm/mach-imx/gpc.c1
-rw-r--r--arch/arm/mach-imx/headsmp.S1
-rw-r--r--arch/arm/mach-imx/mach-cpuimx35.c206
-rw-r--r--arch/arm/mach-iop13xx/include/mach/time.h2
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/platform.h2
-rw-r--r--arch/arm/mach-ks8695/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-mvebu/headsmp-a9.S1
-rw-r--r--arch/arm/mach-omap2/Kconfig22
-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c769
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c595
-rw-r--r--arch/arm/mach-omap2/board-overo.c571
-rw-r--r--arch/arm/mach-omap2/devices.c4
-rw-r--r--arch/arm/mach-omap2/fb.c2
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c4
-rw-r--r--arch/arm/mach-omap2/hsmmc.c2
-rw-r--r--arch/arm/mach-omap2/omap-wakeupgen.c2
-rw-r--r--arch/arm/mach-omap2/opp2430_data.c4
-rw-r--r--arch/arm/mach-omap2/pmu.c2
-rw-r--r--arch/arm/mach-omap2/sdrc2xxx.c2
-rw-r--r--arch/arm/mach-omap2/serial.c2
-rw-r--r--arch/arm/mach-omap2/sram242x.S2
-rw-r--r--arch/arm/mach-omap2/sram243x.S2
-rw-r--r--arch/arm/mach-prima2/headsmp.S1
-rw-r--r--arch/arm/mach-pxa/mp900.c2
-rw-r--r--arch/arm/mach-rockchip/core.h1
-rw-r--r--arch/arm/mach-rockchip/headsmp.S8
-rw-r--r--arch/arm/mach-rockchip/platsmp.c5
-rw-r--r--arch/arm/mach-shmobile/common.h1
-rw-r--r--arch/arm/mach-shmobile/headsmp-scu.S4
-rw-r--r--arch/arm/mach-shmobile/headsmp.S7
-rw-r--r--arch/arm/mach-shmobile/platsmp-apmu.c2
-rw-r--r--arch/arm/mach-socfpga/core.h1
-rw-r--r--arch/arm/mach-socfpga/headsmp.S5
-rw-r--r--arch/arm/mach-socfpga/platsmp.c2
-rw-r--r--arch/arm/mach-tegra/Makefile2
-rw-r--r--arch/arm/mach-tegra/headsmp.S12
-rw-r--r--arch/arm/mach-tegra/reset.c2
-rw-r--r--arch/arm/mach-tegra/reset.h1
-rw-r--r--arch/arm/mach-tegra/sleep-tegra30.S2
-rw-r--r--arch/arm/mach-ux500/cache-l2x0.c11
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c60
-rw-r--r--arch/arm/mach-ux500/cpu.c20
-rw-r--r--arch/arm/mach-ux500/id.c2
-rw-r--r--arch/arm/mach-ux500/platsmp.c35
-rw-r--r--arch/arm/mach-ux500/pm.c15
-rw-r--r--arch/arm/mach-ux500/setup.h16
-rw-r--r--arch/arm/mach-zynq/common.h2
-rw-r--r--arch/arm/mach-zynq/headsmp.S5
-rw-r--r--arch/arm/mach-zynq/platsmp.c5
-rw-r--r--arch/arm/mm/proc-v7.S2
-rw-r--r--arch/arm64/boot/dts/skeleton.dtsi13
-rw-r--r--drivers/ata/Kconfig1
-rw-r--r--drivers/ata/pata_at91.c92
-rw-r--r--drivers/pcmcia/Kconfig1
-rw-r--r--drivers/pcmcia/at91_cf.c25
-rw-r--r--include/linux/mfd/syscon/atmel-mc.h144
-rw-r--r--include/soc/at91/at91rm9200_sdramc.h63
92 files changed, 367 insertions, 3312 deletions
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 2e99b5b57350..424ac8cbfa08 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -98,7 +98,7 @@ Example:
98 }; 98 };
99 99
100RAMC SDRAM/DDR Controller required properties: 100RAMC SDRAM/DDR Controller required properties:
101- compatible: Should be "atmel,at91rm9200-sdramc", 101- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
102 "atmel,at91sam9260-sdramc", 102 "atmel,at91sam9260-sdramc",
103 "atmel,at91sam9g45-ddramc", 103 "atmel,at91sam9g45-ddramc",
104 "atmel,sama5d3-ddramc", 104 "atmel,sama5d3-ddramc",
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
index 23e1d3194174..41372d441131 100644
--- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
+++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
@@ -29,7 +29,7 @@ Example:
29 29
30 fuse@7000f800 { 30 fuse@7000f800 {
31 compatible = "nvidia,tegra20-efuse"; 31 compatible = "nvidia,tegra20-efuse";
32 reg = <0x7000F800 0x400>, 32 reg = <0x7000f800 0x400>,
33 <0x70000000 0x400>; 33 <0x70000000 0x400>;
34 clocks = <&tegra_car TEGRA20_CLK_FUSE>; 34 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
35 clock-names = "fuse"; 35 clock-names = "fuse";
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 4fb333bd1f85..6d0fa9b87f46 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -92,7 +92,7 @@
92 }; 92 };
93 93
94 ramc0: ramc@ffffff00 { 94 ramc0: ramc@ffffff00 {
95 compatible = "atmel,at91rm9200-sdramc"; 95 compatible = "atmel,at91rm9200-sdramc", "syscon";
96 reg = <0xffffff00 0x100>; 96 reg = <0xffffff00 0x100>;
97 }; 97 };
98 98
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index a803b605051b..3daef94bee38 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -70,7 +70,7 @@
70 broken-cd; 70 broken-cd;
71 bypass-smu; 71 bypass-smu;
72 cap-mmc-highspeed; 72 cap-mmc-highspeed;
73 supports-hs200-mode; /* 200 Mhz */ 73 supports-hs200-mode; /* 200 MHz */
74 card-detect-delay = <200>; 74 card-detect-delay = <200>;
75 samsung,dw-mshc-ciu-div = <3>; 75 samsung,dw-mshc-ciu-div = <3>;
76 samsung,dw-mshc-sdr-timing = <0 4>; 76 samsung,dw-mshc-sdr-timing = <0 4>;
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
index f5b5a1d96cd7..53ae04f9104d 100644
--- a/arch/arm/boot/dts/omap3-cm-t3517.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -66,7 +66,7 @@
66 66
67 otg_drv_vbus: pinmux_otg_drv_vbus { 67 otg_drv_vbus: pinmux_otg_drv_vbus {
68 pinctrl-single,pins = < 68 pinctrl-single,pins = <
69 OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50Mhz_clk.usb0_drvvbus */ 69 OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */
70 >; 70 >;
71 }; 71 };
72 72
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 13cc7ca5e031..4db9be02399e 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -300,7 +300,7 @@
300 apbmisc@0,70000800 { 300 apbmisc@0,70000800 {
301 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 301 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
302 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 302 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
303 <0x0 0x7000E864 0x0 0x04>; /* Strapping options */ 303 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
304 }; 304 };
305 305
306 pinmux: pinmux@0,70000868 { 306 pinmux: pinmux@0,70000868 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index adf6b048d0bb..f444b67f55c6 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -563,7 +563,7 @@
563 563
564 fuse@7000f800 { 564 fuse@7000f800 {
565 compatible = "nvidia,tegra20-efuse"; 565 compatible = "nvidia,tegra20-efuse";
566 reg = <0x7000F800 0x400>; 566 reg = <0x7000f800 0x400>;
567 clocks = <&tegra_car TEGRA20_CLK_FUSE>; 567 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
568 clock-names = "fuse"; 568 clock-names = "fuse";
569 resets = <&tegra_car 39>; 569 resets = <&tegra_car 39>;
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
index cd20029bcd94..6c7182f32cef 100644
--- a/arch/arm/include/asm/suspend.h
+++ b/arch/arm/include/asm/suspend.h
@@ -7,6 +7,7 @@ struct sleep_save_sp {
7}; 7};
8 8
9extern void cpu_resume(void); 9extern void cpu_resume(void);
10extern void cpu_resume_arm(void);
10extern int cpu_suspend(unsigned long, int (*)(unsigned long)); 11extern int cpu_suspend(unsigned long, int (*)(unsigned long));
11 12
12#endif 13#endif
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 7d37bfc50830..6060dbc7844e 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -118,6 +118,16 @@ ENDPROC(cpu_resume_after_mmu)
118 118
119 .text 119 .text
120 .align 120 .align
121
122#ifdef CONFIG_MMU
123 .arm
124ENTRY(cpu_resume_arm)
125 THUMB( adr r9, BSYM(1f) ) @ Kernel is entered in ARM.
126 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
127 THUMB( .thumb ) @ switch to Thumb now.
128 THUMB(1: )
129#endif
130
121ENTRY(cpu_resume) 131ENTRY(cpu_resume)
122ARM_BE8(setend be) @ ensure we are in BE mode 132ARM_BE8(setend be) @ ensure we are in BE mode
123#ifdef CONFIG_ARM_VIRT_EXT 133#ifdef CONFIG_ARM_VIRT_EXT
@@ -150,6 +160,10 @@ THUMB( mov sp, r2 )
150THUMB( bx r3 ) 160THUMB( bx r3 )
151ENDPROC(cpu_resume) 161ENDPROC(cpu_resume)
152 162
163#ifdef CONFIG_MMU
164ENDPROC(cpu_resume_arm)
165#endif
166
153 .align 2 167 .align 2
154_sleep_save_sp: 168_sleep_save_sp:
155 .long sleep_save_sp - . 169 .long sleep_save_sp - .
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 4fa8b4541e64..c5bbf8bb8c0f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,13 +1,8 @@
1# 1#
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
5asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
6
7obj-y := soc.o 4obj-y := soc.o
8 5
9obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
10
11# CPU-specific support 6# CPU-specific support
12obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o 7obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
13obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o 8obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
deleted file mode 100644
index 29ed0fa374ca..000000000000
--- a/arch/arm/mach-at91/Makefile.boot
+++ /dev/null
@@ -1,8 +0,0 @@
1# Note: the following conditions must always be true:
2# ZRELADDR == virt_to_phys(TEXTADDR)
3# PARAMS_PHYS must be within 4MB of ZRELADDR
4# INITRD_PHYS must be in RAM
5
6 zreladdr-y += 0x20008000
7params_phys-y := 0x20000100
8initrd_phys-y := 0x20410000
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
deleted file mode 100644
index 493bc486e858..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_ramc.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Header file for the Atmel RAM Controller
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#ifndef __AT91_RAMC_H__
10#define __AT91_RAMC_H__
11
12#ifndef __ASSEMBLY__
13extern void __iomem *at91_ramc_base[];
14
15#define at91_ramc_read(id, field) \
16 __raw_readl(at91_ramc_base[id] + field)
17
18#define at91_ramc_write(id, field, value) \
19 __raw_writel(value, at91_ramc_base[id] + field)
20#else
21.extern at91_ramc_base
22#endif
23
24#include <soc/at91/at91rm9200_sdramc.h>
25#include <soc/at91/at91sam9_ddrsdr.h>
26#include <soc/at91/at91sam9_sdramc.h>
27
28#endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
deleted file mode 100644
index aeaadfb452af..000000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91rm9200_mc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_MC_H
17#define AT91RM9200_MC_H
18
19/* Memory Controller */
20#define AT91_MC_RCR 0x00 /* MC Remap Control Register */
21#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
22
23#define AT91_MC_ASR 0x04 /* MC Abort Status Register */
24#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
25#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
26#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
27#define AT91_MC_ABTSZ_BYTE (0 << 8)
28#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
29#define AT91_MC_ABTSZ_WORD (2 << 8)
30#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
31#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
32#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
33#define AT91_MC_ABTTYP_FETCH (2 << 10)
34#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
35#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
36#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
37#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
38#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
39#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
40#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
41#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
42
43#define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */
44
45#define AT91_MC_MPR 0x0c /* MC Master Priority Register */
46#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
47#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
48#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
49#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
50
51/* External Bus Interface (EBI) registers */
52#define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */
53#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
54#define AT91_EBI_CS0A_SMC (0 << 0)
55#define AT91_EBI_CS0A_BFC (1 << 0)
56#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
57#define AT91_EBI_CS1A_SMC (0 << 1)
58#define AT91_EBI_CS1A_SDRAMC (1 << 1)
59#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
60#define AT91_EBI_CS3A_SMC (0 << 3)
61#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
62#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
63#define AT91_EBI_CS4A_SMC (0 << 4)
64#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
65#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
66#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
67
68/* Static Memory Controller (SMC) registers */
69#define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */
70#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
71#define AT91_SMC_NWS_(x) ((x) << 0)
72#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
73#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
74#define AT91_SMC_TDF_(x) ((x) << 8)
75#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
76#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
77#define AT91_SMC_DBW_16 (1 << 13)
78#define AT91_SMC_DBW_8 (2 << 13)
79#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
80#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
81#define AT91_SMC_ACSS_STD (0 << 16)
82#define AT91_SMC_ACSS_1 (1 << 16)
83#define AT91_SMC_ACSS_2 (2 << 16)
84#define AT91_SMC_ACSS_3 (3 << 16)
85#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
86#define AT91_SMC_RWSETUP_(x) ((x) << 24)
87#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
88#define AT91_SMC_RWHOLD_(x) ((x) << 28)
89
90/* Burst Flash Controller register */
91#define AT91_BFC_MR 0xc0 /* Mode Register */
92#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
93#define AT91_BFC_BFCOM_DISABLED (0 << 0)
94#define AT91_BFC_BFCOM_ASYNC (1 << 0)
95#define AT91_BFC_BFCOM_BURST (2 << 0)
96#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
97#define AT91_BFC_BFCC_MCK (1 << 2)
98#define AT91_BFC_BFCC_DIV2 (2 << 2)
99#define AT91_BFC_BFCC_DIV4 (3 << 2)
100#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
101#define AT91_BFC_PAGES (7 << 8) /* Page Size */
102#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
103#define AT91_BFC_PAGES_16 (1 << 8)
104#define AT91_BFC_PAGES_32 (2 << 8)
105#define AT91_BFC_PAGES_64 (3 << 8)
106#define AT91_BFC_PAGES_128 (4 << 8)
107#define AT91_BFC_PAGES_256 (5 << 8)
108#define AT91_BFC_PAGES_512 (6 << 8)
109#define AT91_BFC_PAGES_1024 (7 << 8)
110#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
111#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
112#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
113#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
114#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
115
116#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
deleted file mode 100644
index ff54a0ce90e3..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9_smc.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * Static Memory Controllers (SMC) - System peripherals registers.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91SAM9_SMC_H
17#define AT91SAM9_SMC_H
18
19#ifndef __ASSEMBLY__
20struct sam9_smc_config {
21 /* Setup register */
22 u8 ncs_read_setup;
23 u8 nrd_setup;
24 u8 ncs_write_setup;
25 u8 nwe_setup;
26
27 /* Pulse register */
28 u8 ncs_read_pulse;
29 u8 nrd_pulse;
30 u8 ncs_write_pulse;
31 u8 nwe_pulse;
32
33 /* Cycle register */
34 u16 read_cycle;
35 u16 write_cycle;
36
37 /* Mode register */
38 u32 mode;
39 u8 tdf_cycles:4;
40};
41
42extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
43extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
44extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
45extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
46#endif
47
48#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
49#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
50#define AT91_SMC_NWESETUP_(x) ((x) << 0)
51#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
52#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
53#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
54#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
55#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
56#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
57
58#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
59#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
60#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
61#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
62#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
63#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
64#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
65#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
66#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
67
68#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
69#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
70#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
71#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
72#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
73
74#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
75#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
76#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
77#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
78#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
79#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
80#define AT91_SMC_EXNWMODE_READY (3 << 4)
81#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
82#define AT91_SMC_BAT_SELECT (0 << 8)
83#define AT91_SMC_BAT_WRITE (1 << 8)
84#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
85#define AT91_SMC_DBW_8 (0 << 12)
86#define AT91_SMC_DBW_16 (1 << 12)
87#define AT91_SMC_DBW_32 (2 << 12)
88#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
89#define AT91_SMC_TDF_(x) ((x) << 16)
90#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
91#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
92#define AT91_SMC_PS (3 << 28) /* Page Size */
93#define AT91_SMC_PS_4 (0 << 28)
94#define AT91_SMC_PS_8 (1 << 28)
95#define AT91_SMC_PS_16 (2 << 28)
96#define AT91_SMC_PS_32 (3 << 28)
97
98#endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 5062699cbb12..1e184767c3be 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -233,7 +233,7 @@ static void at91_pm_set_standby(void (*at91_standby)(void))
233 */ 233 */
234static void at91rm9200_standby(void) 234static void at91rm9200_standby(void)
235{ 235{
236 u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR); 236 u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
237 237
238 asm volatile( 238 asm volatile(
239 "b 1f\n\t" 239 "b 1f\n\t"
@@ -244,8 +244,8 @@ static void at91rm9200_standby(void)
244 " mcr p15, 0, %0, c7, c0, 4\n\t" 244 " mcr p15, 0, %0, c7, c0, 4\n\t"
245 " str %5, [%1, %2]" 245 " str %5, [%1, %2]"
246 : 246 :
247 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR), 247 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
248 "r" (1), "r" (AT91RM9200_SDRAMC_SRR), 248 "r" (1), "r" (AT91_MC_SDRAMC_SRR),
249 "r" (lpr)); 249 "r" (lpr));
250} 250}
251 251
@@ -414,7 +414,7 @@ void __init at91rm9200_pm_init(void)
414 /* 414 /*
415 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. 415 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
416 */ 416 */
417 at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); 417 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
418 418
419 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP; 419 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
420 at91_pm_data.memctrl = AT91_MEMCTRL_MC; 420 at91_pm_data.memctrl = AT91_MEMCTRL_MC;
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index ecd875a91d52..3fcf8810f14e 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -13,7 +13,19 @@
13 13
14#include <asm/proc-fns.h> 14#include <asm/proc-fns.h>
15 15
16#include <mach/at91_ramc.h> 16#include <linux/mfd/syscon/atmel-mc.h>
17#include <soc/at91/at91sam9_ddrsdr.h>
18#include <soc/at91/at91sam9_sdramc.h>
19
20#ifndef __ASSEMBLY__
21extern void __iomem *at91_ramc_base[];
22
23#define at91_ramc_read(id, field) \
24 __raw_readl(at91_ramc_base[id] + field)
25
26#define at91_ramc_write(id, field, value) \
27 __raw_writel(value, at91_ramc_base[id] + field)
28#endif
17 29
18#define AT91_MEMCTRL_MC 0 30#define AT91_MEMCTRL_MC 0
19#define AT91_MEMCTRL_SDRAMC 1 31#define AT91_MEMCTRL_SDRAMC 1
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index bd22b2c8a051..0d95f488b47a 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -13,7 +13,6 @@
13 */ 13 */
14#include <linux/linkage.h> 14#include <linux/linkage.h>
15#include <linux/clk/at91_pmc.h> 15#include <linux/clk/at91_pmc.h>
16#include <mach/at91_ramc.h>
17#include "pm.h" 16#include "pm.h"
18 17
19#define SRAMC_SELF_FRESH_ACTIVE 0x01 18#define SRAMC_SELF_FRESH_ACTIVE 0x01
@@ -216,7 +215,7 @@ ENTRY(at91_sramc_self_refresh)
216 215
217 /* Active SDRAM self-refresh mode */ 216 /* Active SDRAM self-refresh mode */
218 mov r3, #1 217 mov r3, #1
219 str r3, [r2, #AT91RM9200_SDRAMC_SRR] 218 str r3, [r2, #AT91_MC_SDRAMC_SRR]
220 b exit_sramc_sf 219 b exit_sramc_sf
221 220
222ddrc_sf: 221ddrc_sf:
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
deleted file mode 100644
index 826315af6d11..000000000000
--- a/arch/arm/mach-at91/sam9_smc.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/sam9_smc.c
3 *
4 * Copyright (C) 2008 Andrew Victor
5 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/io.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16
17#include <mach/at91sam9_smc.h>
18
19#include "sam9_smc.h"
20
21
22#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10))
23
24static void __iomem *smc_base_addr[2];
25
26static void sam9_smc_cs_write_mode(void __iomem *base,
27 struct sam9_smc_config *config)
28{
29 __raw_writel(config->mode
30 | AT91_SMC_TDF_(config->tdf_cycles),
31 base + AT91_SMC_MODE);
32}
33
34void sam9_smc_write_mode(int id, int cs,
35 struct sam9_smc_config *config)
36{
37 sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
38}
39EXPORT_SYMBOL_GPL(sam9_smc_write_mode);
40
41static void sam9_smc_cs_configure(void __iomem *base,
42 struct sam9_smc_config *config)
43{
44
45 /* Setup register */
46 __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
47 | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
48 | AT91_SMC_NRDSETUP_(config->nrd_setup)
49 | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
50 base + AT91_SMC_SETUP);
51
52 /* Pulse register */
53 __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
54 | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
55 | AT91_SMC_NRDPULSE_(config->nrd_pulse)
56 | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
57 base + AT91_SMC_PULSE);
58
59 /* Cycle register */
60 __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
61 | AT91_SMC_NRDCYCLE_(config->read_cycle),
62 base + AT91_SMC_CYCLE);
63
64 /* Mode register */
65 sam9_smc_cs_write_mode(base, config);
66}
67
68void sam9_smc_configure(int id, int cs,
69 struct sam9_smc_config *config)
70{
71 sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
72}
73EXPORT_SYMBOL_GPL(sam9_smc_configure);
74
75static void sam9_smc_cs_read_mode(void __iomem *base,
76 struct sam9_smc_config *config)
77{
78 u32 val = __raw_readl(base + AT91_SMC_MODE);
79
80 config->mode = (val & ~AT91_SMC_NWECYCLE);
81 config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
82}
83
84void sam9_smc_read_mode(int id, int cs,
85 struct sam9_smc_config *config)
86{
87 sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
88}
89EXPORT_SYMBOL_GPL(sam9_smc_read_mode);
90
91static void sam9_smc_cs_read(void __iomem *base,
92 struct sam9_smc_config *config)
93{
94 u32 val;
95
96 /* Setup register */
97 val = __raw_readl(base + AT91_SMC_SETUP);
98
99 config->nwe_setup = val & AT91_SMC_NWESETUP;
100 config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
101 config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
102 config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
103
104 /* Pulse register */
105 val = __raw_readl(base + AT91_SMC_PULSE);
106
107 config->nwe_pulse = val & AT91_SMC_NWEPULSE;
108 config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
109 config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
110 config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
111
112 /* Cycle register */
113 val = __raw_readl(base + AT91_SMC_CYCLE);
114
115 config->write_cycle = val & AT91_SMC_NWECYCLE;
116 config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
117
118 /* Mode register */
119 sam9_smc_cs_read_mode(base, config);
120}
121
122void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
123{
124 sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
125}
126
127void __init at91sam9_ioremap_smc(int id, u32 addr)
128{
129 if (id > 1) {
130 pr_warn("%s: id > 2\n", __func__);
131 return;
132 }
133 smc_base_addr[id] = ioremap(addr, 512);
134 if (!smc_base_addr[id])
135 pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr);
136}
diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h
deleted file mode 100644
index 3e52dcd4a59f..000000000000
--- a/arch/arm/mach-at91/sam9_smc.h
+++ /dev/null
@@ -1,11 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/sam9_smc.
3 *
4 * Copyright (C) 2008 Andrew Victor
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11extern void __init at91sam9_ioremap_smc(int id, u32 addr);
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 4c38674c73ec..54d274da7ccb 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -43,5 +43,5 @@ obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o
43ifeq ($(CONFIG_ARCH_BRCMSTB),y) 43ifeq ($(CONFIG_ARCH_BRCMSTB),y)
44CFLAGS_platsmp-brcmstb.o += -march=armv7-a 44CFLAGS_platsmp-brcmstb.o += -march=armv7-a
45obj-y += brcmstb.o 45obj-y += brcmstb.o
46obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o 46obj-$(CONFIG_SMP) += platsmp-brcmstb.o
47endif 47endif
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
deleted file mode 100644
index ec0c3d112b36..000000000000
--- a/arch/arm/mach-bcm/brcmstb.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (C) 2013-2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __BRCMSTB_H__
15#define __BRCMSTB_H__
16
17void brcmstb_secondary_startup(void);
18
19#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
deleted file mode 100644
index 199c1ea58248..000000000000
--- a/arch/arm/mach-bcm/headsmp-brcmstb.S
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * SMP boot code for secondary CPUs
3 * Based on arch/arm/mach-tegra/headsmp.S
4 *
5 * Copyright (C) 2010 NVIDIA, Inc.
6 * Copyright (C) 2013-2014 Broadcom Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <asm/assembler.h>
19#include <linux/linkage.h>
20#include <linux/init.h>
21
22 .section ".text.head", "ax"
23
24ENTRY(brcmstb_secondary_startup)
25 /*
26 * Ensure CPU is in a sane state by disabling all IRQs and switching
27 * into SVC mode.
28 */
29 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
30
31 bl v7_invalidate_l1
32 b secondary_startup
33ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
index e209e6fc7caf..44d6bddf7a4e 100644
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -30,8 +30,6 @@
30#include <asm/mach-types.h> 30#include <asm/mach-types.h>
31#include <asm/smp_plat.h> 31#include <asm/smp_plat.h>
32 32
33#include "brcmstb.h"
34
35enum { 33enum {
36 ZONE_MAN_CLKEN_MASK = BIT(0), 34 ZONE_MAN_CLKEN_MASK = BIT(0),
37 ZONE_MAN_RESET_CNTL_MASK = BIT(1), 35 ZONE_MAN_RESET_CNTL_MASK = BIT(1),
@@ -153,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
153 * Set the reset vector to point to the secondary_startup 151 * Set the reset vector to point to the secondary_startup
154 * routine 152 * routine
155 */ 153 */
156 cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup)); 154 cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
157 155
158 /* Unhalt the cpu */ 156 /* Unhalt the cpu */
159 cpu_rst_cfg_set(cpu, 0); 157 cpu_rst_cfg_set(cpu, 0);
diff --git a/arch/arm/mach-berlin/headsmp.S b/arch/arm/mach-berlin/headsmp.S
index 4a4c56a58ad3..dc82a3486b05 100644
--- a/arch/arm/mach-berlin/headsmp.S
+++ b/arch/arm/mach-berlin/headsmp.S
@@ -12,12 +12,6 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/assembler.h> 13#include <asm/assembler.h>
14 14
15ENTRY(berlin_secondary_startup)
16 ARM_BE8(setend be)
17 bl v7_invalidate_l1
18 b secondary_startup
19ENDPROC(berlin_secondary_startup)
20
21/* 15/*
22 * If the following instruction is set in the reset exception vector, CPUs 16 * If the following instruction is set in the reset exception vector, CPUs
23 * will fetch the value of the software reset address vector when being 17 * will fetch the value of the software reset address vector when being
diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c
index 702e7982015a..34a3753e7356 100644
--- a/arch/arm/mach-berlin/platsmp.c
+++ b/arch/arm/mach-berlin/platsmp.c
@@ -22,7 +22,6 @@
22#define RESET_VECT 0x00 22#define RESET_VECT 0x00
23#define SW_RESET_ADDR 0x94 23#define SW_RESET_ADDR 0x94
24 24
25extern void berlin_secondary_startup(void);
26extern u32 boot_inst; 25extern u32 boot_inst;
27 26
28static void __iomem *cpu_ctrl; 27static void __iomem *cpu_ctrl;
@@ -85,7 +84,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
85 * Write the secondary startup address into the SW reset address 84 * Write the secondary startup address into the SW reset address
86 * vector. This is used by boot_inst. 85 * vector. This is used by boot_inst.
87 */ 86 */
88 writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR); 87 writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
89 88
90 iounmap(vectors_base); 89 iounmap(vectors_base);
91unmap_scu: 90unmap_scu:
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 39e58b48e826..f9f9713aacdd 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -36,7 +36,7 @@ extern void __iomem *da8xx_syscfg1_base;
36 36
37/* 37/*
38 * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade 38 * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade
39 * (than the regular 300Mhz variant), the board code should set this up 39 * (than the regular 300MHz variant), the board code should set this up
40 * with the supported speed before calling da850_register_cpufreq(). 40 * with the supported speed before calling da850_register_cpufreq().
41 */ 41 */
42extern unsigned int da850_max_speed; 42extern unsigned int da850_max_speed;
diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile
index 6b7b3033de0b..659db1933ed3 100644
--- a/arch/arm/mach-hisi/Makefile
+++ b/arch/arm/mach-hisi/Makefile
@@ -6,4 +6,4 @@ CFLAGS_platmcpm.o := -march=armv7-a
6 6
7obj-y += hisilicon.o 7obj-y += hisilicon.o
8obj-$(CONFIG_MCPM) += platmcpm.o 8obj-$(CONFIG_MCPM) += platmcpm.o
9obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o 9obj-$(CONFIG_SMP) += platsmp.o hotplug.o
diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h
index 92a682d8e939..c7648ef1825c 100644
--- a/arch/arm/mach-hisi/core.h
+++ b/arch/arm/mach-hisi/core.h
@@ -12,7 +12,6 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
12extern int hi3xxx_cpu_kill(unsigned int cpu); 12extern int hi3xxx_cpu_kill(unsigned int cpu);
13extern void hi3xxx_set_cpu(int cpu, bool enable); 13extern void hi3xxx_set_cpu(int cpu, bool enable);
14 14
15extern void hisi_secondary_startup(void);
16extern struct smp_operations hix5hd2_smp_ops; 15extern struct smp_operations hix5hd2_smp_ops;
17extern void hix5hd2_set_cpu(int cpu, bool enable); 16extern void hix5hd2_set_cpu(int cpu, bool enable);
18extern void hix5hd2_cpu_die(unsigned int cpu); 17extern void hix5hd2_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-hisi/headsmp.S b/arch/arm/mach-hisi/headsmp.S
deleted file mode 100644
index 81e35b159e75..000000000000
--- a/arch/arm/mach-hisi/headsmp.S
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * Copyright (c) 2014 Hisilicon Limited.
3 * Copyright (c) 2014 Linaro Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/linkage.h>
10#include <linux/init.h>
11
12 __CPUINIT
13
14ENTRY(hisi_secondary_startup)
15 bl v7_invalidate_l1
16 b secondary_startup
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index 8880c8e8b296..51744127db66 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
118{ 118{
119 phys_addr_t jumpaddr; 119 phys_addr_t jumpaddr;
120 120
121 jumpaddr = virt_to_phys(hisi_secondary_startup); 121 jumpaddr = virt_to_phys(secondary_startup);
122 hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr); 122 hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
123 hix5hd2_set_cpu(cpu, true); 123 hix5hd2_set_cpu(cpu, true);
124 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 124 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
156 struct device_node *node; 156 struct device_node *node;
157 157
158 158
159 jumpaddr = virt_to_phys(hisi_secondary_startup); 159 jumpaddr = virt_to_phys(secondary_startup);
160 hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr); 160 hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
161 161
162 node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl"); 162 node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3a3d3e9d7bfd..388232ce92fc 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -444,40 +444,6 @@ config MACH_MX35_3DS
444 Include support for MX35PDK platform. This includes specific 444 Include support for MX35PDK platform. This includes specific
445 configurations for the board and its peripherals. 445 configurations for the board and its peripherals.
446 446
447config MACH_EUKREA_CPUIMX35SD
448 bool "Support Eukrea CPUIMX35 Platform"
449 select IMX_HAVE_PLATFORM_FLEXCAN
450 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
451 select IMX_HAVE_PLATFORM_IMX2_WDT
452 select IMX_HAVE_PLATFORM_IMX_I2C
453 select IMX_HAVE_PLATFORM_IMX_UART
454 select IMX_HAVE_PLATFORM_MXC_EHCI
455 select IMX_HAVE_PLATFORM_MXC_NAND
456 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
457 select USB_ULPI_VIEWPORT if USB_ULPI
458 select SOC_IMX35
459 help
460 Include support for Eukrea CPUIMX35 platform. This includes
461 specific configurations for the board and its peripherals.
462
463choice
464 prompt "Baseboard"
465 depends on MACH_EUKREA_CPUIMX35SD
466 default MACH_EUKREA_MBIMXSD35_BASEBOARD
467
468config MACH_EUKREA_MBIMXSD35_BASEBOARD
469 bool "Eukrea MBIMXSD development board"
470 select IMX_HAVE_PLATFORM_GPIO_KEYS
471 select IMX_HAVE_PLATFORM_IMX_SSI
472 select IMX_HAVE_PLATFORM_IPU_CORE
473 select IMX_HAVE_PLATFORM_SPI_IMX
474 select LEDS_GPIO_REGISTER
475 help
476 This adds board specific devices that can be found on Eukrea's
477 MBIMXSD evaluation board.
478
479endchoice
480
481config MACH_VPR200 447config MACH_VPR200
482 bool "Support VPR200 platform" 448 bool "Support VPR200 platform"
483 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 449 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 3244cf1d2773..eed609834ffb 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -73,8 +73,6 @@ obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o
73# i.MX35 based machines 73# i.MX35 based machines
74obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o 74obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
75obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o 75obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
76obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
77obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
78obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o 76obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
79obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o 77obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
80 78
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index 5a3e5a159e70..87c5b0911ddd 100644
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -216,7 +216,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
216 clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); 216 clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
217 clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); 217 clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
218 218
219 /* FIXME 100Mhz is used for pcie ref for all imx6 pcie, excepted imx6q */ 219 /* FIXME 100MHz is used for pcie ref for all imx6 pcie, excepted imx6q */
220 clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5); 220 clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
221 clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); 221 clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
222 222
@@ -520,7 +520,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
520 pr_err("Failed to set pcie parent clk.\n"); 520 pr_err("Failed to set pcie parent clk.\n");
521 521
522 /* 522 /*
523 * Init enet system AHB clock, set to 200Mhz 523 * Init enet system AHB clock, set to 200MHz
524 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB 524 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
525 */ 525 */
526 clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); 526 clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
deleted file mode 100644
index 6edc940e0865..000000000000
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ /dev/null
@@ -1,318 +0,0 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/leds.h>
28#include <linux/platform_device.h>
29#include <linux/input.h>
30#include <linux/spi/spi.h>
31#include <video/platform_lcd.h>
32#include <linux/i2c.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/mach/map.h>
38
39#include "common.h"
40#include "devices-imx35.h"
41#include "hardware.h"
42#include "iomux-mx35.h"
43
44static const struct fb_videomode fb_modedb[] = {
45 {
46 .name = "CMO-QVGA",
47 .refresh = 60,
48 .xres = 320,
49 .yres = 240,
50 .pixclock = KHZ2PICOS(6500),
51 .left_margin = 68,
52 .right_margin = 20,
53 .upper_margin = 15,
54 .lower_margin = 4,
55 .hsync_len = 30,
56 .vsync_len = 3,
57 .sync = 0,
58 .vmode = FB_VMODE_NONINTERLACED,
59 .flag = 0,
60 },
61 {
62 .name = "DVI-VGA",
63 .refresh = 60,
64 .xres = 640,
65 .yres = 480,
66 .pixclock = 32000,
67 .left_margin = 100,
68 .right_margin = 100,
69 .upper_margin = 7,
70 .lower_margin = 100,
71 .hsync_len = 7,
72 .vsync_len = 7,
73 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
74 FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
75 .vmode = FB_VMODE_NONINTERLACED,
76 .flag = 0,
77 },
78 {
79 .name = "DVI-SVGA",
80 .refresh = 60,
81 .xres = 800,
82 .yres = 600,
83 .pixclock = 25000,
84 .left_margin = 75,
85 .right_margin = 75,
86 .upper_margin = 7,
87 .lower_margin = 75,
88 .hsync_len = 7,
89 .vsync_len = 7,
90 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
91 FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
92 .vmode = FB_VMODE_NONINTERLACED,
93 .flag = 0,
94 },
95};
96
97static struct mx3fb_platform_data mx3fb_pdata __initdata = {
98 .name = "CMO-QVGA",
99 .mode = fb_modedb,
100 .num_modes = ARRAY_SIZE(fb_modedb),
101};
102
103static const iomux_v3_cfg_t eukrea_mbimxsd_pads[] __initconst = {
104 /* LCD */
105 MX35_PAD_LD0__IPU_DISPB_DAT_0,
106 MX35_PAD_LD1__IPU_DISPB_DAT_1,
107 MX35_PAD_LD2__IPU_DISPB_DAT_2,
108 MX35_PAD_LD3__IPU_DISPB_DAT_3,
109 MX35_PAD_LD4__IPU_DISPB_DAT_4,
110 MX35_PAD_LD5__IPU_DISPB_DAT_5,
111 MX35_PAD_LD6__IPU_DISPB_DAT_6,
112 MX35_PAD_LD7__IPU_DISPB_DAT_7,
113 MX35_PAD_LD8__IPU_DISPB_DAT_8,
114 MX35_PAD_LD9__IPU_DISPB_DAT_9,
115 MX35_PAD_LD10__IPU_DISPB_DAT_10,
116 MX35_PAD_LD11__IPU_DISPB_DAT_11,
117 MX35_PAD_LD12__IPU_DISPB_DAT_12,
118 MX35_PAD_LD13__IPU_DISPB_DAT_13,
119 MX35_PAD_LD14__IPU_DISPB_DAT_14,
120 MX35_PAD_LD15__IPU_DISPB_DAT_15,
121 MX35_PAD_LD16__IPU_DISPB_DAT_16,
122 MX35_PAD_LD17__IPU_DISPB_DAT_17,
123 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
124 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
125 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
126 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
127 /* Backlight */
128 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
129 /* LCD_PWR */
130 MX35_PAD_D3_CLS__GPIO1_4,
131 /* LED */
132 MX35_PAD_LD23__GPIO3_29,
133 /* SWITCH */
134 MX35_PAD_LD19__GPIO3_25,
135 /* UART2 */
136 MX35_PAD_CTS2__UART2_CTS,
137 MX35_PAD_RTS2__UART2_RTS,
138 MX35_PAD_TXD2__UART2_TXD_MUX,
139 MX35_PAD_RXD2__UART2_RXD_MUX,
140 /* I2S */
141 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
142 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
143 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
144 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
145 /* CAN2 */
146 MX35_PAD_TX5_RX0__CAN2_TXCAN,
147 MX35_PAD_TX4_RX1__CAN2_RXCAN,
148 /* SDCARD */
149 MX35_PAD_SD1_CMD__ESDHC1_CMD,
150 MX35_PAD_SD1_CLK__ESDHC1_CLK,
151 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
152 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
153 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
154 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
155 /* SD1 CD */
156 MX35_PAD_LD18__GPIO3_24,
157 /* SPI */
158 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
159 MX35_PAD_CSPI1_MISO__CSPI1_MISO,
160 MX35_PAD_CSPI1_SS0__GPIO1_18,
161 MX35_PAD_CSPI1_SS1__GPIO1_19,
162 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
163 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5,
164};
165
166#define GPIO_LED1 IMX_GPIO_NR(3, 29)
167#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25)
168#define GPIO_LCDPWR IMX_GPIO_NR(1, 4)
169#define GPIO_SD1CD IMX_GPIO_NR(3, 24)
170#define GPIO_SPI1_SS0 IMX_GPIO_NR(1, 18)
171#define GPIO_SPI1_SS1 IMX_GPIO_NR(1, 19)
172#define GPIO_SPI1_IRQ IMX_GPIO_NR(3, 5)
173
174static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
175 unsigned int power)
176{
177 if (power)
178 gpio_direction_output(GPIO_LCDPWR, 1);
179 else
180 gpio_direction_output(GPIO_LCDPWR, 0);
181}
182
183static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
184 .set_power = eukrea_mbimxsd_lcd_power_set,
185};
186
187static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
188 .name = "platform-lcd",
189 .dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
190};
191
192static struct gpio_led eukrea_mbimxsd_leds[] = {
193 {
194 .name = "led1",
195 .default_trigger = "heartbeat",
196 .active_low = 1,
197 .gpio = GPIO_LED1,
198 },
199};
200
201static const struct gpio_led_platform_data
202 eukrea_mbimxsd_led_info __initconst = {
203 .leds = eukrea_mbimxsd_leds,
204 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
205};
206
207static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
208 {
209 .gpio = GPIO_SWITCH1,
210 .code = BTN_0,
211 .desc = "BP1",
212 .active_low = 1,
213 .wakeup = 1,
214 },
215};
216
217static const struct gpio_keys_platform_data
218 eukrea_mbimxsd_button_data __initconst = {
219 .buttons = eukrea_mbimxsd_gpio_buttons,
220 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
221};
222
223static struct platform_device *platform_devices[] __initdata = {
224 &eukrea_mbimxsd_lcd_powerdev,
225};
226
227static const struct imxuart_platform_data uart_pdata __initconst = {
228 .flags = IMXUART_HAVE_RTSCTS,
229};
230
231static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
232 {
233 I2C_BOARD_INFO("tlv320aic23", 0x1a),
234 },
235};
236
237static const
238struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
239 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
240};
241
242static struct esdhc_platform_data sd1_pdata = {
243 .cd_gpio = GPIO_SD1CD,
244 .cd_type = ESDHC_CD_GPIO,
245 .wp_type = ESDHC_WP_NONE,
246};
247
248static struct spi_board_info eukrea_mbimxsd35_spi_board_info[] __initdata = {
249 {
250 .modalias = "spidev",
251 .max_speed_hz = 20000000,
252 .bus_num = 0,
253 .chip_select = 0,
254 .mode = SPI_MODE_0,
255 },
256 {
257 .modalias = "spidev",
258 .max_speed_hz = 20000000,
259 .bus_num = 0,
260 .chip_select = 1,
261 .mode = SPI_MODE_0,
262 },
263};
264
265static int eukrea_mbimxsd35_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
266
267static const struct spi_imx_master eukrea_mbimxsd35_spi0_data __initconst = {
268 .chipselect = eukrea_mbimxsd35_spi_cs,
269 .num_chipselect = ARRAY_SIZE(eukrea_mbimxsd35_spi_cs),
270};
271
272/*
273 * system init for baseboard usage. Will be called by cpuimx35 init.
274 *
275 * Add platform devices present on this baseboard and init
276 * them from CPU side as far as required to use them later on
277 */
278void __init eukrea_mbimxsd35_baseboard_init(void)
279{
280 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
281 ARRAY_SIZE(eukrea_mbimxsd_pads)))
282 printk(KERN_ERR "error setting mbimxsd pads !\n");
283
284 imx35_add_imx_uart1(&uart_pdata);
285 imx35_add_ipu_core();
286 imx35_add_mx3_sdc_fb(&mx3fb_pdata);
287
288 imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
289
290 imx35_add_flexcan1();
291 imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
292
293 gpio_request(GPIO_LED1, "LED1");
294 gpio_direction_output(GPIO_LED1, 1);
295 gpio_free(GPIO_LED1);
296
297 gpio_request(GPIO_SWITCH1, "SWITCH1");
298 gpio_direction_input(GPIO_SWITCH1);
299 gpio_free(GPIO_SWITCH1);
300
301 gpio_request(GPIO_LCDPWR, "LCDPWR");
302 gpio_direction_output(GPIO_LCDPWR, 1);
303
304 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
305 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
306
307 gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ");
308 gpio_direction_input(GPIO_SPI1_IRQ);
309 gpio_free(GPIO_SPI1_IRQ);
310 imx35_add_spi_imx0(&eukrea_mbimxsd35_spi0_data);
311 spi_register_board_info(eukrea_mbimxsd35_spi_board_info,
312 ARRAY_SIZE(eukrea_mbimxsd35_spi_board_info));
313
314 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
315 gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
316 imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
317 imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
318}
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 6d0893a3828e..0ea77ed25b25 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -474,7 +474,6 @@ static const struct of_device_id imx_gpc_dt_ids[] = {
474static struct platform_driver imx_gpc_driver = { 474static struct platform_driver imx_gpc_driver = {
475 .driver = { 475 .driver = {
476 .name = "imx-gpc", 476 .name = "imx-gpc",
477 .owner = THIS_MODULE,
478 .of_match_table = imx_gpc_dt_ids, 477 .of_match_table = imx_gpc_dt_ids,
479 }, 478 },
480 .probe = imx_gpc_probe, 479 .probe = imx_gpc_probe,
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index de5047c8a6c8..b5e976816b63 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -25,7 +25,6 @@ diag_reg_offset:
25 .endm 25 .endm
26 26
27ENTRY(v7_secondary_startup) 27ENTRY(v7_secondary_startup)
28 bl v7_invalidate_l1
29 set_diag_reg 28 set_diag_reg
30 b secondary_startup 29 b secondary_startup
31ENDPROC(v7_secondary_startup) 30ENDPROC(v7_secondary_startup)
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
deleted file mode 100644
index 922ffd6ca039..000000000000
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ /dev/null
@@ -1,206 +0,0 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 * Copyright (C) 2009 Sascha Hauer, Pengutronix
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/types.h>
21#include <linux/init.h>
22
23#include <linux/platform_device.h>
24#include <linux/mtd/physmap.h>
25#include <linux/memory.h>
26#include <linux/gpio.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/i2c.h>
30#include <linux/i2c/tsc2007.h>
31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
33#include <linux/i2c-gpio.h>
34
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37#include <asm/mach/time.h>
38#include <asm/mach/map.h>
39
40#include "common.h"
41#include "devices-imx35.h"
42#include "ehci.h"
43#include "eukrea-baseboards.h"
44#include "hardware.h"
45#include "iomux-mx35.h"
46
47static const struct imxuart_platform_data uart_pdata __initconst = {
48 .flags = IMXUART_HAVE_RTSCTS,
49};
50
51static const struct imxi2c_platform_data
52 eukrea_cpuimx35_i2c0_data __initconst = {
53 .bitrate = 100000,
54};
55
56#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 2)
57static int tsc2007_get_pendown_state(struct device *dev)
58{
59 return !gpio_get_value(TSC2007_IRQGPIO);
60}
61
62static struct tsc2007_platform_data tsc2007_info = {
63 .model = 2007,
64 .x_plate_ohms = 180,
65 .get_pendown_state = tsc2007_get_pendown_state,
66};
67
68static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
69 {
70 I2C_BOARD_INFO("pcf8563", 0x51),
71 }, {
72 I2C_BOARD_INFO("tsc2007", 0x48),
73 .platform_data = &tsc2007_info,
74 /* irq number is run-time assigned */
75 },
76};
77
78static const iomux_v3_cfg_t eukrea_cpuimx35_pads[] __initconst = {
79 /* UART1 */
80 MX35_PAD_CTS1__UART1_CTS,
81 MX35_PAD_RTS1__UART1_RTS,
82 MX35_PAD_TXD1__UART1_TXD_MUX,
83 MX35_PAD_RXD1__UART1_RXD_MUX,
84 /* FEC */
85 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
86 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
87 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
88 MX35_PAD_FEC_COL__FEC_COL,
89 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
90 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
91 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
92 MX35_PAD_FEC_MDC__FEC_MDC,
93 MX35_PAD_FEC_MDIO__FEC_MDIO,
94 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
95 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
96 MX35_PAD_FEC_CRS__FEC_CRS,
97 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
98 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
99 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
100 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
101 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
102 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
103 /* I2C1 */
104 MX35_PAD_I2C1_CLK__I2C1_SCL,
105 MX35_PAD_I2C1_DAT__I2C1_SDA,
106 /* TSC2007 IRQ */
107 MX35_PAD_ATA_DA2__GPIO3_2,
108};
109
110static const struct mxc_nand_platform_data
111 eukrea_cpuimx35_nand_board_info __initconst = {
112 .width = 1,
113 .hw_ecc = 1,
114 .flash_bbt = 1,
115};
116
117static int eukrea_cpuimx35_otg_init(struct platform_device *pdev)
118{
119 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
120}
121
122static const struct mxc_usbh_platform_data otg_pdata __initconst = {
123 .init = eukrea_cpuimx35_otg_init,
124 .portsc = MXC_EHCI_MODE_UTMI,
125};
126
127static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev)
128{
129 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
130 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
131}
132
133static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
134 .init = eukrea_cpuimx35_usbh1_init,
135 .portsc = MXC_EHCI_MODE_SERIAL,
136};
137
138static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
139 .operating_mode = FSL_USB2_DR_DEVICE,
140 .phy_mode = FSL_USB2_PHY_UTMI,
141 .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
142};
143
144static bool otg_mode_host __initdata;
145
146static int __init eukrea_cpuimx35_otg_mode(char *options)
147{
148 if (!strcmp(options, "host"))
149 otg_mode_host = true;
150 else if (!strcmp(options, "device"))
151 otg_mode_host = false;
152 else
153 pr_info("otg_mode neither \"host\" nor \"device\". "
154 "Defaulting to device\n");
155 return 1;
156}
157__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
158
159/*
160 * Board specific initialization.
161 */
162static void __init eukrea_cpuimx35_init(void)
163{
164 imx35_soc_init();
165
166 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
167 ARRAY_SIZE(eukrea_cpuimx35_pads));
168
169 imx35_add_fec(NULL);
170 imx35_add_imx2_wdt();
171
172 imx35_add_imx_uart0(&uart_pdata);
173 imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
174
175 eukrea_cpuimx35_i2c_devices[1].irq = gpio_to_irq(TSC2007_IRQGPIO);
176 i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
177 ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
178 imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
179
180 if (otg_mode_host)
181 imx35_add_mxc_ehci_otg(&otg_pdata);
182 else
183 imx35_add_fsl_usb2_udc(&otg_device_pdata);
184
185 imx35_add_mxc_ehci_hs(&usbh1_pdata);
186
187#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
188 eukrea_mbimxsd35_baseboard_init();
189#endif
190}
191
192static void __init eukrea_cpuimx35_timer_init(void)
193{
194 mx35_clocks_init();
195}
196
197MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
198 /* Maintainer: Eukrea Electromatique */
199 .atag_offset = 0x100,
200 .map_io = mx35_map_io,
201 .init_early = imx35_init_early,
202 .init_irq = mx35_init_irq,
203 .init_time = eukrea_cpuimx35_timer_init,
204 .init_machine = eukrea_cpuimx35_init,
205 .restart = mxc_restart,
206MACHINE_END
diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h
index 15bc9bb78a6b..c871e6874594 100644
--- a/arch/arm/mach-iop13xx/include/mach/time.h
+++ b/arch/arm/mach-iop13xx/include/mach/time.h
@@ -42,7 +42,7 @@ static inline unsigned long iop13xx_core_freq(void)
42 case IOP13XX_CORE_FREQ_1200: 42 case IOP13XX_CORE_FREQ_1200:
43 return 1200000000; 43 return 1200000000;
44 default: 44 default:
45 printk("%s: warning unknown frequency, defaulting to 800Mhz\n", 45 printk("%s: warning unknown frequency, defaulting to 800MHz\n",
46 __func__); 46 __func__);
47 } 47 }
48 48
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index 75c4c6572ad0..34b3d3f3f131 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -74,7 +74,7 @@ extern unsigned long ixp4xx_exp_bus_size;
74/* 74/*
75 * Clock Speed Definitions. 75 * Clock Speed Definitions.
76 */ 76 */
77#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ 77#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66MHzi APB BUS */
78#define IXP4XX_UART_XTAL 14745600 78#define IXP4XX_UART_XTAL 14745600
79 79
80/* 80/*
diff --git a/arch/arm/mach-ks8695/include/mach/hardware.h b/arch/arm/mach-ks8695/include/mach/hardware.h
index 5090338c0db2..959c748ee8bb 100644
--- a/arch/arm/mach-ks8695/include/mach/hardware.h
+++ b/arch/arm/mach-ks8695/include/mach/hardware.h
@@ -17,7 +17,7 @@
17#include <asm/sizes.h> 17#include <asm/sizes.h>
18 18
19/* 19/*
20 * Clocks are derived from MCLK, which is 25Mhz 20 * Clocks are derived from MCLK, which is 25MHz
21 */ 21 */
22#define KS8695_CLOCK_RATE 25000000 22#define KS8695_CLOCK_RATE 25000000
23 23
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
index 08d5ed46b996..48e4c4b3cd1c 100644
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -21,7 +21,6 @@
21 21
22ENTRY(mvebu_cortex_a9_secondary_startup) 22ENTRY(mvebu_cortex_a9_secondary_startup)
23ARM_BE8(setend be) 23ARM_BE8(setend be)
24 bl v7_invalidate_l1
25 bl armada_38x_scu_power_up 24 bl armada_38x_scu_power_up
26 b secondary_startup 25 b secondary_startup
27ENDPROC(mvebu_cortex_a9_secondary_startup) 26ENDPROC(mvebu_cortex_a9_secondary_startup)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 6468f15f060c..ecc04ff13e95 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -171,12 +171,6 @@ config MACH_OMAP2_TUSB6010
171 depends on ARCH_OMAP2 && SOC_OMAP2420 171 depends on ARCH_OMAP2 && SOC_OMAP2420
172 default y if MACH_NOKIA_N8X0 172 default y if MACH_NOKIA_N8X0
173 173
174config MACH_OMAP3_BEAGLE
175 bool "OMAP3 BEAGLE board"
176 depends on ARCH_OMAP3
177 default y
178 select OMAP_PACKAGE_CBB
179
180config MACH_OMAP_LDP 174config MACH_OMAP_LDP
181 bool "OMAP3 LDP board" 175 bool "OMAP3 LDP board"
182 depends on ARCH_OMAP3 176 depends on ARCH_OMAP3
@@ -203,12 +197,6 @@ config MACH_OMAP3_TORPEDO
203 for full description please see the products webpage at 197 for full description please see the products webpage at
204 http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit 198 http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
205 199
206config MACH_OVERO
207 bool "Gumstix Overo board"
208 depends on ARCH_OMAP3
209 default y
210 select OMAP_PACKAGE_CBB
211
212config MACH_OMAP3517EVM 200config MACH_OMAP3517EVM
213 bool "OMAP3517/ AM3517 EVM board" 201 bool "OMAP3517/ AM3517 EVM board"
214 depends on ARCH_OMAP3 202 depends on ARCH_OMAP3
@@ -240,16 +228,6 @@ config MACH_NOKIA_RX51
240 default y 228 default y
241 select OMAP_PACKAGE_CBB 229 select OMAP_PACKAGE_CBB
242 230
243config MACH_CM_T35
244 bool "CompuLab CM-T35/CM-T3730 modules"
245 depends on ARCH_OMAP3
246 default y
247 select MACH_CM_T3730
248 select OMAP_PACKAGE_CUS
249
250config MACH_CM_T3730
251 bool
252
253config OMAP3_SDRC_AC_TIMING 231config OMAP3_SDRC_AC_TIMING
254 bool "Enable SDRC AC timing register changes" 232 bool "Enable SDRC AC timing register changes"
255 depends on ARCH_OMAP3 233 depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ec002bd4af77..f1a68c63dc99 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -242,17 +242,14 @@ obj-$(CONFIG_SOC_OMAP2420) += msdi.o
242 242
243# Specific board support 243# Specific board support
244obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o 244obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
245obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
246obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o 245obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
247obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o 246obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
248obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o 247obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
249obj-$(CONFIG_MACH_OVERO) += board-overo.o
250obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o 248obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o
251obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o 249obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
252obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o 250obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o
253obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o 251obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o
254obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o 252obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o
255obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
256 253
257# Platform specific device init code 254# Platform specific device init code
258 255
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
deleted file mode 100644
index b5dfbc1b1fc6..000000000000
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ /dev/null
@@ -1,769 +0,0 @@
1/*
2 * CompuLab CM-T35/CM-T3730 modules support
3 *
4 * Copyright (C) 2009-2011 CompuLab, Ltd.
5 * Authors: Mike Rapoport <mike@compulab.co.il>
6 * Igor Grinberg <grinberg@compulab.co.il>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 */
18
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/input.h>
25#include <linux/input/matrix_keypad.h>
26#include <linux/delay.h>
27#include <linux/gpio.h>
28#include <linux/omap-gpmc.h>
29#include <linux/platform_data/gpio-omap.h>
30
31#include <linux/platform_data/at24.h>
32#include <linux/i2c/twl.h>
33#include <linux/regulator/fixed.h>
34#include <linux/regulator/machine.h>
35#include <linux/mmc/host.h>
36#include <linux/usb/phy.h>
37
38#include <linux/spi/spi.h>
39#include <linux/spi/tdo24m.h>
40
41#include <asm/mach-types.h>
42#include <asm/mach/arch.h>
43#include <asm/mach/map.h>
44
45#include <linux/platform_data/mtd-nand-omap2.h>
46#include <video/omapdss.h>
47#include <video/omap-panel-data.h>
48#include <linux/platform_data/spi-omap2-mcspi.h>
49
50#include "common.h"
51#include "mux.h"
52#include "sdram-micron-mt46h32m32lf-6.h"
53#include "hsmmc.h"
54#include "common-board-devices.h"
55
56#define CM_T35_GPIO_PENDOWN 57
57#define SB_T35_USB_HUB_RESET_GPIO 167
58
59#define CM_T35_SMSC911X_CS 5
60#define CM_T35_SMSC911X_GPIO 163
61#define SB_T35_SMSC911X_CS 4
62#define SB_T35_SMSC911X_GPIO 65
63
64#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
65#include <linux/smsc911x.h>
66#include "gpmc-smsc911x.h"
67
68static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = {
69 .id = 0,
70 .cs = CM_T35_SMSC911X_CS,
71 .gpio_irq = CM_T35_SMSC911X_GPIO,
72 .gpio_reset = -EINVAL,
73 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
74};
75
76static struct omap_smsc911x_platform_data sb_t35_smsc911x_cfg = {
77 .id = 1,
78 .cs = SB_T35_SMSC911X_CS,
79 .gpio_irq = SB_T35_SMSC911X_GPIO,
80 .gpio_reset = -EINVAL,
81 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
82};
83
84static struct regulator_consumer_supply cm_t35_smsc911x_supplies[] = {
85 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
86 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
87};
88
89static struct regulator_consumer_supply sb_t35_smsc911x_supplies[] = {
90 REGULATOR_SUPPLY("vddvario", "smsc911x.1"),
91 REGULATOR_SUPPLY("vdd33a", "smsc911x.1"),
92};
93
94static void __init cm_t35_init_ethernet(void)
95{
96 regulator_register_fixed(0, cm_t35_smsc911x_supplies,
97 ARRAY_SIZE(cm_t35_smsc911x_supplies));
98 regulator_register_fixed(1, sb_t35_smsc911x_supplies,
99 ARRAY_SIZE(sb_t35_smsc911x_supplies));
100
101 gpmc_smsc911x_init(&cm_t35_smsc911x_cfg);
102 gpmc_smsc911x_init(&sb_t35_smsc911x_cfg);
103}
104#else
105static inline void __init cm_t35_init_ethernet(void) { return; }
106#endif
107
108#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
109#include <linux/leds.h>
110
111static struct gpio_led cm_t35_leds[] = {
112 [0] = {
113 .gpio = 186,
114 .name = "cm-t35:green",
115 .default_trigger = "heartbeat",
116 .active_low = 0,
117 },
118};
119
120static struct gpio_led_platform_data cm_t35_led_pdata = {
121 .num_leds = ARRAY_SIZE(cm_t35_leds),
122 .leds = cm_t35_leds,
123};
124
125static struct platform_device cm_t35_led_device = {
126 .name = "leds-gpio",
127 .id = -1,
128 .dev = {
129 .platform_data = &cm_t35_led_pdata,
130 },
131};
132
133static void __init cm_t35_init_led(void)
134{
135 platform_device_register(&cm_t35_led_device);
136}
137#else
138static inline void cm_t35_init_led(void) {}
139#endif
140
141#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
142#include <linux/mtd/mtd.h>
143#include <linux/mtd/nand.h>
144#include <linux/mtd/partitions.h>
145
146static struct mtd_partition cm_t35_nand_partitions[] = {
147 {
148 .name = "xloader",
149 .offset = 0, /* Offset = 0x00000 */
150 .size = 4 * NAND_BLOCK_SIZE,
151 .mask_flags = MTD_WRITEABLE
152 },
153 {
154 .name = "uboot",
155 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
156 .size = 15 * NAND_BLOCK_SIZE,
157 },
158 {
159 .name = "uboot environment",
160 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
161 .size = 2 * NAND_BLOCK_SIZE,
162 },
163 {
164 .name = "linux",
165 .offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */
166 .size = 32 * NAND_BLOCK_SIZE,
167 },
168 {
169 .name = "rootfs",
170 .offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */
171 .size = MTDPART_SIZ_FULL,
172 },
173};
174
175static struct omap_nand_platform_data cm_t35_nand_data = {
176 .parts = cm_t35_nand_partitions,
177 .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions),
178 .cs = 0,
179};
180
181static void __init cm_t35_init_nand(void)
182{
183 if (gpmc_nand_init(&cm_t35_nand_data, NULL) < 0)
184 pr_err("CM-T35: Unable to register NAND device\n");
185}
186#else
187static inline void cm_t35_init_nand(void) {}
188#endif
189
190#define CM_T35_LCD_EN_GPIO 157
191#define CM_T35_LCD_BL_GPIO 58
192#define CM_T35_DVI_EN_GPIO 54
193
194static const struct display_timing cm_t35_lcd_videomode = {
195 .pixelclock = { 0, 26000000, 0 },
196
197 .hactive = { 0, 480, 0 },
198 .hfront_porch = { 0, 104, 0 },
199 .hback_porch = { 0, 8, 0 },
200 .hsync_len = { 0, 8, 0 },
201
202 .vactive = { 0, 640, 0 },
203 .vfront_porch = { 0, 4, 0 },
204 .vback_porch = { 0, 2, 0 },
205 .vsync_len = { 0, 2, 0 },
206
207 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
208 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE,
209};
210
211static struct panel_dpi_platform_data cm_t35_lcd_pdata = {
212 .name = "lcd",
213 .source = "dpi.0",
214
215 .data_lines = 18,
216
217 .display_timing = &cm_t35_lcd_videomode,
218
219 .enable_gpio = -1,
220 .backlight_gpio = CM_T35_LCD_BL_GPIO,
221};
222
223static struct platform_device cm_t35_lcd_device = {
224 .name = "panel-dpi",
225 .id = 0,
226 .dev.platform_data = &cm_t35_lcd_pdata,
227};
228
229static struct connector_dvi_platform_data cm_t35_dvi_connector_pdata = {
230 .name = "dvi",
231 .source = "tfp410.0",
232 .i2c_bus_num = -1,
233};
234
235static struct platform_device cm_t35_dvi_connector_device = {
236 .name = "connector-dvi",
237 .id = 0,
238 .dev.platform_data = &cm_t35_dvi_connector_pdata,
239};
240
241static struct encoder_tfp410_platform_data cm_t35_tfp410_pdata = {
242 .name = "tfp410.0",
243 .source = "dpi.0",
244 .data_lines = 24,
245 .power_down_gpio = CM_T35_DVI_EN_GPIO,
246};
247
248static struct platform_device cm_t35_tfp410_device = {
249 .name = "tfp410",
250 .id = 0,
251 .dev.platform_data = &cm_t35_tfp410_pdata,
252};
253
254static struct connector_atv_platform_data cm_t35_tv_pdata = {
255 .name = "tv",
256 .source = "venc.0",
257 .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
258 .invert_polarity = false,
259};
260
261static struct platform_device cm_t35_tv_connector_device = {
262 .name = "connector-analog-tv",
263 .id = 0,
264 .dev.platform_data = &cm_t35_tv_pdata,
265};
266
267static struct omap_dss_board_info cm_t35_dss_data = {
268 .default_display_name = "dvi",
269};
270
271static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
272 .turbo_mode = 0,
273};
274
275static struct tdo24m_platform_data tdo24m_config = {
276 .model = TDO35S,
277};
278
279static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
280 {
281 .modalias = "tdo24m",
282 .bus_num = 4,
283 .chip_select = 0,
284 .max_speed_hz = 1000000,
285 .controller_data = &tdo24m_mcspi_config,
286 .platform_data = &tdo24m_config,
287 },
288};
289
290static void __init cm_t35_init_display(void)
291{
292 int err;
293
294 spi_register_board_info(cm_t35_lcd_spi_board_info,
295 ARRAY_SIZE(cm_t35_lcd_spi_board_info));
296
297
298 err = gpio_request_one(CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW,
299 "lcd bl enable");
300 if (err) {
301 pr_err("CM-T35: failed to request LCD EN GPIO\n");
302 return;
303 }
304
305 msleep(50);
306 gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
307
308 err = omap_display_init(&cm_t35_dss_data);
309 if (err) {
310 pr_err("CM-T35: failed to register DSS device\n");
311 gpio_free(CM_T35_LCD_EN_GPIO);
312 }
313
314 platform_device_register(&cm_t35_tfp410_device);
315 platform_device_register(&cm_t35_dvi_connector_device);
316 platform_device_register(&cm_t35_lcd_device);
317 platform_device_register(&cm_t35_tv_connector_device);
318}
319
320static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = {
321 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
322};
323
324static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
325 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
326};
327
328static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
329 REGULATOR_SUPPLY("vcc", "spi1.0"),
330 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
331 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
332 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
333};
334
335/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
336static struct regulator_init_data cm_t35_vmmc1 = {
337 .constraints = {
338 .min_uV = 1850000,
339 .max_uV = 3150000,
340 .valid_modes_mask = REGULATOR_MODE_NORMAL
341 | REGULATOR_MODE_STANDBY,
342 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
343 | REGULATOR_CHANGE_MODE
344 | REGULATOR_CHANGE_STATUS,
345 },
346 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply),
347 .consumer_supplies = cm_t35_vmmc1_supply,
348};
349
350/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
351static struct regulator_init_data cm_t35_vsim = {
352 .constraints = {
353 .min_uV = 1800000,
354 .max_uV = 3000000,
355 .valid_modes_mask = REGULATOR_MODE_NORMAL
356 | REGULATOR_MODE_STANDBY,
357 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
358 | REGULATOR_CHANGE_MODE
359 | REGULATOR_CHANGE_STATUS,
360 },
361 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply),
362 .consumer_supplies = cm_t35_vsim_supply,
363};
364
365static struct regulator_init_data cm_t35_vio = {
366 .constraints = {
367 .min_uV = 1800000,
368 .max_uV = 1800000,
369 .apply_uV = true,
370 .valid_modes_mask = REGULATOR_MODE_NORMAL
371 | REGULATOR_MODE_STANDBY,
372 .valid_ops_mask = REGULATOR_CHANGE_MODE,
373 },
374 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vio_supplies),
375 .consumer_supplies = cm_t35_vio_supplies,
376};
377
378static uint32_t cm_t35_keymap[] = {
379 KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT),
380 KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN),
381 KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D),
382};
383
384static struct matrix_keymap_data cm_t35_keymap_data = {
385 .keymap = cm_t35_keymap,
386 .keymap_size = ARRAY_SIZE(cm_t35_keymap),
387};
388
389static struct twl4030_keypad_data cm_t35_kp_data = {
390 .keymap_data = &cm_t35_keymap_data,
391 .rows = 3,
392 .cols = 3,
393 .rep = 1,
394};
395
396static struct omap2_hsmmc_info mmc[] = {
397 {
398 .mmc = 1,
399 .caps = MMC_CAP_4_BIT_DATA,
400 .gpio_cd = -EINVAL,
401 .gpio_wp = -EINVAL,
402 .deferred = true,
403 },
404 {
405 .mmc = 2,
406 .caps = MMC_CAP_4_BIT_DATA,
407 .transceiver = 1,
408 .gpio_cd = -EINVAL,
409 .gpio_wp = -EINVAL,
410 .ocr_mask = 0x00100000, /* 3.3V */
411 },
412 {} /* Terminator */
413};
414
415static struct usbhs_phy_data phy_data[] __initdata = {
416 {
417 .port = 1,
418 .reset_gpio = OMAP_MAX_GPIO_LINES + 6,
419 .vcc_gpio = -EINVAL,
420 },
421 {
422 .port = 2,
423 .reset_gpio = OMAP_MAX_GPIO_LINES + 7,
424 .vcc_gpio = -EINVAL,
425 },
426};
427
428static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
429 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
430 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
431};
432
433static void __init cm_t35_init_usbh(void)
434{
435 int err;
436
437 err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO,
438 GPIOF_OUT_INIT_LOW, "usb hub rst");
439 if (err) {
440 pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err);
441 } else {
442 udelay(10);
443 gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
444 msleep(1);
445 }
446
447 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
448 usbhs_init(&usbhs_bdata);
449}
450
451static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
452 unsigned ngpio)
453{
454 int wlan_rst = gpio + 2;
455
456 if (gpio_request_one(wlan_rst, GPIOF_OUT_INIT_HIGH, "WLAN RST") == 0) {
457 gpio_export(wlan_rst, 0);
458 udelay(10);
459 gpio_set_value_cansleep(wlan_rst, 0);
460 udelay(10);
461 gpio_set_value_cansleep(wlan_rst, 1);
462 } else {
463 pr_err("CM-T35: could not obtain gpio for WiFi reset\n");
464 }
465
466 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
467 mmc[0].gpio_cd = gpio + 0;
468 omap_hsmmc_late_init(mmc);
469
470 return 0;
471}
472
473static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
474 .setup = cm_t35_twl_gpio_setup,
475};
476
477static struct twl4030_power_data cm_t35_power_data = {
478 .use_poweroff = true,
479};
480
481static struct twl4030_platform_data cm_t35_twldata = {
482 /* platform_data for children goes here */
483 .keypad = &cm_t35_kp_data,
484 .gpio = &cm_t35_gpio_data,
485 .vmmc1 = &cm_t35_vmmc1,
486 .vsim = &cm_t35_vsim,
487 .vio = &cm_t35_vio,
488 .power = &cm_t35_power_data,
489};
490
491#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
492#include <media/omap3isp.h>
493#include "devices.h"
494
495static struct isp_platform_subdev cm_t35_isp_subdevs[] = {
496 {
497 .board_info = &(struct i2c_board_info){
498 I2C_BOARD_INFO("mt9t001", 0x5d)
499 },
500 .i2c_adapter_id = 3,
501 .bus = &(struct isp_bus_cfg){
502 .interface = ISP_INTERFACE_PARALLEL,
503 .bus = {
504 .parallel = {
505 .clk_pol = 1,
506 },
507 },
508 },
509 },
510 {
511 .board_info = &(struct i2c_board_info){
512 I2C_BOARD_INFO("tvp5150", 0x5c),
513 },
514 .i2c_adapter_id = 3,
515 .bus = &(struct isp_bus_cfg){
516 .interface = ISP_INTERFACE_PARALLEL,
517 .bus = {
518 .parallel = {
519 .clk_pol = 0,
520 },
521 },
522 },
523 },
524 { 0 },
525};
526
527static struct isp_platform_data cm_t35_isp_pdata = {
528 .subdevs = cm_t35_isp_subdevs,
529};
530
531static struct regulator_consumer_supply cm_t35_camera_supplies[] = {
532 REGULATOR_SUPPLY("vaa", "3-005d"),
533 REGULATOR_SUPPLY("vdd", "3-005d"),
534};
535
536static void __init cm_t35_init_camera(void)
537{
538 struct clk *clk;
539
540 clk = clk_register_fixed_rate(NULL, "mt9t001-clkin", NULL, CLK_IS_ROOT,
541 48000000);
542 clk_register_clkdev(clk, NULL, "3-005d");
543
544 regulator_register_fixed(2, cm_t35_camera_supplies,
545 ARRAY_SIZE(cm_t35_camera_supplies));
546
547 if (omap3_init_camera(&cm_t35_isp_pdata) < 0)
548 pr_warn("CM-T3x: Failed registering camera device!\n");
549}
550
551#else
552static inline void cm_t35_init_camera(void) {}
553#endif /* CONFIG_VIDEO_OMAP3 */
554
555static void __init cm_t35_init_i2c(void)
556{
557 omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
558 TWL_COMMON_REGULATOR_VDAC |
559 TWL_COMMON_PDATA_AUDIO);
560
561 omap3_pmic_init("tps65930", &cm_t35_twldata);
562
563 omap_register_i2c_bus(3, 400, NULL, 0);
564}
565
566#ifdef CONFIG_OMAP_MUX
567static struct omap_board_mux board_mux[] __initdata = {
568 /* nCS and IRQ for CM-T35 ethernet */
569 OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
570 OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
571
572 /* nCS and IRQ for SB-T35 ethernet */
573 OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0),
574 OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
575
576 /* PENDOWN GPIO */
577 OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
578
579 /* mUSB */
580 OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
581 OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
582 OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
583 OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
584 OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
585 OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
586 OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
587 OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
588 OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
589 OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
590 OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
591 OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
592
593 /* MMC 2 */
594 OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
595 OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
596 OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
597 OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
598
599 /* McSPI 1 */
600 OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
601 OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
602 OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
603 OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
604
605 /* McSPI 4 */
606 OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
607 OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
608 OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
609 OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
610
611 /* McBSP 2 */
612 OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
613 OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
614 OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
615 OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
616
617 /* serial ports */
618 OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
619 OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
620 OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
621 OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
622
623 /* common DSS */
624 OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
625 OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
626 OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
627 OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
628 OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
629 OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
630 OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
631 OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
632 OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
633 OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
634 OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
635 OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
636 OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
637 OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
638 OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
639 OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
640
641 /* Camera */
642 OMAP3_MUX(CAM_HS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
643 OMAP3_MUX(CAM_VS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
644 OMAP3_MUX(CAM_XCLKA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
645 OMAP3_MUX(CAM_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
646 OMAP3_MUX(CAM_FLD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
647 OMAP3_MUX(CAM_D0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
648 OMAP3_MUX(CAM_D1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
649 OMAP3_MUX(CAM_D2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
650 OMAP3_MUX(CAM_D3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
651 OMAP3_MUX(CAM_D4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
652 OMAP3_MUX(CAM_D5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
653 OMAP3_MUX(CAM_D6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
654 OMAP3_MUX(CAM_D7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
655 OMAP3_MUX(CAM_D8, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
656 OMAP3_MUX(CAM_D9, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
657 OMAP3_MUX(CAM_STROBE, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
658
659 OMAP3_MUX(CAM_D10, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN),
660 OMAP3_MUX(CAM_D11, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN),
661
662 /* display controls */
663 OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
664 OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
665 OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
666
667 /* TPS IRQ */
668 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
669 OMAP_PIN_INPUT_PULLUP),
670
671 { .reg_offset = OMAP_MUX_TERMINATOR },
672};
673
674static void __init cm_t3x_common_dss_mux_init(int mux_mode)
675{
676 omap_mux_init_signal("dss_data18", mux_mode);
677 omap_mux_init_signal("dss_data19", mux_mode);
678 omap_mux_init_signal("dss_data20", mux_mode);
679 omap_mux_init_signal("dss_data21", mux_mode);
680 omap_mux_init_signal("dss_data22", mux_mode);
681 omap_mux_init_signal("dss_data23", mux_mode);
682}
683
684static void __init cm_t35_init_mux(void)
685{
686 int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT;
687
688 omap_mux_init_signal("dss_data0.dss_data0", mux_mode);
689 omap_mux_init_signal("dss_data1.dss_data1", mux_mode);
690 omap_mux_init_signal("dss_data2.dss_data2", mux_mode);
691 omap_mux_init_signal("dss_data3.dss_data3", mux_mode);
692 omap_mux_init_signal("dss_data4.dss_data4", mux_mode);
693 omap_mux_init_signal("dss_data5.dss_data5", mux_mode);
694 cm_t3x_common_dss_mux_init(mux_mode);
695}
696
697static void __init cm_t3730_init_mux(void)
698{
699 int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT;
700
701 omap_mux_init_signal("sys_boot0", mux_mode);
702 omap_mux_init_signal("sys_boot1", mux_mode);
703 omap_mux_init_signal("sys_boot3", mux_mode);
704 omap_mux_init_signal("sys_boot4", mux_mode);
705 omap_mux_init_signal("sys_boot5", mux_mode);
706 omap_mux_init_signal("sys_boot6", mux_mode);
707 cm_t3x_common_dss_mux_init(mux_mode);
708}
709#else
710static inline void cm_t35_init_mux(void) {}
711static inline void cm_t3730_init_mux(void) {}
712#endif
713
714static void __init cm_t3x_common_init(void)
715{
716 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
717 omap_serial_init();
718 omap_sdrc_init(mt46h32m32lf6_sdrc_params,
719 mt46h32m32lf6_sdrc_params);
720 omap_hsmmc_init(mmc);
721 cm_t35_init_i2c();
722 omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
723 cm_t35_init_ethernet();
724 cm_t35_init_led();
725 cm_t35_init_display();
726 omap_twl4030_audio_init("cm-t3x", NULL);
727
728 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
729 usb_musb_init(NULL);
730 cm_t35_init_usbh();
731 cm_t35_init_camera();
732}
733
734static void __init cm_t35_init(void)
735{
736 cm_t3x_common_init();
737 cm_t35_init_mux();
738 cm_t35_init_nand();
739}
740
741static void __init cm_t3730_init(void)
742{
743 cm_t3x_common_init();
744 cm_t3730_init_mux();
745}
746
747MACHINE_START(CM_T35, "Compulab CM-T35")
748 .atag_offset = 0x100,
749 .reserve = omap_reserve,
750 .map_io = omap3_map_io,
751 .init_early = omap35xx_init_early,
752 .init_irq = omap3_init_irq,
753 .init_machine = cm_t35_init,
754 .init_late = omap35xx_init_late,
755 .init_time = omap3_sync32k_timer_init,
756 .restart = omap3xxx_restart,
757MACHINE_END
758
759MACHINE_START(CM_T3730, "Compulab CM-T3730")
760 .atag_offset = 0x100,
761 .reserve = omap_reserve,
762 .map_io = omap3_map_io,
763 .init_early = omap3630_init_early,
764 .init_irq = omap3_init_irq,
765 .init_machine = cm_t3730_init,
766 .init_late = omap3630_init_late,
767 .init_time = omap3_sync32k_timer_init,
768 .restart = omap3xxx_restart,
769MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
deleted file mode 100644
index 81de1c68b360..000000000000
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ /dev/null
@@ -1,595 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-omap3beagle.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/leds.h>
23#include <linux/pwm.h>
24#include <linux/leds_pwm.h>
25#include <linux/gpio.h>
26#include <linux/input.h>
27#include <linux/gpio_keys.h>
28#include <linux/pm_opp.h>
29#include <linux/cpu.h>
30
31#include <linux/mtd/mtd.h>
32#include <linux/mtd/partitions.h>
33#include <linux/mtd/nand.h>
34#include <linux/mmc/host.h>
35#include <linux/usb/phy.h>
36
37#include <linux/regulator/machine.h>
38#include <linux/i2c/twl.h>
39
40#include <asm/mach-types.h>
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43#include <asm/mach/flash.h>
44
45#include <video/omapdss.h>
46#include <video/omap-panel-data.h>
47#include <linux/platform_data/mtd-nand-omap2.h>
48
49#include "common.h"
50#include "omap_device.h"
51#include "gpmc.h"
52#include "soc.h"
53#include "mux.h"
54#include "hsmmc.h"
55#include "pm.h"
56#include "board-flash.h"
57#include "common-board-devices.h"
58
59#define NAND_CS 0
60
61static struct pwm_lookup pwm_lookup[] = {
62 /* LEDB -> PMU_STAT */
63 PWM_LOOKUP("twl-pwmled", 1, "leds_pwm", "beagleboard::pmu_stat",
64 7812500, PWM_POLARITY_NORMAL),
65};
66
67static struct led_pwm pwm_leds[] = {
68 {
69 .name = "beagleboard::pmu_stat",
70 .max_brightness = 127,
71 .pwm_period_ns = 7812500,
72 },
73};
74
75static struct led_pwm_platform_data pwm_data = {
76 .num_leds = ARRAY_SIZE(pwm_leds),
77 .leds = pwm_leds,
78};
79
80static struct platform_device leds_pwm = {
81 .name = "leds_pwm",
82 .id = -1,
83 .dev = {
84 .platform_data = &pwm_data,
85 },
86};
87
88/*
89 * OMAP3 Beagle revision
90 * Run time detection of Beagle revision is done by reading GPIO.
91 * GPIO ID -
92 * AXBX = GPIO173, GPIO172, GPIO171: 1 1 1
93 * C1_3 = GPIO173, GPIO172, GPIO171: 1 1 0
94 * C4 = GPIO173, GPIO172, GPIO171: 1 0 1
95 * XMA/XMB = GPIO173, GPIO172, GPIO171: 0 0 0
96 * XMC = GPIO173, GPIO172, GPIO171: 0 1 0
97 */
98enum {
99 OMAP3BEAGLE_BOARD_UNKN = 0,
100 OMAP3BEAGLE_BOARD_AXBX,
101 OMAP3BEAGLE_BOARD_C1_3,
102 OMAP3BEAGLE_BOARD_C4,
103 OMAP3BEAGLE_BOARD_XM,
104 OMAP3BEAGLE_BOARD_XMC,
105};
106
107static u8 omap3_beagle_version;
108
109/*
110 * Board-specific configuration
111 * Defaults to BeagleBoard-xMC
112 */
113static struct {
114 int mmc1_gpio_wp;
115 bool usb_pwr_level; /* 0 - Active Low, 1 - Active High */
116 int dvi_pd_gpio;
117 int usr_button_gpio;
118 int mmc_caps;
119} beagle_config = {
120 .mmc1_gpio_wp = -EINVAL,
121 .usb_pwr_level = 0,
122 .dvi_pd_gpio = -EINVAL,
123 .usr_button_gpio = 4,
124 .mmc_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
125};
126
127static struct gpio omap3_beagle_rev_gpios[] __initdata = {
128 { 171, GPIOF_IN, "rev_id_0" },
129 { 172, GPIOF_IN, "rev_id_1" },
130 { 173, GPIOF_IN, "rev_id_2" },
131};
132
133static void __init omap3_beagle_init_rev(void)
134{
135 int ret;
136 u16 beagle_rev = 0;
137
138 omap_mux_init_gpio(171, OMAP_PIN_INPUT_PULLUP);
139 omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP);
140 omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP);
141
142 ret = gpio_request_array(omap3_beagle_rev_gpios,
143 ARRAY_SIZE(omap3_beagle_rev_gpios));
144 if (ret < 0) {
145 printk(KERN_ERR "Unable to get revision detection GPIO pins\n");
146 omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
147 return;
148 }
149
150 beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1)
151 | (gpio_get_value(173) << 2);
152
153 gpio_free_array(omap3_beagle_rev_gpios,
154 ARRAY_SIZE(omap3_beagle_rev_gpios));
155
156 switch (beagle_rev) {
157 case 7:
158 printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n");
159 omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX;
160 beagle_config.mmc1_gpio_wp = 29;
161 beagle_config.dvi_pd_gpio = 170;
162 beagle_config.usr_button_gpio = 7;
163 break;
164 case 6:
165 printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n");
166 omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3;
167 beagle_config.mmc1_gpio_wp = 23;
168 beagle_config.dvi_pd_gpio = 170;
169 beagle_config.usr_button_gpio = 7;
170 break;
171 case 5:
172 printk(KERN_INFO "OMAP3 Beagle Rev: C4\n");
173 omap3_beagle_version = OMAP3BEAGLE_BOARD_C4;
174 beagle_config.mmc1_gpio_wp = 23;
175 beagle_config.dvi_pd_gpio = 170;
176 beagle_config.usr_button_gpio = 7;
177 break;
178 case 0:
179 printk(KERN_INFO "OMAP3 Beagle Rev: xM Ax/Bx\n");
180 omap3_beagle_version = OMAP3BEAGLE_BOARD_XM;
181 beagle_config.usb_pwr_level = 1;
182 beagle_config.mmc_caps &= ~MMC_CAP_8_BIT_DATA;
183 break;
184 case 2:
185 printk(KERN_INFO "OMAP3 Beagle Rev: xM C\n");
186 omap3_beagle_version = OMAP3BEAGLE_BOARD_XMC;
187 beagle_config.mmc_caps &= ~MMC_CAP_8_BIT_DATA;
188 break;
189 default:
190 printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
191 omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
192 }
193}
194
195static struct mtd_partition omap3beagle_nand_partitions[] = {
196 /* All the partition sizes are listed in terms of NAND block size */
197 {
198 .name = "X-Loader",
199 .offset = 0,
200 .size = 4 * NAND_BLOCK_SIZE,
201 .mask_flags = MTD_WRITEABLE, /* force read-only */
202 },
203 {
204 .name = "U-Boot",
205 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
206 .size = 15 * NAND_BLOCK_SIZE,
207 .mask_flags = MTD_WRITEABLE, /* force read-only */
208 },
209 {
210 .name = "U-Boot Env",
211 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
212 .size = 1 * NAND_BLOCK_SIZE,
213 },
214 {
215 .name = "Kernel",
216 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
217 .size = 32 * NAND_BLOCK_SIZE,
218 },
219 {
220 .name = "File System",
221 .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
222 .size = MTDPART_SIZ_FULL,
223 },
224};
225
226/* DSS */
227
228static struct connector_dvi_platform_data beagle_dvi_connector_pdata = {
229 .name = "dvi",
230 .source = "tfp410.0",
231 .i2c_bus_num = 3,
232};
233
234static struct platform_device beagle_dvi_connector_device = {
235 .name = "connector-dvi",
236 .id = 0,
237 .dev.platform_data = &beagle_dvi_connector_pdata,
238};
239
240static struct encoder_tfp410_platform_data beagle_tfp410_pdata = {
241 .name = "tfp410.0",
242 .source = "dpi.0",
243 .data_lines = 24,
244 .power_down_gpio = -1,
245};
246
247static struct platform_device beagle_tfp410_device = {
248 .name = "tfp410",
249 .id = 0,
250 .dev.platform_data = &beagle_tfp410_pdata,
251};
252
253static struct connector_atv_platform_data beagle_tv_pdata = {
254 .name = "tv",
255 .source = "venc.0",
256 .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
257 .invert_polarity = false,
258};
259
260static struct platform_device beagle_tv_connector_device = {
261 .name = "connector-analog-tv",
262 .id = 0,
263 .dev.platform_data = &beagle_tv_pdata,
264};
265
266static struct omap_dss_board_info beagle_dss_data = {
267 .default_display_name = "dvi",
268};
269
270#include "sdram-micron-mt46h32m32lf-6.h"
271
272static struct omap2_hsmmc_info mmc[] = {
273 {
274 .mmc = 1,
275 .caps = MMC_CAP_4_BIT_DATA,
276 .gpio_wp = -EINVAL,
277 .deferred = true,
278 },
279 {} /* Terminator */
280};
281
282static struct regulator_consumer_supply beagle_vmmc1_supply[] = {
283 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
284};
285
286static struct regulator_consumer_supply beagle_vsim_supply[] = {
287 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
288};
289
290static struct gpio_led gpio_leds[];
291
292static struct usbhs_phy_data phy_data[] = {
293 {
294 .port = 2,
295 .reset_gpio = 147,
296 .vcc_gpio = -1, /* updated in beagle_twl_gpio_setup */
297 .vcc_polarity = 1, /* updated in beagle_twl_gpio_setup */
298 },
299};
300
301static int beagle_twl_gpio_setup(struct device *dev,
302 unsigned gpio, unsigned ngpio)
303{
304 int r;
305
306 mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
307 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
308 mmc[0].gpio_cd = gpio + 0;
309 omap_hsmmc_late_init(mmc);
310
311 /*
312 * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
313 * high / others active low)
314 * DVI reset GPIO is different between beagle revisions
315 */
316 /* Valid for all -xM revisions */
317 if (cpu_is_omap3630()) {
318 /*
319 * gpio + 1 on Xm controls the TFP410's enable line (active low)
320 * gpio + 2 control varies depending on the board rev as below:
321 * P7/P8 revisions(prototype): Camera EN
322 * A2+ revisions (production): LDO (DVI, serial, led blocks)
323 */
324 r = gpio_request_one(gpio + 1, GPIOF_OUT_INIT_LOW,
325 "nDVI_PWR_EN");
326 if (r)
327 pr_err("%s: unable to configure nDVI_PWR_EN\n",
328 __func__);
329
330 beagle_config.dvi_pd_gpio = gpio + 2;
331
332 } else {
333 /*
334 * REVISIT: need ehci-omap hooks for external VBUS
335 * power switch and overcurrent detect
336 */
337 if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
338 pr_err("%s: unable to configure EHCI_nOC\n", __func__);
339 }
340 beagle_tfp410_pdata.power_down_gpio = beagle_config.dvi_pd_gpio;
341
342 platform_device_register(&beagle_tfp410_device);
343 platform_device_register(&beagle_dvi_connector_device);
344 platform_device_register(&beagle_tv_connector_device);
345
346 /* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */
347 phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX;
348 phy_data[0].vcc_polarity = beagle_config.usb_pwr_level;
349
350 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
351 return 0;
352}
353
354static struct twl4030_gpio_platform_data beagle_gpio_data = {
355 .use_leds = true,
356 .pullups = BIT(1),
357 .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
358 | BIT(15) | BIT(16) | BIT(17),
359 .setup = beagle_twl_gpio_setup,
360};
361
362/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
363static struct regulator_init_data beagle_vmmc1 = {
364 .constraints = {
365 .min_uV = 1850000,
366 .max_uV = 3150000,
367 .valid_modes_mask = REGULATOR_MODE_NORMAL
368 | REGULATOR_MODE_STANDBY,
369 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
370 | REGULATOR_CHANGE_MODE
371 | REGULATOR_CHANGE_STATUS,
372 },
373 .num_consumer_supplies = ARRAY_SIZE(beagle_vmmc1_supply),
374 .consumer_supplies = beagle_vmmc1_supply,
375};
376
377/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
378static struct regulator_init_data beagle_vsim = {
379 .constraints = {
380 .min_uV = 1800000,
381 .max_uV = 3000000,
382 .valid_modes_mask = REGULATOR_MODE_NORMAL
383 | REGULATOR_MODE_STANDBY,
384 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
385 | REGULATOR_CHANGE_MODE
386 | REGULATOR_CHANGE_STATUS,
387 },
388 .num_consumer_supplies = ARRAY_SIZE(beagle_vsim_supply),
389 .consumer_supplies = beagle_vsim_supply,
390};
391
392static struct twl4030_platform_data beagle_twldata = {
393 /* platform_data for children goes here */
394 .gpio = &beagle_gpio_data,
395 .vmmc1 = &beagle_vmmc1,
396 .vsim = &beagle_vsim,
397};
398
399static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
400 {
401 I2C_BOARD_INFO("eeprom", 0x50),
402 },
403};
404
405static int __init omap3_beagle_i2c_init(void)
406{
407 omap3_pmic_get_config(&beagle_twldata,
408 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
409 TWL_COMMON_PDATA_AUDIO,
410 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
411
412 beagle_twldata.vpll2->constraints.name = "VDVI";
413
414 omap3_pmic_init("twl4030", &beagle_twldata);
415 /* Bus 3 is attached to the DVI port where devices like the pico DLP
416 * projector don't work reliably with 400kHz */
417 omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom));
418 return 0;
419}
420
421static struct gpio_led gpio_leds[] = {
422 {
423 .name = "beagleboard::usr0",
424 .default_trigger = "heartbeat",
425 .gpio = 150,
426 },
427 {
428 .name = "beagleboard::usr1",
429 .default_trigger = "mmc0",
430 .gpio = 149,
431 },
432};
433
434static struct gpio_led_platform_data gpio_led_info = {
435 .leds = gpio_leds,
436 .num_leds = ARRAY_SIZE(gpio_leds),
437};
438
439static struct platform_device leds_gpio = {
440 .name = "leds-gpio",
441 .id = -1,
442 .dev = {
443 .platform_data = &gpio_led_info,
444 },
445};
446
447static struct gpio_keys_button gpio_buttons[] = {
448 {
449 .code = BTN_EXTRA,
450 /* Dynamically assigned depending on board */
451 .gpio = -EINVAL,
452 .desc = "user",
453 .wakeup = 1,
454 },
455};
456
457static struct gpio_keys_platform_data gpio_key_info = {
458 .buttons = gpio_buttons,
459 .nbuttons = ARRAY_SIZE(gpio_buttons),
460};
461
462static struct platform_device keys_gpio = {
463 .name = "gpio-keys",
464 .id = -1,
465 .dev = {
466 .platform_data = &gpio_key_info,
467 },
468};
469
470static struct platform_device madc_hwmon = {
471 .name = "twl4030_madc_hwmon",
472 .id = -1,
473};
474
475static struct platform_device *omap3_beagle_devices[] __initdata = {
476 &leds_gpio,
477 &keys_gpio,
478 &madc_hwmon,
479 &leds_pwm,
480};
481
482static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
483 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
484};
485
486#ifdef CONFIG_OMAP_MUX
487static struct omap_board_mux board_mux[] __initdata = {
488 { .reg_offset = OMAP_MUX_TERMINATOR },
489};
490#endif
491
492static int __init beagle_opp_init(void)
493{
494 int r = 0;
495
496 if (!machine_is_omap3_beagle())
497 return 0;
498
499 /* Initialize the omap3 opp table if not already created. */
500 r = omap3_opp_init();
501 if (r < 0 && (r != -EEXIST)) {
502 pr_err("%s: opp default init failed\n", __func__);
503 return r;
504 }
505
506 /* Custom OPP enabled for all xM versions */
507 if (cpu_is_omap3630()) {
508 struct device *mpu_dev, *iva_dev;
509
510 mpu_dev = get_cpu_device(0);
511 iva_dev = omap_device_get_by_hwmod_name("iva");
512
513 if (!mpu_dev || IS_ERR(iva_dev)) {
514 pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
515 __func__, mpu_dev, iva_dev);
516 return -ENODEV;
517 }
518 /* Enable MPU 1GHz and lower opps */
519 r = dev_pm_opp_enable(mpu_dev, 800000000);
520 /* TODO: MPU 1GHz needs SR and ABB */
521
522 /* Enable IVA 800MHz and lower opps */
523 r |= dev_pm_opp_enable(iva_dev, 660000000);
524 /* TODO: DSP 800MHz needs SR and ABB */
525 if (r) {
526 pr_err("%s: failed to enable higher opp %d\n",
527 __func__, r);
528 /*
529 * Cleanup - disable the higher freqs - we dont care
530 * about the results
531 */
532 dev_pm_opp_disable(mpu_dev, 800000000);
533 dev_pm_opp_disable(iva_dev, 660000000);
534 }
535 }
536 return 0;
537}
538omap_device_initcall(beagle_opp_init);
539
540static void __init omap3_beagle_init(void)
541{
542 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
543 omap3_beagle_init_rev();
544
545 if (gpio_is_valid(beagle_config.mmc1_gpio_wp))
546 omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
547 mmc[0].caps = beagle_config.mmc_caps;
548 omap_hsmmc_init(mmc);
549
550 omap3_beagle_i2c_init();
551
552 gpio_buttons[0].gpio = beagle_config.usr_button_gpio;
553
554 platform_add_devices(omap3_beagle_devices,
555 ARRAY_SIZE(omap3_beagle_devices));
556 if (gpio_is_valid(beagle_config.dvi_pd_gpio))
557 omap_mux_init_gpio(beagle_config.dvi_pd_gpio, OMAP_PIN_OUTPUT);
558 omap_display_init(&beagle_dss_data);
559
560 omap_serial_init();
561 omap_sdrc_init(mt46h32m32lf6_sdrc_params,
562 mt46h32m32lf6_sdrc_params);
563
564 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
565 usb_musb_init(NULL);
566
567 usbhs_init(&usbhs_bdata);
568
569 board_nand_init(omap3beagle_nand_partitions,
570 ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
571 NAND_BUSWIDTH_16, NULL);
572 omap_twl4030_audio_init("omap3beagle", NULL);
573
574 /* Ensure msecure is mux'd to be able to set the RTC. */
575 omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
576
577 /* Ensure SDRC pins are mux'd for self-refresh */
578 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
579 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
580
581 pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup));
582}
583
584MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
585 /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
586 .atag_offset = 0x100,
587 .reserve = omap_reserve,
588 .map_io = omap3_map_io,
589 .init_early = omap3_init_early,
590 .init_irq = omap3_init_irq,
591 .init_machine = omap3_beagle_init,
592 .init_late = omap3_init_late,
593 .init_time = omap3_secure_sync32k_timer_init,
594 .restart = omap3xxx_restart,
595MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
deleted file mode 100644
index 2dae6ccd39bb..000000000000
--- a/arch/arm/mach-omap2/board-overo.c
+++ /dev/null
@@ -1,571 +0,0 @@
1/*
2 * board-overo.c (Gumstix Overo)
3 *
4 * Initial code: Steve Sakoman <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/io.h>
27#include <linux/gpio.h>
28#include <linux/kernel.h>
29#include <linux/platform_device.h>
30#include <linux/i2c/twl.h>
31#include <linux/regulator/machine.h>
32#include <linux/regulator/fixed.h>
33#include <linux/spi/spi.h>
34
35#include <linux/mtd/mtd.h>
36#include <linux/mtd/nand.h>
37#include <linux/mtd/partitions.h>
38#include <linux/mmc/host.h>
39#include <linux/usb/phy.h>
40
41#include <linux/platform_data/mtd-nand-omap2.h>
42#include <linux/platform_data/spi-omap2-mcspi.h>
43
44#include <asm/mach-types.h>
45#include <asm/mach/arch.h>
46#include <asm/mach/flash.h>
47#include <asm/mach/map.h>
48
49#include <video/omapdss.h>
50#include <video/omap-panel-data.h>
51
52#include "common.h"
53#include "mux.h"
54#include "sdram-micron-mt46h32m32lf-6.h"
55#include "gpmc.h"
56#include "hsmmc.h"
57#include "board-flash.h"
58#include "common-board-devices.h"
59
60#define NAND_CS 0
61
62#define OVERO_GPIO_BT_XGATE 15
63#define OVERO_GPIO_W2W_NRESET 16
64#define OVERO_GPIO_PENDOWN 114
65#define OVERO_GPIO_BT_NRESET 164
66#define OVERO_GPIO_USBH_CPEN 168
67#define OVERO_GPIO_USBH_NRESET 183
68
69#define OVERO_SMSC911X_CS 5
70#define OVERO_SMSC911X_GPIO 176
71#define OVERO_SMSC911X_NRESET 64
72#define OVERO_SMSC911X2_CS 4
73#define OVERO_SMSC911X2_GPIO 65
74
75/* whether to register LCD35 instead of LCD43 */
76static bool overo_use_lcd35;
77
78#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
79 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
80
81/* fixed regulator for ads7846 */
82static struct regulator_consumer_supply ads7846_supply[] = {
83 REGULATOR_SUPPLY("vcc", "spi1.0"),
84};
85
86static struct regulator_init_data vads7846_regulator = {
87 .constraints = {
88 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
89 },
90 .num_consumer_supplies = ARRAY_SIZE(ads7846_supply),
91 .consumer_supplies = ads7846_supply,
92};
93
94static struct fixed_voltage_config vads7846 = {
95 .supply_name = "vads7846",
96 .microvolts = 3300000, /* 3.3V */
97 .gpio = -EINVAL,
98 .startup_delay = 0,
99 .init_data = &vads7846_regulator,
100};
101
102static struct platform_device vads7846_device = {
103 .name = "reg-fixed-voltage",
104 .id = 1,
105 .dev = {
106 .platform_data = &vads7846,
107 },
108};
109
110static void __init overo_ads7846_init(void)
111{
112 omap_ads7846_init(1, OVERO_GPIO_PENDOWN, 0, NULL);
113 platform_device_register(&vads7846_device);
114}
115
116#else
117static inline void __init overo_ads7846_init(void) { return; }
118#endif
119
120#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
121
122#include <linux/smsc911x.h>
123#include "gpmc-smsc911x.h"
124
125static struct omap_smsc911x_platform_data smsc911x_cfg = {
126 .id = 0,
127 .cs = OVERO_SMSC911X_CS,
128 .gpio_irq = OVERO_SMSC911X_GPIO,
129 .gpio_reset = OVERO_SMSC911X_NRESET,
130 .flags = SMSC911X_USE_32BIT,
131};
132
133static struct omap_smsc911x_platform_data smsc911x2_cfg = {
134 .id = 1,
135 .cs = OVERO_SMSC911X2_CS,
136 .gpio_irq = OVERO_SMSC911X2_GPIO,
137 .gpio_reset = -EINVAL,
138 .flags = SMSC911X_USE_32BIT,
139};
140
141static void __init overo_init_smsc911x(void)
142{
143 gpmc_smsc911x_init(&smsc911x_cfg);
144 gpmc_smsc911x_init(&smsc911x2_cfg);
145}
146
147#else
148static inline void __init overo_init_smsc911x(void) { return; }
149#endif
150
151/* DSS */
152#define OVERO_GPIO_LCD_EN 144
153#define OVERO_GPIO_LCD_BL 145
154
155static struct connector_atv_platform_data overo_tv_pdata = {
156 .name = "tv",
157 .source = "venc.0",
158 .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
159 .invert_polarity = false,
160};
161
162static struct platform_device overo_tv_connector_device = {
163 .name = "connector-analog-tv",
164 .id = 0,
165 .dev.platform_data = &overo_tv_pdata,
166};
167
168static const struct display_timing overo_lcd43_videomode = {
169 .pixelclock = { 0, 9200000, 0 },
170
171 .hactive = { 0, 480, 0 },
172 .hfront_porch = { 0, 8, 0 },
173 .hback_porch = { 0, 4, 0 },
174 .hsync_len = { 0, 41, 0 },
175
176 .vactive = { 0, 272, 0 },
177 .vfront_porch = { 0, 4, 0 },
178 .vback_porch = { 0, 2, 0 },
179 .vsync_len = { 0, 10, 0 },
180
181 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
182 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
183};
184
185static struct panel_dpi_platform_data overo_lcd43_pdata = {
186 .name = "lcd43",
187 .source = "dpi.0",
188
189 .data_lines = 24,
190
191 .display_timing = &overo_lcd43_videomode,
192
193 .enable_gpio = OVERO_GPIO_LCD_EN,
194 .backlight_gpio = OVERO_GPIO_LCD_BL,
195};
196
197static struct platform_device overo_lcd43_device = {
198 .name = "panel-dpi",
199 .id = 0,
200 .dev.platform_data = &overo_lcd43_pdata,
201};
202
203static struct connector_dvi_platform_data overo_dvi_connector_pdata = {
204 .name = "dvi",
205 .source = "tfp410.0",
206 .i2c_bus_num = 3,
207};
208
209static struct platform_device overo_dvi_connector_device = {
210 .name = "connector-dvi",
211 .id = 0,
212 .dev.platform_data = &overo_dvi_connector_pdata,
213};
214
215static struct encoder_tfp410_platform_data overo_tfp410_pdata = {
216 .name = "tfp410.0",
217 .source = "dpi.0",
218 .data_lines = 24,
219 .power_down_gpio = -1,
220};
221
222static struct platform_device overo_tfp410_device = {
223 .name = "tfp410",
224 .id = 0,
225 .dev.platform_data = &overo_tfp410_pdata,
226};
227
228static struct omap_dss_board_info overo_dss_data = {
229 .default_display_name = "lcd43",
230};
231
232static void __init overo_display_init(void)
233{
234 omap_display_init(&overo_dss_data);
235
236 if (!overo_use_lcd35)
237 platform_device_register(&overo_lcd43_device);
238 platform_device_register(&overo_tfp410_device);
239 platform_device_register(&overo_dvi_connector_device);
240 platform_device_register(&overo_tv_connector_device);
241}
242
243static struct mtd_partition overo_nand_partitions[] = {
244 {
245 .name = "xloader",
246 .offset = 0, /* Offset = 0x00000 */
247 .size = 4 * NAND_BLOCK_SIZE,
248 .mask_flags = MTD_WRITEABLE
249 },
250 {
251 .name = "uboot",
252 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
253 .size = 14 * NAND_BLOCK_SIZE,
254 },
255 {
256 .name = "uboot environment",
257 .offset = MTDPART_OFS_APPEND, /* Offset = 0x240000 */
258 .size = 2 * NAND_BLOCK_SIZE,
259 },
260 {
261 .name = "linux",
262 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
263 .size = 32 * NAND_BLOCK_SIZE,
264 },
265 {
266 .name = "rootfs",
267 .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
268 .size = MTDPART_SIZ_FULL,
269 },
270};
271
272static struct omap2_hsmmc_info mmc[] = {
273 {
274 .mmc = 1,
275 .caps = MMC_CAP_4_BIT_DATA,
276 .gpio_cd = -EINVAL,
277 .gpio_wp = -EINVAL,
278 },
279 {
280 .mmc = 2,
281 .caps = MMC_CAP_4_BIT_DATA,
282 .gpio_cd = -EINVAL,
283 .gpio_wp = -EINVAL,
284 .transceiver = true,
285 .ocr_mask = 0x00100000, /* 3.3V */
286 },
287 {} /* Terminator */
288};
289
290static struct regulator_consumer_supply overo_vmmc1_supply[] = {
291 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
292};
293
294#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
295#include <linux/leds.h>
296
297static struct gpio_led gpio_leds[] = {
298 {
299 .name = "overo:red:gpio21",
300 .default_trigger = "heartbeat",
301 .gpio = 21,
302 .active_low = true,
303 },
304 {
305 .name = "overo:blue:gpio22",
306 .default_trigger = "none",
307 .gpio = 22,
308 .active_low = true,
309 },
310 {
311 .name = "overo:blue:COM",
312 .default_trigger = "mmc0",
313 .gpio = -EINVAL, /* gets replaced */
314 .active_low = true,
315 },
316};
317
318static struct gpio_led_platform_data gpio_leds_pdata = {
319 .leds = gpio_leds,
320 .num_leds = ARRAY_SIZE(gpio_leds),
321};
322
323static struct platform_device gpio_leds_device = {
324 .name = "leds-gpio",
325 .id = -1,
326 .dev = {
327 .platform_data = &gpio_leds_pdata,
328 },
329};
330
331static void __init overo_init_led(void)
332{
333 platform_device_register(&gpio_leds_device);
334}
335
336#else
337static inline void __init overo_init_led(void) { return; }
338#endif
339
340#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
341#include <linux/input.h>
342#include <linux/gpio_keys.h>
343
344static struct gpio_keys_button gpio_buttons[] = {
345 {
346 .code = BTN_0,
347 .gpio = 23,
348 .desc = "button0",
349 .wakeup = 1,
350 },
351 {
352 .code = BTN_1,
353 .gpio = 14,
354 .desc = "button1",
355 .wakeup = 1,
356 },
357};
358
359static struct gpio_keys_platform_data gpio_keys_pdata = {
360 .buttons = gpio_buttons,
361 .nbuttons = ARRAY_SIZE(gpio_buttons),
362};
363
364static struct platform_device gpio_keys_device = {
365 .name = "gpio-keys",
366 .id = -1,
367 .dev = {
368 .platform_data = &gpio_keys_pdata,
369 },
370};
371
372static void __init overo_init_keys(void)
373{
374 platform_device_register(&gpio_keys_device);
375}
376
377#else
378static inline void __init overo_init_keys(void) { return; }
379#endif
380
381static int overo_twl_gpio_setup(struct device *dev,
382 unsigned gpio, unsigned ngpio)
383{
384#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
385 /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
386 gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
387#endif
388
389 return 0;
390}
391
392static struct twl4030_gpio_platform_data overo_gpio_data = {
393 .use_leds = true,
394 .setup = overo_twl_gpio_setup,
395};
396
397static struct regulator_init_data overo_vmmc1 = {
398 .constraints = {
399 .min_uV = 1850000,
400 .max_uV = 3150000,
401 .valid_modes_mask = REGULATOR_MODE_NORMAL
402 | REGULATOR_MODE_STANDBY,
403 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
404 | REGULATOR_CHANGE_MODE
405 | REGULATOR_CHANGE_STATUS,
406 },
407 .num_consumer_supplies = ARRAY_SIZE(overo_vmmc1_supply),
408 .consumer_supplies = overo_vmmc1_supply,
409};
410
411static struct twl4030_platform_data overo_twldata = {
412 .gpio = &overo_gpio_data,
413 .vmmc1 = &overo_vmmc1,
414};
415
416static int __init overo_i2c_init(void)
417{
418 omap3_pmic_get_config(&overo_twldata,
419 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
420 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
421
422 overo_twldata.vpll2->constraints.name = "VDVI";
423
424 omap3_pmic_init("tps65950", &overo_twldata);
425 /* i2c2 pins are used for gpio */
426 omap_register_i2c_bus(3, 400, NULL, 0);
427 return 0;
428}
429
430static struct panel_lb035q02_platform_data overo_lcd35_pdata = {
431 .name = "lcd35",
432 .source = "dpi.0",
433
434 .data_lines = 24,
435
436 .enable_gpio = OVERO_GPIO_LCD_EN,
437 .backlight_gpio = OVERO_GPIO_LCD_BL,
438};
439
440/*
441 * NOTE: We need to add either the lgphilips panel, or the lcd43 panel. The
442 * selection is done based on the overo_use_lcd35 field. If new SPI
443 * devices are added here, extra work is needed to make only the lgphilips panel
444 * affected by the overo_use_lcd35 field.
445 */
446static struct spi_board_info overo_spi_board_info[] __initdata = {
447 {
448 .modalias = "panel_lgphilips_lb035q02",
449 .bus_num = 1,
450 .chip_select = 1,
451 .max_speed_hz = 500000,
452 .mode = SPI_MODE_3,
453 .platform_data = &overo_lcd35_pdata,
454 },
455};
456
457static int __init overo_spi_init(void)
458{
459 overo_ads7846_init();
460
461 if (overo_use_lcd35) {
462 spi_register_board_info(overo_spi_board_info,
463 ARRAY_SIZE(overo_spi_board_info));
464 }
465 return 0;
466}
467
468static struct usbhs_phy_data phy_data[] __initdata = {
469 {
470 .port = 2,
471 .reset_gpio = OVERO_GPIO_USBH_NRESET,
472 .vcc_gpio = -EINVAL,
473 },
474};
475
476static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
477 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
478};
479
480#ifdef CONFIG_OMAP_MUX
481static struct omap_board_mux board_mux[] __initdata = {
482 { .reg_offset = OMAP_MUX_TERMINATOR },
483};
484#endif
485
486static struct gpio overo_bt_gpios[] __initdata = {
487 { OVERO_GPIO_BT_XGATE, GPIOF_OUT_INIT_LOW, "lcd enable" },
488 { OVERO_GPIO_BT_NRESET, GPIOF_OUT_INIT_HIGH, "lcd bl enable" },
489};
490
491static struct regulator_consumer_supply dummy_supplies[] = {
492 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
493 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
494 REGULATOR_SUPPLY("vddvario", "smsc911x.1"),
495 REGULATOR_SUPPLY("vdd33a", "smsc911x.1"),
496};
497
498static void __init overo_init(void)
499{
500 int ret;
501
502 if (strstr(boot_command_line, "omapdss.def_disp=lcd35"))
503 overo_use_lcd35 = true;
504
505 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
506 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
507 overo_i2c_init();
508 omap_hsmmc_init(mmc);
509 omap_serial_init();
510 omap_sdrc_init(mt46h32m32lf6_sdrc_params,
511 mt46h32m32lf6_sdrc_params);
512 board_nand_init(overo_nand_partitions,
513 ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
514 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
515 usb_musb_init(NULL);
516
517 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
518 usbhs_init(&usbhs_bdata);
519 overo_spi_init();
520 overo_init_smsc911x();
521 overo_init_led();
522 overo_init_keys();
523 omap_twl4030_audio_init("overo", NULL);
524
525 overo_display_init();
526
527 /* Ensure SDRC pins are mux'd for self-refresh */
528 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
529 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
530
531 ret = gpio_request_one(OVERO_GPIO_W2W_NRESET, GPIOF_OUT_INIT_HIGH,
532 "OVERO_GPIO_W2W_NRESET");
533 if (ret == 0) {
534 gpio_export(OVERO_GPIO_W2W_NRESET, 0);
535 gpio_set_value(OVERO_GPIO_W2W_NRESET, 0);
536 udelay(10);
537 gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
538 } else {
539 pr_err("could not obtain gpio for OVERO_GPIO_W2W_NRESET\n");
540 }
541
542 ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios));
543 if (ret) {
544 pr_err("%s: could not obtain BT gpios\n", __func__);
545 } else {
546 gpio_export(OVERO_GPIO_BT_XGATE, 0);
547 gpio_export(OVERO_GPIO_BT_NRESET, 0);
548 gpio_set_value(OVERO_GPIO_BT_NRESET, 0);
549 mdelay(6);
550 gpio_set_value(OVERO_GPIO_BT_NRESET, 1);
551 }
552
553 ret = gpio_request_one(OVERO_GPIO_USBH_CPEN, GPIOF_OUT_INIT_HIGH,
554 "OVERO_GPIO_USBH_CPEN");
555 if (ret == 0)
556 gpio_export(OVERO_GPIO_USBH_CPEN, 0);
557 else
558 pr_err("could not obtain gpio for OVERO_GPIO_USBH_CPEN\n");
559}
560
561MACHINE_START(OVERO, "Gumstix Overo")
562 .atag_offset = 0x100,
563 .reserve = omap_reserve,
564 .map_io = omap3_map_io,
565 .init_early = omap35xx_init_early,
566 .init_irq = omap3_init_irq,
567 .init_machine = overo_init,
568 .init_late = omap35xx_init_late,
569 .init_time = omap3_sync32k_timer_init,
570 .restart = omap3xxx_restart,
571MACHINE_END
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 990338fbaa59..a69bd67e9028 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -63,7 +63,7 @@ static int __init omap3_l3_init(void)
63 63
64 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); 64 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
65 65
66 return PTR_RET(pdev); 66 return PTR_ERR_OR_ZERO(pdev);
67} 67}
68omap_postcore_initcall(omap3_l3_init); 68omap_postcore_initcall(omap3_l3_init);
69 69
@@ -333,6 +333,6 @@ static int __init omap_gpmc_init(void)
333 pdev = omap_device_build("omap-gpmc", -1, oh, NULL, 0); 333 pdev = omap_device_build("omap-gpmc", -1, oh, NULL, 0);
334 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); 334 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
335 335
336 return PTR_RET(pdev); 336 return PTR_ERR_OR_ZERO(pdev);
337} 337}
338omap_postcore_initcall(omap_gpmc_init); 338omap_postcore_initcall(omap_gpmc_init);
diff --git a/arch/arm/mach-omap2/fb.c b/arch/arm/mach-omap2/fb.c
index 26e28e94f625..1f1ecf8807eb 100644
--- a/arch/arm/mach-omap2/fb.c
+++ b/arch/arm/mach-omap2/fb.c
@@ -84,7 +84,7 @@ int __init omap_init_vrfb(void)
84 pdev = platform_device_register_resndata(NULL, "omapvrfb", -1, 84 pdev = platform_device_register_resndata(NULL, "omapvrfb", -1,
85 res, num_res, NULL, 0); 85 res, num_res, NULL, 0);
86 86
87 return PTR_RET(pdev); 87 return PTR_ERR_OR_ZERO(pdev);
88} 88}
89#else 89#else
90int __init omap_init_vrfb(void) { return 0; } 90int __init omap_init_vrfb(void) { return 0; }
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index f899e77ff5e6..17a6f752a436 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -216,11 +216,11 @@ static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
216 216
217 div = gpmc_calc_divider(min_gpmc_clk_period); 217 div = gpmc_calc_divider(min_gpmc_clk_period);
218 gpmc_clk_ns = gpmc_ticks_to_ns(div); 218 gpmc_clk_ns = gpmc_ticks_to_ns(div);
219 if (gpmc_clk_ns < 15) /* >66Mhz */ 219 if (gpmc_clk_ns < 15) /* >66MHz */
220 onenand_flags |= ONENAND_FLAG_HF; 220 onenand_flags |= ONENAND_FLAG_HF;
221 else 221 else
222 onenand_flags &= ~ONENAND_FLAG_HF; 222 onenand_flags &= ~ONENAND_FLAG_HF;
223 if (gpmc_clk_ns < 12) /* >83Mhz */ 223 if (gpmc_clk_ns < 12) /* >83MHz */
224 onenand_flags |= ONENAND_FLAG_VHF; 224 onenand_flags |= ONENAND_FLAG_VHF;
225 else 225 else
226 onenand_flags &= ~ONENAND_FLAG_VHF; 226 onenand_flags &= ~ONENAND_FLAG_VHF;
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 9a8611ab5dfa..cff079e563f4 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -70,7 +70,7 @@ static void omap_hsmmc1_before_set_reg(struct device *dev,
70 70
71 reg = omap_ctrl_readl(control_pbias_offset); 71 reg = omap_ctrl_readl(control_pbias_offset);
72 if (cpu_is_omap3630()) { 72 if (cpu_is_omap3630()) {
73 /* Set MMC I/O to 52Mhz */ 73 /* Set MMC I/O to 52MHz */
74 prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 74 prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
75 prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL; 75 prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
76 omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1); 76 omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 3b56722dfd8a..8e52621b5a6b 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -444,7 +444,7 @@ static int wakeupgen_domain_alloc(struct irq_domain *domain,
444 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args); 444 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args);
445} 445}
446 446
447static struct irq_domain_ops wakeupgen_domain_ops = { 447static const struct irq_domain_ops wakeupgen_domain_ops = {
448 .xlate = wakeupgen_domain_xlate, 448 .xlate = wakeupgen_domain_xlate,
449 .alloc = wakeupgen_domain_alloc, 449 .alloc = wakeupgen_domain_alloc,
450 .free = irq_domain_free_irqs_common, 450 .free = irq_domain_free_irqs_common,
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
index 0e75ec3e114b..b2233b72b24d 100644
--- a/arch/arm/mach-omap2/opp2430_data.c
+++ b/arch/arm/mach-omap2/opp2430_data.c
@@ -116,7 +116,7 @@ const struct prcm_config omap2430_rate_table[] = {
116 RATE_IN_243X}, 116 RATE_IN_243X},
117 117
118 /* PRCM-boot/bypass */ 118 /* PRCM-boot/bypass */
119 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ 119 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13MHz */
120 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, 120 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
121 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, 121 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
122 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, 122 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
@@ -124,7 +124,7 @@ const struct prcm_config omap2430_rate_table[] = {
124 RATE_IN_243X}, 124 RATE_IN_243X},
125 125
126 /* PRCM-boot/bypass */ 126 /* PRCM-boot/bypass */
127 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ 127 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12MHz */
128 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, 128 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
129 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, 129 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
130 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, 130 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
index a69e9a33cb6d..d2adfebd3b3f 100644
--- a/arch/arm/mach-omap2/pmu.c
+++ b/arch/arm/mach-omap2/pmu.c
@@ -55,7 +55,7 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
55 WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n", 55 WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
56 dev_name); 56 dev_name);
57 57
58 return PTR_RET(omap_pmu_dev); 58 return PTR_ERR_OR_ZERO(omap_pmu_dev);
59} 59}
60 60
61static int __init omap_init_pmu(void) 61static int __init omap_init_pmu(void)
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index ae3f1553158d..339b0ecb7c32 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -164,6 +164,6 @@ void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
164 mem_timings.slow_dll_ctrl |= 164 mem_timings.slow_dll_ctrl |=
165 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2)); 165 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
166 166
167 /* 90 degree phase for anything below 133Mhz + disable DLL filter */ 167 /* 90 degree phase for anything below 133MHz + disable DLL filter */
168 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); 168 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
169} 169}
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 57dee0c7cd2b..5fb50fe54153 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -203,7 +203,7 @@ static int __init omap_serial_early_init(void)
203 if (cmdline_find_option(uart_name)) { 203 if (cmdline_find_option(uart_name)) {
204 console_uart_id = uart->num; 204 console_uart_id = uart->num;
205 205
206 if (console_loglevel >= 10) { 206 if (console_loglevel >= CONSOLE_LOGLEVEL_DEBUG) {
207 uart_debug = true; 207 uart_debug = true;
208 pr_info("%s used as console in debug mode: uart%d clocks will not be gated", 208 pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
209 uart_name, uart->num); 209 uart_name, uart->num);
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 2c88ff2d0236..53a2537cd75a 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -64,7 +64,7 @@ ENTRY(omap242x_sram_ddr_init)
64 mvn r9, #0x4 @ mask to get clear bit2 64 mvn r9, #0x4 @ mask to get clear bit2
65 and r10, r10, r9 @ clear bit2 for lock mode. 65 and r10, r10, r9 @ clear bit2 for lock mode.
66 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) 66 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
67 orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz 67 orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
68 str r10, [r11] @ commit to DLLA_CTRL 68 str r10, [r11] @ commit to DLLA_CTRL
69 bl i_dll_wait @ wait for dll to lock 69 bl i_dll_wait @ wait for dll to lock
70 70
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index d5deb9761fc7..b3edd6f7f7db 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -64,7 +64,7 @@ ENTRY(omap243x_sram_ddr_init)
64 mvn r9, #0x4 @ mask to get clear bit2 64 mvn r9, #0x4 @ mask to get clear bit2
65 and r10, r10, r9 @ clear bit2 for lock mode. 65 and r10, r10, r9 @ clear bit2 for lock mode.
66 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) 66 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
67 orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz 67 orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
68 str r10, [r11] @ commit to DLLA_CTRL 68 str r10, [r11] @ commit to DLLA_CTRL
69 bl i_dll_wait @ wait for dll to lock 69 bl i_dll_wait @ wait for dll to lock
70 70
diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
index d86fe33c5f53..209d9fc5c16c 100644
--- a/arch/arm/mach-prima2/headsmp.S
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -15,7 +15,6 @@
15 * ready for them to initialise. 15 * ready for them to initialise.
16 */ 16 */
17ENTRY(sirfsoc_secondary_startup) 17ENTRY(sirfsoc_secondary_startup)
18 bl v7_invalidate_l1
19 mrc p15, 0, r0, c0, c0, 5 18 mrc p15, 0, r0, c0, c0, 5
20 and r0, r0, #15 19 and r0, r0, #15
21 adr r4, 1f 20 adr r4, 1f
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index 854f1f562d6b..14f6aaf8fcc9 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -28,7 +28,7 @@
28static void isp116x_pfm_delay(struct device *dev, int delay) 28static void isp116x_pfm_delay(struct device *dev, int delay)
29{ 29{
30 30
31 /* 400Mhz PXA2 = 2.5ns / instruction */ 31 /* 400MHz PXA2 = 2.5ns / instruction */
32 32
33 int cyc = delay / 10; 33 int cyc = delay / 10;
34 34
diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
index 39bca96b555a..492c048813da 100644
--- a/arch/arm/mach-rockchip/core.h
+++ b/arch/arm/mach-rockchip/core.h
@@ -17,4 +17,3 @@ extern char rockchip_secondary_trampoline;
17extern char rockchip_secondary_trampoline_end; 17extern char rockchip_secondary_trampoline_end;
18 18
19extern unsigned long rockchip_boot_fn; 19extern unsigned long rockchip_boot_fn;
20extern void rockchip_secondary_startup(void);
diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
index 46c22dedf632..d69708b07282 100644
--- a/arch/arm/mach-rockchip/headsmp.S
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -15,14 +15,6 @@
15#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18ENTRY(rockchip_secondary_startup)
19 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
20 ldr r1, =0x00000c09 @ Cortex-A9 primary part number
21 teq r0, r1
22 beq v7_invalidate_l1
23 b secondary_startup
24ENDPROC(rockchip_secondary_startup)
25
26ENTRY(rockchip_secondary_trampoline) 18ENTRY(rockchip_secondary_trampoline)
27 ldr pc, 1f 19 ldr pc, 1f
28ENDPROC(rockchip_secondary_trampoline) 20ENDPROC(rockchip_secondary_trampoline)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 5b4ca3c3c879..2e6ab67e2284 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -149,8 +149,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
149 * sram_base_addr + 8: start address for pc 149 * sram_base_addr + 8: start address for pc
150 * */ 150 * */
151 udelay(10); 151 udelay(10);
152 writel(virt_to_phys(rockchip_secondary_startup), 152 writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
153 sram_base_addr + 8);
154 writel(0xDEADBEAF, sram_base_addr + 4); 153 writel(0xDEADBEAF, sram_base_addr + 4);
155 dsb_sev(); 154 dsb_sev();
156 } 155 }
@@ -189,7 +188,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
189 } 188 }
190 189
191 /* set the boot function for the sram code */ 190 /* set the boot function for the sram code */
192 rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup); 191 rockchip_boot_fn = virt_to_phys(secondary_startup);
193 192
194 /* copy the trampoline to sram, that runs during startup of the core */ 193 /* copy the trampoline to sram, that runs during startup of the core */
195 memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz); 194 memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index afc60bad6fd6..476092b86c6e 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -14,7 +14,6 @@ extern void shmobile_smp_sleep(void);
14extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, 14extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
15 unsigned long arg); 15 unsigned long arg);
16extern int shmobile_smp_cpu_disable(unsigned int cpu); 16extern int shmobile_smp_cpu_disable(unsigned int cpu);
17extern void shmobile_invalidate_start(void);
18extern void shmobile_boot_scu(void); 17extern void shmobile_boot_scu(void);
19extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); 18extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
20extern void shmobile_smp_scu_cpu_die(unsigned int cpu); 19extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index 69df8bfac167..fa5248c52399 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -22,7 +22,7 @@
22 * Boot code for secondary CPUs. 22 * Boot code for secondary CPUs.
23 * 23 *
24 * First we turn on L1 cache coherency for our CPU. Then we jump to 24 * First we turn on L1 cache coherency for our CPU. Then we jump to
25 * shmobile_invalidate_start that invalidates the cache and hands over control 25 * secondary_startup that invalidates the cache and hands over control
26 * to the common ARM startup code. 26 * to the common ARM startup code.
27 */ 27 */
28ENTRY(shmobile_boot_scu) 28ENTRY(shmobile_boot_scu)
@@ -36,7 +36,7 @@ ENTRY(shmobile_boot_scu)
36 bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) 36 bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
37 str r2, [r0, #8] @ write back 37 str r2, [r0, #8] @ write back
38 38
39 b shmobile_invalidate_start 39 b secondary_startup
40ENDPROC(shmobile_boot_scu) 40ENDPROC(shmobile_boot_scu)
41 41
42 .text 42 .text
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 50c491567e11..330c1fc63197 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -16,13 +16,6 @@
16#include <asm/assembler.h> 16#include <asm/assembler.h>
17#include <asm/memory.h> 17#include <asm/memory.h>
18 18
19#ifdef CONFIG_SMP
20ENTRY(shmobile_invalidate_start)
21 bl v7_invalidate_l1
22 b secondary_startup
23ENDPROC(shmobile_invalidate_start)
24#endif
25
26/* 19/*
27 * Reset vector for secondary CPUs. 20 * Reset vector for secondary CPUs.
28 * This will be mapped at address 0 by SBAR register. 21 * This will be mapped at address 0 by SBAR register.
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index f483b560b066..b0790fc32282 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -133,7 +133,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
133int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) 133int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
134{ 134{
135 /* For this particular CPU register boot vector */ 135 /* For this particular CPU register boot vector */
136 shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0); 136 shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
137 137
138 return apmu_wrap(cpu, apmu_power_on); 138 return apmu_wrap(cpu, apmu_power_on);
139} 139}
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index a0f3b1cd497c..767c09e954a0 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -31,7 +31,6 @@
31 31
32#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ 32#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
33 33
34extern void socfpga_secondary_startup(void);
35extern void __iomem *socfpga_scu_base_addr; 34extern void __iomem *socfpga_scu_base_addr;
36 35
37extern void socfpga_init_clocks(void); 36extern void socfpga_init_clocks(void);
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index f65ea0af4af3..5bb016427107 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -30,8 +30,3 @@ ENTRY(secondary_trampoline)
301: .long . 301: .long .
31 .long socfpga_cpu1start_addr 31 .long socfpga_cpu1start_addr
32ENTRY(secondary_trampoline_end) 32ENTRY(secondary_trampoline_end)
33
34ENTRY(socfpga_secondary_startup)
35 bl v7_invalidate_l1
36 b secondary_startup
37ENDPROC(socfpga_secondary_startup)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index c64d89b7c0ca..79c5336c569f 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
40 40
41 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); 41 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
42 42
43 writel(virt_to_phys(socfpga_secondary_startup), 43 writel(virt_to_phys(secondary_startup),
44 sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)); 44 sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
45 45
46 flush_cache_all(); 46 flush_cache_all();
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e48a74458c25..fffad2426ee4 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
19ifeq ($(CONFIG_CPU_IDLE),y) 19ifeq ($(CONFIG_CPU_IDLE),y)
20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o 20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
21endif 21endif
22obj-$(CONFIG_SMP) += platsmp.o headsmp.o 22obj-$(CONFIG_SMP) += platsmp.o
23obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 23obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
24 24
25obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o 25obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
deleted file mode 100644
index 2072e7322c39..000000000000
--- a/arch/arm/mach-tegra/headsmp.S
+++ /dev/null
@@ -1,12 +0,0 @@
1#include <linux/linkage.h>
2#include <linux/init.h>
3
4#include "sleep.h"
5
6 .section ".text.head", "ax"
7
8ENTRY(tegra_secondary_startup)
9 check_cpu_part_num 0xc09, r8, r9
10 bleq v7_invalidate_l1
11 b secondary_startup
12ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 894c5c472184..6fd9db54887e 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -94,7 +94,7 @@ void __init tegra_cpu_reset_handler_init(void)
94 __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = 94 __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
95 *((u32 *)cpu_possible_mask); 95 *((u32 *)cpu_possible_mask);
96 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = 96 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
97 virt_to_phys((void *)tegra_secondary_startup); 97 virt_to_phys((void *)secondary_startup);
98#endif 98#endif
99 99
100#ifdef CONFIG_PM_SLEEP 100#ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index 76a93434c6ee..0aee0129f8d7 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -36,7 +36,6 @@ extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
36void __tegra_cpu_reset_handler_start(void); 36void __tegra_cpu_reset_handler_start(void);
37void __tegra_cpu_reset_handler(void); 37void __tegra_cpu_reset_handler(void);
38void __tegra_cpu_reset_handler_end(void); 38void __tegra_cpu_reset_handler_end(void);
39void tegra_secondary_startup(void);
40 39
41#ifdef CONFIG_PM_SLEEP 40#ifdef CONFIG_PM_SLEEP
42#define tegra_cpu_lp1_mask \ 41#define tegra_cpu_lp1_mask \
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 5d8d13aeab93..9a2f0b051e10 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -223,7 +223,7 @@ wfe_war:
223 b __cpu_reset_again 223 b __cpu_reset_again
224 224
225 /* 225 /*
226 * 38 nop's, which fills reset of wfe cache line and 226 * 38 nop's, which fills rest of wfe cache line and
227 * 4 more cachelines with nop 227 * 4 more cachelines with nop
228 */ 228 */
229 .rept 38 229 .rept 38
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index e97ee556f92f..7557bede7ae6 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -6,6 +6,7 @@
6 6
7#include <linux/io.h> 7#include <linux/io.h>
8#include <linux/of.h> 8#include <linux/of.h>
9#include <linux/of_address.h>
9 10
10#include <asm/hardware/cache-l2x0.h> 11#include <asm/hardware/cache-l2x0.h>
11 12
@@ -15,7 +16,14 @@
15static int __init ux500_l2x0_unlock(void) 16static int __init ux500_l2x0_unlock(void)
16{ 17{
17 int i; 18 int i;
18 void __iomem *l2x0_base = __io_address(U8500_L2CC_BASE); 19 struct device_node *np;
20 void __iomem *l2x0_base;
21
22 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
23 l2x0_base = of_iomap(np, 0);
24 of_node_put(np);
25 if (!l2x0_base)
26 return -ENODEV;
19 27
20 /* 28 /*
21 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions 29 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
@@ -30,6 +38,7 @@ static int __init ux500_l2x0_unlock(void)
30 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + 38 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
31 i * L2X0_LOCKDOWN_STRIDE); 39 i * L2X0_LOCKDOWN_STRIDE);
32 } 40 }
41 iounmap(l2x0_base);
33 return 0; 42 return 0;
34} 43}
35 44
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 6f63954c8bde..16913800bbf9 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -43,60 +43,10 @@ static struct prcmu_pdata db8500_prcmu_pdata = {
43 .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, 43 .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET,
44}; 44};
45 45
46/* minimum static i/o mapping required to boot U8500 platforms */
47static struct map_desc u8500_uart_io_desc[] __initdata = {
48 __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
49 __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
50};
51/* U8500 and U9540 common io_desc */
52static struct map_desc u8500_common_io_desc[] __initdata = {
53 /* SCU base also covers GIC CPU BASE and TWD with its 4K page */
54 __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
55 __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
56 __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
57 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
58 __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
59
60 __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
61 __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
62 __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
63 __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
64 __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
65
66 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
67 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
68 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
69 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
70};
71
72/* U8500 IO map specific description */
73static struct map_desc u8500_io_desc[] __initdata = {
74 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
75 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
76
77};
78
79/* U9540 IO map specific description */
80static struct map_desc u9540_io_desc[] __initdata = {
81 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K),
82 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K),
83};
84
85static void __init u8500_map_io(void) 46static void __init u8500_map_io(void)
86{ 47{
87 /* 48 debug_ll_io_init();
88 * Map the UARTs early so that the DEBUG_LL stuff continues to work. 49 ux500_setup_id();
89 */
90 iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
91
92 ux500_map_io();
93
94 iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
95
96 if (cpu_is_ux540_family())
97 iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
98 else
99 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
100} 50}
101 51
102/* 52/*
@@ -125,14 +75,18 @@ static struct arm_pmu_platdata db8500_pmu_platdata = {
125 75
126static const char *db8500_read_soc_id(void) 76static const char *db8500_read_soc_id(void)
127{ 77{
128 void __iomem *uid = __io_address(U8500_BB_UID_BASE); 78 void __iomem *uid;
129 79
80 uid = ioremap(U8500_BB_UID_BASE, 0x20);
81 if (!uid)
82 return NULL;
130 /* Throw these device-specific numbers into the entropy pool */ 83 /* Throw these device-specific numbers into the entropy pool */
131 add_device_randomness(uid, 0x14); 84 add_device_randomness(uid, 0x14);
132 return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x", 85 return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
133 readl((u32 *)uid+0), 86 readl((u32 *)uid+0),
134 readl((u32 *)uid+1), readl((u32 *)uid+2), 87 readl((u32 *)uid+1), readl((u32 *)uid+2),
135 readl((u32 *)uid+3), readl((u32 *)uid+4)); 88 readl((u32 *)uid+3), readl((u32 *)uid+4));
89 iounmap(uid);
136} 90}
137 91
138static struct device * __init db8500_soc_device_init(void) 92static struct device * __init db8500_soc_device_init(void)
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 6ced0f680262..e31d3d61c998 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -16,6 +16,7 @@
16#include <linux/stat.h> 16#include <linux/stat.h>
17#include <linux/of.h> 17#include <linux/of.h>
18#include <linux/of_irq.h> 18#include <linux/of_irq.h>
19#include <linux/of_address.h>
19#include <linux/irq.h> 20#include <linux/irq.h>
20#include <linux/irqchip.h> 21#include <linux/irqchip.h>
21#include <linux/irqchip/arm-gic.h> 22#include <linux/irqchip/arm-gic.h>
@@ -52,31 +53,36 @@ void ux500_restart(enum reboot_mode mode, const char *cmd)
52*/ 53*/
53void __init ux500_init_irq(void) 54void __init ux500_init_irq(void)
54{ 55{
56 struct device_node *np;
57 struct resource r;
58
55 gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND); 59 gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND);
56 irqchip_init(); 60 irqchip_init();
61 np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
62 of_address_to_resource(np, 0, &r);
63 of_node_put(np);
64 if (!r.start) {
65 pr_err("could not find PRCMU base resource\n");
66 return;
67 }
68 prcmu_early_init(r.start, r.end-r.start);
69 ux500_pm_init(r.start, r.end-r.start);
57 70
58 /* 71 /*
59 * Init clocks here so that they are available for system timer 72 * Init clocks here so that they are available for system timer
60 * initialization. 73 * initialization.
61 */ 74 */
62 if (cpu_is_u8500_family()) { 75 if (cpu_is_u8500_family()) {
63 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
64 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
65
66 u8500_of_clk_init(U8500_CLKRST1_BASE, 76 u8500_of_clk_init(U8500_CLKRST1_BASE,
67 U8500_CLKRST2_BASE, 77 U8500_CLKRST2_BASE,
68 U8500_CLKRST3_BASE, 78 U8500_CLKRST3_BASE,
69 U8500_CLKRST5_BASE, 79 U8500_CLKRST5_BASE,
70 U8500_CLKRST6_BASE); 80 U8500_CLKRST6_BASE);
71 } else if (cpu_is_u9540()) { 81 } else if (cpu_is_u9540()) {
72 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
73 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
74 u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, 82 u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
75 U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, 83 U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
76 U8500_CLKRST6_BASE); 84 U8500_CLKRST6_BASE);
77 } else if (cpu_is_u8540()) { 85 } else if (cpu_is_u8540()) {
78 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
79 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
80 u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, 86 u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
81 U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, 87 U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
82 U8500_CLKRST6_BASE); 88 U8500_CLKRST6_BASE);
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index 392f2fdb37d0..1e81e990044b 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -72,7 +72,7 @@ static unsigned int partnumber(unsigned int asicid)
72 * DB9540 0x413fc090 0xFFFFDBF4 0x009540xx 72 * DB9540 0x413fc090 0xFFFFDBF4 0x009540xx
73 */ 73 */
74 74
75void __init ux500_map_io(void) 75void __init ux500_setup_id(void)
76{ 76{
77 unsigned int cpuid = read_cpuid_id(); 77 unsigned int cpuid = read_cpuid_id();
78 unsigned int asicid = 0; 78 unsigned int asicid = 0;
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index a44967f3168c..62b1de922bd8 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -16,6 +16,8 @@
16#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/smp.h> 17#include <linux/smp.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
19 21
20#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
21#include <asm/smp_plat.h> 23#include <asm/smp_plat.h>
@@ -26,6 +28,9 @@
26#include "db8500-regs.h" 28#include "db8500-regs.h"
27#include "id.h" 29#include "id.h"
28 30
31static void __iomem *scu_base;
32static void __iomem *backupram;
33
29/* This is called from headsmp.S to wakeup the secondary core */ 34/* This is called from headsmp.S to wakeup the secondary core */
30extern void u8500_secondary_startup(void); 35extern void u8500_secondary_startup(void);
31 36
@@ -41,16 +46,6 @@ static void write_pen_release(int val)
41 sync_cache_w(&pen_release); 46 sync_cache_w(&pen_release);
42} 47}
43 48
44static void __iomem *scu_base_addr(void)
45{
46 if (cpu_is_u8500_family() || cpu_is_ux540_family())
47 return __io_address(U8500_SCU_BASE);
48 else
49 ux500_unknown_soc();
50
51 return NULL;
52}
53
54static DEFINE_SPINLOCK(boot_lock); 49static DEFINE_SPINLOCK(boot_lock);
55 50
56static void ux500_secondary_init(unsigned int cpu) 51static void ux500_secondary_init(unsigned int cpu)
@@ -104,13 +99,6 @@ static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
104 99
105static void __init wakeup_secondary(void) 100static void __init wakeup_secondary(void)
106{ 101{
107 void __iomem *backupram;
108
109 if (cpu_is_u8500_family() || cpu_is_ux540_family())
110 backupram = __io_address(U8500_BACKUPRAM0_BASE);
111 else
112 ux500_unknown_soc();
113
114 /* 102 /*
115 * write the address of secondary startup into the backup ram register 103 * write the address of secondary startup into the backup ram register
116 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the 104 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
@@ -135,10 +123,16 @@ static void __init wakeup_secondary(void)
135 */ 123 */
136static void __init ux500_smp_init_cpus(void) 124static void __init ux500_smp_init_cpus(void)
137{ 125{
138 void __iomem *scu_base = scu_base_addr();
139 unsigned int i, ncores; 126 unsigned int i, ncores;
127 struct device_node *np;
140 128
141 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 129 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
130 scu_base = of_iomap(np, 0);
131 of_node_put(np);
132 if (!scu_base)
133 return;
134 backupram = ioremap(U8500_BACKUPRAM0_BASE, SZ_8K);
135 ncores = scu_get_core_count(scu_base);
142 136
143 /* sanity check */ 137 /* sanity check */
144 if (ncores > nr_cpu_ids) { 138 if (ncores > nr_cpu_ids) {
@@ -153,8 +147,7 @@ static void __init ux500_smp_init_cpus(void)
153 147
154static void __init ux500_smp_prepare_cpus(unsigned int max_cpus) 148static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
155{ 149{
156 150 scu_enable(scu_base);
157 scu_enable(scu_base_addr());
158 wakeup_secondary(); 151 wakeup_secondary();
159} 152}
160 153
diff --git a/arch/arm/mach-ux500/pm.c b/arch/arm/mach-ux500/pm.c
index 2cb587b50905..8538910db202 100644
--- a/arch/arm/mach-ux500/pm.c
+++ b/arch/arm/mach-ux500/pm.c
@@ -15,6 +15,8 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/suspend.h> 16#include <linux/suspend.h>
17#include <linux/platform_data/arm-ux500-pm.h> 17#include <linux/platform_data/arm-ux500-pm.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
18 20
19#include "db8500-regs.h" 21#include "db8500-regs.h"
20#include "pm_domains.h" 22#include "pm_domains.h"
@@ -42,6 +44,7 @@
42#define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C) 44#define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C)
43 45
44static void __iomem *prcmu_base; 46static void __iomem *prcmu_base;
47static void __iomem *dist_base;
45 48
46/* This function decouple the gic from the prcmu */ 49/* This function decouple the gic from the prcmu */
47int prcmu_gic_decouple(void) 50int prcmu_gic_decouple(void)
@@ -88,7 +91,6 @@ bool prcmu_gic_pending_irq(void)
88{ 91{
89 u32 pr; /* Pending register */ 92 u32 pr; /* Pending register */
90 u32 er; /* Enable register */ 93 u32 er; /* Enable register */
91 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
92 int i; 94 int i;
93 95
94 /* 5 registers. STI & PPI not skipped */ 96 /* 5 registers. STI & PPI not skipped */
@@ -143,7 +145,6 @@ bool prcmu_is_cpu_in_wfi(int cpu)
143int prcmu_copy_gic_settings(void) 145int prcmu_copy_gic_settings(void)
144{ 146{
145 u32 er; /* Enable register */ 147 u32 er; /* Enable register */
146 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
147 int i; 148 int i;
148 149
149 /* We skip the STI and PPI */ 150 /* We skip the STI and PPI */
@@ -179,11 +180,21 @@ static const struct platform_suspend_ops ux500_suspend_ops = {
179 180
180void __init ux500_pm_init(u32 phy_base, u32 size) 181void __init ux500_pm_init(u32 phy_base, u32 size)
181{ 182{
183 struct device_node *np;
184
182 prcmu_base = ioremap(phy_base, size); 185 prcmu_base = ioremap(phy_base, size);
183 if (!prcmu_base) { 186 if (!prcmu_base) {
184 pr_err("could not remap PRCMU for PM functions\n"); 187 pr_err("could not remap PRCMU for PM functions\n");
185 return; 188 return;
186 } 189 }
190 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
191 dist_base = of_iomap(np, 0);
192 of_node_put(np);
193 if (!dist_base) {
194 pr_err("could not remap GIC dist base for PM functions\n");
195 return;
196 }
197
187 /* 198 /*
188 * On watchdog reboot the GIC is in some cases decoupled. 199 * On watchdog reboot the GIC is in some cases decoupled.
189 * This will make sure that the GIC is correctly configured. 200 * This will make sure that the GIC is correctly configured.
diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h
index 2dea8b59d222..1fb6ad2789f1 100644
--- a/arch/arm/mach-ux500/setup.h
+++ b/arch/arm/mach-ux500/setup.h
@@ -18,7 +18,7 @@
18 18
19void ux500_restart(enum reboot_mode mode, const char *cmd); 19void ux500_restart(enum reboot_mode mode, const char *cmd);
20 20
21void __init ux500_map_io(void); 21void __init ux500_setup_id(void);
22 22
23extern void __init ux500_init_irq(void); 23extern void __init ux500_init_irq(void);
24 24
@@ -26,20 +26,6 @@ extern struct device *ux500_soc_device_init(const char *soc_id);
26 26
27extern void ux500_timer_init(void); 27extern void ux500_timer_init(void);
28 28
29#define __IO_DEV_DESC(x, sz) { \
30 .virtual = IO_ADDRESS(x), \
31 .pfn = __phys_to_pfn(x), \
32 .length = sz, \
33 .type = MT_DEVICE, \
34}
35
36#define __MEM_DEV_DESC(x, sz) { \
37 .virtual = IO_ADDRESS(x), \
38 .pfn = __phys_to_pfn(x), \
39 .length = sz, \
40 .type = MT_MEMORY_RWX, \
41}
42
43extern struct smp_operations ux500_smp_ops; 29extern struct smp_operations ux500_smp_ops;
44extern void ux500_cpu_die(unsigned int cpu); 30extern void ux500_cpu_die(unsigned int cpu);
45 31
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 382c60e9aa16..7038cae95ddc 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,8 +17,6 @@
17#ifndef __MACH_ZYNQ_COMMON_H__ 17#ifndef __MACH_ZYNQ_COMMON_H__
18#define __MACH_ZYNQ_COMMON_H__ 18#define __MACH_ZYNQ_COMMON_H__
19 19
20void zynq_secondary_startup(void);
21
22extern int zynq_slcr_init(void); 20extern int zynq_slcr_init(void);
23extern int zynq_early_slcr_init(void); 21extern int zynq_early_slcr_init(void);
24extern void zynq_slcr_system_reset(void); 22extern void zynq_slcr_system_reset(void);
diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S
index dd8c071941e7..045c72720a4d 100644
--- a/arch/arm/mach-zynq/headsmp.S
+++ b/arch/arm/mach-zynq/headsmp.S
@@ -22,8 +22,3 @@ zynq_secondary_trampoline_jump:
22.globl zynq_secondary_trampoline_end 22.globl zynq_secondary_trampoline_end
23zynq_secondary_trampoline_end: 23zynq_secondary_trampoline_end:
24ENDPROC(zynq_secondary_trampoline) 24ENDPROC(zynq_secondary_trampoline)
25
26ENTRY(zynq_secondary_startup)
27 bl v7_invalidate_l1
28 b secondary_startup
29ENDPROC(zynq_secondary_startup)
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index 52d768ff7857..f66816c49186 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -87,10 +87,9 @@ int zynq_cpun_start(u32 address, int cpu)
87} 87}
88EXPORT_SYMBOL(zynq_cpun_start); 88EXPORT_SYMBOL(zynq_cpun_start);
89 89
90static int zynq_boot_secondary(unsigned int cpu, 90static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
91 struct task_struct *idle)
92{ 91{
93 return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu); 92 return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
94} 93}
95 94
96/* 95/*
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3d1054f11a8a..75ae72160099 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -336,7 +336,7 @@ __v7_pj4b_setup:
336__v7_setup: 336__v7_setup:
337 adr r12, __v7_setup_stack @ the local stack 337 adr r12, __v7_setup_stack @ the local stack
338 stmia r12, {r0-r5, r7, r9, r11, lr} 338 stmia r12, {r0-r5, r7, r9, r11, lr}
339 bl v7_flush_dcache_louis 339 bl v7_invalidate_l1
340 ldmia r12, {r0-r5, r7, r9, r11, lr} 340 ldmia r12, {r0-r5, r7, r9, r11, lr}
341 341
342 mrc p15, 0, r0, c0, c0, 0 @ read main ID register 342 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
diff --git a/arch/arm64/boot/dts/skeleton.dtsi b/arch/arm64/boot/dts/skeleton.dtsi
deleted file mode 100644
index 38ead821bb42..000000000000
--- a/arch/arm64/boot/dts/skeleton.dtsi
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * Skeleton device tree; the bare minimum needed to boot; just include and
3 * add a compatible value. The bootloader will typically populate the memory
4 * node.
5 */
6
7/ {
8 #address-cells = <2>;
9 #size-cells = <1>;
10 chosen { };
11 aliases { };
12 memory { device_type = "memory"; reg = <0 0 0>; };
13};
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 9dca4b995be0..f7bf7d9249e7 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -827,7 +827,6 @@ config PATA_AT32
827config PATA_AT91 827config PATA_AT91
828 tristate "PATA support for AT91SAM9260" 828 tristate "PATA support for AT91SAM9260"
829 depends on ARM && SOC_AT91SAM9 829 depends on ARM && SOC_AT91SAM9
830 depends on !ARCH_MULTIPLATFORM
831 help 830 help
832 This option enables support for IDE devices on the Atmel AT91SAM9260 SoC. 831 This option enables support for IDE devices on the Atmel AT91SAM9260 SoC.
833 832
diff --git a/drivers/ata/pata_at91.c b/drivers/ata/pata_at91.c
index 9e85937d36a9..ace0a4de3449 100644
--- a/drivers/ata/pata_at91.c
+++ b/drivers/ata/pata_at91.c
@@ -24,11 +24,13 @@
24#include <linux/ata.h> 24#include <linux/ata.h>
25#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/libata.h> 26#include <linux/libata.h>
27#include <linux/mfd/syscon.h>
28#include <linux/mfd/syscon/atmel-smc.h>
27#include <linux/platform_device.h> 29#include <linux/platform_device.h>
28#include <linux/ata_platform.h> 30#include <linux/ata_platform.h>
29#include <linux/platform_data/atmel.h> 31#include <linux/platform_data/atmel.h>
32#include <linux/regmap.h>
30 33
31#include <mach/at91sam9_smc.h>
32#include <asm/gpio.h> 34#include <asm/gpio.h>
33 35
34#define DRV_NAME "pata_at91" 36#define DRV_NAME "pata_at91"
@@ -57,6 +59,15 @@ struct smc_range {
57 int max; 59 int max;
58}; 60};
59 61
62struct regmap *smc;
63
64struct at91sam9_smc_generic_fields {
65 struct regmap_field *setup;
66 struct regmap_field *pulse;
67 struct regmap_field *cycle;
68 struct regmap_field *mode;
69} fields;
70
60/** 71/**
61 * adjust_smc_value - adjust value for one of SMC registers. 72 * adjust_smc_value - adjust value for one of SMC registers.
62 * @value: adjusted value 73 * @value: adjusted value
@@ -206,7 +217,6 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev,
206{ 217{
207 int ret = 0; 218 int ret = 0;
208 int use_iordy; 219 int use_iordy;
209 struct sam9_smc_config smc;
210 unsigned int t6z; /* data tristate time in ns */ 220 unsigned int t6z; /* data tristate time in ns */
211 unsigned int cycle; /* SMC Cycle width in MCK ticks */ 221 unsigned int cycle; /* SMC Cycle width in MCK ticks */
212 unsigned int setup; /* SMC Setup width in MCK ticks */ 222 unsigned int setup; /* SMC Setup width in MCK ticks */
@@ -244,19 +254,21 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev,
244 254
245 dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles); 255 dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
246 256
247 /* SMC Setup Register */ 257 regmap_fields_write(fields.setup, info->cs,
248 smc.nwe_setup = smc.nrd_setup = setup; 258 AT91SAM9_SMC_NRDSETUP(setup) |
249 smc.ncs_write_setup = smc.ncs_read_setup = 0; 259 AT91SAM9_SMC_NWESETUP(setup) |
250 /* SMC Pulse Register */ 260 AT91SAM9_SMC_NCS_NRDSETUP(0) |
251 smc.nwe_pulse = smc.nrd_pulse = pulse; 261 AT91SAM9_SMC_NCS_WRSETUP(0));
252 smc.ncs_write_pulse = smc.ncs_read_pulse = cs_pulse; 262 regmap_fields_write(fields.pulse, info->cs,
253 /* SMC Cycle Register */ 263 AT91SAM9_SMC_NRDPULSE(pulse) |
254 smc.write_cycle = smc.read_cycle = cycle; 264 AT91SAM9_SMC_NWEPULSE(pulse) |
255 /* SMC Mode Register*/ 265 AT91SAM9_SMC_NCS_NRDPULSE(cs_pulse) |
256 smc.tdf_cycles = tdf_cycles; 266 AT91SAM9_SMC_NCS_WRPULSE(cs_pulse));
257 smc.mode = info->mode; 267 regmap_fields_write(fields.cycle, info->cs,
258 268 AT91SAM9_SMC_NRDCYCLE(cycle) |
259 sam9_smc_configure(0, info->cs, &smc); 269 AT91SAM9_SMC_NWECYCLE(cycle));
270 regmap_fields_write(fields.mode, info->cs, info->mode |
271 AT91_SMC_TDF_(tdf_cycles));
260} 272}
261 273
262static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev) 274static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
@@ -280,21 +292,21 @@ static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
280{ 292{
281 struct at91_ide_info *info = dev->link->ap->host->private_data; 293 struct at91_ide_info *info = dev->link->ap->host->private_data;
282 unsigned int consumed; 294 unsigned int consumed;
295 unsigned int mode;
283 unsigned long flags; 296 unsigned long flags;
284 struct sam9_smc_config smc;
285 297
286 local_irq_save(flags); 298 local_irq_save(flags);
287 sam9_smc_read_mode(0, info->cs, &smc); 299 regmap_fields_read(fields.mode, info->cs, &mode);
288 300
289 /* set 16bit mode before writing data */ 301 /* set 16bit mode before writing data */
290 smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16; 302 regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
291 sam9_smc_write_mode(0, info->cs, &smc); 303 AT91_SMC_DBW_16);
292 304
293 consumed = ata_sff_data_xfer(dev, buf, buflen, rw); 305 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
294 306
295 /* restore 8bit mode after data is written */ 307 /* restore 8bit mode after data is written */
296 smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8; 308 regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
297 sam9_smc_write_mode(0, info->cs, &smc); 309 AT91_SMC_DBW_8);
298 310
299 local_irq_restore(flags); 311 local_irq_restore(flags);
300 return consumed; 312 return consumed;
@@ -312,6 +324,36 @@ static struct ata_port_operations pata_at91_port_ops = {
312 .cable_detect = ata_cable_40wire, 324 .cable_detect = ata_cable_40wire,
313}; 325};
314 326
327static int at91sam9_smc_fields_init(struct device *dev)
328{
329 struct reg_field field = REG_FIELD(0, 0, 31);
330
331 field.id_size = 8;
332 field.id_offset = AT91SAM9_SMC_GENERIC_BLK_SZ;
333
334 field.reg = AT91SAM9_SMC_SETUP(AT91SAM9_SMC_GENERIC);
335 fields.setup = devm_regmap_field_alloc(dev, smc, field);
336 if (IS_ERR(fields.setup))
337 return PTR_ERR(fields.setup);
338
339 field.reg = AT91SAM9_SMC_PULSE(AT91SAM9_SMC_GENERIC);
340 fields.pulse = devm_regmap_field_alloc(dev, smc, field);
341 if (IS_ERR(fields.pulse))
342 return PTR_ERR(fields.pulse);
343
344 field.reg = AT91SAM9_SMC_CYCLE(AT91SAM9_SMC_GENERIC);
345 fields.cycle = devm_regmap_field_alloc(dev, smc, field);
346 if (IS_ERR(fields.cycle))
347 return PTR_ERR(fields.cycle);
348
349 field.reg = AT91SAM9_SMC_MODE(AT91SAM9_SMC_GENERIC);
350 fields.mode = devm_regmap_field_alloc(dev, smc, field);
351 if (IS_ERR(fields.mode))
352 return PTR_ERR(fields.mode);
353
354 return 0;
355}
356
315static int pata_at91_probe(struct platform_device *pdev) 357static int pata_at91_probe(struct platform_device *pdev)
316{ 358{
317 struct at91_cf_data *board = dev_get_platdata(&pdev->dev); 359 struct at91_cf_data *board = dev_get_platdata(&pdev->dev);
@@ -341,6 +383,14 @@ static int pata_at91_probe(struct platform_device *pdev)
341 383
342 irq = board->irq_pin; 384 irq = board->irq_pin;
343 385
386 smc = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "atmel,smc");
387 if (IS_ERR(smc))
388 return PTR_ERR(smc);
389
390 ret = at91sam9_smc_fields_init(dev);
391 if (ret < 0)
392 return ret;
393
344 /* init ata host */ 394 /* init ata host */
345 395
346 host = ata_host_alloc(dev, 1); 396 host = ata_host_alloc(dev, 1);
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index a65f821f52eb..d3c378b4db6c 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -277,7 +277,6 @@ config AT91_CF
277 tristate "AT91 CompactFlash Controller" 277 tristate "AT91 CompactFlash Controller"
278 depends on PCI 278 depends on PCI
279 depends on PCMCIA && ARCH_AT91 279 depends on PCMCIA && ARCH_AT91
280 depends on !ARCH_MULTIPLATFORM
281 help 280 help
282 Say Y here to support the CompactFlash controller on AT91 chips. 281 Say Y here to support the CompactFlash controller on AT91 chips.
283 Or choose M to compile the driver as a module named "at91_cf". 282 Or choose M to compile the driver as a module named "at91_cf".
diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c
index e7775a41ae5d..87147bcd1655 100644
--- a/drivers/pcmcia/at91_cf.c
+++ b/drivers/pcmcia/at91_cf.c
@@ -20,16 +20,15 @@
20#include <linux/platform_data/atmel.h> 20#include <linux/platform_data/atmel.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/sizes.h> 22#include <linux/sizes.h>
23#include <linux/mfd/syscon.h>
24#include <linux/mfd/syscon/atmel-mc.h>
23#include <linux/of.h> 25#include <linux/of.h>
24#include <linux/of_device.h> 26#include <linux/of_device.h>
25#include <linux/of_gpio.h> 27#include <linux/of_gpio.h>
28#include <linux/regmap.h>
26 29
27#include <pcmcia/ss.h> 30#include <pcmcia/ss.h>
28 31
29#include <mach/at91rm9200_mc.h>
30#include <mach/at91_ramc.h>
31
32
33/* 32/*
34 * A0..A10 work in each range; A23 indicates I/O space; A25 is CFRNW; 33 * A0..A10 work in each range; A23 indicates I/O space; A25 is CFRNW;
35 * some other bit in {A24,A22..A11} is nREG to flag memory access 34 * some other bit in {A24,A22..A11} is nREG to flag memory access
@@ -40,6 +39,8 @@
40#define CF_IO_PHYS (1 << 23) 39#define CF_IO_PHYS (1 << 23)
41#define CF_MEM_PHYS (0x017ff800) 40#define CF_MEM_PHYS (0x017ff800)
42 41
42struct regmap *mc;
43
43/*--------------------------------------------------------------------------*/ 44/*--------------------------------------------------------------------------*/
44 45
45struct at91_cf_socket { 46struct at91_cf_socket {
@@ -155,10 +156,7 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
155 156
156 /* 157 /*
157 * Use 16 bit accesses unless/until we need 8-bit i/o space. 158 * Use 16 bit accesses unless/until we need 8-bit i/o space.
158 */ 159 *
159 csr = at91_ramc_read(0, AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
160
161 /*
162 * NOTE: this CF controller ignores IOIS16, so we can't really do 160 * NOTE: this CF controller ignores IOIS16, so we can't really do
163 * MAP_AUTOSZ. The 16bit mode allows single byte access on either 161 * MAP_AUTOSZ. The 16bit mode allows single byte access on either
164 * D0-D7 (even addr) or D8-D15 (odd), so it's close enough for many 162 * D0-D7 (even addr) or D8-D15 (odd), so it's close enough for many
@@ -169,13 +167,14 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
169 * CF 3.0 spec table 35 also giving the D8-D15 option. 167 * CF 3.0 spec table 35 also giving the D8-D15 option.
170 */ 168 */
171 if (!(io->flags & (MAP_16BIT | MAP_AUTOSZ))) { 169 if (!(io->flags & (MAP_16BIT | MAP_AUTOSZ))) {
172 csr |= AT91_SMC_DBW_8; 170 csr = AT91_MC_SMC_DBW_8;
173 dev_dbg(&cf->pdev->dev, "8bit i/o bus\n"); 171 dev_dbg(&cf->pdev->dev, "8bit i/o bus\n");
174 } else { 172 } else {
175 csr |= AT91_SMC_DBW_16; 173 csr = AT91_MC_SMC_DBW_16;
176 dev_dbg(&cf->pdev->dev, "16bit i/o bus\n"); 174 dev_dbg(&cf->pdev->dev, "16bit i/o bus\n");
177 } 175 }
178 at91_ramc_write(0, AT91_SMC_CSR(cf->board->chipselect), csr); 176 regmap_update_bits(mc, AT91_MC_SMC_CSR(cf->board->chipselect),
177 AT91_MC_SMC_DBW, csr);
179 178
180 io->start = cf->socket.io_offset; 179 io->start = cf->socket.io_offset;
181 io->stop = io->start + SZ_2K - 1; 180 io->stop = io->start + SZ_2K - 1;
@@ -236,6 +235,10 @@ static int at91_cf_dt_init(struct platform_device *pdev)
236 235
237 pdev->dev.platform_data = board; 236 pdev->dev.platform_data = board;
238 237
238 mc = syscon_regmap_lookup_by_compatible("atmel,at91rm9200-sdramc");
239 if (IS_ERR(mc))
240 return PTR_ERR(mc);
241
239 return 0; 242 return 0;
240} 243}
241#else 244#else
diff --git a/include/linux/mfd/syscon/atmel-mc.h b/include/linux/mfd/syscon/atmel-mc.h
new file mode 100644
index 000000000000..afd9b8f1e363
--- /dev/null
+++ b/include/linux/mfd/syscon/atmel-mc.h
@@ -0,0 +1,144 @@
1/*
2 * Copyright (C) 2005 Ivan Kokshaysky
3 * Copyright (C) SAN People
4 *
5 * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals
6 * registers.
7 * Based on AT91RM9200 datasheet revision E.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_
16#define _LINUX_MFD_SYSCON_ATMEL_MC_H_
17
18/* Memory Controller */
19#define AT91_MC_RCR 0x00
20#define AT91_MC_RCB BIT(0)
21
22#define AT91_MC_ASR 0x04
23#define AT91_MC_UNADD BIT(0)
24#define AT91_MC_MISADD BIT(1)
25#define AT91_MC_ABTSZ GENMASK(9, 8)
26#define AT91_MC_ABTSZ_BYTE (0 << 8)
27#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
28#define AT91_MC_ABTSZ_WORD (2 << 8)
29#define AT91_MC_ABTTYP GENMASK(11, 10)
30#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
31#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
32#define AT91_MC_ABTTYP_FETCH (2 << 10)
33#define AT91_MC_MST(n) BIT(16 + (n))
34#define AT91_MC_SVMST(n) BIT(24 + (n))
35
36#define AT91_MC_AASR 0x08
37
38#define AT91_MC_MPR 0x0c
39#define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))
40
41/* External Bus Interface (EBI) registers */
42#define AT91_MC_EBI_CSA 0x60
43#define AT91_MC_EBI_CS(n) BIT(x)
44#define AT91_MC_EBI_NUM_CS 8
45
46#define AT91_MC_EBI_CFGR 0x64
47#define AT91_MC_EBI_DBPUC BIT(0)
48
49/* Static Memory Controller (SMC) registers */
50#define AT91_MC_SMC_CSR(n) (0x70 + ((n) * 4))
51#define AT91_MC_SMC_NWS GENMASK(6, 0)
52#define AT91_MC_SMC_NWS_(x) ((x) << 0)
53#define AT91_MC_SMC_WSEN BIT(7)
54#define AT91_MC_SMC_TDF GENMASK(11, 8)
55#define AT91_MC_SMC_TDF_(x) ((x) << 8)
56#define AT91_MC_SMC_TDF_MAX 0xf
57#define AT91_MC_SMC_BAT BIT(12)
58#define AT91_MC_SMC_DBW GENMASK(14, 13)
59#define AT91_MC_SMC_DBW_16 (1 << 13)
60#define AT91_MC_SMC_DBW_8 (2 << 13)
61#define AT91_MC_SMC_DPR BIT(15)
62#define AT91_MC_SMC_ACSS GENMASK(17, 16)
63#define AT91_MC_SMC_ACSS_(x) ((x) << 16)
64#define AT91_MC_SMC_ACSS_MAX 3
65#define AT91_MC_SMC_RWSETUP GENMASK(26, 24)
66#define AT91_MC_SMC_RWSETUP_(x) ((x) << 24)
67#define AT91_MC_SMC_RWHOLD GENMASK(30, 28)
68#define AT91_MC_SMC_RWHOLD_(x) ((x) << 28)
69#define AT91_MC_SMC_RWHOLDSETUP_MAX 7
70
71/* SDRAM Controller registers */
72#define AT91_MC_SDRAMC_MR 0x90
73#define AT91_MC_SDRAMC_MODE GENMASK(3, 0)
74#define AT91_MC_SDRAMC_MODE_NORMAL (0 << 0)
75#define AT91_MC_SDRAMC_MODE_NOP (1 << 0)
76#define AT91_MC_SDRAMC_MODE_PRECHARGE (2 << 0)
77#define AT91_MC_SDRAMC_MODE_LMR (3 << 0)
78#define AT91_MC_SDRAMC_MODE_REFRESH (4 << 0)
79#define AT91_MC_SDRAMC_DBW_16 BIT(4)
80
81#define AT91_MC_SDRAMC_TR 0x94
82#define AT91_MC_SDRAMC_COUNT GENMASK(11, 0)
83
84#define AT91_MC_SDRAMC_CR 0x98
85#define AT91_MC_SDRAMC_NC GENMASK(1, 0)
86#define AT91_MC_SDRAMC_NC_8 (0 << 0)
87#define AT91_MC_SDRAMC_NC_9 (1 << 0)
88#define AT91_MC_SDRAMC_NC_10 (2 << 0)
89#define AT91_MC_SDRAMC_NC_11 (3 << 0)
90#define AT91_MC_SDRAMC_NR GENMASK(3, 2)
91#define AT91_MC_SDRAMC_NR_11 (0 << 2)
92#define AT91_MC_SDRAMC_NR_12 (1 << 2)
93#define AT91_MC_SDRAMC_NR_13 (2 << 2)
94#define AT91_MC_SDRAMC_NB BIT(4)
95#define AT91_MC_SDRAMC_NB_2 (0 << 4)
96#define AT91_MC_SDRAMC_NB_4 (1 << 4)
97#define AT91_MC_SDRAMC_CAS GENMASK(6, 5)
98#define AT91_MC_SDRAMC_CAS_2 (2 << 5)
99#define AT91_MC_SDRAMC_TWR GENMASK(10, 7)
100#define AT91_MC_SDRAMC_TRC GENMASK(14, 11)
101#define AT91_MC_SDRAMC_TRP GENMASK(18, 15)
102#define AT91_MC_SDRAMC_TRCD GENMASK(22, 19)
103#define AT91_MC_SDRAMC_TRAS GENMASK(26, 23)
104#define AT91_MC_SDRAMC_TXSR GENMASK(30, 27)
105
106#define AT91_MC_SDRAMC_SRR 0x9c
107#define AT91_MC_SDRAMC_SRCB BIT(0)
108
109#define AT91_MC_SDRAMC_LPR 0xa0
110#define AT91_MC_SDRAMC_LPCB BIT(0)
111
112#define AT91_MC_SDRAMC_IER 0xa4
113#define AT91_MC_SDRAMC_IDR 0xa8
114#define AT91_MC_SDRAMC_IMR 0xac
115#define AT91_MC_SDRAMC_ISR 0xb0
116#define AT91_MC_SDRAMC_RES BIT(0)
117
118/* Burst Flash Controller register */
119#define AT91_MC_BFC_MR 0xc0
120#define AT91_MC_BFC_BFCOM GENMASK(1, 0)
121#define AT91_MC_BFC_BFCOM_DISABLED (0 << 0)
122#define AT91_MC_BFC_BFCOM_ASYNC (1 << 0)
123#define AT91_MC_BFC_BFCOM_BURST (2 << 0)
124#define AT91_MC_BFC_BFCC GENMASK(3, 2)
125#define AT91_MC_BFC_BFCC_MCK (1 << 2)
126#define AT91_MC_BFC_BFCC_DIV2 (2 << 2)
127#define AT91_MC_BFC_BFCC_DIV4 (3 << 2)
128#define AT91_MC_BFC_AVL GENMASK(7, 4)
129#define AT91_MC_BFC_PAGES GENMASK(10, 8)
130#define AT91_MC_BFC_PAGES_NO_PAGE (0 << 8)
131#define AT91_MC_BFC_PAGES_16 (1 << 8)
132#define AT91_MC_BFC_PAGES_32 (2 << 8)
133#define AT91_MC_BFC_PAGES_64 (3 << 8)
134#define AT91_MC_BFC_PAGES_128 (4 << 8)
135#define AT91_MC_BFC_PAGES_256 (5 << 8)
136#define AT91_MC_BFC_PAGES_512 (6 << 8)
137#define AT91_MC_BFC_PAGES_1024 (7 << 8)
138#define AT91_MC_BFC_OEL GENMASK(13, 12)
139#define AT91_MC_BFC_BAAEN BIT(16)
140#define AT91_MC_BFC_BFOEH BIT(17)
141#define AT91_MC_BFC_MUXEN BIT(18)
142#define AT91_MC_BFC_RDYEN BIT(19)
143
144#endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */
diff --git a/include/soc/at91/at91rm9200_sdramc.h b/include/soc/at91/at91rm9200_sdramc.h
deleted file mode 100644
index aa047f458f1b..000000000000
--- a/include/soc/at91/at91rm9200_sdramc.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Memory Controllers (SDRAMC only) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_SDRAMC_H
17#define AT91RM9200_SDRAMC_H
18
19/* SDRAM Controller registers */
20#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
21#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
22#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
23#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
24#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
25#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
26#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
27#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
28#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
29#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
30
31#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
32#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
33
34#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
35#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
36#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
37#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
38#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
39#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
40#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
41#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
42#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
43#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
44#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
45#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
46#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
47#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
48#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
49#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
50#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
51#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
52#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
53#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
54#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
55
56#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
57#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
58#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
59#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
60#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
61#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
62
63#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 06:41:03 -0400