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authorLinus Torvalds <torvalds@linux-foundation.org>2015-09-01 16:29:48 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-09-01 16:29:48 -0400
commit8d01b66b4f23a9fcf5c6787b27f0be5f8cbae98c (patch)
tree877f5bf0006a8ea3e7cc01a6fbde8f8fed33340b
parent2faf962d90ca4c5ee7ba026b7351b1f74500bcdf (diff)
parent341a670abd1c086d44e09901f0ebee3dd86a60ba (diff)
Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC 64-bit changes from Olof Johansson: "Here's our branch of ARM64 contents for this merge window. Most of this is DT contents for new SoCs (or those who have seen new device support added). Maybe we should stop separating out the arm64 contents here to avoid the kind of internal conflicts as we got this time around, where 32- and 64-bit contents conflicted. Anyhow, on the actual contents: New SoCs: - Broadcom North Star 2 (ns2) - Marvell Berlin4CT - Mediatek MT6795 - Rockchip RK3368 In addition, there are enhancements for the following platforms: - Mediatek MT8173: cpuidle-dt updates, misc other additions - ZyncMP: A bunch of devices added to the existing DTSI - Qualcomm MSM8916 and APQ8016 updates for USB, etc. + a handful of other updates for various platforms" * tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (47 commits) ARM64: dts: vexpress: Use assigned-clock-parents for sp810 ARM64: dts: mt6795: enable basic SMP bringup for MT6795 arm64: Enable Marvell Berlin SoC family in defconfig arm64: Enable Marvell Berlin SoC family in Kconfig arm64: dts: Add dts files for Marvell Berlin4CT SoC ARM64: zynqmp: Move SPI nodes to the right location ARM64: zynqmp: Move uart and ttcs to the right location ARM64: zynqmp: Enable spi flashes on ep108 ARM64: zynqmp: Add eeprom memories on i2c bus ARM64: zynqmp: Enable sdhci on ep108 ARM64: zynqmp: Enable watchdog on ep108 ARM64: zynqmp: Add DWC3 usb support ARM64: zynqmp: Add SMMU support ARM64: zynqmp: Add CANs node for platform ARM64: zynqmp: Use zynqmp specific compatible string for gpio devicetree: xilinx: zynqmp: add sata node PCI: iproc: Fix BCMA dependency in Kconfig arm64: dts: Add Broadcom North Star 2 support arm64: Add Broadcom iProc family support PCI: iproc: Fix ARM64 dependency in Kconfig ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/bcm/ns2.txt9
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek.txt9
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt3
-rw-r--r--Documentation/devicetree/bindings/serial/mtk-uart.txt5
-rw-r--r--arch/arm64/Kconfig105
-rw-r--r--arch/arm64/Kconfig.platforms125
-rw-r--r--arch/arm64/boot/dts/Makefile3
-rw-r--r--arch/arm64/boot/dts/arm/juno-motherboard.dtsi2
-rw-r--r--arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi2
-rw-r--r--arch/arm64/boot/dts/broadcom/Makefile5
-rw-r--r--arch/arm64/boot/dts/broadcom/ns2-svk.dts59
-rw-r--r--arch/arm64/boot/dts/broadcom/ns2.dtsi118
-rw-r--r--arch/arm64/boot/dts/marvell/Makefile5
-rw-r--r--arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts66
-rw-r--r--arch/arm64/boot/dts/marvell/berlin4ct.dtsi164
-rw-r--r--arch/arm64/boot/dts/mediatek/Makefile1
-rw-r--r--arch/arm64/boot/dts/mediatek/mt6795-evb.dts41
-rw-r--r--arch/arm64/boot/dts/mediatek/mt6795.dtsi175
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8173-evb.dts353
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8173.dtsi327
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi34
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi14
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi51
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-pins.dtsi430
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi227
-rw-r--r--arch/arm64/boot/dts/rockchip/Makefile5
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368-r88.dts354
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368.dtsi900
-rw-r--r--arch/arm64/boot/dts/sprd/sc9836.dtsi99
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts89
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp.dtsi233
-rw-r--r--arch/arm64/configs/defconfig4
-rw-r--r--drivers/pci/host/Kconfig4
33 files changed, 3763 insertions, 258 deletions
diff --git a/Documentation/devicetree/bindings/arm/bcm/ns2.txt b/Documentation/devicetree/bindings/arm/bcm/ns2.txt
new file mode 100644
index 000000000000..35f056f4a1c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/ns2.txt
@@ -0,0 +1,9 @@
1Broadcom North Star 2 (NS2) device tree bindings
2------------------------------------------------
3
4Boards with NS2 shall have the following properties:
5
6Required root node property:
7
8NS2 SVK board
9compatible = "brcm,ns2-svk", "brcm,ns2";
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index 2daa424a13a4..618a91994a18 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -1,6 +1,7 @@
1MediaTek mt65xx & mt81xx Platforms Device Tree Bindings 1MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
2 2
3Boards with a MediaTek mt65xx/mt81xx SoC shall have the following property: 3Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
4following property:
4 5
5Required root node property: 6Required root node property:
6 7
@@ -8,6 +9,7 @@ compatible: Must contain one of
8 "mediatek,mt6580" 9 "mediatek,mt6580"
9 "mediatek,mt6589" 10 "mediatek,mt6589"
10 "mediatek,mt6592" 11 "mediatek,mt6592"
12 "mediatek,mt6795"
11 "mediatek,mt8127" 13 "mediatek,mt8127"
12 "mediatek,mt8135" 14 "mediatek,mt8135"
13 "mediatek,mt8173" 15 "mediatek,mt8173"
@@ -24,6 +26,9 @@ Supported boards:
24- Evaluation board for MT6592: 26- Evaluation board for MT6592:
25 Required root node properties: 27 Required root node properties:
26 - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; 28 - compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
29- Evaluation board for MT6795(Helio X10):
30 Required root node properties:
31 - compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
27- MTK mt8127 tablet moose EVB: 32- MTK mt8127 tablet moose EVB:
28 Required root node properties: 33 Required root node properties:
29 - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; 34 - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
index 3c9c3a7f3d25..afef6a85ac51 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
@@ -1,4 +1,4 @@
1Mediatek 65xx/81xx sysirq 1+Mediatek 65xx/67xx/81xx sysirq
2 2
3Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI 3Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
4interrupt. 4interrupt.
@@ -8,6 +8,7 @@ Required properties:
8 "mediatek,mt8173-sysirq" 8 "mediatek,mt8173-sysirq"
9 "mediatek,mt8135-sysirq" 9 "mediatek,mt8135-sysirq"
10 "mediatek,mt8127-sysirq" 10 "mediatek,mt8127-sysirq"
11 "mediatek,mt6795-sysirq"
11 "mediatek,mt6592-sysirq" 12 "mediatek,mt6592-sysirq"
12 "mediatek,mt6589-sysirq" 13 "mediatek,mt6589-sysirq"
13 "mediatek,mt6582-sysirq" 14 "mediatek,mt6582-sysirq"
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index a875997f2062..2d47add34765 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -5,11 +5,12 @@ Required properties:
5 * "mediatek,mt8135-uart" for MT8135 compatible UARTS 5 * "mediatek,mt8135-uart" for MT8135 compatible UARTS
6 * "mediatek,mt8127-uart" for MT8127 compatible UARTS 6 * "mediatek,mt8127-uart" for MT8127 compatible UARTS
7 * "mediatek,mt8173-uart" for MT8173 compatible UARTS 7 * "mediatek,mt8173-uart" for MT8173 compatible UARTS
8 * "mediatek,mt6795-uart" for MT6795 compatible UARTS
8 * "mediatek,mt6589-uart" for MT6589 compatible UARTS 9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
9 * "mediatek,mt6582-uart" for MT6582 compatible UARTS 10 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
10 * "mediatek,mt6580-uart" for MT6580 compatible UARTS 11 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
11 * "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6589, MT6582, 12 * "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6795,
12 MT6580, MT6577) 13 MT6589, MT6582, MT6580, MT6577)
13 14
14- reg: The base address of the UART register bank. 15- reg: The base address of the UART register bank.
15 16
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 318175f62c24..b7b9ceaa684a 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -160,110 +160,7 @@ source "init/Kconfig"
160 160
161source "kernel/Kconfig.freezer" 161source "kernel/Kconfig.freezer"
162 162
163menu "Platform selection" 163source "arch/arm64/Kconfig.platforms"
164
165config ARCH_EXYNOS
166 bool
167 help
168 This enables support for Samsung Exynos SoC family
169
170config ARCH_EXYNOS7
171 bool "ARMv8 based Samsung Exynos7"
172 select ARCH_EXYNOS
173 select COMMON_CLK_SAMSUNG
174 select HAVE_S3C2410_WATCHDOG if WATCHDOG
175 select HAVE_S3C_RTC if RTC_CLASS
176 select PINCTRL
177 select PINCTRL_EXYNOS
178
179 help
180 This enables support for Samsung Exynos7 SoC family
181
182config ARCH_FSL_LS2085A
183 bool "Freescale LS2085A SOC"
184 help
185 This enables support for Freescale LS2085A SOC.
186
187config ARCH_HISI
188 bool "Hisilicon SoC Family"
189 help
190 This enables support for Hisilicon ARMv8 SoC family
191
192config ARCH_MEDIATEK
193 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
194 select ARM_GIC
195 select PINCTRL
196 help
197 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
198
199config ARCH_QCOM
200 bool "Qualcomm Platforms"
201 select PINCTRL
202 help
203 This enables support for the ARMv8 based Qualcomm chipsets.
204
205config ARCH_SEATTLE
206 bool "AMD Seattle SoC Family"
207 help
208 This enables support for AMD Seattle SOC Family
209
210config ARCH_TEGRA
211 bool "NVIDIA Tegra SoC Family"
212 select ARCH_HAS_RESET_CONTROLLER
213 select ARCH_REQUIRE_GPIOLIB
214 select CLKDEV_LOOKUP
215 select CLKSRC_MMIO
216 select CLKSRC_OF
217 select GENERIC_CLOCKEVENTS
218 select HAVE_CLK
219 select PINCTRL
220 select RESET_CONTROLLER
221 help
222 This enables support for the NVIDIA Tegra SoC family.
223
224config ARCH_TEGRA_132_SOC
225 bool "NVIDIA Tegra132 SoC"
226 depends on ARCH_TEGRA
227 select PINCTRL_TEGRA124
228 select USB_ULPI if USB_PHY
229 select USB_ULPI_VIEWPORT if USB_PHY
230 help
231 Enable support for NVIDIA Tegra132 SoC, based on the Denver
232 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
233 but contains an NVIDIA Denver CPU complex in place of
234 Tegra124's "4+1" Cortex-A15 CPU complex.
235
236config ARCH_SPRD
237 bool "Spreadtrum SoC platform"
238 help
239 Support for Spreadtrum ARM based SoCs
240
241config ARCH_THUNDER
242 bool "Cavium Inc. Thunder SoC Family"
243 help
244 This enables support for Cavium's Thunder Family of SoCs.
245
246config ARCH_VEXPRESS
247 bool "ARMv8 software model (Versatile Express)"
248 select ARCH_REQUIRE_GPIOLIB
249 select COMMON_CLK_VERSATILE
250 select POWER_RESET_VEXPRESS
251 select VEXPRESS_CONFIG
252 help
253 This enables support for the ARMv8 software model (Versatile
254 Express).
255
256config ARCH_XGENE
257 bool "AppliedMicro X-Gene SOC Family"
258 help
259 This enables support for AppliedMicro X-Gene SOC Family
260
261config ARCH_ZYNQMP
262 bool "Xilinx ZynqMP Family"
263 help
264 This enables support for Xilinx ZynqMP Family
265
266endmenu
267 164
268menu "Bus support" 165menu "Bus support"
269 166
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
new file mode 100644
index 000000000000..23800a19a7bc
--- /dev/null
+++ b/arch/arm64/Kconfig.platforms
@@ -0,0 +1,125 @@
1menu "Platform selection"
2
3config ARCH_BCM_IPROC
4 bool "Broadcom iProc SoC Family"
5 help
6 This enables support for Broadcom iProc based SoCs
7
8config ARCH_BERLIN
9 bool "Marvell Berlin SoC Family"
10 select DW_APB_ICTL
11 help
12 This enables support for Marvell Berlin SoC Family
13
14config ARCH_EXYNOS
15 bool
16 help
17 This enables support for Samsung Exynos SoC family
18
19config ARCH_EXYNOS7
20 bool "ARMv8 based Samsung Exynos7"
21 select ARCH_EXYNOS
22 select COMMON_CLK_SAMSUNG
23 select HAVE_S3C2410_WATCHDOG if WATCHDOG
24 select HAVE_S3C_RTC if RTC_CLASS
25 select PINCTRL
26 select PINCTRL_EXYNOS
27
28 help
29 This enables support for Samsung Exynos7 SoC family
30
31config ARCH_FSL_LS2085A
32 bool "Freescale LS2085A SOC"
33 help
34 This enables support for Freescale LS2085A SOC.
35
36config ARCH_HISI
37 bool "Hisilicon SoC Family"
38 help
39 This enables support for Hisilicon ARMv8 SoC family
40
41config ARCH_MEDIATEK
42 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
43 select ARM_GIC
44 select PINCTRL
45 help
46 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
47
48config ARCH_QCOM
49 bool "Qualcomm Platforms"
50 select PINCTRL
51 help
52 This enables support for the ARMv8 based Qualcomm chipsets.
53
54config ARCH_ROCKCHIP
55 bool "Rockchip Platforms"
56 select ARCH_HAS_RESET_CONTROLLER
57 select ARCH_REQUIRE_GPIOLIB
58 select PINCTRL
59 select PINCTRL_ROCKCHIP
60 help
61 This enables support for the ARMv8 based Rockchip chipsets,
62 like the RK3368.
63
64config ARCH_SEATTLE
65 bool "AMD Seattle SoC Family"
66 help
67 This enables support for AMD Seattle SOC Family
68
69config ARCH_TEGRA
70 bool "NVIDIA Tegra SoC Family"
71 select ARCH_HAS_RESET_CONTROLLER
72 select ARCH_REQUIRE_GPIOLIB
73 select CLKDEV_LOOKUP
74 select CLKSRC_MMIO
75 select CLKSRC_OF
76 select GENERIC_CLOCKEVENTS
77 select HAVE_CLK
78 select PINCTRL
79 select RESET_CONTROLLER
80 help
81 This enables support for the NVIDIA Tegra SoC family.
82
83config ARCH_TEGRA_132_SOC
84 bool "NVIDIA Tegra132 SoC"
85 depends on ARCH_TEGRA
86 select PINCTRL_TEGRA124
87 select USB_ULPI if USB_PHY
88 select USB_ULPI_VIEWPORT if USB_PHY
89 help
90 Enable support for NVIDIA Tegra132 SoC, based on the Denver
91 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
92 but contains an NVIDIA Denver CPU complex in place of
93 Tegra124's "4+1" Cortex-A15 CPU complex.
94
95config ARCH_SPRD
96 bool "Spreadtrum SoC platform"
97 help
98 Support for Spreadtrum ARM based SoCs
99
100config ARCH_THUNDER
101 bool "Cavium Inc. Thunder SoC Family"
102 help
103 This enables support for Cavium's Thunder Family of SoCs.
104
105config ARCH_VEXPRESS
106 bool "ARMv8 software model (Versatile Express)"
107 select ARCH_REQUIRE_GPIOLIB
108 select COMMON_CLK_VERSATILE
109 select POWER_RESET_VEXPRESS
110 select VEXPRESS_CONFIG
111 help
112 This enables support for the ARMv8 software model (Versatile
113 Express).
114
115config ARCH_XGENE
116 bool "AppliedMicro X-Gene SOC Family"
117 help
118 This enables support for AppliedMicro X-Gene SOC Family
119
120config ARCH_ZYNQMP
121 bool "Xilinx ZynqMP Family"
122 help
123 This enables support for Xilinx ZynqMP Family
124
125endmenu
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 38913be23695..d9f88330e7b0 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,12 +1,15 @@
1dts-dirs += amd 1dts-dirs += amd
2dts-dirs += apm 2dts-dirs += apm
3dts-dirs += arm 3dts-dirs += arm
4dts-dirs += broadcom
4dts-dirs += cavium 5dts-dirs += cavium
5dts-dirs += exynos 6dts-dirs += exynos
6dts-dirs += freescale 7dts-dirs += freescale
7dts-dirs += hisilicon 8dts-dirs += hisilicon
9dts-dirs += marvell
8dts-dirs += mediatek 10dts-dirs += mediatek
9dts-dirs += qcom 11dts-dirs += qcom
12dts-dirs += rockchip
10dts-dirs += sprd 13dts-dirs += sprd
11dts-dirs += xilinx 14dts-dirs += xilinx
12 15
diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
index 021e0f40f419..637e046f0e36 100644
--- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
@@ -136,6 +136,8 @@
136 clock-names = "refclk", "timclk", "apb_pclk"; 136 clock-names = "refclk", "timclk", "apb_pclk";
137 #clock-cells = <1>; 137 #clock-cells = <1>;
138 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; 138 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
139 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
140 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
139 }; 141 };
140 142
141 apbregs@010000 { 143 apbregs@010000 {
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
index c46cbb29f3c6..88a7583ed7a7 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
@@ -74,6 +74,8 @@
74 clock-names = "refclk", "timclk", "apb_pclk"; 74 clock-names = "refclk", "timclk", "apb_pclk";
75 #clock-cells = <1>; 75 #clock-cells = <1>;
76 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; 76 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
77 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
78 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
77 }; 79 };
78 80
79 aaci@040000 { 81 aaci@040000 {
diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
new file mode 100644
index 000000000000..e21fe66f1837
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
new file mode 100644
index 000000000000..244baf879dc9
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -0,0 +1,59 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/dts-v1/;
34
35#include "ns2.dtsi"
36
37/ {
38 model = "Broadcom NS2 SVK";
39 compatible = "brcm,ns2-svk", "brcm,ns2";
40
41 aliases {
42 serial0 = &uart3;
43 };
44
45 chosen {
46 stdout-path = "serial0:115200n8";
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
52 };
53
54 soc: soc {
55 uart3: serial@66130000 {
56 status = "ok";
57 };
58 };
59};
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
new file mode 100644
index 000000000000..3c92d92278e5
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -0,0 +1,118 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <dt-bindings/interrupt-controller/arm-gic.h>
34
35/memreserve/ 0x84b00000 0x00000008;
36
37/ {
38 compatible = "brcm,ns2";
39 interrupt-parent = <&gic>;
40 #address-cells = <2>;
41 #size-cells = <2>;
42
43 cpus {
44 #address-cells = <2>;
45 #size-cells = <0>;
46
47 cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a57", "arm,armv8";
50 reg = <0 0>;
51 enable-method = "spin-table";
52 cpu-release-addr = <0 0x84b00000>;
53 };
54
55 cpu@1 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a57", "arm,armv8";
58 reg = <0 1>;
59 enable-method = "spin-table";
60 cpu-release-addr = <0 0x84b00000>;
61 };
62
63 cpu@2 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a57", "arm,armv8";
66 reg = <0 2>;
67 enable-method = "spin-table";
68 cpu-release-addr = <0 0x84b00000>;
69 };
70
71 cpu@3 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a57", "arm,armv8";
74 reg = <0 3>;
75 enable-method = "spin-table";
76 cpu-release-addr = <0 0x84b00000>;
77 };
78 };
79
80 timer {
81 compatible = "arm,armv8-timer";
82 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
83 IRQ_TYPE_EDGE_RISING)>,
84 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
85 IRQ_TYPE_EDGE_RISING)>,
86 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
87 IRQ_TYPE_EDGE_RISING)>,
88 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
89 IRQ_TYPE_EDGE_RISING)>;
90 };
91
92 soc: soc {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges = <0 0 0 0xffffffff>;
97
98 gic: interrupt-controller@65210000 {
99 compatible = "arm,gic-400";
100 #interrupt-cells = <3>;
101 interrupt-controller;
102 reg = <0x65210000 0x1000>,
103 <0x65220000 0x1000>,
104 <0x65240000 0x2000>,
105 <0x65260000 0x1000>;
106 };
107
108 uart3: serial@66130000 {
109 compatible = "snps,dw-apb-uart";
110 reg = <0x66130000 0x100>;
111 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
112 reg-shift = <2>;
113 reg-io-width = <4>;
114 clock-frequency = <23961600>;
115 status = "disabled";
116 };
117 };
118};
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
new file mode 100644
index 000000000000..e2f6afa7f849
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts
new file mode 100644
index 000000000000..0d70d39fa8d2
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts
@@ -0,0 +1,66 @@
1/*
2 * Copyright (C) 2015 Marvell Technology Group Ltd.
3 *
4 * Author: Jisheng Zhang <jszhang@marvell.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPLv2 or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45/dts-v1/;
46
47#include "berlin4ct.dtsi"
48
49/ {
50 model = "Marvell BG4CT DMP board";
51 compatible = "marvell,berlin4ct-dmp", "marvell,berlin4ct", "marvell,berlin";
52
53 chosen {
54 stdout-path = "serial0:115200n8";
55 };
56
57 memory {
58 device_type = "memory";
59 /* the first 16MB is for firmwares' usage */
60 reg = <0 0x01000000 0 0x7f000000>;
61 };
62};
63
64&uart0 {
65 status = "okay";
66};
diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
new file mode 100644
index 000000000000..dd4a10d605d9
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi
@@ -0,0 +1,164 @@
1/*
2 * Copyright (C) 2015 Marvell Technology Group Ltd.
3 *
4 * Author: Jisheng Zhang <jszhang@marvell.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPLv2 or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46
47/ {
48 compatible = "marvell,berlin4ct", "marvell,berlin";
49 interrupt-parent = <&gic>;
50 #address-cells = <2>;
51 #size-cells = <2>;
52
53 aliases {
54 serial0 = &uart0;
55 };
56
57 psci {
58 compatible = "arm,psci-0.2";
59 method = "smc";
60 };
61
62 cpus {
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 cpu0: cpu@0 {
67 compatible = "arm,cortex-a53", "arm,armv8";
68 device_type = "cpu";
69 reg = <0x0>;
70 enable-method = "psci";
71 };
72
73 cpu1: cpu@1 {
74 compatible = "arm,cortex-a53", "arm,armv8";
75 device_type = "cpu";
76 reg = <0x1>;
77 enable-method = "psci";
78 };
79
80 cpu2: cpu@2 {
81 compatible = "arm,cortex-a53", "arm,armv8";
82 device_type = "cpu";
83 reg = <0x2>;
84 enable-method = "psci";
85 };
86
87 cpu3: cpu@3 {
88 compatible = "arm,cortex-a53", "arm,armv8";
89 device_type = "cpu";
90 reg = <0x3>;
91 enable-method = "psci";
92 };
93 };
94
95 osc: osc {
96 compatible = "fixed-clock";
97 #clock-cells = <0>;
98 clock-frequency = <25000000>;
99 };
100
101 pmu {
102 compatible = "arm,armv8-pmuv3";
103 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-affinity = <&cpu0>,
108 <&cpu1>,
109 <&cpu2>,
110 <&cpu3>;
111 };
112
113 timer {
114 compatible = "arm,armv8-timer";
115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
119 };
120
121 soc {
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0 0xf7000000 0x1000000>;
126
127 gic: interrupt-controller@901000 {
128 compatible = "arm,gic-400";
129 #interrupt-cells = <3>;
130 interrupt-controller;
131 reg = <0x901000 0x1000>,
132 <0x902000 0x2000>,
133 <0x904000 0x2000>,
134 <0x906000 0x2000>;
135 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
136 };
137
138 apb@fc0000 {
139 compatible = "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0 0xfc0000 0x10000>;
143 interrupt-parent = <&sic>;
144
145 sic: interrupt-controller@1000 {
146 compatible = "snps,dw-apb-ictl";
147 reg = <0x1000 0x30>;
148 interrupt-controller;
149 #interrupt-cells = <1>;
150 interrupt-parent = <&gic>;
151 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
152 };
153
154 uart0: uart@d000 {
155 compatible = "snps,dw-apb-uart";
156 reg = <0xd000 0x100>;
157 interrupts = <8>;
158 clocks = <&osc>;
159 reg-shift = <2>;
160 status = "disabled";
161 };
162 };
163 };
164};
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 3ce24622b231..e0a4bff2fc17 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
1dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
1dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb 2dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
2 3
3always := $(dtb-y) 4always := $(dtb-y)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
new file mode 100644
index 000000000000..ad665f5835f0
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
@@ -0,0 +1,41 @@
1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Mars.C <mars.cheng@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15/dts-v1/;
16#include "mt6795.dtsi"
17
18/ {
19 model = "MediaTek MT6795 Evaluation Board";
20 compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
21
22 aliases {
23 serial0 = &uart0;
24 serial1 = &uart1;
25 serial2 = &uart2;
26 serial3 = &uart3;
27 };
28
29 memory@40000000 {
30 device_type = "memory";
31 reg = <0 0x40000000 0 0x1e800000>;
32 };
33
34 chosen {
35 stdout-path = "serial0:921600n8";
36 };
37};
38
39&uart0 {
40 status = "okay";
41};
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
new file mode 100644
index 000000000000..c85659d0ff5d
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -0,0 +1,175 @@
1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Mars.C <mars.cheng@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16
17/ {
18 compatible = "mediatek,mt6795";
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 psci {
24 compatible = "arm,psci-0.2";
25 method = "smc";
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu0: cpu@0 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a53";
35 enable-method = "psci";
36 reg = <0x000>;
37 };
38
39 cpu1: cpu@1 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a53";
42 enable-method = "psci";
43 reg = <0x001>;
44 };
45
46 cpu2: cpu@2 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 reg = <0x002>;
51 };
52
53 cpu3: cpu@3 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a53";
56 enable-method = "psci";
57 reg = <0x003>;
58 };
59
60 cpu4: cpu@100 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a53";
63 enable-method = "psci";
64 reg = <0x100>;
65 };
66
67 cpu5: cpu@101 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a53";
70 enable-method = "psci";
71 reg = <0x101>;
72 };
73
74 cpu6: cpu@102 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 enable-method = "psci";
78 reg = <0x102>;
79 };
80
81 cpu7: cpu@103 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a53";
84 enable-method = "psci";
85 reg = <0x103>;
86 };
87 };
88
89 system_clk: dummy13m {
90 compatible = "fixed-clock";
91 clock-frequency = <13000000>;
92 #clock-cells = <0>;
93 };
94
95 rtc_clk: dummy32k {
96 compatible = "fixed-clock";
97 clock-frequency = <32000>;
98 #clock-cells = <0>;
99 };
100
101 uart_clk: dummy26m {
102 compatible = "fixed-clock";
103 clock-frequency = <26000000>;
104 #clock-cells = <0>;
105 };
106
107 timer {
108 compatible = "arm,armv8-timer";
109 interrupt-parent = <&gic>;
110 interrupts = <GIC_PPI 13
111 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 14
113 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
114 <GIC_PPI 11
115 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 10
117 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
118 };
119
120 sysirq: intpol-controller@10200620 {
121 compatible = "mediatek,mt6795-sysirq",
122 "mediatek,mt6577-sysirq";
123 interrupt-controller;
124 #interrupt-cells = <3>;
125 interrupt-parent = <&gic>;
126 reg = <0 0x10200620 0 0x20>;
127 };
128
129 gic: interrupt-controller@10221000 {
130 compatible = "arm,gic-400";
131 #interrupt-cells = <3>;
132 interrupt-parent = <&gic>;
133 interrupt-controller;
134 reg = <0 0x10221000 0 0x1000>,
135 <0 0x10222000 0 0x2000>,
136 <0 0x10224000 0 0x2000>,
137 <0 0x10226000 0 0x2000>;
138 };
139
140 uart0: serial@11002000 {
141 compatible = "mediatek,mt6795-uart",
142 "mediatek,mt6577-uart";
143 reg = <0 0x11002000 0 0x400>;
144 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
145 clocks = <&uart_clk>;
146 status = "disabled";
147 };
148
149 uart1: serial@11003000 {
150 compatible = "mediatek,mt6795-uart",
151 "mediatek,mt6577-uart";
152 reg = <0 0x11003000 0 0x400>;
153 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
154 clocks = <&uart_clk>;
155 status = "disabled";
156 };
157
158 uart2: serial@11004000 {
159 compatible = "mediatek,mt6795-uart",
160 "mediatek,mt6577-uart";
161 reg = <0 0x11004000 0 0x400>;
162 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
163 clocks = <&uart_clk>;
164 status = "disabled";
165 };
166
167 uart3: serial@11005000 {
168 compatible = "mediatek,mt6795-uart",
169 "mediatek,mt6577-uart";
170 reg = <0 0x11005000 0 0x400>;
171 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
172 clocks = <&uart_clk>;
173 status = "disabled";
174 };
175};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index d0ab012fa379..4be66cadbc7c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -34,6 +34,359 @@
34 chosen { }; 34 chosen { };
35}; 35};
36 36
37&i2c1 {
38 status = "okay";
39
40 buck: da9211@68 {
41 compatible = "dlg,da9211";
42 reg = <0x68>;
43
44 regulators {
45 da9211_vcpu_reg: BUCKA {
46 regulator-name = "VBUCKA";
47 regulator-min-microvolt = < 700000>;
48 regulator-max-microvolt = <1310000>;
49 regulator-min-microamp = <2000000>;
50 regulator-max-microamp = <4400000>;
51 regulator-ramp-delay = <10000>;
52 regulator-always-on;
53 };
54
55 da9211_vgpu_reg: BUCKB {
56 regulator-name = "VBUCKB";
57 regulator-min-microvolt = < 700000>;
58 regulator-max-microvolt = <1310000>;
59 regulator-min-microamp = <2000000>;
60 regulator-max-microamp = <3000000>;
61 regulator-ramp-delay = <10000>;
62 };
63 };
64 };
65};
66
67&mmc0 {
68 status = "okay";
69 pinctrl-names = "default", "state_uhs";
70 pinctrl-0 = <&mmc0_pins_default>;
71 pinctrl-1 = <&mmc0_pins_uhs>;
72 bus-width = <8>;
73 max-frequency = <50000000>;
74 cap-mmc-highspeed;
75 vmmc-supply = <&mt6397_vemc_3v3_reg>;
76 vqmmc-supply = <&mt6397_vio18_reg>;
77 non-removable;
78};
79
80&mmc1 {
81 status = "okay";
82 pinctrl-names = "default", "state_uhs";
83 pinctrl-0 = <&mmc1_pins_default>;
84 pinctrl-1 = <&mmc1_pins_uhs>;
85 bus-width = <4>;
86 max-frequency = <50000000>;
87 cap-sd-highspeed;
88 sd-uhs-sdr25;
89 cd-gpios = <&pio 132 0>;
90 vmmc-supply = <&mt6397_vmch_reg>;
91 vqmmc-supply = <&mt6397_vmc_reg>;
92};
93
94&pio {
95 mmc0_pins_default: mmc0default {
96 pins_cmd_dat {
97 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
98 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
99 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
100 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
101 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
102 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
103 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
104 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
105 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
106 input-enable;
107 bias-pull-up;
108 };
109
110 pins_clk {
111 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
112 bias-pull-down;
113 };
114
115 pins_rst {
116 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
117 bias-pull-up;
118 };
119 };
120
121 mmc1_pins_default: mmc1default {
122 pins_cmd_dat {
123 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
124 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
125 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
126 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
127 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
128 input-enable;
129 drive-strength = <MTK_DRIVE_4mA>;
130 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
131 };
132
133 pins_clk {
134 pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
135 bias-pull-down;
136 drive-strength = <MTK_DRIVE_4mA>;
137 };
138
139 pins_insert {
140 pinmux = <MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132>;
141 bias-pull-up;
142 };
143 };
144
145 mmc0_pins_uhs: mmc0 {
146 pins_cmd_dat {
147 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
148 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
149 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
150 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
151 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
152 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
153 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
154 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
155 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
156 input-enable;
157 drive-strength = <MTK_DRIVE_2mA>;
158 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
159 };
160
161 pins_clk {
162 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
163 drive-strength = <MTK_DRIVE_2mA>;
164 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
165 };
166
167 pins_rst {
168 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
169 bias-pull-up;
170 };
171 };
172
173 mmc1_pins_uhs: mmc1 {
174 pins_cmd_dat {
175 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
176 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
177 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
178 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
179 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
180 input-enable;
181 drive-strength = <MTK_DRIVE_4mA>;
182 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
183 };
184
185 pins_clk {
186 pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
187 drive-strength = <MTK_DRIVE_4mA>;
188 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
189 };
190 };
191};
192
193&pwrap {
194 pmic: mt6397 {
195 compatible = "mediatek,mt6397";
196 interrupt-parent = <&pio>;
197 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
198 interrupt-controller;
199 #interrupt-cells = <2>;
200
201 mt6397regulator: mt6397regulator {
202 compatible = "mediatek,mt6397-regulator";
203
204 mt6397_vpca15_reg: buck_vpca15 {
205 regulator-compatible = "buck_vpca15";
206 regulator-name = "vpca15";
207 regulator-min-microvolt = < 700000>;
208 regulator-max-microvolt = <1350000>;
209 regulator-ramp-delay = <12500>;
210 regulator-always-on;
211 };
212
213 mt6397_vpca7_reg: buck_vpca7 {
214 regulator-compatible = "buck_vpca7";
215 regulator-name = "vpca7";
216 regulator-min-microvolt = < 700000>;
217 regulator-max-microvolt = <1350000>;
218 regulator-ramp-delay = <12500>;
219 regulator-enable-ramp-delay = <115>;
220 };
221
222 mt6397_vsramca15_reg: buck_vsramca15 {
223 regulator-compatible = "buck_vsramca15";
224 regulator-name = "vsramca15";
225 regulator-min-microvolt = < 700000>;
226 regulator-max-microvolt = <1350000>;
227 regulator-ramp-delay = <12500>;
228 regulator-always-on;
229 };
230
231 mt6397_vsramca7_reg: buck_vsramca7 {
232 regulator-compatible = "buck_vsramca7";
233 regulator-name = "vsramca7";
234 regulator-min-microvolt = < 700000>;
235 regulator-max-microvolt = <1350000>;
236 regulator-ramp-delay = <12500>;
237 regulator-always-on;
238 };
239
240 mt6397_vcore_reg: buck_vcore {
241 regulator-compatible = "buck_vcore";
242 regulator-name = "vcore";
243 regulator-min-microvolt = < 700000>;
244 regulator-max-microvolt = <1350000>;
245 regulator-ramp-delay = <12500>;
246 regulator-always-on;
247 };
248
249 mt6397_vgpu_reg: buck_vgpu {
250 regulator-compatible = "buck_vgpu";
251 regulator-name = "vgpu";
252 regulator-min-microvolt = < 700000>;
253 regulator-max-microvolt = <1350000>;
254 regulator-ramp-delay = <12500>;
255 regulator-enable-ramp-delay = <115>;
256 };
257
258 mt6397_vdrm_reg: buck_vdrm {
259 regulator-compatible = "buck_vdrm";
260 regulator-name = "vdrm";
261 regulator-min-microvolt = <1200000>;
262 regulator-max-microvolt = <1400000>;
263 regulator-ramp-delay = <12500>;
264 regulator-always-on;
265 };
266
267 mt6397_vio18_reg: buck_vio18 {
268 regulator-compatible = "buck_vio18";
269 regulator-name = "vio18";
270 regulator-min-microvolt = <1620000>;
271 regulator-max-microvolt = <1980000>;
272 regulator-ramp-delay = <12500>;
273 regulator-always-on;
274 };
275
276 mt6397_vtcxo_reg: ldo_vtcxo {
277 regulator-compatible = "ldo_vtcxo";
278 regulator-name = "vtcxo";
279 regulator-always-on;
280 };
281
282 mt6397_va28_reg: ldo_va28 {
283 regulator-compatible = "ldo_va28";
284 regulator-name = "va28";
285 regulator-always-on;
286 };
287
288 mt6397_vcama_reg: ldo_vcama {
289 regulator-compatible = "ldo_vcama";
290 regulator-name = "vcama";
291 regulator-min-microvolt = <1500000>;
292 regulator-max-microvolt = <2800000>;
293 regulator-enable-ramp-delay = <218>;
294 };
295
296 mt6397_vio28_reg: ldo_vio28 {
297 regulator-compatible = "ldo_vio28";
298 regulator-name = "vio28";
299 regulator-always-on;
300 };
301
302 mt6397_vusb_reg: ldo_vusb {
303 regulator-compatible = "ldo_vusb";
304 regulator-name = "vusb";
305 };
306
307 mt6397_vmc_reg: ldo_vmc {
308 regulator-compatible = "ldo_vmc";
309 regulator-name = "vmc";
310 regulator-min-microvolt = <1800000>;
311 regulator-max-microvolt = <3300000>;
312 regulator-enable-ramp-delay = <218>;
313 };
314
315 mt6397_vmch_reg: ldo_vmch {
316 regulator-compatible = "ldo_vmch";
317 regulator-name = "vmch";
318 regulator-min-microvolt = <3000000>;
319 regulator-max-microvolt = <3300000>;
320 regulator-enable-ramp-delay = <218>;
321 };
322
323 mt6397_vemc_3v3_reg: ldo_vemc3v3 {
324 regulator-compatible = "ldo_vemc3v3";
325 regulator-name = "vemc_3v3";
326 regulator-min-microvolt = <3000000>;
327 regulator-max-microvolt = <3300000>;
328 regulator-enable-ramp-delay = <218>;
329 };
330
331 mt6397_vgp1_reg: ldo_vgp1 {
332 regulator-compatible = "ldo_vgp1";
333 regulator-name = "vcamd";
334 regulator-min-microvolt = <1220000>;
335 regulator-max-microvolt = <3300000>;
336 regulator-enable-ramp-delay = <240>;
337 };
338
339 mt6397_vgp2_reg: ldo_vgp2 {
340 regulator-compatible = "ldo_vgp2";
341 regulator-name = "vcamio";
342 regulator-min-microvolt = <1000000>;
343 regulator-max-microvolt = <3300000>;
344 regulator-enable-ramp-delay = <218>;
345 };
346
347 mt6397_vgp3_reg: ldo_vgp3 {
348 regulator-compatible = "ldo_vgp3";
349 regulator-name = "vcamaf";
350 regulator-min-microvolt = <1200000>;
351 regulator-max-microvolt = <3300000>;
352 regulator-enable-ramp-delay = <218>;
353 };
354
355 mt6397_vgp4_reg: ldo_vgp4 {
356 regulator-compatible = "ldo_vgp4";
357 regulator-name = "vgp4";
358 regulator-min-microvolt = <1200000>;
359 regulator-max-microvolt = <3300000>;
360 regulator-enable-ramp-delay = <218>;
361 };
362
363 mt6397_vgp5_reg: ldo_vgp5 {
364 regulator-compatible = "ldo_vgp5";
365 regulator-name = "vgp5";
366 regulator-min-microvolt = <1200000>;
367 regulator-max-microvolt = <3000000>;
368 regulator-enable-ramp-delay = <218>;
369 };
370
371 mt6397_vgp6_reg: ldo_vgp6 {
372 regulator-compatible = "ldo_vgp6";
373 regulator-name = "vgp6";
374 regulator-min-microvolt = <1200000>;
375 regulator-max-microvolt = <3300000>;
376 regulator-enable-ramp-delay = <218>;
377 };
378
379 mt6397_vibr_reg: ldo_vibr {
380 regulator-compatible = "ldo_vibr";
381 regulator-name = "vibr";
382 regulator-min-microvolt = <1300000>;
383 regulator-max-microvolt = <3300000>;
384 regulator-enable-ramp-delay = <218>;
385 };
386 };
387 };
388};
389
37&uart0 { 390&uart0 {
38 status = "okay"; 391 status = "okay";
39}; 392};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 27237a1c1a87..d18ee4259ee5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -11,8 +11,11 @@
11 * GNU General Public License for more details. 11 * GNU General Public License for more details.
12 */ 12 */
13 13
14#include <dt-bindings/clock/mt8173-clk.h>
14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/power/mt8173-power.h>
18#include <dt-bindings/reset-controller/mt8173-resets.h>
16#include "mt8173-pinfunc.h" 19#include "mt8173-pinfunc.h"
17 20
18/ { 21/ {
@@ -49,6 +52,8 @@
49 device_type = "cpu"; 52 device_type = "cpu";
50 compatible = "arm,cortex-a53"; 53 compatible = "arm,cortex-a53";
51 reg = <0x000>; 54 reg = <0x000>;
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
52 }; 57 };
53 58
54 cpu1: cpu@1 { 59 cpu1: cpu@1 {
@@ -56,6 +61,7 @@
56 compatible = "arm,cortex-a53"; 61 compatible = "arm,cortex-a53";
57 reg = <0x001>; 62 reg = <0x001>;
58 enable-method = "psci"; 63 enable-method = "psci";
64 cpu-idle-states = <&CPU_SLEEP_0>;
59 }; 65 };
60 66
61 cpu2: cpu@100 { 67 cpu2: cpu@100 {
@@ -63,6 +69,7 @@
63 compatible = "arm,cortex-a57"; 69 compatible = "arm,cortex-a57";
64 reg = <0x100>; 70 reg = <0x100>;
65 enable-method = "psci"; 71 enable-method = "psci";
72 cpu-idle-states = <&CPU_SLEEP_0>;
66 }; 73 };
67 74
68 cpu3: cpu@101 { 75 cpu3: cpu@101 {
@@ -70,6 +77,20 @@
70 compatible = "arm,cortex-a57"; 77 compatible = "arm,cortex-a57";
71 reg = <0x101>; 78 reg = <0x101>;
72 enable-method = "psci"; 79 enable-method = "psci";
80 cpu-idle-states = <&CPU_SLEEP_0>;
81 };
82
83 idle-states {
84 entry-method = "arm,psci";
85
86 CPU_SLEEP_0: cpu-sleep-0 {
87 compatible = "arm,idle-state";
88 local-timer-stop;
89 entry-latency-us = <639>;
90 exit-latency-us = <680>;
91 min-residency-us = <1088>;
92 arm,psci-suspend-param = <0x0010000>;
93 };
73 }; 94 };
74 }; 95 };
75 96
@@ -81,10 +102,18 @@
81 cpu_on = <0x84000003>; 102 cpu_on = <0x84000003>;
82 }; 103 };
83 104
84 uart_clk: dummy26m { 105 clk26m: oscillator@0 {
85 compatible = "fixed-clock"; 106 compatible = "fixed-clock";
107 #clock-cells = <0>;
86 clock-frequency = <26000000>; 108 clock-frequency = <26000000>;
109 clock-output-names = "clk26m";
110 };
111
112 clk32k: oscillator@1 {
113 compatible = "fixed-clock";
87 #clock-cells = <0>; 114 #clock-cells = <0>;
115 clock-frequency = <32000>;
116 clock-output-names = "clk32k";
88 }; 117 };
89 118
90 timer { 119 timer {
@@ -106,11 +135,32 @@
106 compatible = "simple-bus"; 135 compatible = "simple-bus";
107 ranges; 136 ranges;
108 137
109 /* 138 topckgen: clock-controller@10000000 {
110 * Pinctrl access register at 0x10005000 through regmap. 139 compatible = "mediatek,mt8173-topckgen";
111 * Register 0x1000b000 is used by EINT. 140 reg = <0 0x10000000 0 0x1000>;
112 */ 141 #clock-cells = <1>;
113 pio: pinctrl@10005000 { 142 };
143
144 infracfg: power-controller@10001000 {
145 compatible = "mediatek,mt8173-infracfg", "syscon";
146 reg = <0 0x10001000 0 0x1000>;
147 #clock-cells = <1>;
148 #reset-cells = <1>;
149 };
150
151 pericfg: power-controller@10003000 {
152 compatible = "mediatek,mt8173-pericfg", "syscon";
153 reg = <0 0x10003000 0 0x1000>;
154 #clock-cells = <1>;
155 #reset-cells = <1>;
156 };
157
158 syscfg_pctl_a: syscfg_pctl_a@10005000 {
159 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
160 reg = <0 0x10005000 0 0x1000>;
161 };
162
163 pio: pinctrl@0x10005000 {
114 compatible = "mediatek,mt8173-pinctrl"; 164 compatible = "mediatek,mt8173-pinctrl";
115 reg = <0 0x1000b000 0 0x1000>; 165 reg = <0 0x1000b000 0 0x1000>;
116 mediatek,pctl-regmap = <&syscfg_pctl_a>; 166 mediatek,pctl-regmap = <&syscfg_pctl_a>;
@@ -122,11 +172,81 @@
122 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 172 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 174 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
175
176 i2c0_pins_a: i2c0 {
177 pins1 {
178 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
179 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
180 bias-disable;
181 };
182 };
183
184 i2c1_pins_a: i2c1 {
185 pins1 {
186 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
187 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
188 bias-disable;
189 };
190 };
191
192 i2c2_pins_a: i2c2 {
193 pins1 {
194 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
195 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
196 bias-disable;
197 };
198 };
199
200 i2c3_pins_a: i2c3 {
201 pins1 {
202 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
203 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
204 bias-disable;
205 };
206 };
207
208 i2c4_pins_a: i2c4 {
209 pins1 {
210 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
211 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
212 bias-disable;
213 };
214 };
215
216 i2c6_pins_a: i2c6 {
217 pins1 {
218 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
219 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
220 bias-disable;
221 };
222 };
125 }; 223 };
126 224
127 syscfg_pctl_a: syscfg_pctl_a@10005000 { 225 scpsys: scpsys@10006000 {
128 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 226 compatible = "mediatek,mt8173-scpsys";
129 reg = <0 0x10005000 0 0x1000>; 227 #power-domain-cells = <1>;
228 reg = <0 0x10006000 0 0x1000>;
229 clocks = <&clk26m>,
230 <&topckgen CLK_TOP_MM_SEL>;
231 clock-names = "mfg", "mm";
232 infracfg = <&infracfg>;
233 };
234
235 watchdog: watchdog@10007000 {
236 compatible = "mediatek,mt8173-wdt",
237 "mediatek,mt6589-wdt";
238 reg = <0 0x10007000 0 0x100>;
239 };
240
241 pwrap: pwrap@1000d000 {
242 compatible = "mediatek,mt8173-pwrap";
243 reg = <0 0x1000d000 0 0x1000>;
244 reg-names = "pwrap";
245 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
246 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
247 reset-names = "pwrap";
248 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
249 clock-names = "spi", "wrap";
130 }; 250 };
131 251
132 sysirq: intpol-controller@10200620 { 252 sysirq: intpol-controller@10200620 {
@@ -138,6 +258,12 @@
138 reg = <0 0x10200620 0 0x20>; 258 reg = <0 0x10200620 0 0x20>;
139 }; 259 };
140 260
261 apmixedsys: clock-controller@10209000 {
262 compatible = "mediatek,mt8173-apmixedsys";
263 reg = <0 0x10209000 0 0x1000>;
264 #clock-cells = <1>;
265 };
266
141 gic: interrupt-controller@10220000 { 267 gic: interrupt-controller@10220000 {
142 compatible = "arm,gic-400"; 268 compatible = "arm,gic-400";
143 #interrupt-cells = <3>; 269 #interrupt-cells = <3>;
@@ -156,7 +282,8 @@
156 "mediatek,mt6577-uart"; 282 "mediatek,mt6577-uart";
157 reg = <0 0x11002000 0 0x400>; 283 reg = <0 0x11002000 0 0x400>;
158 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 284 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
159 clocks = <&uart_clk>; 285 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
286 clock-names = "baud", "bus";
160 status = "disabled"; 287 status = "disabled";
161 }; 288 };
162 289
@@ -165,7 +292,8 @@
165 "mediatek,mt6577-uart"; 292 "mediatek,mt6577-uart";
166 reg = <0 0x11003000 0 0x400>; 293 reg = <0 0x11003000 0 0x400>;
167 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 294 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
168 clocks = <&uart_clk>; 295 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
296 clock-names = "baud", "bus";
169 status = "disabled"; 297 status = "disabled";
170 }; 298 };
171 299
@@ -174,7 +302,8 @@
174 "mediatek,mt6577-uart"; 302 "mediatek,mt6577-uart";
175 reg = <0 0x11004000 0 0x400>; 303 reg = <0 0x11004000 0 0x400>;
176 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 304 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
177 clocks = <&uart_clk>; 305 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
306 clock-names = "baud", "bus";
178 status = "disabled"; 307 status = "disabled";
179 }; 308 };
180 309
@@ -183,7 +312,179 @@
183 "mediatek,mt6577-uart"; 312 "mediatek,mt6577-uart";
184 reg = <0 0x11005000 0 0x400>; 313 reg = <0 0x11005000 0 0x400>;
185 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 314 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
186 clocks = <&uart_clk>; 315 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
316 clock-names = "baud", "bus";
317 status = "disabled";
318 };
319
320 i2c0: i2c@11007000 {
321 compatible = "mediatek,mt8173-i2c";
322 reg = <0 0x11007000 0 0x70>,
323 <0 0x11000100 0 0x80>;
324 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
325 clock-div = <16>;
326 clocks = <&pericfg CLK_PERI_I2C0>,
327 <&pericfg CLK_PERI_AP_DMA>;
328 clock-names = "main", "dma";
329 pinctrl-names = "default";
330 pinctrl-0 = <&i2c0_pins_a>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 status = "disabled";
334 };
335
336 i2c1: i2c@11008000 {
337 compatible = "mediatek,mt8173-i2c";
338 reg = <0 0x11008000 0 0x70>,
339 <0 0x11000180 0 0x80>;
340 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
341 clock-div = <16>;
342 clocks = <&pericfg CLK_PERI_I2C1>,
343 <&pericfg CLK_PERI_AP_DMA>;
344 clock-names = "main", "dma";
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c1_pins_a>;
347 #address-cells = <1>;
348 #size-cells = <0>;
349 status = "disabled";
350 };
351
352 i2c2: i2c@11009000 {
353 compatible = "mediatek,mt8173-i2c";
354 reg = <0 0x11009000 0 0x70>,
355 <0 0x11000200 0 0x80>;
356 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
357 clock-div = <16>;
358 clocks = <&pericfg CLK_PERI_I2C2>,
359 <&pericfg CLK_PERI_AP_DMA>;
360 clock-names = "main", "dma";
361 pinctrl-names = "default";
362 pinctrl-0 = <&i2c2_pins_a>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365 status = "disabled";
366 };
367
368 i2c3: i2c3@11010000 {
369 compatible = "mediatek,mt8173-i2c";
370 reg = <0 0x11010000 0 0x70>,
371 <0 0x11000280 0 0x80>;
372 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
373 clock-div = <16>;
374 clocks = <&pericfg CLK_PERI_I2C3>,
375 <&pericfg CLK_PERI_AP_DMA>;
376 clock-names = "main", "dma";
377 pinctrl-names = "default";
378 pinctrl-0 = <&i2c3_pins_a>;
379 #address-cells = <1>;
380 #size-cells = <0>;
381 status = "disabled";
382 };
383
384 i2c4: i2c4@11011000 {
385 compatible = "mediatek,mt8173-i2c";
386 reg = <0 0x11011000 0 0x70>,
387 <0 0x11000300 0 0x80>;
388 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
389 clock-div = <16>;
390 clocks = <&pericfg CLK_PERI_I2C4>,
391 <&pericfg CLK_PERI_AP_DMA>;
392 clock-names = "main", "dma";
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c4_pins_a>;
395 #address-cells = <1>;
396 #size-cells = <0>;
397 status = "disabled";
398 };
399
400 i2c6: i2c6@11013000 {
401 compatible = "mediatek,mt8173-i2c";
402 reg = <0 0x11013000 0 0x70>,
403 <0 0x11000080 0 0x80>;
404 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
405 clock-div = <16>;
406 clocks = <&pericfg CLK_PERI_I2C6>,
407 <&pericfg CLK_PERI_AP_DMA>;
408 clock-names = "main", "dma";
409 pinctrl-names = "default";
410 pinctrl-0 = <&i2c6_pins_a>;
411 #address-cells = <1>;
412 #size-cells = <0>;
413 status = "disabled";
414 };
415
416 afe: audio-controller@11220000 {
417 compatible = "mediatek,mt8173-afe-pcm";
418 reg = <0 0x11220000 0 0x1000>;
419 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
420 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
421 clocks = <&infracfg CLK_INFRA_AUDIO>,
422 <&topckgen CLK_TOP_AUDIO_SEL>,
423 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
424 <&topckgen CLK_TOP_APLL1_DIV0>,
425 <&topckgen CLK_TOP_APLL2_DIV0>,
426 <&topckgen CLK_TOP_I2S0_M_SEL>,
427 <&topckgen CLK_TOP_I2S1_M_SEL>,
428 <&topckgen CLK_TOP_I2S2_M_SEL>,
429 <&topckgen CLK_TOP_I2S3_M_SEL>,
430 <&topckgen CLK_TOP_I2S3_B_SEL>;
431 clock-names = "infra_sys_audio_clk",
432 "top_pdn_audio",
433 "top_pdn_aud_intbus",
434 "bck0",
435 "bck1",
436 "i2s0_m",
437 "i2s1_m",
438 "i2s2_m",
439 "i2s3_m",
440 "i2s3_b";
441 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
442 <&topckgen CLK_TOP_AUD_2_SEL>;
443 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
444 <&topckgen CLK_TOP_APLL2>;
445 };
446
447 mmc0: mmc@11230000 {
448 compatible = "mediatek,mt8173-mmc",
449 "mediatek,mt8135-mmc";
450 reg = <0 0x11230000 0 0x1000>;
451 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
452 clocks = <&pericfg CLK_PERI_MSDC30_0>,
453 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
454 clock-names = "source", "hclk";
455 status = "disabled";
456 };
457
458 mmc1: mmc@11240000 {
459 compatible = "mediatek,mt8173-mmc",
460 "mediatek,mt8135-mmc";
461 reg = <0 0x11240000 0 0x1000>;
462 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
463 clocks = <&pericfg CLK_PERI_MSDC30_1>,
464 <&topckgen CLK_TOP_AXI_SEL>;
465 clock-names = "source", "hclk";
466 status = "disabled";
467 };
468
469 mmc2: mmc@11250000 {
470 compatible = "mediatek,mt8173-mmc",
471 "mediatek,mt8135-mmc";
472 reg = <0 0x11250000 0 0x1000>;
473 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
474 clocks = <&pericfg CLK_PERI_MSDC30_2>,
475 <&topckgen CLK_TOP_AXI_SEL>;
476 clock-names = "source", "hclk";
477 status = "disabled";
478 };
479
480 mmc3: mmc@11260000 {
481 compatible = "mediatek,mt8173-mmc",
482 "mediatek,mt8135-mmc";
483 reg = <0 0x11260000 0 0x1000>;
484 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
485 clocks = <&pericfg CLK_PERI_MSDC30_3>,
486 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
487 clock-names = "source", "hclk";
187 status = "disabled"; 488 status = "disabled";
188 }; 489 };
189 }; 490 };
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
index 535532b9287f..e03c11d9d834 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
@@ -2,27 +2,37 @@
2 2
3&pm8916_gpios { 3&pm8916_gpios {
4 4
5 pinctrl-names = "default"; 5 usb_hub_reset_pm: usb_hub_reset_pm {
6 pinctrl-0 = <&pm8916_gpios_default>; 6 pinconf {
7 7 pins = "gpio3";
8 pm8916_gpios_default: default {
9 usb_hub_reset_pm {
10 pins = "gpio1";
11 function = PMIC_GPIO_FUNC_NORMAL; 8 function = PMIC_GPIO_FUNC_NORMAL;
12 output-low; 9 output-low;
13 }; 10 };
14 usb_sw_sel_pm { 11 };
15 pins = "gpio2"; 12
13 usb_sw_sel_pm: usb_sw_sel_pm {
14 pinconf {
15 pins = "gpio4";
16 function = PMIC_GPIO_FUNC_NORMAL; 16 function = PMIC_GPIO_FUNC_NORMAL;
17 power-source = <PM8916_GPIO_VPH>;
17 input-disable; 18 input-disable;
18 }; 19 };
19 usr_led_3_ctrl { 20 };
20 pins = "gpio3"; 21
22 pm8916_gpios_leds: pm8916_gpios_leds {
23 pinconf {
24 pins = "gpio1", "gpio2";
21 function = PMIC_GPIO_FUNC_NORMAL; 25 function = PMIC_GPIO_FUNC_NORMAL;
22 output-low; 26 output-low;
23 }; 27 };
24 usr_led_4_ctrl { 28 };
25 pins = "gpio4"; 29};
30
31&pm8916_mpps {
32
33 pm8916_mpps_leds: pm8916_mpps_leds {
34 pinconf {
35 pins = "mpp2", "mpp3";
26 function = PMIC_GPIO_FUNC_NORMAL; 36 function = PMIC_GPIO_FUNC_NORMAL;
27 output-low; 37 output-low;
28 }; 38 };
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
index 5f7023f90df7..cbeee0bcdf52 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
@@ -3,17 +3,9 @@
3 3
4&msmgpio { 4&msmgpio {
5 5
6 pinctrl-names = "default"; 6 msmgpio_leds: msmgpio_leds {
7 pinctrl-0 = <&soc_gpios_default>; 7 pinconf {
8 8 pins = "gpio21", "gpio120";
9 soc_gpios_default: default {
10 usr_led_1_ctrl_default: usr_led_1_ctrl_default {
11 pins = "gpio21";
12 function = "gpio";
13 output-low;
14 };
15 usr_led_2_ctrl_default: usr_led_2_ctrl_default {
16 pins = "gpio120";
17 function = "gpio"; 9 function = "gpio";
18 output-low; 10 output-low;
19 }; 11 };
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 98abece6b233..66804ffbc6d2 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -32,5 +32,56 @@
32 pinctrl-0 = <&blsp1_uart2_default>; 32 pinctrl-0 = <&blsp1_uart2_default>;
33 pinctrl-1 = <&blsp1_uart2_sleep>; 33 pinctrl-1 = <&blsp1_uart2_sleep>;
34 }; 34 };
35
36 leds {
37 pinctrl-names = "default";
38 pinctrl-0 = <&msmgpio_leds>,
39 <&pm8916_gpios_leds>,
40 <&pm8916_mpps_leds>;
41
42 compatible = "gpio-leds";
43
44 led@1 {
45 label = "apq8016-sbc:green:user1";
46 gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>;
47 linux,default-trigger = "heartbeat";
48 default-state = "off";
49 };
50
51 led@2 {
52 label = "apq8016-sbc:green:user2";
53 gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>;
54 linux,default-trigger = "mmc0";
55 default-state = "off";
56 };
57
58 led@3 {
59 label = "apq8016-sbc:green:user3";
60 gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>;
61 linux,default-trigger = "mmc1";
62 default-state = "off";
63 };
64
65 led@4 {
66 label = "apq8016-sbc:green:user4";
67 gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>;
68 linux,default-trigger = "none";
69 default-state = "off";
70 };
71
72 led@5 {
73 label = "apq8016-sbc:yellow:wlan";
74 gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
75 linux,default-trigger = "wlan";
76 default-state = "off";
77 };
78
79 led@6 {
80 label = "apq8016-sbc:blue:bt";
81 gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
82 linux,default-trigger = "bt";
83 default-state = "off";
84 };
85 };
35 }; 86 };
36}; 87};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
new file mode 100644
index 000000000000..568956859088
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -0,0 +1,430 @@
1/*
2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14&msmgpio {
15
16 blsp1_uart2_default: blsp1_uart2_default {
17 pinmux {
18 function = "blsp_uart2";
19 pins = "gpio4", "gpio5";
20 };
21 pinconf {
22 pins = "gpio4", "gpio5";
23 drive-strength = <16>;
24 bias-disable;
25 };
26 };
27
28 blsp1_uart2_sleep: blsp1_uart2_sleep {
29 pinmux {
30 function = "blsp_uart2";
31 pins = "gpio4", "gpio5";
32 };
33 pinconf {
34 pins = "gpio4", "gpio5";
35 drive-strength = <2>;
36 bias-pull-down;
37 };
38 };
39
40 spi1_default: spi1_default {
41 pinmux {
42 function = "blsp_spi1";
43 pins = "gpio0", "gpio1", "gpio3";
44 };
45 pinmux_cs {
46 function = "gpio";
47 pins = "gpio2";
48 };
49 pinconf {
50 pins = "gpio0", "gpio1", "gpio3";
51 drive-strength = <12>;
52 bias-disable;
53 };
54 pinconf_cs {
55 pins = "gpio2";
56 drive-strength = <2>;
57 bias-disable;
58 output-high;
59 };
60 };
61
62 spi1_sleep: spi1_sleep {
63 pinmux {
64 function = "gpio";
65 pins = "gpio0", "gpio1", "gpio2", "gpio3";
66 };
67 pinconf {
68 pins = "gpio0", "gpio1", "gpio2", "gpio3";
69 drive-strength = <2>;
70 bias-pull-down;
71 };
72 };
73
74 spi2_default: spi2_default {
75 pinmux {
76 function = "blsp_spi2";
77 pins = "gpio4", "gpio5", "gpio7";
78 };
79 pinmux_cs {
80 function = "gpio";
81 pins = "gpio6";
82 };
83 pinconf {
84 pins = "gpio4", "gpio5", "gpio6", "gpio7";
85 drive-strength = <12>;
86 bias-disable;
87 };
88 pinconf_cs {
89 pins = "gpio6";
90 drive-strength = <2>;
91 bias-disable;
92 output-high;
93 };
94 };
95
96 spi2_sleep: spi2_sleep {
97 pinmux {
98 function = "gpio";
99 pins = "gpio4", "gpio5", "gpio6", "gpio7";
100 };
101 pinconf {
102 pins = "gpio4", "gpio5", "gpio6", "gpio7";
103 drive-strength = <2>;
104 bias-pull-down;
105 };
106 };
107
108 spi3_default: spi3_default {
109 pinmux {
110 function = "blsp_spi3";
111 pins = "gpio8", "gpio9", "gpio11";
112 };
113 pinmux_cs {
114 function = "gpio";
115 pins = "gpio10";
116 };
117 pinconf {
118 pins = "gpio8", "gpio9", "gpio10", "gpio11";
119 drive-strength = <12>;
120 bias-disable;
121 };
122 pinconf_cs {
123 pins = "gpio10";
124 drive-strength = <2>;
125 bias-disable;
126 output-high;
127 };
128 };
129
130 spi3_sleep: spi3_sleep {
131 pinmux {
132 function = "gpio";
133 pins = "gpio8", "gpio9", "gpio10", "gpio11";
134 };
135 pinconf {
136 pins = "gpio8", "gpio9", "gpio10", "gpio11";
137 drive-strength = <2>;
138 bias-pull-down;
139 };
140 };
141
142 spi4_default: spi4_default {
143 pinmux {
144 function = "blsp_spi4";
145 pins = "gpio12", "gpio13", "gpio15";
146 };
147 pinmux_cs {
148 function = "gpio";
149 pins = "gpio14";
150 };
151 pinconf {
152 pins = "gpio12", "gpio13", "gpio14", "gpio15";
153 drive-strength = <12>;
154 bias-disable;
155 };
156 pinconf_cs {
157 pins = "gpio14";
158 drive-strength = <2>;
159 bias-disable;
160 output-high;
161 };
162 };
163
164 spi4_sleep: spi4_sleep {
165 pinmux {
166 function = "gpio";
167 pins = "gpio12", "gpio13", "gpio14", "gpio15";
168 };
169 pinconf {
170 pins = "gpio12", "gpio13", "gpio14", "gpio15";
171 drive-strength = <2>;
172 bias-pull-down;
173 };
174 };
175
176 spi5_default: spi5_default {
177 pinmux {
178 function = "blsp_spi5";
179 pins = "gpio16", "gpio17", "gpio19";
180 };
181 pinmux_cs {
182 function = "gpio";
183 pins = "gpio18";
184 };
185 pinconf {
186 pins = "gpio16", "gpio17", "gpio18", "gpio19";
187 drive-strength = <12>;
188 bias-disable;
189 };
190 pinconf_cs {
191 pins = "gpio18";
192 drive-strength = <2>;
193 bias-disable;
194 output-high;
195 };
196 };
197
198 spi5_sleep: spi5_sleep {
199 pinmux {
200 function = "gpio";
201 pins = "gpio16", "gpio17", "gpio18", "gpio19";
202 };
203 pinconf {
204 pins = "gpio16", "gpio17", "gpio18", "gpio19";
205 drive-strength = <2>;
206 bias-pull-down;
207 };
208 };
209
210 spi6_default: spi6_default {
211 pinmux {
212 function = "blsp_spi6";
213 pins = "gpio20", "gpio21", "gpio23";
214 };
215 pinmux_cs {
216 function = "gpio";
217 pins = "gpio22";
218 };
219 pinconf {
220 pins = "gpio20", "gpio21", "gpio22", "gpio23";
221 drive-strength = <12>;
222 bias-disable;
223 };
224 pinconf_cs {
225 pins = "gpio22";
226 drive-strength = <2>;
227 bias-disable;
228 output-high;
229 };
230 };
231
232 spi6_sleep: spi6_sleep {
233 pinmux {
234 function = "gpio";
235 pins = "gpio20", "gpio21", "gpio22", "gpio23";
236 };
237 pinconf {
238 pins = "gpio20", "gpio21", "gpio22", "gpio23";
239 drive-strength = <2>;
240 bias-pull-down;
241 };
242 };
243
244 i2c4_default: i2c4_default {
245 pinmux {
246 function = "blsp_i2c4";
247 pins = "gpio14", "gpio15";
248 };
249 pinconf {
250 pins = "gpio14", "gpio15";
251 drive-strength = <2>;
252 bias-disable = <0>;
253 };
254 };
255
256 i2c4_sleep: i2c4_sleep {
257 pinmux {
258 function = "blsp_i2c4";
259 pins = "gpio14", "gpio15";
260 };
261 pinconf {
262 pins = "gpio14", "gpio15";
263 drive-strength = <2>;
264 bias-disable = <0>;
265 };
266 };
267
268 sdhc2_cd_pin {
269 sdc2_cd_on: cd_on {
270 pinmux {
271 function = "gpio";
272 pins = "gpio38";
273 };
274 pinconf {
275 pins = "gpio38";
276 drive-strength = <2>;
277 bias-pull-up;
278 };
279 };
280 sdc2_cd_off: cd_off {
281 pinmux {
282 function = "gpio";
283 pins = "gpio38";
284 };
285 pinconf {
286 pins = "gpio38";
287 drive-strength = <2>;
288 bias-disable;
289 };
290 };
291 };
292
293 pmx_sdc1_clk {
294 sdc1_clk_on: clk_on {
295 pinmux {
296 pins = "sdc1_clk";
297 };
298 pinconf {
299 pins = "sdc1_clk";
300 bias-disable;
301 drive-strength = <16>;
302 };
303 };
304 sdc1_clk_off: clk_off {
305 pinmux {
306 pins = "sdc1_clk";
307 };
308 pinconf {
309 pins = "sdc1_clk";
310 bias-disable;
311 drive-strength = <2>;
312 };
313 };
314 };
315
316 pmx_sdc1_cmd {
317 sdc1_cmd_on: cmd_on {
318 pinmux {
319 pins = "sdc1_cmd";
320 };
321 pinconf {
322 pins = "sdc1_cmd";
323 bias-pull-up;
324 drive-strength = <10>;
325 };
326 };
327 sdc1_cmd_off: cmd_off {
328 pinmux {
329 pins = "sdc1_cmd";
330 };
331 pinconf {
332 pins = "sdc1_cmd";
333 bias-pull-up;
334 drive-strength = <2>;
335 };
336 };
337 };
338
339 pmx_sdc1_data {
340 sdc1_data_on: data_on {
341 pinmux {
342 pins = "sdc1_data";
343 };
344 pinconf {
345 pins = "sdc1_data";
346 bias-pull-up;
347 drive-strength = <10>;
348 };
349 };
350 sdc1_data_off: data_off {
351 pinmux {
352 pins = "sdc1_data";
353 };
354 pinconf {
355 pins = "sdc1_data";
356 bias-pull-up;
357 drive-strength = <2>;
358 };
359 };
360 };
361
362 pmx_sdc2_clk {
363 sdc2_clk_on: clk_on {
364 pinmux {
365 pins = "sdc2_clk";
366 };
367 pinconf {
368 pins = "sdc2_clk";
369 bias-disable;
370 drive-strength = <16>;
371 };
372 };
373 sdc2_clk_off: clk_off {
374 pinmux {
375 pins = "sdc2_clk";
376 };
377 pinconf {
378 pins = "sdc2_clk";
379 bias-disable;
380 drive-strength = <2>;
381 };
382 };
383 };
384
385 pmx_sdc2_cmd {
386 sdc2_cmd_on: cmd_on {
387 pinmux {
388 pins = "sdc2_cmd";
389 };
390 pinconf {
391 pins = "sdc2_cmd";
392 bias-pull-up;
393 drive-strength = <10>;
394 };
395 };
396 sdc2_cmd_off: cmd_off {
397 pinmux {
398 pins = "sdc2_cmd";
399 };
400 pinconf {
401 pins = "sdc2_cmd";
402 bias-pull-up;
403 drive-strength = <2>;
404 };
405 };
406 };
407
408 pmx_sdc2_data {
409 sdc2_data_on: data_on {
410 pinmux {
411 pins = "sdc2_data";
412 };
413 pinconf {
414 pins = "sdc2_data";
415 bias-pull-up;
416 drive-strength = <10>;
417 };
418 };
419 sdc2_data_off: data_off {
420 pinmux {
421 pins = "sdc2_data";
422 };
423 pinconf {
424 pins = "sdc2_data";
425 bias-pull-up;
426 drive-strength = <2>;
427 };
428 };
429 };
430};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 0f49ebd0aa8b..5911de008dd5 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -24,7 +24,10 @@
24 #address-cells = <2>; 24 #address-cells = <2>;
25 #size-cells = <2>; 25 #size-cells = <2>;
26 26
27 aliases { }; 27 aliases {
28 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
29 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
30 };
28 31
29 chosen { }; 32 chosen { };
30 33
@@ -90,30 +93,6 @@
90 #gpio-cells = <2>; 93 #gpio-cells = <2>;
91 interrupt-controller; 94 interrupt-controller;
92 #interrupt-cells = <2>; 95 #interrupt-cells = <2>;
93
94 blsp1_uart2_default: blsp1_uart2_default {
95 pinmux {
96 function = "blsp_uart2";
97 pins = "gpio4", "gpio5";
98 };
99 pinconf {
100 pins = "gpio4", "gpio5";
101 drive-strength = <16>;
102 bias-disable;
103 };
104 };
105
106 blsp1_uart2_sleep: blsp1_uart2_sleep {
107 pinmux {
108 function = "blsp_uart2";
109 pins = "gpio4", "gpio5";
110 };
111 pinconf {
112 pins = "gpio4", "gpio5";
113 drive-strength = <2>;
114 bias-pull-down;
115 };
116 };
117 }; 96 };
118 97
119 gcc: qcom,gcc@1800000 { 98 gcc: qcom,gcc@1800000 {
@@ -132,6 +111,202 @@
132 status = "disabled"; 111 status = "disabled";
133 }; 112 };
134 113
114 blsp_dma: dma@7884000 {
115 compatible = "qcom,bam-v1.7.0";
116 reg = <0x07884000 0x23000>;
117 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
119 clock-names = "bam_clk";
120 #dma-cells = <1>;
121 qcom,ee = <0>;
122 status = "disabled";
123 };
124
125 blsp_spi1: spi@78b5000 {
126 compatible = "qcom,spi-qup-v2.2.1";
127 reg = <0x078b5000 0x600>;
128 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
130 <&gcc GCC_BLSP1_AHB_CLK>;
131 clock-names = "core", "iface";
132 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
133 dma-names = "rx", "tx";
134 pinctrl-names = "default", "sleep";
135 pinctrl-0 = <&spi1_default>;
136 pinctrl-1 = <&spi1_sleep>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139 status = "disabled";
140 };
141
142 blsp_spi2: spi@78b6000 {
143 compatible = "qcom,spi-qup-v2.2.1";
144 reg = <0x078b6000 0x600>;
145 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
147 <&gcc GCC_BLSP1_AHB_CLK>;
148 clock-names = "core", "iface";
149 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
150 dma-names = "rx", "tx";
151 pinctrl-names = "default", "sleep";
152 pinctrl-0 = <&spi2_default>;
153 pinctrl-1 = <&spi2_sleep>;
154 #address-cells = <1>;
155 #size-cells = <0>;
156 status = "disabled";
157 };
158
159 blsp_spi3: spi@78b7000 {
160 compatible = "qcom,spi-qup-v2.2.1";
161 reg = <0x078b7000 0x600>;
162 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
164 <&gcc GCC_BLSP1_AHB_CLK>;
165 clock-names = "core", "iface";
166 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
167 dma-names = "rx", "tx";
168 pinctrl-names = "default", "sleep";
169 pinctrl-0 = <&spi3_default>;
170 pinctrl-1 = <&spi3_sleep>;
171 #address-cells = <1>;
172 #size-cells = <0>;
173 status = "disabled";
174 };
175
176 blsp_spi4: spi@78b8000 {
177 compatible = "qcom,spi-qup-v2.2.1";
178 reg = <0x078b8000 0x600>;
179 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
181 <&gcc GCC_BLSP1_AHB_CLK>;
182 clock-names = "core", "iface";
183 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
184 dma-names = "rx", "tx";
185 pinctrl-names = "default", "sleep";
186 pinctrl-0 = <&spi4_default>;
187 pinctrl-1 = <&spi4_sleep>;
188 #address-cells = <1>;
189 #size-cells = <0>;
190 status = "disabled";
191 };
192
193 blsp_spi5: spi@78b9000 {
194 compatible = "qcom,spi-qup-v2.2.1";
195 reg = <0x078b9000 0x600>;
196 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
198 <&gcc GCC_BLSP1_AHB_CLK>;
199 clock-names = "core", "iface";
200 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
201 dma-names = "rx", "tx";
202 pinctrl-names = "default", "sleep";
203 pinctrl-0 = <&spi5_default>;
204 pinctrl-1 = <&spi5_sleep>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207 status = "disabled";
208 };
209
210 blsp_spi6: spi@78ba000 {
211 compatible = "qcom,spi-qup-v2.2.1";
212 reg = <0x078ba000 0x600>;
213 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
215 <&gcc GCC_BLSP1_AHB_CLK>;
216 clock-names = "core", "iface";
217 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
218 dma-names = "rx", "tx";
219 pinctrl-names = "default", "sleep";
220 pinctrl-0 = <&spi6_default>;
221 pinctrl-1 = <&spi6_sleep>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224 status = "disabled";
225 };
226
227 blsp_i2c4: i2c@78b8000 {
228 compatible = "qcom,i2c-qup-v2.2.1";
229 reg = <0x78b8000 0x1000>;
230 interrupts = <GIC_SPI 98 0>;
231 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
232 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
233 clock-names = "iface", "core";
234 pinctrl-names = "default", "sleep";
235 pinctrl-0 = <&i2c4_default>;
236 pinctrl-1 = <&i2c4_sleep>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 status = "disabled";
240 };
241
242 sdhc_1: sdhci@07824000 {
243 compatible = "qcom,sdhci-msm-v4";
244 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
245 reg-names = "hc_mem", "core_mem";
246
247 interrupts = <0 123 0>, <0 138 0>;
248 interrupt-names = "hc_irq", "pwr_irq";
249 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
250 <&gcc GCC_SDCC1_AHB_CLK>;
251 clock-names = "core", "iface";
252 bus-width = <8>;
253 non-removable;
254 status = "disabled";
255 };
256
257 sdhc_2: sdhci@07864000 {
258 compatible = "qcom,sdhci-msm-v4";
259 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
260 reg-names = "hc_mem", "core_mem";
261
262 interrupts = <0 125 0>, <0 221 0>;
263 interrupt-names = "hc_irq", "pwr_irq";
264 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
265 <&gcc GCC_SDCC2_AHB_CLK>;
266 clock-names = "core", "iface";
267 bus-width = <4>;
268 status = "disabled";
269 };
270
271 usb_dev: usb@78d9000 {
272 compatible = "qcom,ci-hdrc";
273 reg = <0x78d9000 0x400>;
274 dr_mode = "peripheral";
275 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
276 usb-phy = <&usb_otg>;
277 status = "disabled";
278 };
279
280 usb_host: ehci@78d9000 {
281 compatible = "qcom,ehci-host";
282 reg = <0x78d9000 0x400>;
283 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
284 usb-phy = <&usb_otg>;
285 status = "disabled";
286 };
287
288 usb_otg: phy@78d9000 {
289 compatible = "qcom,usb-otg-snps";
290 reg = <0x78d9000 0x400>;
291 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
292 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
293
294 qcom,vdd-levels = <1 5 7>;
295 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
296 dr_mode = "peripheral";
297 qcom,otg-control = <2>; // PMIC
298
299 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
300 <&gcc GCC_USB_HS_SYSTEM_CLK>,
301 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
302 clock-names = "iface", "core", "sleep";
303
304 resets = <&gcc GCC_USB2A_PHY_BCR>,
305 <&gcc GCC_USB_HS_BCR>;
306 reset-names = "phy", "link";
307 status = "disabled";
308 };
309
135 intc: interrupt-controller@b000000 { 310 intc: interrupt-controller@b000000 {
136 compatible = "qcom,msm-qgic2"; 311 compatible = "qcom,msm-qgic2";
137 interrupt-controller; 312 interrupt-controller;
@@ -217,3 +392,5 @@
217 }; 392 };
218 }; 393 };
219}; 394};
395
396#include "msm8916-pins.dtsi"
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
new file mode 100644
index 000000000000..601e6a236c1d
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
new file mode 100644
index 000000000000..401a81231eb9
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
@@ -0,0 +1,354 @@
1/*
2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44#include "rk3368.dtsi"
45
46/ {
47 model = "Rockchip R88";
48 compatible = "rockchip,r88", "rockchip,rk3368";
49
50 chosen {
51 stdout-path = "serial2:115200n8";
52 };
53
54 memory {
55 device_type = "memory";
56 reg = <0x0 0x0 0x0 0x40000000>;
57 };
58
59 emmc_pwrseq: emmc-pwrseq {
60 compatible = "mmc-pwrseq-emmc";
61 pinctrl-0 = <&emmc_reset>;
62 pinctrl-names = "default";
63 reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
64 };
65
66 keys: gpio-keys {
67 compatible = "gpio-keys";
68 #address-cells = <1>;
69 #size-cells = <0>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pwr_key>;
72
73 button@0 {
74 gpio-key,wakeup = <1>;
75 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
76 label = "GPIO Power";
77 linux,code = <116>;
78 };
79 };
80
81 leds: gpio-leds {
82 compatible = "gpio-leds";
83
84 work {
85 gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
86 label = "r88:green:led";
87 pinctrl-names = "default";
88 pinctrl-0 = <&led_ctl>;
89 };
90 };
91
92 ir: ir-receiver {
93 compatible = "gpio-ir-receiver";
94 gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&ir_int>;
97 };
98
99 sdio_pwrseq: sdio-pwrseq {
100 compatible = "mmc-pwrseq-simple";
101 clocks = <&hym8563>;
102 clock-names = "ext_clock";
103 pinctrl-names = "default";
104 pinctrl-0 = <&bt_rst>, <&wifi_reg_on>;
105
106 reset-gpios =
107 /* BT_RST_N */
108 <&gpio3 5 GPIO_ACTIVE_LOW>,
109
110 /* WL_REG_ON */
111 <&gpio3 4 GPIO_ACTIVE_LOW>;
112 };
113
114 vcc_18: vcc18-regulator {
115 compatible = "regulator-fixed";
116 regulator-name = "vcc_18";
117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <1800000>;
119 regulator-always-on;
120 regulator-boot-on;
121 vin-supply = <&vcc_sys>;
122 };
123
124 /* supplies both host and otg */
125 vcc_host: vcc-host-regulator {
126 compatible = "regulator-fixed";
127 enable-active-high;
128 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&host_vbus_drv>;
131 regulator-name = "vcc_host";
132 regulator-always-on;
133 regulator-boot-on;
134 vin-supply = <&vcc_sys>;
135 };
136
137 vcc_io: vcc-io-regulator {
138 compatible = "regulator-fixed";
139 regulator-name = "vcc_io";
140 regulator-min-microvolt = <3300000>;
141 regulator-max-microvolt = <3300000>;
142 regulator-always-on;
143 regulator-boot-on;
144 vin-supply = <&vcc_sys>;
145 };
146
147 vcc_lan: vcc-lan-regulator {
148 compatible = "regulator-fixed";
149 regulator-name = "vcc_lan";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 regulator-always-on;
153 regulator-boot-on;
154 vin-supply = <&vcc_io>;
155 };
156
157 vcc_sys: vcc-sys-regulator {
158 compatible = "regulator-fixed";
159 regulator-name = "vcc_sys";
160 regulator-min-microvolt = <5000000>;
161 regulator-max-microvolt = <5000000>;
162 regulator-always-on;
163 regulator-boot-on;
164 };
165
166 vccio_wl: vccio-wl-regulator {
167 compatible = "regulator-fixed";
168 regulator-name = "vccio_wl";
169 regulator-min-microvolt = <3300000>;
170 regulator-max-microvolt = <3300000>;
171 regulator-always-on;
172 regulator-boot-on;
173 vin-supply = <&vcc_io>;
174 };
175
176 vdd_10: vdd-10-regulator {
177 compatible = "regulator-fixed";
178 regulator-name = "vdd_10";
179 regulator-min-microvolt = <1000000>;
180 regulator-max-microvolt = <1000000>;
181 regulator-always-on;
182 regulator-boot-on;
183 vin-supply = <&vcc_sys>;
184 };
185};
186
187&emmc {
188 broken-cd;
189 bus-width = <8>;
190 cap-mmc-highspeed;
191 disable-wp;
192 mmc-pwrseq = <&emmc_pwrseq>;
193 non-removable;
194 num-slots = <1>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
197 status = "okay";
198};
199
200&gmac {
201 phy-supply = <&vcc_lan>;
202 phy-mode = "rmii";
203 clock_in_out = "output";
204 snps,reset-gpio = <&gpio3 12 0>;
205 snps,reset-active-low;
206 snps,reset-delays-us = <0 10000 1000000>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&rmii_pins>;
209 tx_delay = <0x30>;
210 rx_delay = <0x10>;
211 status = "ok";
212};
213
214&i2c0 {
215 status = "okay";
216
217 vdd_cpu: syr827@40 {
218 compatible = "silergy,syr827";
219 reg = <0x40>;
220 fcs,suspend-voltage-selector = <1>;
221 regulator-name = "vdd_cpu";
222 regulator-enable-ramp-delay = <300>;
223 regulator-min-microvolt = <712500>;
224 regulator-max-microvolt = <1500000>;
225 regulator-ramp-delay = <8000>;
226 regulator-always-on;
227 regulator-boot-on;
228 vin-supply = <&vcc_sys>;
229 };
230
231 hym8563: hym8563@51 {
232 compatible = "haoyu,hym8563";
233 reg = <0x51>;
234 #clock-cells = <0>;
235 clock-frequency = <32768>;
236 clock-output-names = "xin32k";
237 /* rtc_int is not connected */
238 };
239};
240
241&sdio0 {
242 assigned-clocks = <&cru SCLK_SDIO0>;
243 assigned-clock-parents = <&cru PLL_CPLL>;
244 broken-cd;
245 bus-width = <4>;
246 cap-sd-highspeed;
247 cap-sdio-irq;
248 keep-power-in-suspend;
249 mmc-pwrseq = <&sdio_pwrseq>;
250 non-removable;
251 num-slots = <1>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
254 vmmc-supply = <&vcc_io>;
255 vqmmc-supply = <&vccio_wl>;
256 status = "okay";
257};
258
259&pinctrl {
260 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
261 bias-disable;
262 drive-strength = <8>;
263 };
264
265 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
266 bias-pull-up;
267 drive-strength = <8>;
268 };
269
270 emmc {
271 emmc_bus8: emmc-bus8 {
272 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
273 <1 19 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
274 <1 20 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
275 <1 21 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
276 <1 22 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
277 <1 23 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
278 <1 24 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
279 <1 25 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
280 };
281
282 emmc-clk {
283 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
284 };
285
286 emmc-cmd {
287 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
288 };
289
290 emmc_reset: emmc-reset {
291 rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
292 };
293 };
294
295 ir {
296 ir_int: ir-int {
297 rockchip,pins = <3 30 RK_FUNC_GPIO &pcfg_pull_up>;
298 };
299 };
300
301 keys {
302 pwr_key: pwr-key {
303 rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_up>;
304 };
305 };
306
307 leds {
308 stby_pwren: stby-pwren {
309 rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
310 };
311
312 led_ctl: led-ctl {
313 rockchip,pins = <3 29 RK_FUNC_GPIO &pcfg_pull_none>;
314 };
315 };
316
317 sdio {
318 wifi_reg_on: wifi-reg-on {
319 rockchip,pins = <3 4 RK_FUNC_GPIO &pcfg_pull_none>;
320 };
321
322 bt_rst: bt-rst {
323 rockchip,pins = <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
324 };
325 };
326
327 usb {
328 host_vbus_drv: host-vbus-drv {
329 rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>;
330 };
331 };
332};
333
334&saradc {
335 vref-supply = <&vcc_18>;
336 status = "okay";
337};
338
339&uart2 {
340 status = "okay";
341};
342
343&usb_host0_ehci {
344 status = "okay";
345};
346
347&usb_otg {
348 dr_mode = "host";
349 status = "okay";
350};
351
352&wdt {
353 status = "okay";
354};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
new file mode 100644
index 000000000000..a712bea3bf2c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -0,0 +1,900 @@
1/*
2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/rk3368-cru.h>
44#include <dt-bindings/gpio/gpio.h>
45#include <dt-bindings/interrupt-controller/irq.h>
46#include <dt-bindings/interrupt-controller/arm-gic.h>
47#include <dt-bindings/pinctrl/rockchip.h>
48
49/ {
50 compatible = "rockchip,rk3368";
51 interrupt-parent = <&gic>;
52 #address-cells = <2>;
53 #size-cells = <2>;
54
55 aliases {
56 i2c0 = &i2c0;
57 i2c1 = &i2c1;
58 i2c2 = &i2c2;
59 i2c3 = &i2c3;
60 i2c4 = &i2c4;
61 i2c5 = &i2c5;
62 serial0 = &uart0;
63 serial1 = &uart1;
64 serial2 = &uart2;
65 serial3 = &uart3;
66 serial4 = &uart4;
67 spi0 = &spi0;
68 spi1 = &spi1;
69 spi2 = &spi2;
70 };
71
72 cpus {
73 #address-cells = <0x2>;
74 #size-cells = <0x0>;
75
76 cpu-map {
77 cluster0 {
78 core0 {
79 cpu = <&cpu_b0>;
80 };
81 core1 {
82 cpu = <&cpu_b1>;
83 };
84 core2 {
85 cpu = <&cpu_b2>;
86 };
87 core3 {
88 cpu = <&cpu_b3>;
89 };
90 };
91
92 cluster1 {
93 core0 {
94 cpu = <&cpu_l0>;
95 };
96 core1 {
97 cpu = <&cpu_l1>;
98 };
99 core2 {
100 cpu = <&cpu_l2>;
101 };
102 core3 {
103 cpu = <&cpu_l3>;
104 };
105 };
106 };
107
108 idle-states {
109 entry-method = "arm,psci";
110
111 cpu_sleep: cpu-sleep-0 {
112 compatible = "arm,idle-state";
113 arm,psci-suspend-param = <0x1010000>;
114 entry-latency-us = <0x3fffffff>;
115 exit-latency-us = <0x40000000>;
116 min-residency-us = <0xffffffff>;
117 };
118 };
119
120 cpu_l0: cpu@0 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a53", "arm,armv8";
123 reg = <0x0 0x0>;
124 cpu-idle-states = <&cpu_sleep>;
125 enable-method = "psci";
126 };
127
128 cpu_l1: cpu@1 {
129 device_type = "cpu";
130 compatible = "arm,cortex-a53", "arm,armv8";
131 reg = <0x0 0x1>;
132 cpu-idle-states = <&cpu_sleep>;
133 enable-method = "psci";
134 };
135
136 cpu_l2: cpu@2 {
137 device_type = "cpu";
138 compatible = "arm,cortex-a53", "arm,armv8";
139 reg = <0x0 0x2>;
140 cpu-idle-states = <&cpu_sleep>;
141 enable-method = "psci";
142 };
143
144 cpu_l3: cpu@3 {
145 device_type = "cpu";
146 compatible = "arm,cortex-a53", "arm,armv8";
147 reg = <0x0 0x3>;
148 cpu-idle-states = <&cpu_sleep>;
149 enable-method = "psci";
150 };
151
152 cpu_b0: cpu@100 {
153 device_type = "cpu";
154 compatible = "arm,cortex-a53", "arm,armv8";
155 reg = <0x0 0x100>;
156 cpu-idle-states = <&cpu_sleep>;
157 enable-method = "psci";
158 };
159
160 cpu_b1: cpu@101 {
161 device_type = "cpu";
162 compatible = "arm,cortex-a53", "arm,armv8";
163 reg = <0x0 0x101>;
164 cpu-idle-states = <&cpu_sleep>;
165 enable-method = "psci";
166 };
167
168 cpu_b2: cpu@102 {
169 device_type = "cpu";
170 compatible = "arm,cortex-a53", "arm,armv8";
171 reg = <0x0 0x102>;
172 cpu-idle-states = <&cpu_sleep>;
173 enable-method = "psci";
174 };
175
176 cpu_b3: cpu@103 {
177 device_type = "cpu";
178 compatible = "arm,cortex-a53", "arm,armv8";
179 reg = <0x0 0x103>;
180 cpu-idle-states = <&cpu_sleep>;
181 enable-method = "psci";
182 };
183 };
184
185 arm-pmu {
186 compatible = "arm,armv8-pmuv3";
187 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
195 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
196 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
197 <&cpu_b2>, <&cpu_b3>;
198 };
199
200 psci {
201 compatible = "arm,psci-0.2";
202 method = "smc";
203 };
204
205 timer {
206 compatible = "arm,armv8-timer";
207 interrupts = <GIC_PPI 13
208 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 14
210 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
211 <GIC_PPI 11
212 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
213 <GIC_PPI 10
214 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
215 };
216
217 xin24m: oscillator {
218 compatible = "fixed-clock";
219 clock-frequency = <24000000>;
220 clock-output-names = "xin24m";
221 #clock-cells = <0>;
222 };
223
224 sdmmc: dwmmc@ff0c0000 {
225 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
226 reg = <0x0 0xff0c0000 0x0 0x4000>;
227 clock-freq-min-max = <400000 150000000>;
228 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
229 clock-names = "biu", "ciu";
230 fifo-depth = <0x100>;
231 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
232 status = "disabled";
233 };
234
235 sdio0: dwmmc@ff0d0000 {
236 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
237 reg = <0x0 0xff0d0000 0x0 0x4000>;
238 clock-freq-min-max = <400000 150000000>;
239 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
240 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
241 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
242 fifo-depth = <0x100>;
243 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
244 status = "disabled";
245 };
246
247 emmc: dwmmc@ff0f0000 {
248 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
249 reg = <0x0 0xff0f0000 0x0 0x4000>;
250 clock-freq-min-max = <400000 150000000>;
251 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
252 clock-names = "biu", "ciu";
253 fifo-depth = <0x100>;
254 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
255 status = "disabled";
256 };
257
258 saradc: saradc@ff100000 {
259 compatible = "rockchip,saradc";
260 reg = <0x0 0xff100000 0x0 0x100>;
261 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
262 #io-channel-cells = <1>;
263 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
264 clock-names = "saradc", "apb_pclk";
265 status = "disabled";
266 };
267
268 spi0: spi@ff110000 {
269 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
270 reg = <0x0 0xff110000 0x0 0x1000>;
271 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
272 clock-names = "spiclk", "apb_pclk";
273 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
274 pinctrl-names = "default";
275 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 status = "disabled";
279 };
280
281 spi1: spi@ff120000 {
282 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
283 reg = <0x0 0xff120000 0x0 0x1000>;
284 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
285 clock-names = "spiclk", "apb_pclk";
286 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 status = "disabled";
292 };
293
294 spi2: spi@ff130000 {
295 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
296 reg = <0x0 0xff130000 0x0 0x1000>;
297 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
298 clock-names = "spiclk", "apb_pclk";
299 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 status = "disabled";
305 };
306
307 i2c1: i2c@ff140000 {
308 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
309 reg = <0x0 0xff140000 0x0 0x1000>;
310 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 clock-names = "i2c";
314 clocks = <&cru PCLK_I2C1>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&i2c1_xfer>;
317 status = "disabled";
318 };
319
320 i2c3: i2c@ff150000 {
321 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
322 reg = <0x0 0xff150000 0x0 0x1000>;
323 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 clock-names = "i2c";
327 clocks = <&cru PCLK_I2C3>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&i2c3_xfer>;
330 status = "disabled";
331 };
332
333 i2c4: i2c@ff160000 {
334 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
335 reg = <0x0 0xff160000 0x0 0x1000>;
336 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
337 #address-cells = <1>;
338 #size-cells = <0>;
339 clock-names = "i2c";
340 clocks = <&cru PCLK_I2C4>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&i2c4_xfer>;
343 status = "disabled";
344 };
345
346 i2c5: i2c@ff170000 {
347 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
348 reg = <0x0 0xff170000 0x0 0x1000>;
349 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
350 #address-cells = <1>;
351 #size-cells = <0>;
352 clock-names = "i2c";
353 clocks = <&cru PCLK_I2C5>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c5_xfer>;
356 status = "disabled";
357 };
358
359 uart0: serial@ff180000 {
360 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
361 reg = <0x0 0xff180000 0x0 0x100>;
362 clock-frequency = <24000000>;
363 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
364 clock-names = "baudclk", "apb_pclk";
365 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
366 reg-shift = <2>;
367 reg-io-width = <4>;
368 status = "disabled";
369 };
370
371 uart1: serial@ff190000 {
372 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
373 reg = <0x0 0xff190000 0x0 0x100>;
374 clock-frequency = <24000000>;
375 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
376 clock-names = "baudclk", "apb_pclk";
377 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
378 reg-shift = <2>;
379 reg-io-width = <4>;
380 status = "disabled";
381 };
382
383 uart3: serial@ff1b0000 {
384 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
385 reg = <0x0 0xff1b0000 0x0 0x100>;
386 clock-frequency = <24000000>;
387 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
388 clock-names = "baudclk", "apb_pclk";
389 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
390 reg-shift = <2>;
391 reg-io-width = <4>;
392 status = "disabled";
393 };
394
395 uart4: serial@ff1c0000 {
396 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
397 reg = <0x0 0xff1c0000 0x0 0x100>;
398 clock-frequency = <24000000>;
399 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
400 clock-names = "baudclk", "apb_pclk";
401 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
402 reg-shift = <2>;
403 reg-io-width = <4>;
404 status = "disabled";
405 };
406
407 gmac: ethernet@ff290000 {
408 compatible = "rockchip,rk3368-gmac";
409 reg = <0x0 0xff290000 0x0 0x10000>;
410 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
411 interrupt-names = "macirq";
412 rockchip,grf = <&grf>;
413 clocks = <&cru SCLK_MAC>,
414 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
415 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
416 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
417 clock-names = "stmmaceth",
418 "mac_clk_rx", "mac_clk_tx",
419 "clk_mac_ref", "clk_mac_refout",
420 "aclk_mac", "pclk_mac";
421 status = "disabled";
422 };
423
424 usb_host0_ehci: usb@ff500000 {
425 compatible = "generic-ehci";
426 reg = <0x0 0xff500000 0x0 0x100>;
427 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&cru HCLK_HOST0>;
429 clock-names = "usbhost";
430 status = "disabled";
431 };
432
433 usb_otg: usb@ff580000 {
434 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
435 "snps,dwc2";
436 reg = <0x0 0xff580000 0x0 0x40000>;
437 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&cru HCLK_OTG0>;
439 clock-names = "otg";
440 dr_mode = "otg";
441 g-np-tx-fifo-size = <16>;
442 g-rx-fifo-size = <275>;
443 g-tx-fifo-size = <256 128 128 64 64 32>;
444 g-use-dma;
445 status = "disabled";
446 };
447
448 i2c0: i2c@ff650000 {
449 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
450 reg = <0x0 0xff650000 0x0 0x1000>;
451 clocks = <&cru PCLK_I2C0>;
452 clock-names = "i2c";
453 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&i2c0_xfer>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 status = "disabled";
459 };
460
461 i2c2: i2c@ff660000 {
462 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
463 reg = <0x0 0xff660000 0x0 0x1000>;
464 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
465 #address-cells = <1>;
466 #size-cells = <0>;
467 clock-names = "i2c";
468 clocks = <&cru PCLK_I2C2>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&i2c2_xfer>;
471 status = "disabled";
472 };
473
474 uart2: serial@ff690000 {
475 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
476 reg = <0x0 0xff690000 0x0 0x100>;
477 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
478 clock-names = "baudclk", "apb_pclk";
479 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&uart2_xfer>;
482 reg-shift = <2>;
483 reg-io-width = <4>;
484 status = "disabled";
485 };
486
487 pmugrf: syscon@ff738000 {
488 compatible = "rockchip,rk3368-pmugrf", "syscon";
489 reg = <0x0 0xff738000 0x0 0x1000>;
490 };
491
492 cru: clock-controller@ff760000 {
493 compatible = "rockchip,rk3368-cru";
494 reg = <0x0 0xff760000 0x0 0x1000>;
495 rockchip,grf = <&grf>;
496 #clock-cells = <1>;
497 #reset-cells = <1>;
498 };
499
500 grf: syscon@ff770000 {
501 compatible = "rockchip,rk3368-grf", "syscon";
502 reg = <0x0 0xff770000 0x0 0x1000>;
503 };
504
505 wdt: watchdog@ff800000 {
506 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
507 reg = <0x0 0xff800000 0x0 0x100>;
508 clocks = <&cru PCLK_WDT>;
509 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
510 status = "disabled";
511 };
512
513 gic: interrupt-controller@ffb71000 {
514 compatible = "arm,gic-400";
515 interrupt-controller;
516 #interrupt-cells = <3>;
517 #address-cells = <0>;
518
519 reg = <0x0 0xffb71000 0x0 0x1000>,
520 <0x0 0xffb72000 0x0 0x1000>,
521 <0x0 0xffb74000 0x0 0x2000>,
522 <0x0 0xffb76000 0x0 0x2000>;
523 interrupts = <GIC_PPI 9
524 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
525 };
526
527 pinctrl: pinctrl {
528 compatible = "rockchip,rk3368-pinctrl";
529 rockchip,grf = <&grf>;
530 rockchip,pmu = <&pmugrf>;
531 #address-cells = <0x2>;
532 #size-cells = <0x2>;
533 ranges;
534
535 gpio0: gpio0@ff750000 {
536 compatible = "rockchip,gpio-bank";
537 reg = <0x0 0xff750000 0x0 0x100>;
538 clocks = <&cru PCLK_GPIO0>;
539 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
540
541 gpio-controller;
542 #gpio-cells = <0x2>;
543
544 interrupt-controller;
545 #interrupt-cells = <0x2>;
546 };
547
548 gpio1: gpio1@ff780000 {
549 compatible = "rockchip,gpio-bank";
550 reg = <0x0 0xff780000 0x0 0x100>;
551 clocks = <&cru PCLK_GPIO1>;
552 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
553
554 gpio-controller;
555 #gpio-cells = <0x2>;
556
557 interrupt-controller;
558 #interrupt-cells = <0x2>;
559 };
560
561 gpio2: gpio2@ff790000 {
562 compatible = "rockchip,gpio-bank";
563 reg = <0x0 0xff790000 0x0 0x100>;
564 clocks = <&cru PCLK_GPIO2>;
565 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
566
567 gpio-controller;
568 #gpio-cells = <0x2>;
569
570 interrupt-controller;
571 #interrupt-cells = <0x2>;
572 };
573
574 gpio3: gpio3@ff7a0000 {
575 compatible = "rockchip,gpio-bank";
576 reg = <0x0 0xff7a0000 0x0 0x100>;
577 clocks = <&cru PCLK_GPIO3>;
578 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
579
580 gpio-controller;
581 #gpio-cells = <0x2>;
582
583 interrupt-controller;
584 #interrupt-cells = <0x2>;
585 };
586
587 pcfg_pull_up: pcfg-pull-up {
588 bias-pull-up;
589 };
590
591 pcfg_pull_down: pcfg-pull-down {
592 bias-pull-down;
593 };
594
595 pcfg_pull_none: pcfg-pull-none {
596 bias-disable;
597 };
598
599 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
600 bias-disable;
601 drive-strength = <12>;
602 };
603
604 emmc {
605 emmc_clk: emmc-clk {
606 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
607 };
608
609 emmc_cmd: emmc-cmd {
610 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
611 };
612
613 emmc_pwr: emmc-pwr {
614 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
615 };
616
617 emmc_bus1: emmc-bus1 {
618 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
619 };
620
621 emmc_bus4: emmc-bus4 {
622 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
623 <1 19 RK_FUNC_2 &pcfg_pull_up>,
624 <1 20 RK_FUNC_2 &pcfg_pull_up>,
625 <1 21 RK_FUNC_2 &pcfg_pull_up>;
626 };
627
628 emmc_bus8: emmc-bus8 {
629 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
630 <1 19 RK_FUNC_2 &pcfg_pull_up>,
631 <1 20 RK_FUNC_2 &pcfg_pull_up>,
632 <1 21 RK_FUNC_2 &pcfg_pull_up>,
633 <1 22 RK_FUNC_2 &pcfg_pull_up>,
634 <1 23 RK_FUNC_2 &pcfg_pull_up>,
635 <1 24 RK_FUNC_2 &pcfg_pull_up>,
636 <1 25 RK_FUNC_2 &pcfg_pull_up>;
637 };
638 };
639
640 gmac {
641 rgmii_pins: rgmii-pins {
642 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
643 <3 24 RK_FUNC_1 &pcfg_pull_none>,
644 <3 19 RK_FUNC_1 &pcfg_pull_none>,
645 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
646 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
647 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
648 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
649 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
650 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
651 <3 15 RK_FUNC_1 &pcfg_pull_none>,
652 <3 16 RK_FUNC_1 &pcfg_pull_none>,
653 <3 17 RK_FUNC_1 &pcfg_pull_none>,
654 <3 18 RK_FUNC_1 &pcfg_pull_none>,
655 <3 25 RK_FUNC_1 &pcfg_pull_none>,
656 <3 20 RK_FUNC_1 &pcfg_pull_none>;
657 };
658
659 rmii_pins: rmii-pins {
660 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
661 <3 24 RK_FUNC_1 &pcfg_pull_none>,
662 <3 19 RK_FUNC_1 &pcfg_pull_none>,
663 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
664 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
665 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
666 <3 15 RK_FUNC_1 &pcfg_pull_none>,
667 <3 16 RK_FUNC_1 &pcfg_pull_none>,
668 <3 20 RK_FUNC_1 &pcfg_pull_none>,
669 <3 21 RK_FUNC_1 &pcfg_pull_none>;
670 };
671 };
672
673 i2c0 {
674 i2c0_xfer: i2c0-xfer {
675 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
676 <0 7 RK_FUNC_1 &pcfg_pull_none>;
677 };
678 };
679
680 i2c1 {
681 i2c1_xfer: i2c1-xfer {
682 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
683 <2 22 RK_FUNC_1 &pcfg_pull_none>;
684 };
685 };
686
687 i2c2 {
688 i2c2_xfer: i2c2-xfer {
689 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
690 <3 31 RK_FUNC_2 &pcfg_pull_none>;
691 };
692 };
693
694 i2c3 {
695 i2c3_xfer: i2c3-xfer {
696 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
697 <1 17 RK_FUNC_1 &pcfg_pull_none>;
698 };
699 };
700
701 i2c4 {
702 i2c4_xfer: i2c4-xfer {
703 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
704 <3 25 RK_FUNC_2 &pcfg_pull_none>;
705 };
706 };
707
708 i2c5 {
709 i2c5_xfer: i2c5-xfer {
710 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
711 <3 27 RK_FUNC_2 &pcfg_pull_none>;
712 };
713 };
714
715 sdio0 {
716 sdio0_bus1: sdio0-bus1 {
717 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
718 };
719
720 sdio0_bus4: sdio0-bus4 {
721 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
722 <2 29 RK_FUNC_1 &pcfg_pull_up>,
723 <2 30 RK_FUNC_1 &pcfg_pull_up>,
724 <2 31 RK_FUNC_1 &pcfg_pull_up>;
725 };
726
727 sdio0_cmd: sdio0-cmd {
728 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
729 };
730
731 sdio0_clk: sdio0-clk {
732 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
733 };
734
735 sdio0_cd: sdio0-cd {
736 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
737 };
738
739 sdio0_wp: sdio0-wp {
740 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
741 };
742
743 sdio0_pwr: sdio0-pwr {
744 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
745 };
746
747 sdio0_bkpwr: sdio0-bkpwr {
748 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
749 };
750
751 sdio0_int: sdio0-int {
752 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
753 };
754 };
755
756 sdmmc {
757 sdmmc_clk: sdmmc-clk {
758 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
759 };
760
761 sdmmc_cmd: sdmmc-cmd {
762 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
763 };
764
765 sdmmc_cd: sdmcc-cd {
766 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
767 };
768
769 sdmmc_bus1: sdmmc-bus1 {
770 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
771 };
772
773 sdmmc_bus4: sdmmc-bus4 {
774 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
775 <2 6 RK_FUNC_1 &pcfg_pull_up>,
776 <2 7 RK_FUNC_1 &pcfg_pull_up>,
777 <2 8 RK_FUNC_1 &pcfg_pull_up>;
778 };
779 };
780
781 spi0 {
782 spi0_clk: spi0-clk {
783 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
784 };
785 spi0_cs0: spi0-cs0 {
786 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
787 };
788 spi0_cs1: spi0-cs1 {
789 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
790 };
791 spi0_tx: spi0-tx {
792 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
793 };
794 spi0_rx: spi0-rx {
795 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
796 };
797 };
798
799 spi1 {
800 spi1_clk: spi1-clk {
801 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
802 };
803 spi1_cs0: spi1-cs0 {
804 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
805 };
806 spi1_cs1: spi1-cs1 {
807 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
808 };
809 spi1_rx: spi1-rx {
810 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
811 };
812 spi1_tx: spi1-tx {
813 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
814 };
815 };
816
817 spi2 {
818 spi2_clk: spi2-clk {
819 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
820 };
821 spi2_cs0: spi2-cs0 {
822 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
823 };
824 spi2_rx: spi2-rx {
825 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
826 };
827 spi2_tx: spi2-tx {
828 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
829 };
830 };
831
832 uart0 {
833 uart0_xfer: uart0-xfer {
834 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
835 <2 25 RK_FUNC_1 &pcfg_pull_none>;
836 };
837
838 uart0_cts: uart0-cts {
839 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
840 };
841
842 uart0_rts: uart0-rts {
843 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
844 };
845 };
846
847 uart1 {
848 uart1_xfer: uart1-xfer {
849 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
850 <0 21 RK_FUNC_3 &pcfg_pull_none>;
851 };
852
853 uart1_cts: uart1-cts {
854 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
855 };
856
857 uart1_rts: uart1-rts {
858 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
859 };
860 };
861
862 uart2 {
863 uart2_xfer: uart2-xfer {
864 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
865 <2 5 RK_FUNC_2 &pcfg_pull_none>;
866 };
867 /* no rts / cts for uart2 */
868 };
869
870 uart3 {
871 uart3_xfer: uart3-xfer {
872 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
873 <3 30 RK_FUNC_3 &pcfg_pull_none>;
874 };
875
876 uart3_cts: uart3-cts {
877 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
878 };
879
880 uart3_rts: uart3-rts {
881 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
882 };
883 };
884
885 uart4 {
886 uart4_xfer: uart4-xfer {
887 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
888 <0 26 RK_FUNC_3 &pcfg_pull_none>;
889 };
890
891 uart4_cts: uart4-cts {
892 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
893 };
894
895 uart4_rts: uart4-rts {
896 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
897 };
898 };
899 };
900};
diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi
index ee34e1a36e03..63894c456969 100644
--- a/arch/arm64/boot/dts/sprd/sc9836.dtsi
+++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi
@@ -16,28 +16,28 @@
16 #address-cells = <2>; 16 #address-cells = <2>;
17 #size-cells = <0>; 17 #size-cells = <0>;
18 18
19 cpu@0 { 19 cpu0: cpu@0 {
20 device_type = "cpu"; 20 device_type = "cpu";
21 compatible = "arm,cortex-a53", "arm,armv8"; 21 compatible = "arm,cortex-a53", "arm,armv8";
22 reg = <0x0 0x0>; 22 reg = <0x0 0x0>;
23 enable-method = "psci"; 23 enable-method = "psci";
24 }; 24 };
25 25
26 cpu@1 { 26 cpu1: cpu@1 {
27 device_type = "cpu"; 27 device_type = "cpu";
28 compatible = "arm,cortex-a53", "arm,armv8"; 28 compatible = "arm,cortex-a53", "arm,armv8";
29 reg = <0x0 0x1>; 29 reg = <0x0 0x1>;
30 enable-method = "psci"; 30 enable-method = "psci";
31 }; 31 };
32 32
33 cpu@2 { 33 cpu2: cpu@2 {
34 device_type = "cpu"; 34 device_type = "cpu";
35 compatible = "arm,cortex-a53", "arm,armv8"; 35 compatible = "arm,cortex-a53", "arm,armv8";
36 reg = <0x0 0x2>; 36 reg = <0x0 0x2>;
37 enable-method = "psci"; 37 enable-method = "psci";
38 }; 38 };
39 39
40 cpu@3 { 40 cpu3: cpu@3 {
41 device_type = "cpu"; 41 device_type = "cpu";
42 compatible = "arm,cortex-a53", "arm,armv8"; 42 compatible = "arm,cortex-a53", "arm,armv8";
43 reg = <0x0 0x3>; 43 reg = <0x0 0x3>;
@@ -75,14 +75,103 @@
75 }; 75 };
76 }; 76 };
77 77
78 /* funnel input port 0~3 is reserved for ETMs */ 78 /* funnel input port 0-4 */
79 port@1 { 79 port@1 {
80 reg = <0>;
81 funnel_in_port0: endpoint {
82 slave-mode;
83 remote-endpoint = <&etm0_out>;
84 };
85 };
86
87 port@2 {
88 reg = <1>;
89 funnel_in_port1: endpoint {
90 slave-mode;
91 remote-endpoint = <&etm1_out>;
92 };
93 };
94
95 port@3 {
96 reg = <2>;
97 funnel_in_port2: endpoint {
98 slave-mode;
99 remote-endpoint = <&etm2_out>;
100 };
101 };
102
103 port@4 {
104 reg = <3>;
105 funnel_in_port3: endpoint {
106 slave-mode;
107 remote-endpoint = <&etm3_out>;
108 };
109 };
110
111 port@5 {
80 reg = <4>; 112 reg = <4>;
81 funnel_in_port4: endpoint { 113 funnel_in_port4: endpoint {
82 slave-mode; 114 slave-mode;
83 remote-endpoint = <&stm_out>; 115 remote-endpoint = <&stm_out>;
84 }; 116 };
85 }; 117 };
118 /* Other input ports aren't connected to anyone */
119 };
120 };
121
122 etm@10440000 {
123 compatible = "arm,coresight-etm4x", "arm,primecell";
124 reg = <0 0x10440000 0 0x1000>;
125
126 cpu = <&cpu0>;
127 clocks = <&clk26mhz>;
128 clock-names = "apb_pclk";
129 port {
130 etm0_out: endpoint {
131 remote-endpoint = <&funnel_in_port0>;
132 };
133 };
134 };
135
136 etm@10540000 {
137 compatible = "arm,coresight-etm4x", "arm,primecell";
138 reg = <0 0x10540000 0 0x1000>;
139
140 cpu = <&cpu1>;
141 clocks = <&clk26mhz>;
142 clock-names = "apb_pclk";
143 port {
144 etm1_out: endpoint {
145 remote-endpoint = <&funnel_in_port1>;
146 };
147 };
148 };
149
150 etm@10640000 {
151 compatible = "arm,coresight-etm4x", "arm,primecell";
152 reg = <0 0x10640000 0 0x1000>;
153
154 cpu = <&cpu2>;
155 clocks = <&clk26mhz>;
156 clock-names = "apb_pclk";
157 port {
158 etm2_out: endpoint {
159 remote-endpoint = <&funnel_in_port2>;
160 };
161 };
162 };
163
164 etm@10740000 {
165 compatible = "arm,coresight-etm4x", "arm,primecell";
166 reg = <0 0x10740000 0 0x1000>;
167
168 cpu = <&cpu3>;
169 clocks = <&clk26mhz>;
170 clock-names = "apb_pclk";
171 port {
172 etm3_out: endpoint {
173 remote-endpoint = <&funnel_in_port3>;
174 };
86 }; 175 };
87 }; 176 };
88 177
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index 0a3f40ecd06d..ce5d848251fa 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -32,6 +32,10 @@
32 }; 32 };
33}; 33};
34 34
35&can0 {
36 status = "okay";
37};
38
35&gem0 { 39&gem0 {
36 status = "okay"; 40 status = "okay";
37 phy-handle = <&phy0>; 41 phy-handle = <&phy0>;
@@ -42,6 +46,91 @@
42 }; 46 };
43}; 47};
44 48
49&gpio {
50 status = "okay";
51};
52
53&i2c0 {
54 status = "okay";
55 clock-frequency = <400000>;
56 eeprom@54 {
57 compatible = "at,24c64";
58 reg = <0x54>;
59 };
60};
61
62&i2c1 {
63 status = "okay";
64 clock-frequency = <400000>;
65 eeprom@55 {
66 compatible = "at,24c64";
67 reg = <0x55>;
68 };
69};
70
71&sata {
72 status = "okay";
73 ceva,broken-gen2;
74};
75
76&sdhci0 {
77 status = "okay";
78};
79
80&sdhci1 {
81 status = "okay";
82};
83
84&spi0 {
85 status = "okay";
86 num-cs = <1>;
87 spi0_flash0: spi0_flash0@0 {
88 compatible = "m25p80";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 spi-max-frequency = <50000000>;
92 reg = <0>;
93
94 spi0_flash0@00000000 {
95 label = "spi0_flash0";
96 reg = <0x0 0x100000>;
97 };
98 };
99};
100
101&spi1 {
102 status = "okay";
103 num-cs = <1>;
104 spi1_flash0: spi1_flash0@0 {
105 compatible = "m25p80";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 spi-max-frequency = <50000000>;
109 reg = <0>;
110
111 spi1_flash0@00000000 {
112 label = "spi1_flash0";
113 reg = <0x0 0x100000>;
114 };
115 };
116};
117
45&uart0 { 118&uart0 {
46 status = "okay"; 119 status = "okay";
47}; 120};
121
122&usb0 {
123 status = "okay";
124 dr_mode = "peripheral";
125 maximum-speed = "high-speed";
126};
127
128&usb1 {
129 status = "okay";
130 dr_mode = "host";
131 maximum-speed = "high-speed";
132};
133
134&watchdog0 {
135 status = "okay";
136};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 11e0b00045cf..857eda5c7217 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -96,74 +96,38 @@
96 #size-cells = <1>; 96 #size-cells = <1>;
97 ranges; 97 ranges;
98 98
99 misc_clk: misc_clk { 99 can0: can@ff060000 {
100 compatible = "fixed-clock"; 100 compatible = "xlnx,zynq-can-1.0";
101 #clock-cells = <0>;
102 clock-frequency = <25000000>;
103 };
104
105 ttc0: timer@ff110000 {
106 compatible = "cdns,ttc";
107 status = "disabled";
108 interrupt-parent = <&gic>;
109 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
110 reg = <0x0 0xff110000 0x1000>;
111 clocks = <&misc_clk>;
112 timer-width = <32>;
113 };
114
115 ttc1: timer@ff120000 {
116 compatible = "cdns,ttc";
117 status = "disabled";
118 interrupt-parent = <&gic>;
119 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
120 reg = <0x0 0xff120000 0x1000>;
121 clocks = <&misc_clk>;
122 timer-width = <32>;
123 };
124
125 ttc2: timer@ff130000 {
126 compatible = "cdns,ttc";
127 status = "disabled";
128 interrupt-parent = <&gic>;
129 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
130 reg = <0x0 0xff130000 0x1000>;
131 clocks = <&misc_clk>;
132 timer-width = <32>;
133 };
134
135 ttc3: timer@ff140000 {
136 compatible = "cdns,ttc";
137 status = "disabled"; 101 status = "disabled";
102 clocks = <&misc_clk &misc_clk>;
103 clock-names = "can_clk", "pclk";
104 reg = <0x0 0xff060000 0x1000>;
105 interrupts = <0 23 4>;
138 interrupt-parent = <&gic>; 106 interrupt-parent = <&gic>;
139 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 107 tx-fifo-depth = <0x40>;
140 reg = <0x0 0xff140000 0x1000>; 108 rx-fifo-depth = <0x40>;
141 clocks = <&misc_clk>;
142 timer-width = <32>;
143 }; 109 };
144 110
145 uart0: serial@ff000000 { 111 can1: can@ff070000 {
146 compatible = "cdns,uart-r1p8"; 112 compatible = "xlnx,zynq-can-1.0";
147 status = "disabled"; 113 status = "disabled";
148 interrupt-parent = <&gic>;
149 interrupts = <0 21 4>;
150 reg = <0x0 0xff000000 0x1000>;
151 clock-names = "uart_clk", "pclk";
152 clocks = <&misc_clk &misc_clk>; 114 clocks = <&misc_clk &misc_clk>;
115 clock-names = "can_clk", "pclk";
116 reg = <0x0 0xff070000 0x1000>;
117 interrupts = <0 24 4>;
118 interrupt-parent = <&gic>;
119 tx-fifo-depth = <0x40>;
120 rx-fifo-depth = <0x40>;
153 }; 121 };
154 122
155 uart1: serial@ff010000 { 123 misc_clk: misc_clk {
156 compatible = "cdns,uart-r1p8"; 124 compatible = "fixed-clock";
157 status = "disabled"; 125 #clock-cells = <0>;
158 interrupt-parent = <&gic>; 126 clock-frequency = <25000000>;
159 interrupts = <0 22 4>;
160 reg = <0x0 0xff010000 0x1000>;
161 clock-names = "uart_clk", "pclk";
162 clocks = <&misc_clk &misc_clk>;
163 }; 127 };
164 128
165 gpio: gpio@ff0a0000 { 129 gpio: gpio@ff0a0000 {
166 compatible = "xlnx,zynq-gpio-1.0"; 130 compatible = "xlnx,zynqmp-gpio-1.0";
167 status = "disabled"; 131 status = "disabled";
168 #gpio-cells = <0x2>; 132 #gpio-cells = <0x2>;
169 clocks = <&misc_clk>; 133 clocks = <&misc_clk>;
@@ -220,30 +184,6 @@
220 #size-cells = <0>; 184 #size-cells = <0>;
221 }; 185 };
222 186
223 spi0: spi@ff040000 {
224 compatible = "cdns,spi-r1p6";
225 status = "disabled";
226 interrupt-parent = <&gic>;
227 interrupts = <0 19 4>;
228 reg = <0x0 0xff040000 0x1000>;
229 clock-names = "ref_clk", "pclk";
230 clocks = <&misc_clk &misc_clk>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 };
234
235 spi1: spi@ff050000 {
236 compatible = "cdns,spi-r1p6";
237 status = "disabled";
238 interrupt-parent = <&gic>;
239 interrupts = <0 20 4>;
240 reg = <0x0 0xff050000 0x1000>;
241 clock-names = "ref_clk", "pclk";
242 clocks = <&misc_clk &misc_clk>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 };
246
247 i2c_clk: i2c_clk { 187 i2c_clk: i2c_clk {
248 compatible = "fixed-clock"; 188 compatible = "fixed-clock";
249 #clock-cells = <0x0>; 189 #clock-cells = <0x0>;
@@ -272,6 +212,21 @@
272 #size-cells = <0>; 212 #size-cells = <0>;
273 }; 213 };
274 214
215 sata_clk: sata_clk {
216 compatible = "fixed-clock";
217 #clock-cells = <0>;
218 clock-frequency = <75000000>;
219 };
220
221 sata: ahci@fd0c0000 {
222 compatible = "ceva,ahci-1v84";
223 status = "disabled";
224 reg = <0x0 0xfd0c0000 0x2000>;
225 interrupt-parent = <&gic>;
226 interrupts = <0 133 4>;
227 clocks = <&sata_clk>;
228 };
229
275 sdhci0: sdhci@ff160000 { 230 sdhci0: sdhci@ff160000 {
276 compatible = "arasan,sdhci-8.9a"; 231 compatible = "arasan,sdhci-8.9a";
277 status = "disabled"; 232 status = "disabled";
@@ -292,6 +247,122 @@
292 clocks = <&misc_clk>, <&misc_clk>; 247 clocks = <&misc_clk>, <&misc_clk>;
293 }; 248 };
294 249
250 smmu: smmu@fd800000 {
251 compatible = "arm,mmu-500";
252 reg = <0x0 0xfd800000 0x20000>;
253 #global-interrupts = <1>;
254 interrupt-parent = <&gic>;
255 interrupts = <0 157 4>,
256 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
257 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
258 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
259 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
260 };
261
262 spi0: spi@ff040000 {
263 compatible = "cdns,spi-r1p6";
264 status = "disabled";
265 interrupt-parent = <&gic>;
266 interrupts = <0 19 4>;
267 reg = <0x0 0xff040000 0x1000>;
268 clock-names = "ref_clk", "pclk";
269 clocks = <&misc_clk &misc_clk>;
270 #address-cells = <1>;
271 #size-cells = <0>;
272 };
273
274 spi1: spi@ff050000 {
275 compatible = "cdns,spi-r1p6";
276 status = "disabled";
277 interrupt-parent = <&gic>;
278 interrupts = <0 20 4>;
279 reg = <0x0 0xff050000 0x1000>;
280 clock-names = "ref_clk", "pclk";
281 clocks = <&misc_clk &misc_clk>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 };
285
286 ttc0: timer@ff110000 {
287 compatible = "cdns,ttc";
288 status = "disabled";
289 interrupt-parent = <&gic>;
290 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
291 reg = <0x0 0xff110000 0x1000>;
292 clocks = <&misc_clk>;
293 timer-width = <32>;
294 };
295
296 ttc1: timer@ff120000 {
297 compatible = "cdns,ttc";
298 status = "disabled";
299 interrupt-parent = <&gic>;
300 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
301 reg = <0x0 0xff120000 0x1000>;
302 clocks = <&misc_clk>;
303 timer-width = <32>;
304 };
305
306 ttc2: timer@ff130000 {
307 compatible = "cdns,ttc";
308 status = "disabled";
309 interrupt-parent = <&gic>;
310 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
311 reg = <0x0 0xff130000 0x1000>;
312 clocks = <&misc_clk>;
313 timer-width = <32>;
314 };
315
316 ttc3: timer@ff140000 {
317 compatible = "cdns,ttc";
318 status = "disabled";
319 interrupt-parent = <&gic>;
320 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
321 reg = <0x0 0xff140000 0x1000>;
322 clocks = <&misc_clk>;
323 timer-width = <32>;
324 };
325
326 uart0: serial@ff000000 {
327 compatible = "cdns,uart-r1p8";
328 status = "disabled";
329 interrupt-parent = <&gic>;
330 interrupts = <0 21 4>;
331 reg = <0x0 0xff000000 0x1000>;
332 clock-names = "uart_clk", "pclk";
333 clocks = <&misc_clk &misc_clk>;
334 };
335
336 uart1: serial@ff010000 {
337 compatible = "cdns,uart-r1p8";
338 status = "disabled";
339 interrupt-parent = <&gic>;
340 interrupts = <0 22 4>;
341 reg = <0x0 0xff010000 0x1000>;
342 clock-names = "uart_clk", "pclk";
343 clocks = <&misc_clk &misc_clk>;
344 };
345
346 usb0: usb@fe200000 {
347 compatible = "snps,dwc3";
348 status = "disabled";
349 interrupt-parent = <&gic>;
350 interrupts = <0 65 4>;
351 reg = <0x0 0xfe200000 0x40000>;
352 clock-names = "clk_xin", "clk_ahb";
353 clocks = <&misc_clk>, <&misc_clk>;
354 };
355
356 usb1: usb@fe300000 {
357 compatible = "snps,dwc3";
358 status = "disabled";
359 interrupt-parent = <&gic>;
360 interrupts = <0 70 4>;
361 reg = <0x0 0xfe300000 0x40000>;
362 clock-names = "clk_xin", "clk_ahb";
363 clocks = <&misc_clk>, <&misc_clk>;
364 };
365
295 watchdog0: watchdog@fd4d0000 { 366 watchdog0: watchdog@fd4d0000 {
296 compatible = "cdns,wdt-r1p2"; 367 compatible = "cdns,wdt-r1p2";
297 status = "disabled"; 368 status = "disabled";
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4e17e7ede33d..34d71dd86781 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -31,10 +31,13 @@ CONFIG_MODULES=y
31CONFIG_MODULE_UNLOAD=y 31CONFIG_MODULE_UNLOAD=y
32# CONFIG_BLK_DEV_BSG is not set 32# CONFIG_BLK_DEV_BSG is not set
33# CONFIG_IOSCHED_DEADLINE is not set 33# CONFIG_IOSCHED_DEADLINE is not set
34CONFIG_ARCH_BCM_IPROC=y
35CONFIG_ARCH_BERLIN=y
34CONFIG_ARCH_EXYNOS7=y 36CONFIG_ARCH_EXYNOS7=y
35CONFIG_ARCH_FSL_LS2085A=y 37CONFIG_ARCH_FSL_LS2085A=y
36CONFIG_ARCH_HISI=y 38CONFIG_ARCH_HISI=y
37CONFIG_ARCH_MEDIATEK=y 39CONFIG_ARCH_MEDIATEK=y
40CONFIG_ARCH_ROCKCHIP=y
38CONFIG_ARCH_SEATTLE=y 41CONFIG_ARCH_SEATTLE=y
39CONFIG_ARCH_TEGRA=y 42CONFIG_ARCH_TEGRA=y
40CONFIG_ARCH_TEGRA_132_SOC=y 43CONFIG_ARCH_TEGRA_132_SOC=y
@@ -102,6 +105,7 @@ CONFIG_SERIO_AMBAKMI=y
102CONFIG_LEGACY_PTY_COUNT=16 105CONFIG_LEGACY_PTY_COUNT=16
103CONFIG_SERIAL_8250=y 106CONFIG_SERIAL_8250=y
104CONFIG_SERIAL_8250_CONSOLE=y 107CONFIG_SERIAL_8250_CONSOLE=y
108CONFIG_SERIAL_8250_DW=y
105CONFIG_SERIAL_8250_MT6577=y 109CONFIG_SERIAL_8250_MT6577=y
106CONFIG_SERIAL_AMBA_PL011=y 110CONFIG_SERIAL_AMBA_PL011=y
107CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 111CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 1272b8002884..d5e58bae95cf 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -117,7 +117,7 @@ config PCI_VERSATILE
117 117
118config PCIE_IPROC 118config PCIE_IPROC
119 tristate "Broadcom iProc PCIe controller" 119 tristate "Broadcom iProc PCIe controller"
120 depends on OF && ARM 120 depends on OF && (ARM || ARM64)
121 default n 121 default n
122 help 122 help
123 This enables the iProc PCIe core controller support for Broadcom's 123 This enables the iProc PCIe core controller support for Broadcom's
@@ -136,7 +136,7 @@ config PCIE_IPROC_PLATFORM
136 136
137config PCIE_IPROC_BCMA 137config PCIE_IPROC_BCMA
138 tristate "Broadcom iProc PCIe BCMA bus driver" 138 tristate "Broadcom iProc PCIe BCMA bus driver"
139 depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST) 139 depends on ARM && (ARCH_BCM_IPROC || COMPILE_TEST)
140 select PCIE_IPROC 140 select PCIE_IPROC
141 select BCMA 141 select BCMA
142 select PCI_DOMAINS 142 select PCI_DOMAINS
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 13:09:34 -0400