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authorAgrawal, Nitesh-kumar <Nitesh-kumar.Agrawal@amd.com>2016-07-26 04:28:19 -0400
committerLinus Walleij <linus.walleij@linaro.org>2016-08-10 09:45:54 -0400
commit8cf4345575a416e6856a6856ac6eaa31ad883126 (patch)
treec7aa1e0c57c8aef17dc84e57a2dbd41a7865ce82
parentb120a3c286520ca465c54e8afa442be10560053b (diff)
pinctrl/amd: Remove the default de-bounce time
In the function amd_gpio_irq_enable() and amd_gpio_direction_input(), remove the code which is setting the default de-bounce time to 2.75ms. The driver code shall use the same settings as specified in BIOS. Any default assignment impacts TouchPad behaviour when the LevelTrig is set to EDGE FALLING. Cc: stable@vger.kernel.org Reviewed-by:  Ken Xue <Ken.Xue@amd.com> Signed-off-by: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--drivers/pinctrl/pinctrl-amd.c20
1 files changed, 0 insertions, 20 deletions
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 634b4d30eefb..b3e772390ab6 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -43,17 +43,6 @@ static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
43 43
44 spin_lock_irqsave(&gpio_dev->lock, flags); 44 spin_lock_irqsave(&gpio_dev->lock, flags);
45 pin_reg = readl(gpio_dev->base + offset * 4); 45 pin_reg = readl(gpio_dev->base + offset * 4);
46 /*
47 * Suppose BIOS or Bootloader sets specific debounce for the
48 * GPIO. if not, set debounce to be 2.75ms and remove glitch.
49 */
50 if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
51 pin_reg |= 0xf;
52 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
53 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
54 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
55 }
56
57 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 46 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
58 writel(pin_reg, gpio_dev->base + offset * 4); 47 writel(pin_reg, gpio_dev->base + offset * 4);
59 spin_unlock_irqrestore(&gpio_dev->lock, flags); 48 spin_unlock_irqrestore(&gpio_dev->lock, flags);
@@ -326,15 +315,6 @@ static void amd_gpio_irq_enable(struct irq_data *d)
326 315
327 spin_lock_irqsave(&gpio_dev->lock, flags); 316 spin_lock_irqsave(&gpio_dev->lock, flags);
328 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 317 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
329 /*
330 Suppose BIOS or Bootloader sets specific debounce for the
331 GPIO. if not, set debounce to be 2.75ms.
332 */
333 if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
334 pin_reg |= 0xf;
335 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
336 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
337 }
338 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 318 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
339 pin_reg |= BIT(INTERRUPT_MASK_OFF); 319 pin_reg |= BIT(INTERRUPT_MASK_OFF);
340 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 320 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);