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authorSinclair Yeh <syeh@vmware.com>2015-07-09 00:20:39 -0400
committerThomas Hellstrom <thellstrom@vmware.com>2015-08-12 13:06:26 -0400
commit8ce75f8ab9044fe11caaaf2b2c82471023212f9f (patch)
treeb63596cd0b9ce2d3ccd11c0e6ac4ac1badc28a67
parent5101020c78c9f242fe77bd7986bc24f7b800172a (diff)
drm/vmwgfx: Update device includes for DX device functionality
Add DX includes and move all device includes to a separate directory. Co-authored with Thomas Hellstrom, Charmaine Lee and above all, the VMware device team. Signed-off-by: Sinclair Yeh <syeh@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Charmaine Lee <charmainel@vmware.com>
Diffstat
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/includeCheck.h3
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_caps.h110
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h2071
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h457
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h1487
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h99
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h50
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h1204
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h1633
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga_escape.h (renamed from drivers/gpu/drm/vmwgfx/svga_escape.h)2
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga_overlay.h (renamed from drivers/gpu/drm/vmwgfx/svga_overlay.h)10
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga_reg.h (renamed from drivers/gpu/drm/vmwgfx/svga_reg.h)499
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/svga_types.h46
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/vm_basic_types.h21
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/vmware_pack_begin.h25
-rw-r--r--drivers/gpu/drm/vmwgfx/device_include/vmware_pack_end.h25
-rw-r--r--drivers/gpu/drm/vmwgfx/svga3d_reg.h2675
-rw-r--r--drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h973
-rw-r--r--drivers/gpu/drm/vmwgfx/svga_types.h48
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_context.c2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c12
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.h2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c1
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_mob.c2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c4
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_reg.h4
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_surface.c2
31 files changed, 7597 insertions, 3879 deletions
diff --git a/drivers/gpu/drm/vmwgfx/device_include/includeCheck.h b/drivers/gpu/drm/vmwgfx/device_include/includeCheck.h
new file mode 100644
index 000000000000..8cce7f15b6eb
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/includeCheck.h
@@ -0,0 +1,3 @@
1/*
2 * Intentionally empty file.
3 */
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_caps.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_caps.h
new file mode 100644
index 000000000000..9ce2466a5d00
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_caps.h
@@ -0,0 +1,110 @@
1/**********************************************************
2 * Copyright 2007-2015 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_caps.h --
28 *
29 * Definitions for SVGA3D hardware capabilities. Capabilities
30 * are used to query for optional rendering features during
31 * driver initialization. The capability data is stored as very
32 * basic key/value dictionary within the "FIFO register" memory
33 * area at the beginning of BAR2.
34 *
35 * Note that these definitions are only for 3D capabilities.
36 * The SVGA device also has "device capabilities" and "FIFO
37 * capabilities", which are non-3D-specific and are stored as
38 * bitfields rather than key/value pairs.
39 */
40
41#ifndef _SVGA3D_CAPS_H_
42#define _SVGA3D_CAPS_H_
43
44#define INCLUDE_ALLOW_MODULE
45#define INCLUDE_ALLOW_USERLEVEL
46
47#include "includeCheck.h"
48
49#include "svga_reg.h"
50
51#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - \
52 SVGA_FIFO_3D_CAPS + 1)
53
54
55/*
56 * SVGA3dCapsRecordType
57 *
58 * Record types that can be found in the caps block.
59 * Related record types are grouped together numerically so that
60 * SVGA3dCaps_FindRecord() can be applied on a range of record
61 * types.
62 */
63
64typedef enum {
65 SVGA3DCAPS_RECORD_UNKNOWN = 0,
66 SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
67 SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
68 SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff,
69} SVGA3dCapsRecordType;
70
71
72/*
73 * SVGA3dCapsRecordHeader
74 *
75 * Header field leading each caps block record. Contains the offset (in
76 * register words, NOT bytes) to the next caps block record (or the end
77 * of caps block records which will be a zero word) and the record type
78 * as defined above.
79 */
80
81typedef
82#include "vmware_pack_begin.h"
83struct SVGA3dCapsRecordHeader {
84 uint32 length;
85 SVGA3dCapsRecordType type;
86}
87#include "vmware_pack_end.h"
88SVGA3dCapsRecordHeader;
89
90
91/*
92 * SVGA3dCapsRecord
93 *
94 * Caps block record; "data" is a placeholder for the actual data structure
95 * contained within the record;
96 */
97
98typedef
99#include "vmware_pack_begin.h"
100struct SVGA3dCapsRecord {
101 SVGA3dCapsRecordHeader header;
102 uint32 data[1];
103}
104#include "vmware_pack_end.h"
105SVGA3dCapsRecord;
106
107
108typedef uint32 SVGA3dCapPair[2];
109
110#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
new file mode 100644
index 000000000000..2dfd57c5f463
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
@@ -0,0 +1,2071 @@
1/**********************************************************
2 * Copyright 1998-2015 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_cmd.h --
28 *
29 * SVGA 3d hardware cmd definitions
30 */
31
32#ifndef _SVGA3D_CMD_H_
33#define _SVGA3D_CMD_H_
34
35#define INCLUDE_ALLOW_MODULE
36#define INCLUDE_ALLOW_USERLEVEL
37#define INCLUDE_ALLOW_VMCORE
38
39#include "includeCheck.h"
40#include "svga3d_types.h"
41
42/*
43 * Identifiers for commands in the command FIFO.
44 *
45 * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
46 * the SVGA3D protocol and remain reserved; they should not be used in the
47 * future.
48 *
49 * IDs between 1040 and 1999 (inclusive) are available for use by the
50 * current SVGA3D protocol.
51 *
52 * FIFO clients other than SVGA3D should stay below 1000, or at 2000
53 * and up.
54 */
55
56typedef enum {
57 SVGA_3D_CMD_LEGACY_BASE = 1000,
58 SVGA_3D_CMD_BASE = 1040,
59
60 SVGA_3D_CMD_SURFACE_DEFINE = 1040,
61 SVGA_3D_CMD_SURFACE_DESTROY = 1041,
62 SVGA_3D_CMD_SURFACE_COPY = 1042,
63 SVGA_3D_CMD_SURFACE_STRETCHBLT = 1043,
64 SVGA_3D_CMD_SURFACE_DMA = 1044,
65 SVGA_3D_CMD_CONTEXT_DEFINE = 1045,
66 SVGA_3D_CMD_CONTEXT_DESTROY = 1046,
67 SVGA_3D_CMD_SETTRANSFORM = 1047,
68 SVGA_3D_CMD_SETZRANGE = 1048,
69 SVGA_3D_CMD_SETRENDERSTATE = 1049,
70 SVGA_3D_CMD_SETRENDERTARGET = 1050,
71 SVGA_3D_CMD_SETTEXTURESTATE = 1051,
72 SVGA_3D_CMD_SETMATERIAL = 1052,
73 SVGA_3D_CMD_SETLIGHTDATA = 1053,
74 SVGA_3D_CMD_SETLIGHTENABLED = 1054,
75 SVGA_3D_CMD_SETVIEWPORT = 1055,
76 SVGA_3D_CMD_SETCLIPPLANE = 1056,
77 SVGA_3D_CMD_CLEAR = 1057,
78 SVGA_3D_CMD_PRESENT = 1058,
79 SVGA_3D_CMD_SHADER_DEFINE = 1059,
80 SVGA_3D_CMD_SHADER_DESTROY = 1060,
81 SVGA_3D_CMD_SET_SHADER = 1061,
82 SVGA_3D_CMD_SET_SHADER_CONST = 1062,
83 SVGA_3D_CMD_DRAW_PRIMITIVES = 1063,
84 SVGA_3D_CMD_SETSCISSORRECT = 1064,
85 SVGA_3D_CMD_BEGIN_QUERY = 1065,
86 SVGA_3D_CMD_END_QUERY = 1066,
87 SVGA_3D_CMD_WAIT_FOR_QUERY = 1067,
88 SVGA_3D_CMD_PRESENT_READBACK = 1068,
89 SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069,
90 SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070,
91 SVGA_3D_CMD_GENERATE_MIPMAPS = 1071,
92 SVGA_3D_CMD_VIDEO_CREATE_DECODER = 1072,
93 SVGA_3D_CMD_VIDEO_DESTROY_DECODER = 1073,
94 SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR = 1074,
95 SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR = 1075,
96 SVGA_3D_CMD_VIDEO_DECODE_START_FRAME = 1076,
97 SVGA_3D_CMD_VIDEO_DECODE_RENDER = 1077,
98 SVGA_3D_CMD_VIDEO_DECODE_END_FRAME = 1078,
99 SVGA_3D_CMD_VIDEO_PROCESS_FRAME = 1079,
100 SVGA_3D_CMD_ACTIVATE_SURFACE = 1080,
101 SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081,
102 SVGA_3D_CMD_SCREEN_DMA = 1082,
103 SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE = 1083,
104 SVGA_3D_CMD_OPEN_CONTEXT_SURFACE = 1084,
105
106 SVGA_3D_CMD_LOGICOPS_BITBLT = 1085,
107 SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1086,
108 SVGA_3D_CMD_LOGICOPS_STRETCHBLT = 1087,
109 SVGA_3D_CMD_LOGICOPS_COLORFILL = 1088,
110 SVGA_3D_CMD_LOGICOPS_ALPHABLEND = 1089,
111 SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND = 1090,
112
113 SVGA_3D_CMD_SET_OTABLE_BASE = 1091,
114 SVGA_3D_CMD_READBACK_OTABLE = 1092,
115
116 SVGA_3D_CMD_DEFINE_GB_MOB = 1093,
117 SVGA_3D_CMD_DESTROY_GB_MOB = 1094,
118 SVGA_3D_CMD_DEAD3 = 1095,
119 SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING = 1096,
120
121 SVGA_3D_CMD_DEFINE_GB_SURFACE = 1097,
122 SVGA_3D_CMD_DESTROY_GB_SURFACE = 1098,
123 SVGA_3D_CMD_BIND_GB_SURFACE = 1099,
124 SVGA_3D_CMD_COND_BIND_GB_SURFACE = 1100,
125 SVGA_3D_CMD_UPDATE_GB_IMAGE = 1101,
126 SVGA_3D_CMD_UPDATE_GB_SURFACE = 1102,
127 SVGA_3D_CMD_READBACK_GB_IMAGE = 1103,
128 SVGA_3D_CMD_READBACK_GB_SURFACE = 1104,
129 SVGA_3D_CMD_INVALIDATE_GB_IMAGE = 1105,
130 SVGA_3D_CMD_INVALIDATE_GB_SURFACE = 1106,
131
132 SVGA_3D_CMD_DEFINE_GB_CONTEXT = 1107,
133 SVGA_3D_CMD_DESTROY_GB_CONTEXT = 1108,
134 SVGA_3D_CMD_BIND_GB_CONTEXT = 1109,
135 SVGA_3D_CMD_READBACK_GB_CONTEXT = 1110,
136 SVGA_3D_CMD_INVALIDATE_GB_CONTEXT = 1111,
137
138 SVGA_3D_CMD_DEFINE_GB_SHADER = 1112,
139 SVGA_3D_CMD_DESTROY_GB_SHADER = 1113,
140 SVGA_3D_CMD_BIND_GB_SHADER = 1114,
141
142 SVGA_3D_CMD_SET_OTABLE_BASE64 = 1115,
143
144 SVGA_3D_CMD_BEGIN_GB_QUERY = 1116,
145 SVGA_3D_CMD_END_GB_QUERY = 1117,
146 SVGA_3D_CMD_WAIT_FOR_GB_QUERY = 1118,
147
148 SVGA_3D_CMD_NOP = 1119,
149
150 SVGA_3D_CMD_ENABLE_GART = 1120,
151 SVGA_3D_CMD_DISABLE_GART = 1121,
152 SVGA_3D_CMD_MAP_MOB_INTO_GART = 1122,
153 SVGA_3D_CMD_UNMAP_GART_RANGE = 1123,
154
155 SVGA_3D_CMD_DEFINE_GB_SCREENTARGET = 1124,
156 SVGA_3D_CMD_DESTROY_GB_SCREENTARGET = 1125,
157 SVGA_3D_CMD_BIND_GB_SCREENTARGET = 1126,
158 SVGA_3D_CMD_UPDATE_GB_SCREENTARGET = 1127,
159
160 SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL = 1128,
161 SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL = 1129,
162
163 SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE = 1130,
164
165 SVGA_3D_CMD_GB_SCREEN_DMA = 1131,
166 SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH = 1132,
167 SVGA_3D_CMD_GB_MOB_FENCE = 1133,
168 SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 = 1134,
169 SVGA_3D_CMD_DEFINE_GB_MOB64 = 1135,
170 SVGA_3D_CMD_REDEFINE_GB_MOB64 = 1136,
171 SVGA_3D_CMD_NOP_ERROR = 1137,
172
173 SVGA_3D_CMD_SET_VERTEX_STREAMS = 1138,
174 SVGA_3D_CMD_SET_VERTEX_DECLS = 1139,
175 SVGA_3D_CMD_SET_VERTEX_DIVISORS = 1140,
176 SVGA_3D_CMD_DRAW = 1141,
177 SVGA_3D_CMD_DRAW_INDEXED = 1142,
178
179 /*
180 * DX10 Commands
181 */
182 SVGA_3D_CMD_DX_MIN = 1143,
183 SVGA_3D_CMD_DX_DEFINE_CONTEXT = 1143,
184 SVGA_3D_CMD_DX_DESTROY_CONTEXT = 1144,
185 SVGA_3D_CMD_DX_BIND_CONTEXT = 1145,
186 SVGA_3D_CMD_DX_READBACK_CONTEXT = 1146,
187 SVGA_3D_CMD_DX_INVALIDATE_CONTEXT = 1147,
188 SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER = 1148,
189 SVGA_3D_CMD_DX_SET_SHADER_RESOURCES = 1149,
190 SVGA_3D_CMD_DX_SET_SHADER = 1150,
191 SVGA_3D_CMD_DX_SET_SAMPLERS = 1151,
192 SVGA_3D_CMD_DX_DRAW = 1152,
193 SVGA_3D_CMD_DX_DRAW_INDEXED = 1153,
194 SVGA_3D_CMD_DX_DRAW_INSTANCED = 1154,
195 SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED = 1155,
196 SVGA_3D_CMD_DX_DRAW_AUTO = 1156,
197 SVGA_3D_CMD_DX_SET_INPUT_LAYOUT = 1157,
198 SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS = 1158,
199 SVGA_3D_CMD_DX_SET_INDEX_BUFFER = 1159,
200 SVGA_3D_CMD_DX_SET_TOPOLOGY = 1160,
201 SVGA_3D_CMD_DX_SET_RENDERTARGETS = 1161,
202 SVGA_3D_CMD_DX_SET_BLEND_STATE = 1162,
203 SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE = 1163,
204 SVGA_3D_CMD_DX_SET_RASTERIZER_STATE = 1164,
205 SVGA_3D_CMD_DX_DEFINE_QUERY = 1165,
206 SVGA_3D_CMD_DX_DESTROY_QUERY = 1166,
207 SVGA_3D_CMD_DX_BIND_QUERY = 1167,
208 SVGA_3D_CMD_DX_SET_QUERY_OFFSET = 1168,
209 SVGA_3D_CMD_DX_BEGIN_QUERY = 1169,
210 SVGA_3D_CMD_DX_END_QUERY = 1170,
211 SVGA_3D_CMD_DX_READBACK_QUERY = 1171,
212 SVGA_3D_CMD_DX_SET_PREDICATION = 1172,
213 SVGA_3D_CMD_DX_SET_SOTARGETS = 1173,
214 SVGA_3D_CMD_DX_SET_VIEWPORTS = 1174,
215 SVGA_3D_CMD_DX_SET_SCISSORRECTS = 1175,
216 SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW = 1176,
217 SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177,
218 SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178,
219 SVGA_3D_CMD_DX_PRED_COPY = 1179,
220 SVGA_3D_CMD_DX_STRETCHBLT = 1180,
221 SVGA_3D_CMD_DX_GENMIPS = 1181,
222 SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182,
223 SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183,
224 SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE = 1184,
225 SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW = 1185,
226 SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW = 1186,
227 SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW = 1187,
228 SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW = 1188,
229 SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW = 1189,
230 SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW = 1190,
231 SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT = 1191,
232 SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT = 1192,
233 SVGA_3D_CMD_DX_DEFINE_BLEND_STATE = 1193,
234 SVGA_3D_CMD_DX_DESTROY_BLEND_STATE = 1194,
235 SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE = 1195,
236 SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE = 1196,
237 SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE = 1197,
238 SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE = 1198,
239 SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE = 1199,
240 SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE = 1200,
241 SVGA_3D_CMD_DX_DEFINE_SHADER = 1201,
242 SVGA_3D_CMD_DX_DESTROY_SHADER = 1202,
243 SVGA_3D_CMD_DX_BIND_SHADER = 1203,
244 SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT = 1204,
245 SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT = 1205,
246 SVGA_3D_CMD_DX_SET_STREAMOUTPUT = 1206,
247 SVGA_3D_CMD_DX_SET_COTABLE = 1207,
248 SVGA_3D_CMD_DX_READBACK_COTABLE = 1208,
249 SVGA_3D_CMD_DX_BUFFER_COPY = 1209,
250 SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER = 1210,
251 SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK = 1211,
252 SVGA_3D_CMD_DX_MOVE_QUERY = 1212,
253 SVGA_3D_CMD_DX_BIND_ALL_QUERY = 1213,
254 SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214,
255 SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215,
256 SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216,
257 SVGA_3D_CMD_DX_BIND_SHADER_ON_CONTEXT = 1217,
258 SVGA_3D_CMD_DX_HINT = 1218,
259 SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219,
260 SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220,
261 SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET = 1221,
262 SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222,
263
264 /*
265 * Reserve some IDs to be used for the DX11 shader types.
266 */
267 SVGA_3D_CMD_DX_RESERVED1 = 1223,
268 SVGA_3D_CMD_DX_RESERVED2 = 1224,
269 SVGA_3D_CMD_DX_RESERVED3 = 1225,
270
271 SVGA_3D_CMD_DX_MAX = 1226,
272 SVGA_3D_CMD_MAX = 1226,
273 SVGA_3D_CMD_FUTURE_MAX = 3000
274} SVGAFifo3dCmdId;
275
276/*
277 * FIFO command format definitions:
278 */
279
280/*
281 * The data size header following cmdNum for every 3d command
282 */
283typedef
284#include "vmware_pack_begin.h"
285struct {
286 uint32 id;
287 uint32 size;
288}
289#include "vmware_pack_end.h"
290SVGA3dCmdHeader;
291
292typedef
293#include "vmware_pack_begin.h"
294struct {
295 uint32 numMipLevels;
296}
297#include "vmware_pack_end.h"
298SVGA3dSurfaceFace;
299
300typedef
301#include "vmware_pack_begin.h"
302struct {
303 uint32 sid;
304 SVGA3dSurfaceFlags surfaceFlags;
305 SVGA3dSurfaceFormat format;
306 /*
307 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
308 * structures must have the same value of numMipLevels field.
309 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
310 * numMipLevels set to 0.
311 */
312 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
313 /*
314 * Followed by an SVGA3dSize structure for each mip level in each face.
315 *
316 * A note on surface sizes: Sizes are always specified in pixels,
317 * even if the true surface size is not a multiple of the minimum
318 * block size of the surface's format. For example, a 3x3x1 DXT1
319 * compressed texture would actually be stored as a 4x4x1 image in
320 * memory.
321 */
322}
323#include "vmware_pack_end.h"
324SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
325
326typedef
327#include "vmware_pack_begin.h"
328struct {
329 uint32 sid;
330 SVGA3dSurfaceFlags surfaceFlags;
331 SVGA3dSurfaceFormat format;
332 /*
333 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
334 * structures must have the same value of numMipLevels field.
335 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
336 * numMipLevels set to 0.
337 */
338 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
339 uint32 multisampleCount;
340 SVGA3dTextureFilter autogenFilter;
341 /*
342 * Followed by an SVGA3dSize structure for each mip level in each face.
343 *
344 * A note on surface sizes: Sizes are always specified in pixels,
345 * even if the true surface size is not a multiple of the minimum
346 * block size of the surface's format. For example, a 3x3x1 DXT1
347 * compressed texture would actually be stored as a 4x4x1 image in
348 * memory.
349 */
350}
351#include "vmware_pack_end.h"
352SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
353
354typedef
355#include "vmware_pack_begin.h"
356struct {
357 uint32 sid;
358}
359#include "vmware_pack_end.h"
360SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
361
362typedef
363#include "vmware_pack_begin.h"
364struct {
365 uint32 cid;
366}
367#include "vmware_pack_end.h"
368SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
369
370typedef
371#include "vmware_pack_begin.h"
372struct {
373 uint32 cid;
374}
375#include "vmware_pack_end.h"
376SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
377
378typedef
379#include "vmware_pack_begin.h"
380struct {
381 uint32 cid;
382 SVGA3dClearFlag clearFlag;
383 uint32 color;
384 float depth;
385 uint32 stencil;
386 /* Followed by variable number of SVGA3dRect structures */
387}
388#include "vmware_pack_end.h"
389SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
390
391typedef
392#include "vmware_pack_begin.h"
393struct {
394 SVGA3dLightType type;
395 SVGA3dBool inWorldSpace;
396 float diffuse[4];
397 float specular[4];
398 float ambient[4];
399 float position[4];
400 float direction[4];
401 float range;
402 float falloff;
403 float attenuation0;
404 float attenuation1;
405 float attenuation2;
406 float theta;
407 float phi;
408}
409#include "vmware_pack_end.h"
410SVGA3dLightData;
411
412typedef
413#include "vmware_pack_begin.h"
414struct {
415 uint32 sid;
416 /* Followed by variable number of SVGA3dCopyRect structures */
417}
418#include "vmware_pack_end.h"
419SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
420
421typedef
422#include "vmware_pack_begin.h"
423struct {
424 SVGA3dRenderStateName state;
425 union {
426 uint32 uintValue;
427 float floatValue;
428 };
429}
430#include "vmware_pack_end.h"
431SVGA3dRenderState;
432
433typedef
434#include "vmware_pack_begin.h"
435struct {
436 uint32 cid;
437 /* Followed by variable number of SVGA3dRenderState structures */
438}
439#include "vmware_pack_end.h"
440SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
441
442typedef
443#include "vmware_pack_begin.h"
444struct {
445 uint32 cid;
446 SVGA3dRenderTargetType type;
447 SVGA3dSurfaceImageId target;
448}
449#include "vmware_pack_end.h"
450SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
451
452typedef
453#include "vmware_pack_begin.h"
454struct {
455 SVGA3dSurfaceImageId src;
456 SVGA3dSurfaceImageId dest;
457 /* Followed by variable number of SVGA3dCopyBox structures */
458}
459#include "vmware_pack_end.h"
460SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
461
462typedef
463#include "vmware_pack_begin.h"
464struct {
465 SVGA3dSurfaceImageId src;
466 SVGA3dSurfaceImageId dest;
467 SVGA3dBox boxSrc;
468 SVGA3dBox boxDest;
469 SVGA3dStretchBltMode mode;
470}
471#include "vmware_pack_end.h"
472SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
473
474typedef
475#include "vmware_pack_begin.h"
476struct {
477 /*
478 * If the discard flag is present in a surface DMA operation, the host may
479 * discard the contents of the current mipmap level and face of the target
480 * surface before applying the surface DMA contents.
481 */
482 uint32 discard : 1;
483
484 /*
485 * If the unsynchronized flag is present, the host may perform this upload
486 * without syncing to pending reads on this surface.
487 */
488 uint32 unsynchronized : 1;
489
490 /*
491 * Guests *MUST* set the reserved bits to 0 before submitting the command
492 * suffix as future flags may occupy these bits.
493 */
494 uint32 reserved : 30;
495}
496#include "vmware_pack_end.h"
497SVGA3dSurfaceDMAFlags;
498
499typedef
500#include "vmware_pack_begin.h"
501struct {
502 SVGAGuestImage guest;
503 SVGA3dSurfaceImageId host;
504 SVGA3dTransferType transfer;
505 /*
506 * Followed by variable number of SVGA3dCopyBox structures. For consistency
507 * in all clipping logic and coordinate translation, we define the
508 * "source" in each copyBox as the guest image and the
509 * "destination" as the host image, regardless of transfer
510 * direction.
511 *
512 * For efficiency, the SVGA3D device is free to copy more data than
513 * specified. For example, it may round copy boxes outwards such
514 * that they lie on particular alignment boundaries.
515 */
516}
517#include "vmware_pack_end.h"
518SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
519
520/*
521 * SVGA3dCmdSurfaceDMASuffix --
522 *
523 * This is a command suffix that will appear after a SurfaceDMA command in
524 * the FIFO. It contains some extra information that hosts may use to
525 * optimize performance or protect the guest. This suffix exists to preserve
526 * backwards compatibility while also allowing for new functionality to be
527 * implemented.
528 */
529
530typedef
531#include "vmware_pack_begin.h"
532struct {
533 uint32 suffixSize;
534
535 /*
536 * The maximum offset is used to determine the maximum offset from the
537 * guestPtr base address that will be accessed or written to during this
538 * surfaceDMA. If the suffix is supported, the host will respect this
539 * boundary while performing surface DMAs.
540 *
541 * Defaults to MAX_UINT32
542 */
543 uint32 maximumOffset;
544
545 /*
546 * A set of flags that describes optimizations that the host may perform
547 * while performing this surface DMA operation. The guest should never rely
548 * on behaviour that is different when these flags are set for correctness.
549 *
550 * Defaults to 0
551 */
552 SVGA3dSurfaceDMAFlags flags;
553}
554#include "vmware_pack_end.h"
555SVGA3dCmdSurfaceDMASuffix;
556
557/*
558 * SVGA_3D_CMD_DRAW_PRIMITIVES --
559 *
560 * This command is the SVGA3D device's generic drawing entry point.
561 * It can draw multiple ranges of primitives, optionally using an
562 * index buffer, using an arbitrary collection of vertex buffers.
563 *
564 * Each SVGA3dVertexDecl defines a distinct vertex array to bind
565 * during this draw call. The declarations specify which surface
566 * the vertex data lives in, what that vertex data is used for,
567 * and how to interpret it.
568 *
569 * Each SVGA3dPrimitiveRange defines a collection of primitives
570 * to render using the same vertex arrays. An index buffer is
571 * optional.
572 */
573
574typedef
575#include "vmware_pack_begin.h"
576struct {
577 /*
578 * A range hint is an optional specification for the range of indices
579 * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
580 * that the entire array will be used.
581 *
582 * These are only hints. The SVGA3D device may use them for
583 * performance optimization if possible, but it's also allowed to
584 * ignore these values.
585 */
586 uint32 first;
587 uint32 last;
588}
589#include "vmware_pack_end.h"
590SVGA3dArrayRangeHint;
591
592typedef
593#include "vmware_pack_begin.h"
594struct {
595 /*
596 * Define the origin and shape of a vertex or index array. Both
597 * 'offset' and 'stride' are in bytes. The provided surface will be
598 * reinterpreted as a flat array of bytes in the same format used
599 * by surface DMA operations. To avoid unnecessary conversions, the
600 * surface should be created with the SVGA3D_BUFFER format.
601 *
602 * Index 0 in the array starts 'offset' bytes into the surface.
603 * Index 1 begins at byte 'offset + stride', etc. Array indices may
604 * not be negative.
605 */
606 uint32 surfaceId;
607 uint32 offset;
608 uint32 stride;
609}
610#include "vmware_pack_end.h"
611SVGA3dArray;
612
613typedef
614#include "vmware_pack_begin.h"
615struct {
616 /*
617 * Describe a vertex array's data type, and define how it is to be
618 * used by the fixed function pipeline or the vertex shader. It
619 * isn't useful to have two VertexDecls with the same
620 * VertexArrayIdentity in one draw call.
621 */
622 SVGA3dDeclType type;
623 SVGA3dDeclMethod method;
624 SVGA3dDeclUsage usage;
625 uint32 usageIndex;
626}
627#include "vmware_pack_end.h"
628SVGA3dVertexArrayIdentity;
629
630typedef
631#include "vmware_pack_begin.h"
632struct SVGA3dVertexDecl {
633 SVGA3dVertexArrayIdentity identity;
634 SVGA3dArray array;
635 SVGA3dArrayRangeHint rangeHint;
636}
637#include "vmware_pack_end.h"
638SVGA3dVertexDecl;
639
640typedef
641#include "vmware_pack_begin.h"
642struct SVGA3dPrimitiveRange {
643 /*
644 * Define a group of primitives to render, from sequential indices.
645 *
646 * The value of 'primitiveType' and 'primitiveCount' imply the
647 * total number of vertices that will be rendered.
648 */
649 SVGA3dPrimitiveType primType;
650 uint32 primitiveCount;
651
652 /*
653 * Optional index buffer. If indexArray.surfaceId is
654 * SVGA3D_INVALID_ID, we render without an index buffer. Rendering
655 * without an index buffer is identical to rendering with an index
656 * buffer containing the sequence [0, 1, 2, 3, ...].
657 *
658 * If an index buffer is in use, indexWidth specifies the width in
659 * bytes of each index value. It must be less than or equal to
660 * indexArray.stride.
661 *
662 * (Currently, the SVGA3D device requires index buffers to be tightly
663 * packed. In other words, indexWidth == indexArray.stride)
664 */
665 SVGA3dArray indexArray;
666 uint32 indexWidth;
667
668 /*
669 * Optional index bias. This number is added to all indices from
670 * indexArray before they are used as vertex array indices. This
671 * can be used in multiple ways:
672 *
673 * - When not using an indexArray, this bias can be used to
674 * specify where in the vertex arrays to begin rendering.
675 *
676 * - A positive number here is equivalent to increasing the
677 * offset in each vertex array.
678 *
679 * - A negative number can be used to render using a small
680 * vertex array and an index buffer that contains large
681 * values. This may be used by some applications that
682 * crop a vertex buffer without modifying their index
683 * buffer.
684 *
685 * Note that rendering with a negative bias value may be slower and
686 * use more memory than rendering with a positive or zero bias.
687 */
688 int32 indexBias;
689}
690#include "vmware_pack_end.h"
691SVGA3dPrimitiveRange;
692
693typedef
694#include "vmware_pack_begin.h"
695struct {
696 uint32 cid;
697 uint32 numVertexDecls;
698 uint32 numRanges;
699
700 /*
701 * There are two variable size arrays after the
702 * SVGA3dCmdDrawPrimitives structure. In order,
703 * they are:
704 *
705 * 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
706 * SVGA3D_MAX_VERTEX_ARRAYS;
707 * 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
708 * SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
709 * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
710 * the frequency divisor for the corresponding vertex decl).
711 */
712}
713#include "vmware_pack_end.h"
714SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
715
716typedef
717#include "vmware_pack_begin.h"
718struct {
719 uint32 cid;
720
721 uint32 primitiveCount; /* How many primitives to render */
722 uint32 startVertexLocation; /* Which vertex do we start rendering at. */
723
724 uint8 primitiveType; /* SVGA3dPrimitiveType */
725 uint8 padding[3];
726}
727#include "vmware_pack_end.h"
728SVGA3dCmdDraw;
729
730typedef
731#include "vmware_pack_begin.h"
732struct {
733 uint32 cid;
734
735 uint8 primitiveType; /* SVGA3dPrimitiveType */
736
737 uint32 indexBufferSid; /* Valid index buffer sid. */
738 uint32 indexBufferOffset; /* Byte offset into the vertex buffer, almost */
739 /* always 0 for DX9 guests, non-zero for OpenGL */
740 /* guests. We can't represent non-multiple of */
741 /* stride offsets in D3D9Renderer... */
742 uint8 indexBufferStride; /* Allowable values = 1, 2, or 4 */
743
744 int32 baseVertexLocation; /* Bias applied to the index when selecting a */
745 /* vertex from the streams, may be negative */
746
747 uint32 primitiveCount; /* How many primitives to render */
748 uint32 pad0;
749 uint16 pad1;
750}
751#include "vmware_pack_end.h"
752SVGA3dCmdDrawIndexed;
753
754typedef
755#include "vmware_pack_begin.h"
756struct {
757 /*
758 * Describe a vertex array's data type, and define how it is to be
759 * used by the fixed function pipeline or the vertex shader. It
760 * isn't useful to have two VertexDecls with the same
761 * VertexArrayIdentity in one draw call.
762 */
763 uint16 streamOffset;
764 uint8 stream;
765 uint8 type; /* SVGA3dDeclType */
766 uint8 method; /* SVGA3dDeclMethod */
767 uint8 usage; /* SVGA3dDeclUsage */
768 uint8 usageIndex;
769 uint8 padding;
770
771}
772#include "vmware_pack_end.h"
773SVGA3dVertexElement;
774
775typedef
776#include "vmware_pack_begin.h"
777struct {
778 uint32 cid;
779
780 uint32 numElements;
781
782 /*
783 * Followed by numElements SVGA3dVertexElement structures.
784 *
785 * If numElements < SVGA3D_MAX_VERTEX_ARRAYS, the remaining elements
786 * are cleared and will not be used by following draws.
787 */
788}
789#include "vmware_pack_end.h"
790SVGA3dCmdSetVertexDecls;
791
792typedef
793#include "vmware_pack_begin.h"
794struct {
795 uint32 sid;
796 uint32 stride;
797 uint32 offset;
798}
799#include "vmware_pack_end.h"
800SVGA3dVertexStream;
801
802typedef
803#include "vmware_pack_begin.h"
804struct {
805 uint32 cid;
806
807 uint32 numStreams;
808 /*
809 * Followed by numStream SVGA3dVertexStream structures.
810 *
811 * If numStreams < SVGA3D_MAX_VERTEX_ARRAYS, the remaining streams
812 * are cleared and will not be used by following draws.
813 */
814}
815#include "vmware_pack_end.h"
816SVGA3dCmdSetVertexStreams;
817
818typedef
819#include "vmware_pack_begin.h"
820struct {
821 uint32 cid;
822 uint32 numDivisors;
823}
824#include "vmware_pack_end.h"
825SVGA3dCmdSetVertexDivisors;
826
827typedef
828#include "vmware_pack_begin.h"
829struct {
830 uint32 stage;
831 SVGA3dTextureStateName name;
832 union {
833 uint32 value;
834 float floatValue;
835 };
836}
837#include "vmware_pack_end.h"
838SVGA3dTextureState;
839
840typedef
841#include "vmware_pack_begin.h"
842struct {
843 uint32 cid;
844 /* Followed by variable number of SVGA3dTextureState structures */
845}
846#include "vmware_pack_end.h"
847SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
848
849typedef
850#include "vmware_pack_begin.h"
851struct {
852 uint32 cid;
853 SVGA3dTransformType type;
854 float matrix[16];
855}
856#include "vmware_pack_end.h"
857SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
858
859typedef
860#include "vmware_pack_begin.h"
861struct {
862 float min;
863 float max;
864}
865#include "vmware_pack_end.h"
866SVGA3dZRange;
867
868typedef
869#include "vmware_pack_begin.h"
870struct {
871 uint32 cid;
872 SVGA3dZRange zRange;
873}
874#include "vmware_pack_end.h"
875SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
876
877typedef
878#include "vmware_pack_begin.h"
879struct {
880 float diffuse[4];
881 float ambient[4];
882 float specular[4];
883 float emissive[4];
884 float shininess;
885}
886#include "vmware_pack_end.h"
887SVGA3dMaterial;
888
889typedef
890#include "vmware_pack_begin.h"
891struct {
892 uint32 cid;
893 SVGA3dFace face;
894 SVGA3dMaterial material;
895}
896#include "vmware_pack_end.h"
897SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
898
899typedef
900#include "vmware_pack_begin.h"
901struct {
902 uint32 cid;
903 uint32 index;
904 SVGA3dLightData data;
905}
906#include "vmware_pack_end.h"
907SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
908
909typedef
910#include "vmware_pack_begin.h"
911struct {
912 uint32 cid;
913 uint32 index;
914 uint32 enabled;
915}
916#include "vmware_pack_end.h"
917SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
918
919typedef
920#include "vmware_pack_begin.h"
921struct {
922 uint32 cid;
923 SVGA3dRect rect;
924}
925#include "vmware_pack_end.h"
926SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
927
928typedef
929#include "vmware_pack_begin.h"
930struct {
931 uint32 cid;
932 SVGA3dRect rect;
933}
934#include "vmware_pack_end.h"
935SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
936
937typedef
938#include "vmware_pack_begin.h"
939struct {
940 uint32 cid;
941 uint32 index;
942 float plane[4];
943}
944#include "vmware_pack_end.h"
945SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
946
947typedef
948#include "vmware_pack_begin.h"
949struct {
950 uint32 cid;
951 uint32 shid;
952 SVGA3dShaderType type;
953 /* Followed by variable number of DWORDs for shader bycode */
954}
955#include "vmware_pack_end.h"
956SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
957
958typedef
959#include "vmware_pack_begin.h"
960struct {
961 uint32 cid;
962 uint32 shid;
963 SVGA3dShaderType type;
964}
965#include "vmware_pack_end.h"
966SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
967
968typedef
969#include "vmware_pack_begin.h"
970struct {
971 uint32 cid;
972 uint32 reg; /* register number */
973 SVGA3dShaderType type;
974 SVGA3dShaderConstType ctype;
975 uint32 values[4];
976
977 /*
978 * Followed by a variable number of additional values.
979 */
980}
981#include "vmware_pack_end.h"
982SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
983
984typedef
985#include "vmware_pack_begin.h"
986struct {
987 uint32 cid;
988 SVGA3dShaderType type;
989 uint32 shid;
990}
991#include "vmware_pack_end.h"
992SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
993
994typedef
995#include "vmware_pack_begin.h"
996struct {
997 uint32 cid;
998 SVGA3dQueryType type;
999}
1000#include "vmware_pack_end.h"
1001SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
1002
1003typedef
1004#include "vmware_pack_begin.h"
1005struct {
1006 uint32 cid;
1007 SVGA3dQueryType type;
1008 SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
1009}
1010#include "vmware_pack_end.h"
1011SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
1012
1013
1014/*
1015 * SVGA3D_CMD_WAIT_FOR_QUERY --
1016 *
1017 * Will read the SVGA3dQueryResult structure pointed to by guestResult,
1018 * and if the state member is set to anything else than
1019 * SVGA3D_QUERYSTATE_PENDING, this command will always be a no-op.
1020 *
1021 * Otherwise, in addition to the query explicitly waited for,
1022 * All queries with the same type and issued with the same cid, for which
1023 * an SVGA_3D_CMD_END_QUERY command has previously been sent, will
1024 * be finished after execution of this command.
1025 *
1026 * A query will be identified by the gmrId and offset of the guestResult
1027 * member. If the device can't find an SVGA_3D_CMD_END_QUERY that has
1028 * been sent previously with an indentical gmrId and offset, it will
1029 * effectively end all queries with an identical type issued with the
1030 * same cid, and the SVGA3dQueryResult structure pointed to by
1031 * guestResult will not be written to. This property can be used to
1032 * implement a query barrier for a given cid and query type.
1033 */
1034
1035typedef
1036#include "vmware_pack_begin.h"
1037struct {
1038 uint32 cid; /* Same parameters passed to END_QUERY */
1039 SVGA3dQueryType type;
1040 SVGAGuestPtr guestResult;
1041}
1042#include "vmware_pack_end.h"
1043SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
1044
1045typedef
1046#include "vmware_pack_begin.h"
1047struct {
1048 uint32 totalSize; /* Set by guest before query is ended. */
1049 SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
1050 union { /* Set by host on exit from PENDING state */
1051 uint32 result32;
1052 uint32 queryCookie; /* May be used to identify which QueryGetData this
1053 result corresponds to. */
1054 };
1055}
1056#include "vmware_pack_end.h"
1057SVGA3dQueryResult;
1058
1059
1060/*
1061 * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
1062 *
1063 * This is a blit from an SVGA3D surface to a Screen Object.
1064 * This blit must be directed at a specific screen.
1065 *
1066 * The blit copies from a rectangular region of an SVGA3D surface
1067 * image to a rectangular region of a screen.
1068 *
1069 * This command takes an optional variable-length list of clipping
1070 * rectangles after the body of the command. If no rectangles are
1071 * specified, there is no clipping region. The entire destRect is
1072 * drawn to. If one or more rectangles are included, they describe
1073 * a clipping region. The clip rectangle coordinates are measured
1074 * relative to the top-left corner of destRect.
1075 *
1076 * The srcImage must be from mip=0 face=0.
1077 *
1078 * This supports scaling if the src and dest are of different sizes.
1079 *
1080 * Availability:
1081 * SVGA_FIFO_CAP_SCREEN_OBJECT
1082 */
1083
1084typedef
1085#include "vmware_pack_begin.h"
1086struct {
1087 SVGA3dSurfaceImageId srcImage;
1088 SVGASignedRect srcRect;
1089 uint32 destScreenId; /* Screen Object ID */
1090 SVGASignedRect destRect;
1091 /* Clipping: zero or more SVGASignedRects follow */
1092}
1093#include "vmware_pack_end.h"
1094SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
1095
1096typedef
1097#include "vmware_pack_begin.h"
1098struct {
1099 uint32 sid;
1100 SVGA3dTextureFilter filter;
1101}
1102#include "vmware_pack_end.h"
1103SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
1104
1105
1106
1107typedef
1108#include "vmware_pack_begin.h"
1109struct {
1110 uint32 sid;
1111}
1112#include "vmware_pack_end.h"
1113SVGA3dCmdActivateSurface; /* SVGA_3D_CMD_ACTIVATE_SURFACE */
1114
1115typedef
1116#include "vmware_pack_begin.h"
1117struct {
1118 uint32 sid;
1119}
1120#include "vmware_pack_end.h"
1121SVGA3dCmdDeactivateSurface; /* SVGA_3D_CMD_DEACTIVATE_SURFACE */
1122
1123/*
1124 * Screen DMA command
1125 *
1126 * Available with SVGA_FIFO_CAP_SCREEN_OBJECT_2. The SVGA_CAP_3D device
1127 * cap bit is not required.
1128 *
1129 * - refBuffer and destBuffer are 32bit BGRX; refBuffer and destBuffer could
1130 * be different, but it is required that guest makes sure refBuffer has
1131 * exactly the same contents that were written to when last time screen DMA
1132 * command is received by host.
1133 *
1134 * - changemap is generated by lib/blit, and it has the changes from last
1135 * received screen DMA or more.
1136 */
1137
1138typedef
1139#include "vmware_pack_begin.h"
1140struct SVGA3dCmdScreenDMA {
1141 uint32 screenId;
1142 SVGAGuestImage refBuffer;
1143 SVGAGuestImage destBuffer;
1144 SVGAGuestImage changeMap;
1145}
1146#include "vmware_pack_end.h"
1147SVGA3dCmdScreenDMA; /* SVGA_3D_CMD_SCREEN_DMA */
1148
1149/*
1150 * Set Unity Surface Cookie
1151 *
1152 * Associates the supplied cookie with the surface id for use with
1153 * Unity. This cookie is a hint from guest to host, there is no way
1154 * for the guest to readback the cookie and the host is free to drop
1155 * the cookie association at will. The default value for the cookie
1156 * on all surfaces is 0.
1157 */
1158
1159typedef
1160#include "vmware_pack_begin.h"
1161struct SVGA3dCmdSetUnitySurfaceCookie {
1162 uint32 sid;
1163 uint64 cookie;
1164}
1165#include "vmware_pack_end.h"
1166SVGA3dCmdSetUnitySurfaceCookie; /* SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE */
1167
1168/*
1169 * Open a context-specific surface in a non-context-specific manner.
1170 */
1171
1172typedef
1173#include "vmware_pack_begin.h"
1174struct SVGA3dCmdOpenContextSurface {
1175 uint32 sid;
1176}
1177#include "vmware_pack_end.h"
1178SVGA3dCmdOpenContextSurface; /* SVGA_3D_CMD_OPEN_CONTEXT_SURFACE */
1179
1180
1181/*
1182 * Logic ops
1183 */
1184
1185#define SVGA3D_LOTRANSBLT_HONORALPHA (0x01)
1186#define SVGA3D_LOSTRETCHBLT_MIRRORX (0x01)
1187#define SVGA3D_LOSTRETCHBLT_MIRRORY (0x02)
1188#define SVGA3D_LOALPHABLEND_SRCHASALPHA (0x01)
1189
1190typedef
1191#include "vmware_pack_begin.h"
1192struct SVGA3dCmdLogicOpsBitBlt {
1193 /*
1194 * All LogicOps surfaces are one-level
1195 * surfaces so mipmap & face should always
1196 * be zero.
1197 */
1198 SVGA3dSurfaceImageId src;
1199 SVGA3dSurfaceImageId dst;
1200 SVGA3dLogicOp logicOp;
1201 /* Followed by variable number of SVGA3dCopyBox structures */
1202}
1203#include "vmware_pack_end.h"
1204SVGA3dCmdLogicOpsBitBlt; /* SVGA_3D_CMD_LOGICOPS_BITBLT */
1205
1206
1207typedef
1208#include "vmware_pack_begin.h"
1209struct SVGA3dCmdLogicOpsTransBlt {
1210 /*
1211 * All LogicOps surfaces are one-level
1212 * surfaces so mipmap & face should always
1213 * be zero.
1214 */
1215 SVGA3dSurfaceImageId src;
1216 SVGA3dSurfaceImageId dst;
1217 uint32 color;
1218 uint32 flags;
1219 SVGA3dBox srcBox;
1220 SVGA3dBox dstBox;
1221}
1222#include "vmware_pack_end.h"
1223SVGA3dCmdLogicOpsTransBlt; /* SVGA_3D_CMD_LOGICOPS_TRANSBLT */
1224
1225
1226typedef
1227#include "vmware_pack_begin.h"
1228struct SVGA3dCmdLogicOpsStretchBlt {
1229 /*
1230 * All LogicOps surfaces are one-level
1231 * surfaces so mipmap & face should always
1232 * be zero.
1233 */
1234 SVGA3dSurfaceImageId src;
1235 SVGA3dSurfaceImageId dst;
1236 uint16 mode;
1237 uint16 flags;
1238 SVGA3dBox srcBox;
1239 SVGA3dBox dstBox;
1240}
1241#include "vmware_pack_end.h"
1242SVGA3dCmdLogicOpsStretchBlt; /* SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
1243
1244
1245typedef
1246#include "vmware_pack_begin.h"
1247struct SVGA3dCmdLogicOpsColorFill {
1248 /*
1249 * All LogicOps surfaces are one-level
1250 * surfaces so mipmap & face should always
1251 * be zero.
1252 */
1253 SVGA3dSurfaceImageId dst;
1254 uint32 color;
1255 SVGA3dLogicOp logicOp;
1256 /* Followed by variable number of SVGA3dRect structures. */
1257}
1258#include "vmware_pack_end.h"
1259SVGA3dCmdLogicOpsColorFill; /* SVGA_3D_CMD_LOGICOPS_COLORFILL */
1260
1261
1262typedef
1263#include "vmware_pack_begin.h"
1264struct SVGA3dCmdLogicOpsAlphaBlend {
1265 /*
1266 * All LogicOps surfaces are one-level
1267 * surfaces so mipmap & face should always
1268 * be zero.
1269 */
1270 SVGA3dSurfaceImageId src;
1271 SVGA3dSurfaceImageId dst;
1272 uint32 alphaVal;
1273 uint32 flags;
1274 SVGA3dBox srcBox;
1275 SVGA3dBox dstBox;
1276}
1277#include "vmware_pack_end.h"
1278SVGA3dCmdLogicOpsAlphaBlend; /* SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
1279
1280#define SVGA3D_CLEARTYPE_INVALID_GAMMA_INDEX 0xFFFFFFFF
1281
1282#define SVGA3D_CLEARTYPE_GAMMA_WIDTH 512
1283#define SVGA3D_CLEARTYPE_GAMMA_HEIGHT 16
1284
1285typedef
1286#include "vmware_pack_begin.h"
1287struct SVGA3dCmdLogicOpsClearTypeBlend {
1288 /*
1289 * All LogicOps surfaces are one-level
1290 * surfaces so mipmap & face should always
1291 * be zero.
1292 */
1293 SVGA3dSurfaceImageId tmp;
1294 SVGA3dSurfaceImageId dst;
1295 SVGA3dSurfaceImageId gammaSurf;
1296 SVGA3dSurfaceImageId alphaSurf;
1297 uint32 gamma;
1298 uint32 color;
1299 uint32 color2;
1300 int32 alphaOffsetX;
1301 int32 alphaOffsetY;
1302 /* Followed by variable number of SVGA3dBox structures */
1303}
1304#include "vmware_pack_end.h"
1305SVGA3dCmdLogicOpsClearTypeBlend; /* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
1306
1307
1308/*
1309 * Guest-backed objects definitions.
1310 */
1311
1312typedef
1313#include "vmware_pack_begin.h"
1314struct {
1315 SVGAMobFormat ptDepth;
1316 uint32 sizeInBytes;
1317 PPN64 base;
1318}
1319#include "vmware_pack_end.h"
1320SVGAOTableMobEntry;
1321#define SVGA3D_OTABLE_MOB_ENTRY_SIZE (sizeof(SVGAOTableMobEntry))
1322
1323typedef
1324#include "vmware_pack_begin.h"
1325struct {
1326 SVGA3dSurfaceFormat format;
1327 SVGA3dSurfaceFlags surfaceFlags;
1328 uint32 numMipLevels;
1329 uint32 multisampleCount;
1330 SVGA3dTextureFilter autogenFilter;
1331 SVGA3dSize size;
1332 SVGAMobId mobid;
1333 uint32 arraySize;
1334 uint32 mobPitch;
1335 uint32 pad[5];
1336}
1337#include "vmware_pack_end.h"
1338SVGAOTableSurfaceEntry;
1339#define SVGA3D_OTABLE_SURFACE_ENTRY_SIZE (sizeof(SVGAOTableSurfaceEntry))
1340
1341typedef
1342#include "vmware_pack_begin.h"
1343struct {
1344 uint32 cid;
1345 SVGAMobId mobid;
1346}
1347#include "vmware_pack_end.h"
1348SVGAOTableContextEntry;
1349#define SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE (sizeof(SVGAOTableContextEntry))
1350
1351typedef
1352#include "vmware_pack_begin.h"
1353struct {
1354 SVGA3dShaderType type;
1355 uint32 sizeInBytes;
1356 uint32 offsetInBytes;
1357 SVGAMobId mobid;
1358}
1359#include "vmware_pack_end.h"
1360SVGAOTableShaderEntry;
1361#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE (sizeof(SVGAOTableShaderEntry))
1362
1363#define SVGA_STFLAG_PRIMARY (1 << 0)
1364typedef uint32 SVGAScreenTargetFlags;
1365
1366typedef
1367#include "vmware_pack_begin.h"
1368struct {
1369 SVGA3dSurfaceImageId image;
1370 uint32 width;
1371 uint32 height;
1372 int32 xRoot;
1373 int32 yRoot;
1374 SVGAScreenTargetFlags flags;
1375 uint32 dpi;
1376 uint32 pad[7];
1377}
1378#include "vmware_pack_end.h"
1379SVGAOTableScreenTargetEntry;
1380#define SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE \
1381 (sizeof(SVGAOTableScreenTargetEntry))
1382
1383typedef
1384#include "vmware_pack_begin.h"
1385struct {
1386 float value[4];
1387}
1388#include "vmware_pack_end.h"
1389SVGA3dShaderConstFloat;
1390
1391typedef
1392#include "vmware_pack_begin.h"
1393struct {
1394 int32 value[4];
1395}
1396#include "vmware_pack_end.h"
1397SVGA3dShaderConstInt;
1398
1399typedef
1400#include "vmware_pack_begin.h"
1401struct {
1402 uint32 value;
1403}
1404#include "vmware_pack_end.h"
1405SVGA3dShaderConstBool;
1406
1407typedef
1408#include "vmware_pack_begin.h"
1409struct {
1410 uint16 streamOffset;
1411 uint8 stream;
1412 uint8 type;
1413 uint8 methodUsage;
1414 uint8 usageIndex;
1415}
1416#include "vmware_pack_end.h"
1417SVGAGBVertexElement;
1418
1419typedef
1420#include "vmware_pack_begin.h"
1421struct {
1422 uint32 sid;
1423 uint16 stride;
1424 uint32 offset;
1425}
1426#include "vmware_pack_end.h"
1427SVGAGBVertexStream;
1428typedef
1429#include "vmware_pack_begin.h"
1430struct {
1431 SVGA3dRect viewport;
1432 SVGA3dRect scissorRect;
1433 SVGA3dZRange zRange;
1434
1435 SVGA3dSurfaceImageId renderTargets[SVGA3D_RT_MAX];
1436 SVGAGBVertexElement decl1[4];
1437
1438 uint32 renderStates[SVGA3D_RS_MAX];
1439 SVGAGBVertexElement decl2[18];
1440 uint32 pad0[2];
1441
1442 struct {
1443 SVGA3dFace face;
1444 SVGA3dMaterial material;
1445 } material;
1446
1447 float clipPlanes[SVGA3D_NUM_CLIPPLANES][4];
1448 float matrices[SVGA3D_TRANSFORM_MAX][16];
1449
1450 SVGA3dBool lightEnabled[SVGA3D_NUM_LIGHTS];
1451 SVGA3dLightData lightData[SVGA3D_NUM_LIGHTS];
1452
1453 /*
1454 * Shaders currently bound
1455 */
1456 uint32 shaders[SVGA3D_NUM_SHADERTYPE_PREDX];
1457 SVGAGBVertexElement decl3[10];
1458 uint32 pad1[3];
1459
1460 uint32 occQueryActive;
1461 uint32 occQueryValue;
1462
1463 /*
1464 * Int/Bool Shader constants
1465 */
1466 SVGA3dShaderConstInt pShaderIValues[SVGA3D_CONSTINTREG_MAX];
1467 SVGA3dShaderConstInt vShaderIValues[SVGA3D_CONSTINTREG_MAX];
1468 uint16 pShaderBValues;
1469 uint16 vShaderBValues;
1470
1471
1472 SVGAGBVertexStream streams[SVGA3D_MAX_VERTEX_ARRAYS];
1473 SVGA3dVertexDivisor divisors[SVGA3D_MAX_VERTEX_ARRAYS];
1474 uint32 numVertexDecls;
1475 uint32 numVertexStreams;
1476 uint32 numVertexDivisors;
1477 uint32 pad2[30];
1478
1479 /*
1480 * Texture Stages
1481 *
1482 * SVGA3D_TS_INVALID through SVGA3D_TS_CONSTANT are in the
1483 * textureStages array.
1484 * SVGA3D_TS_COLOR_KEY is in tsColorKey.
1485 */
1486 uint32 tsColorKey[SVGA3D_NUM_TEXTURE_UNITS];
1487 uint32 textureStages[SVGA3D_NUM_TEXTURE_UNITS][SVGA3D_TS_CONSTANT + 1];
1488 uint32 tsColorKeyEnable[SVGA3D_NUM_TEXTURE_UNITS];
1489
1490 /*
1491 * Float Shader constants.
1492 */
1493 SVGA3dShaderConstFloat pShaderFValues[SVGA3D_CONSTREG_MAX];
1494 SVGA3dShaderConstFloat vShaderFValues[SVGA3D_CONSTREG_MAX];
1495}
1496#include "vmware_pack_end.h"
1497SVGAGBContextData;
1498#define SVGA3D_CONTEXT_DATA_SIZE (sizeof(SVGAGBContextData))
1499
1500/*
1501 * SVGA3dCmdSetOTableBase --
1502 *
1503 * This command allows the guest to specify the base PPN of the
1504 * specified object table.
1505 */
1506
1507typedef
1508#include "vmware_pack_begin.h"
1509struct {
1510 SVGAOTableType type;
1511 PPN baseAddress;
1512 uint32 sizeInBytes;
1513 uint32 validSizeInBytes;
1514 SVGAMobFormat ptDepth;
1515}
1516#include "vmware_pack_end.h"
1517SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */
1518
1519typedef
1520#include "vmware_pack_begin.h"
1521struct {
1522 SVGAOTableType type;
1523 PPN64 baseAddress;
1524 uint32 sizeInBytes;
1525 uint32 validSizeInBytes;
1526 SVGAMobFormat ptDepth;
1527}
1528#include "vmware_pack_end.h"
1529SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
1530
1531typedef
1532#include "vmware_pack_begin.h"
1533struct {
1534 SVGAOTableType type;
1535}
1536#include "vmware_pack_end.h"
1537SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */
1538
1539/*
1540 * Define a memory object (Mob) in the OTable.
1541 */
1542
1543typedef
1544#include "vmware_pack_begin.h"
1545struct SVGA3dCmdDefineGBMob {
1546 SVGAMobId mobid;
1547 SVGAMobFormat ptDepth;
1548 PPN base;
1549 uint32 sizeInBytes;
1550}
1551#include "vmware_pack_end.h"
1552SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
1553
1554
1555/*
1556 * Destroys an object in the OTable.
1557 */
1558
1559typedef
1560#include "vmware_pack_begin.h"
1561struct SVGA3dCmdDestroyGBMob {
1562 SVGAMobId mobid;
1563}
1564#include "vmware_pack_end.h"
1565SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
1566
1567
1568/*
1569 * Define a memory object (Mob) in the OTable with a PPN64 base.
1570 */
1571
1572typedef
1573#include "vmware_pack_begin.h"
1574struct SVGA3dCmdDefineGBMob64 {
1575 SVGAMobId mobid;
1576 SVGAMobFormat ptDepth;
1577 PPN64 base;
1578 uint32 sizeInBytes;
1579}
1580#include "vmware_pack_end.h"
1581SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */
1582
1583/*
1584 * Redefine an object in the OTable with PPN64 base.
1585 */
1586
1587typedef
1588#include "vmware_pack_begin.h"
1589struct SVGA3dCmdRedefineGBMob64 {
1590 SVGAMobId mobid;
1591 SVGAMobFormat ptDepth;
1592 PPN64 base;
1593 uint32 sizeInBytes;
1594}
1595#include "vmware_pack_end.h"
1596SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
1597
1598/*
1599 * Notification that the page tables have been modified.
1600 */
1601
1602typedef
1603#include "vmware_pack_begin.h"
1604struct SVGA3dCmdUpdateGBMobMapping {
1605 SVGAMobId mobid;
1606}
1607#include "vmware_pack_end.h"
1608SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */
1609
1610/*
1611 * Define a guest-backed surface.
1612 */
1613
1614typedef
1615#include "vmware_pack_begin.h"
1616struct SVGA3dCmdDefineGBSurface {
1617 uint32 sid;
1618 SVGA3dSurfaceFlags surfaceFlags;
1619 SVGA3dSurfaceFormat format;
1620 uint32 numMipLevels;
1621 uint32 multisampleCount;
1622 SVGA3dTextureFilter autogenFilter;
1623 SVGA3dSize size;
1624}
1625#include "vmware_pack_end.h"
1626SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
1627
1628/*
1629 * Destroy a guest-backed surface.
1630 */
1631
1632typedef
1633#include "vmware_pack_begin.h"
1634struct SVGA3dCmdDestroyGBSurface {
1635 uint32 sid;
1636}
1637#include "vmware_pack_end.h"
1638SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
1639
1640/*
1641 * Bind a guest-backed surface to a mob.
1642 */
1643
1644typedef
1645#include "vmware_pack_begin.h"
1646struct SVGA3dCmdBindGBSurface {
1647 uint32 sid;
1648 SVGAMobId mobid;
1649}
1650#include "vmware_pack_end.h"
1651SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
1652
1653typedef
1654#include "vmware_pack_begin.h"
1655struct SVGA3dCmdBindGBSurfaceWithPitch {
1656 uint32 sid;
1657 SVGAMobId mobid;
1658 uint32 baseLevelPitch;
1659}
1660#include "vmware_pack_end.h"
1661SVGA3dCmdBindGBSurfaceWithPitch; /* SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH */
1662
1663/*
1664 * Conditionally bind a mob to a guest-backed surface if testMobid
1665 * matches the currently bound mob. Optionally issue a
1666 * readback/update on the surface while it is still bound to the old
1667 * mobid if the mobid is changed by this command.
1668 */
1669
1670#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_READBACK (1 << 0)
1671#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_UPDATE (1 << 1)
1672
1673typedef
1674#include "vmware_pack_begin.h"
1675struct{
1676 uint32 sid;
1677 SVGAMobId testMobid;
1678 SVGAMobId mobid;
1679 uint32 flags;
1680}
1681#include "vmware_pack_end.h"
1682SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
1683
1684/*
1685 * Update an image in a guest-backed surface.
1686 * (Inform the device that the guest-contents have been updated.)
1687 */
1688
1689typedef
1690#include "vmware_pack_begin.h"
1691struct SVGA3dCmdUpdateGBImage {
1692 SVGA3dSurfaceImageId image;
1693 SVGA3dBox box;
1694}
1695#include "vmware_pack_end.h"
1696SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
1697
1698/*
1699 * Update an entire guest-backed surface.
1700 * (Inform the device that the guest-contents have been updated.)
1701 */
1702
1703typedef
1704#include "vmware_pack_begin.h"
1705struct SVGA3dCmdUpdateGBSurface {
1706 uint32 sid;
1707}
1708#include "vmware_pack_end.h"
1709SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
1710
1711/*
1712 * Readback an image in a guest-backed surface.
1713 * (Request the device to flush the dirty contents into the guest.)
1714 */
1715
1716typedef
1717#include "vmware_pack_begin.h"
1718struct SVGA3dCmdReadbackGBImage {
1719 SVGA3dSurfaceImageId image;
1720}
1721#include "vmware_pack_end.h"
1722SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE */
1723
1724/*
1725 * Readback an entire guest-backed surface.
1726 * (Request the device to flush the dirty contents into the guest.)
1727 */
1728
1729typedef
1730#include "vmware_pack_begin.h"
1731struct SVGA3dCmdReadbackGBSurface {
1732 uint32 sid;
1733}
1734#include "vmware_pack_end.h"
1735SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
1736
1737/*
1738 * Readback a sub rect of an image in a guest-backed surface. After
1739 * issuing this command the driver is required to issue an update call
1740 * of the same region before issuing any other commands that reference
1741 * this surface or rendering is not guaranteed.
1742 */
1743
1744typedef
1745#include "vmware_pack_begin.h"
1746struct SVGA3dCmdReadbackGBImagePartial {
1747 SVGA3dSurfaceImageId image;
1748 SVGA3dBox box;
1749 uint32 invertBox;
1750}
1751#include "vmware_pack_end.h"
1752SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
1753
1754
1755/*
1756 * Invalidate an image in a guest-backed surface.
1757 * (Notify the device that the contents can be lost.)
1758 */
1759
1760typedef
1761#include "vmware_pack_begin.h"
1762struct SVGA3dCmdInvalidateGBImage {
1763 SVGA3dSurfaceImageId image;
1764}
1765#include "vmware_pack_end.h"
1766SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
1767
1768/*
1769 * Invalidate an entire guest-backed surface.
1770 * (Notify the device that the contents if all images can be lost.)
1771 */
1772
1773typedef
1774#include "vmware_pack_begin.h"
1775struct SVGA3dCmdInvalidateGBSurface {
1776 uint32 sid;
1777}
1778#include "vmware_pack_end.h"
1779SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
1780
1781/*
1782 * Invalidate a sub rect of an image in a guest-backed surface. After
1783 * issuing this command the driver is required to issue an update call
1784 * of the same region before issuing any other commands that reference
1785 * this surface or rendering is not guaranteed.
1786 */
1787
1788typedef
1789#include "vmware_pack_begin.h"
1790struct SVGA3dCmdInvalidateGBImagePartial {
1791 SVGA3dSurfaceImageId image;
1792 SVGA3dBox box;
1793 uint32 invertBox;
1794}
1795#include "vmware_pack_end.h"
1796SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
1797
1798
1799/*
1800 * Define a guest-backed context.
1801 */
1802
1803typedef
1804#include "vmware_pack_begin.h"
1805struct SVGA3dCmdDefineGBContext {
1806 uint32 cid;
1807}
1808#include "vmware_pack_end.h"
1809SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
1810
1811/*
1812 * Destroy a guest-backed context.
1813 */
1814
1815typedef
1816#include "vmware_pack_begin.h"
1817struct SVGA3dCmdDestroyGBContext {
1818 uint32 cid;
1819}
1820#include "vmware_pack_end.h"
1821SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
1822
1823/*
1824 * Bind a guest-backed context.
1825 *
1826 * validContents should be set to 0 for new contexts,
1827 * and 1 if this is an old context which is getting paged
1828 * back on to the device.
1829 *
1830 * For new contexts, it is recommended that the driver
1831 * issue commands to initialize all interesting state
1832 * prior to rendering.
1833 */
1834
1835typedef
1836#include "vmware_pack_begin.h"
1837struct SVGA3dCmdBindGBContext {
1838 uint32 cid;
1839 SVGAMobId mobid;
1840 uint32 validContents;
1841}
1842#include "vmware_pack_end.h"
1843SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
1844
1845/*
1846 * Readback a guest-backed context.
1847 * (Request that the device flush the contents back into guest memory.)
1848 */
1849
1850typedef
1851#include "vmware_pack_begin.h"
1852struct SVGA3dCmdReadbackGBContext {
1853 uint32 cid;
1854}
1855#include "vmware_pack_end.h"
1856SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
1857
1858/*
1859 * Invalidate a guest-backed context.
1860 */
1861typedef
1862#include "vmware_pack_begin.h"
1863struct SVGA3dCmdInvalidateGBContext {
1864 uint32 cid;
1865}
1866#include "vmware_pack_end.h"
1867SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
1868
1869/*
1870 * Define a guest-backed shader.
1871 */
1872
1873typedef
1874#include "vmware_pack_begin.h"
1875struct SVGA3dCmdDefineGBShader {
1876 uint32 shid;
1877 SVGA3dShaderType type;
1878 uint32 sizeInBytes;
1879}
1880#include "vmware_pack_end.h"
1881SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
1882
1883/*
1884 * Bind a guest-backed shader.
1885 */
1886
1887typedef
1888#include "vmware_pack_begin.h"
1889struct SVGA3dCmdBindGBShader {
1890 uint32 shid;
1891 SVGAMobId mobid;
1892 uint32 offsetInBytes;
1893}
1894#include "vmware_pack_end.h"
1895SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
1896
1897/*
1898 * Destroy a guest-backed shader.
1899 */
1900
1901typedef
1902#include "vmware_pack_begin.h"
1903struct SVGA3dCmdDestroyGBShader {
1904 uint32 shid;
1905}
1906#include "vmware_pack_end.h"
1907SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
1908
1909typedef
1910#include "vmware_pack_begin.h"
1911struct {
1912 uint32 cid;
1913 uint32 regStart;
1914 SVGA3dShaderType shaderType;
1915 SVGA3dShaderConstType constType;
1916
1917 /*
1918 * Followed by a variable number of shader constants.
1919 *
1920 * Note that FLOAT and INT constants are 4-dwords in length, while
1921 * BOOL constants are 1-dword in length.
1922 */
1923}
1924#include "vmware_pack_end.h"
1925SVGA3dCmdSetGBShaderConstInline; /* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
1926
1927
1928typedef
1929#include "vmware_pack_begin.h"
1930struct {
1931 uint32 cid;
1932 SVGA3dQueryType type;
1933}
1934#include "vmware_pack_end.h"
1935SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
1936
1937typedef
1938#include "vmware_pack_begin.h"
1939struct {
1940 uint32 cid;
1941 SVGA3dQueryType type;
1942 SVGAMobId mobid;
1943 uint32 offset;
1944}
1945#include "vmware_pack_end.h"
1946SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
1947
1948
1949/*
1950 * SVGA_3D_CMD_WAIT_FOR_GB_QUERY --
1951 *
1952 * The semantics of this command are identical to the
1953 * SVGA_3D_CMD_WAIT_FOR_QUERY except that the results are written
1954 * to a Mob instead of a GMR.
1955 */
1956
1957typedef
1958#include "vmware_pack_begin.h"
1959struct {
1960 uint32 cid;
1961 SVGA3dQueryType type;
1962 SVGAMobId mobid;
1963 uint32 offset;
1964}
1965#include "vmware_pack_end.h"
1966SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
1967
1968
1969typedef
1970#include "vmware_pack_begin.h"
1971struct {
1972 SVGAMobId mobid;
1973 uint32 mustBeZero;
1974 uint32 initialized;
1975}
1976#include "vmware_pack_end.h"
1977SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
1978
1979typedef
1980#include "vmware_pack_begin.h"
1981struct {
1982 SVGAMobId mobid;
1983 uint32 gartOffset;
1984}
1985#include "vmware_pack_end.h"
1986SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
1987
1988
1989typedef
1990#include "vmware_pack_begin.h"
1991struct {
1992 uint32 gartOffset;
1993 uint32 numPages;
1994}
1995#include "vmware_pack_end.h"
1996SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
1997
1998
1999/*
2000 * Screen Targets
2001 */
2002
2003typedef
2004#include "vmware_pack_begin.h"
2005struct {
2006 uint32 stid;
2007 uint32 width;
2008 uint32 height;
2009 int32 xRoot;
2010 int32 yRoot;
2011 SVGAScreenTargetFlags flags;
2012
2013 /*
2014 * The physical DPI that the guest expects this screen displayed at.
2015 *
2016 * Guests which are not DPI-aware should set this to zero.
2017 */
2018 uint32 dpi;
2019}
2020#include "vmware_pack_end.h"
2021SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
2022
2023typedef
2024#include "vmware_pack_begin.h"
2025struct {
2026 uint32 stid;
2027}
2028#include "vmware_pack_end.h"
2029SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
2030
2031typedef
2032#include "vmware_pack_begin.h"
2033struct {
2034 uint32 stid;
2035 SVGA3dSurfaceImageId image;
2036}
2037#include "vmware_pack_end.h"
2038SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
2039
2040typedef
2041#include "vmware_pack_begin.h"
2042struct {
2043 uint32 stid;
2044 SVGA3dRect rect;
2045}
2046#include "vmware_pack_end.h"
2047SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
2048
2049typedef
2050#include "vmware_pack_begin.h"
2051struct SVGA3dCmdGBScreenDMA {
2052 uint32 screenId;
2053 uint32 dead;
2054 SVGAMobId destMobID;
2055 uint32 destPitch;
2056 SVGAMobId changeMapMobID;
2057}
2058#include "vmware_pack_end.h"
2059SVGA3dCmdGBScreenDMA; /* SVGA_3D_CMD_GB_SCREEN_DMA */
2060
2061typedef
2062#include "vmware_pack_begin.h"
2063struct {
2064 uint32 value;
2065 uint32 mobId;
2066 uint32 mobOffset;
2067}
2068#include "vmware_pack_end.h"
2069SVGA3dCmdGBMobFence; /* SVGA_3D_CMD_GB_MOB_FENCE*/
2070
2071#endif /* _SVGA3D_CMD_H_ */
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h
new file mode 100644
index 000000000000..c18b663f360f
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h
@@ -0,0 +1,457 @@
1/**********************************************************
2 * Copyright 1998-2015 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_devcaps.h --
28 *
29 * SVGA 3d caps definitions
30 */
31
32#ifndef _SVGA3D_DEVCAPS_H_
33#define _SVGA3D_DEVCAPS_H_
34
35#define INCLUDE_ALLOW_MODULE
36#define INCLUDE_ALLOW_USERLEVEL
37#define INCLUDE_ALLOW_VMCORE
38
39#include "includeCheck.h"
40
41/*
42 * 3D Hardware Version
43 *
44 * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
45 * register. Is set by the host and read by the guest. This lets
46 * us make new guest drivers which are backwards-compatible with old
47 * SVGA hardware revisions. It does not let us support old guest
48 * drivers. Good enough for now.
49 *
50 */
51
52#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
53#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
54#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
55
56typedef enum {
57 SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
58 SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
59 SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
60 SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
61 SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
62 SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
63 SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
64 SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
65} SVGA3dHardwareVersion;
66
67/*
68 * DevCap indexes.
69 */
70
71typedef enum {
72 SVGA3D_DEVCAP_INVALID = ((uint32)-1),
73 SVGA3D_DEVCAP_3D = 0,
74 SVGA3D_DEVCAP_MAX_LIGHTS = 1,
75
76 /*
77 * SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
78 * fixed-function texture units available. Each of these units
79 * work in both FFP and Shader modes, and they support texture
80 * transforms and texture coordinates. The host may have additional
81 * texture image units that are only usable with shaders.
82 */
83 SVGA3D_DEVCAP_MAX_TEXTURES = 2,
84 SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3,
85 SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4,
86 SVGA3D_DEVCAP_VERTEX_SHADER = 5,
87 SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6,
88 SVGA3D_DEVCAP_FRAGMENT_SHADER = 7,
89 SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8,
90 SVGA3D_DEVCAP_S23E8_TEXTURES = 9,
91 SVGA3D_DEVCAP_S10E5_TEXTURES = 10,
92 SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11,
93 SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12,
94 SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13,
95 SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14,
96 SVGA3D_DEVCAP_QUERY_TYPES = 15,
97 SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16,
98 SVGA3D_DEVCAP_MAX_POINT_SIZE = 17,
99 SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18,
100 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19,
101 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20,
102 SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21,
103 SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22,
104 SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23,
105 SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24,
106 SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25,
107 SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26,
108 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27,
109 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
110 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29,
111 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30,
112 SVGA3D_DEVCAP_TEXTURE_OPS = 31,
113 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32,
114 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33,
115 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34,
116 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35,
117 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36,
118 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37,
119 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38,
120 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39,
121 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40,
122 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41,
123 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42,
124 SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43,
125 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44,
126 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45,
127 SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46,
128 SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47,
129 SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48,
130 SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49,
131 SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50,
132 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51,
133 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52,
134 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53,
135 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54,
136 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55,
137 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56,
138 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57,
139 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58,
140 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59,
141 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60,
142 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61,
143
144 /*
145 * There is a hole in our devcap definitions for
146 * historical reasons.
147 *
148 * Define a constant just for completeness.
149 */
150 SVGA3D_DEVCAP_MISSING62 = 62,
151
152 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63,
153
154 /*
155 * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
156 * render targets. This does not include the depth or stencil targets.
157 */
158 SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
159
160 SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65,
161 SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66,
162 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67,
163 SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68,
164 SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69,
165 SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = 70,
166 SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = 71,
167 SVGA3D_DEVCAP_ALPHATOCOVERAGE = 72,
168 SVGA3D_DEVCAP_SUPERSAMPLE = 73,
169 SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74,
170 SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75,
171 SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76,
172
173 /*
174 * This is the maximum number of SVGA context IDs that the guest
175 * can define using SVGA_3D_CMD_CONTEXT_DEFINE.
176 */
177 SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77,
178
179 /*
180 * This is the maximum number of SVGA surface IDs that the guest
181 * can define using SVGA_3D_CMD_SURFACE_DEFINE*.
182 */
183 SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78,
184
185 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79,
186 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80,
187 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81,
188
189 SVGA3D_DEVCAP_SURFACEFMT_ATI1 = 82,
190 SVGA3D_DEVCAP_SURFACEFMT_ATI2 = 83,
191
192 /*
193 * Deprecated.
194 */
195 SVGA3D_DEVCAP_DEAD1 = 84,
196
197 /*
198 * This contains several SVGA_3D_CAPS_VIDEO_DECODE elements
199 * ored together, one for every type of video decoding supported.
200 */
201 SVGA3D_DEVCAP_VIDEO_DECODE = 85,
202
203 /*
204 * This contains several SVGA_3D_CAPS_VIDEO_PROCESS elements
205 * ored together, one for every type of video processing supported.
206 */
207 SVGA3D_DEVCAP_VIDEO_PROCESS = 86,
208
209 SVGA3D_DEVCAP_LINE_AA = 87, /* boolean */
210 SVGA3D_DEVCAP_LINE_STIPPLE = 88, /* boolean */
211 SVGA3D_DEVCAP_MAX_LINE_WIDTH = 89, /* float */
212 SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH = 90, /* float */
213
214 SVGA3D_DEVCAP_SURFACEFMT_YV12 = 91,
215
216 /*
217 * Does the host support the SVGA logic ops commands?
218 */
219 SVGA3D_DEVCAP_LOGICOPS = 92,
220
221 /*
222 * Are TS_CONSTANT, TS_COLOR_KEY, and TS_COLOR_KEY_ENABLE supported?
223 */
224 SVGA3D_DEVCAP_TS_COLOR_KEY = 93, /* boolean */
225
226 /*
227 * Deprecated.
228 */
229 SVGA3D_DEVCAP_DEAD2 = 94,
230
231 /*
232 * Does the device support the DX commands?
233 */
234 SVGA3D_DEVCAP_DX = 95,
235
236 /*
237 * What is the maximum size of a texture array?
238 *
239 * (Even if this cap is zero, cubemaps are still allowed.)
240 */
241 SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE = 96,
242
243 /*
244 * What is the maximum number of vertex buffers that can
245 * be used in the DXContext inputAssembly?
246 */
247 SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS = 97,
248
249 /*
250 * What is the maximum number of constant buffers
251 * that can be expected to work correctly with a
252 * DX context?
253 */
254 SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS = 98,
255
256 /*
257 * Does the device support provoking vertex control?
258 * If zero, the first vertex will always be the provoking vertex.
259 */
260 SVGA3D_DEVCAP_DX_PROVOKING_VERTEX = 99,
261
262 SVGA3D_DEVCAP_DXFMT_X8R8G8B8 = 100,
263 SVGA3D_DEVCAP_DXFMT_A8R8G8B8 = 101,
264 SVGA3D_DEVCAP_DXFMT_R5G6B5 = 102,
265 SVGA3D_DEVCAP_DXFMT_X1R5G5B5 = 103,
266 SVGA3D_DEVCAP_DXFMT_A1R5G5B5 = 104,
267 SVGA3D_DEVCAP_DXFMT_A4R4G4B4 = 105,
268 SVGA3D_DEVCAP_DXFMT_Z_D32 = 106,
269 SVGA3D_DEVCAP_DXFMT_Z_D16 = 107,
270 SVGA3D_DEVCAP_DXFMT_Z_D24S8 = 108,
271 SVGA3D_DEVCAP_DXFMT_Z_D15S1 = 109,
272 SVGA3D_DEVCAP_DXFMT_LUMINANCE8 = 110,
273 SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 = 111,
274 SVGA3D_DEVCAP_DXFMT_LUMINANCE16 = 112,
275 SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 = 113,
276 SVGA3D_DEVCAP_DXFMT_DXT1 = 114,
277 SVGA3D_DEVCAP_DXFMT_DXT2 = 115,
278 SVGA3D_DEVCAP_DXFMT_DXT3 = 116,
279 SVGA3D_DEVCAP_DXFMT_DXT4 = 117,
280 SVGA3D_DEVCAP_DXFMT_DXT5 = 118,
281 SVGA3D_DEVCAP_DXFMT_BUMPU8V8 = 119,
282 SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 = 120,
283 SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 = 121,
284 SVGA3D_DEVCAP_DXFMT_BUMPL8V8U8 = 122,
285 SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 = 123,
286 SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 = 124,
287 SVGA3D_DEVCAP_DXFMT_A2R10G10B10 = 125,
288 SVGA3D_DEVCAP_DXFMT_V8U8 = 126,
289 SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 = 127,
290 SVGA3D_DEVCAP_DXFMT_CxV8U8 = 128,
291 SVGA3D_DEVCAP_DXFMT_X8L8V8U8 = 129,
292 SVGA3D_DEVCAP_DXFMT_A2W10V10U10 = 130,
293 SVGA3D_DEVCAP_DXFMT_ALPHA8 = 131,
294 SVGA3D_DEVCAP_DXFMT_R_S10E5 = 132,
295 SVGA3D_DEVCAP_DXFMT_R_S23E8 = 133,
296 SVGA3D_DEVCAP_DXFMT_RG_S10E5 = 134,
297 SVGA3D_DEVCAP_DXFMT_RG_S23E8 = 135,
298 SVGA3D_DEVCAP_DXFMT_BUFFER = 136,
299 SVGA3D_DEVCAP_DXFMT_Z_D24X8 = 137,
300 SVGA3D_DEVCAP_DXFMT_V16U16 = 138,
301 SVGA3D_DEVCAP_DXFMT_G16R16 = 139,
302 SVGA3D_DEVCAP_DXFMT_A16B16G16R16 = 140,
303 SVGA3D_DEVCAP_DXFMT_UYVY = 141,
304 SVGA3D_DEVCAP_DXFMT_YUY2 = 142,
305 SVGA3D_DEVCAP_DXFMT_NV12 = 143,
306 SVGA3D_DEVCAP_DXFMT_AYUV = 144,
307 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS = 145,
308 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT = 146,
309 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT = 147,
310 SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS = 148,
311 SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT = 149,
312 SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT = 150,
313 SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT = 151,
314 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS = 152,
315 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT = 153,
316 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM = 154,
317 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT = 155,
318 SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS = 156,
319 SVGA3D_DEVCAP_DXFMT_R32G32_UINT = 157,
320 SVGA3D_DEVCAP_DXFMT_R32G32_SINT = 158,
321 SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS = 159,
322 SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT = 160,
323 SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS = 161,
324 SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT = 162,
325 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS = 163,
326 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT = 164,
327 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT = 165,
328 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS = 166,
329 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM = 167,
330 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB = 168,
331 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT = 169,
332 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT = 170,
333 SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS = 171,
334 SVGA3D_DEVCAP_DXFMT_R16G16_UINT = 172,
335 SVGA3D_DEVCAP_DXFMT_R16G16_SINT = 173,
336 SVGA3D_DEVCAP_DXFMT_R32_TYPELESS = 174,
337 SVGA3D_DEVCAP_DXFMT_D32_FLOAT = 175,
338 SVGA3D_DEVCAP_DXFMT_R32_UINT = 176,
339 SVGA3D_DEVCAP_DXFMT_R32_SINT = 177,
340 SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS = 178,
341 SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT = 179,
342 SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS = 180,
343 SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT = 181,
344 SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS = 182,
345 SVGA3D_DEVCAP_DXFMT_R8G8_UNORM = 183,
346 SVGA3D_DEVCAP_DXFMT_R8G8_UINT = 184,
347 SVGA3D_DEVCAP_DXFMT_R8G8_SINT = 185,
348 SVGA3D_DEVCAP_DXFMT_R16_TYPELESS = 186,
349 SVGA3D_DEVCAP_DXFMT_R16_UNORM = 187,
350 SVGA3D_DEVCAP_DXFMT_R16_UINT = 188,
351 SVGA3D_DEVCAP_DXFMT_R16_SNORM = 189,
352 SVGA3D_DEVCAP_DXFMT_R16_SINT = 190,
353 SVGA3D_DEVCAP_DXFMT_R8_TYPELESS = 191,
354 SVGA3D_DEVCAP_DXFMT_R8_UNORM = 192,
355 SVGA3D_DEVCAP_DXFMT_R8_UINT = 193,
356 SVGA3D_DEVCAP_DXFMT_R8_SNORM = 194,
357 SVGA3D_DEVCAP_DXFMT_R8_SINT = 195,
358 SVGA3D_DEVCAP_DXFMT_P8 = 196,
359 SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP = 197,
360 SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM = 198,
361 SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM = 199,
362 SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS = 200,
363 SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB = 201,
364 SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS = 202,
365 SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB = 203,
366 SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS = 204,
367 SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB = 205,
368 SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS = 206,
369 SVGA3D_DEVCAP_DXFMT_ATI1 = 207,
370 SVGA3D_DEVCAP_DXFMT_BC4_SNORM = 208,
371 SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS = 209,
372 SVGA3D_DEVCAP_DXFMT_ATI2 = 210,
373 SVGA3D_DEVCAP_DXFMT_BC5_SNORM = 211,
374 SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM = 212,
375 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS = 213,
376 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB = 214,
377 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS = 215,
378 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB = 216,
379 SVGA3D_DEVCAP_DXFMT_Z_DF16 = 217,
380 SVGA3D_DEVCAP_DXFMT_Z_DF24 = 218,
381 SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT = 219,
382 SVGA3D_DEVCAP_DXFMT_YV12 = 220,
383 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT = 221,
384 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT = 222,
385 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM = 223,
386 SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT = 224,
387 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM = 225,
388 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM = 226,
389 SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT = 227,
390 SVGA3D_DEVCAP_DXFMT_R16G16_UNORM = 228,
391 SVGA3D_DEVCAP_DXFMT_R16G16_SNORM = 229,
392 SVGA3D_DEVCAP_DXFMT_R32_FLOAT = 230,
393 SVGA3D_DEVCAP_DXFMT_R8G8_SNORM = 231,
394 SVGA3D_DEVCAP_DXFMT_R16_FLOAT = 232,
395 SVGA3D_DEVCAP_DXFMT_D16_UNORM = 233,
396 SVGA3D_DEVCAP_DXFMT_A8_UNORM = 234,
397 SVGA3D_DEVCAP_DXFMT_BC1_UNORM = 235,
398 SVGA3D_DEVCAP_DXFMT_BC2_UNORM = 236,
399 SVGA3D_DEVCAP_DXFMT_BC3_UNORM = 237,
400 SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM = 238,
401 SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM = 239,
402 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM = 240,
403 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM = 241,
404 SVGA3D_DEVCAP_DXFMT_BC4_UNORM = 242,
405 SVGA3D_DEVCAP_DXFMT_BC5_UNORM = 243,
406
407 SVGA3D_DEVCAP_MAX /* This must be the last index. */
408} SVGA3dDevCapIndex;
409
410/*
411 * Bit definitions for DXFMT devcaps
412 *
413 *
414 * SUPPORTED: Can the format be defined?
415 * SHADER_SAMPLE: Can the format be sampled from a shader?
416 * COLOR_RENDERTARGET: Can the format be a color render target?
417 * DEPTH_RENDERTARGET: Can the format be a depth render target?
418 * BLENDABLE: Is the format blendable?
419 * MIPS: Does the format support mip levels?
420 * ARRAY: Does the format support texture arrays?
421 * VOLUME: Does the format support having volume?
422 * MULTISAMPLE_2: Does the format support 2x multisample?
423 * MULTISAMPLE_4: Does the format support 4x multisample?
424 * MULTISAMPLE_8: Does the format support 8x multisample?
425 */
426#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
427#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
428#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2)
429#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3)
430#define SVGA3D_DXFMT_BLENDABLE (1 << 4)
431#define SVGA3D_DXFMT_MIPS (1 << 5)
432#define SVGA3D_DXFMT_ARRAY (1 << 6)
433#define SVGA3D_DXFMT_VOLUME (1 << 7)
434#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
435#define SVGADX_DXFMT_MULTISAMPLE_2 (1 << 9)
436#define SVGADX_DXFMT_MULTISAMPLE_4 (1 << 10)
437#define SVGADX_DXFMT_MULTISAMPLE_8 (1 << 11)
438#define SVGADX_DXFMT_MAX (1 << 12)
439
440/*
441 * Convenience mask for any multisample capability.
442 *
443 * The multisample bits imply both load and render capability.
444 */
445#define SVGA3D_DXFMT_MULTISAMPLE ( \
446 SVGADX_DXFMT_MULTISAMPLE_2 | \
447 SVGADX_DXFMT_MULTISAMPLE_4 | \
448 SVGADX_DXFMT_MULTISAMPLE_8 )
449
450typedef union {
451 Bool b;
452 uint32 u;
453 int32 i;
454 float f;
455} SVGA3dDevCapResult;
456
457#endif /* _SVGA3D_DEVCAPS_H_ */
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
new file mode 100644
index 000000000000..8c5ae608cfb4
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
@@ -0,0 +1,1487 @@
1/**********************************************************
2 * Copyright 2012-2015 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_dx.h --
28 *
29 * SVGA 3d hardware definitions for DX10 support.
30 */
31
32#ifndef _SVGA3D_DX_H_
33#define _SVGA3D_DX_H_
34
35#define INCLUDE_ALLOW_MODULE
36#define INCLUDE_ALLOW_USERLEVEL
37#define INCLUDE_ALLOW_VMCORE
38#include "includeCheck.h"
39
40#include "svga3d_limits.h"
41
42#define SVGA3D_INPUT_MIN 0
43#define SVGA3D_INPUT_PER_VERTEX_DATA 0
44#define SVGA3D_INPUT_PER_INSTANCE_DATA 1
45#define SVGA3D_INPUT_MAX 2
46typedef uint32 SVGA3dInputClassification;
47
48#define SVGA3D_RESOURCE_TYPE_MIN 1
49#define SVGA3D_RESOURCE_BUFFER 1
50#define SVGA3D_RESOURCE_TEXTURE1D 2
51#define SVGA3D_RESOURCE_TEXTURE2D 3
52#define SVGA3D_RESOURCE_TEXTURE3D 4
53#define SVGA3D_RESOURCE_TEXTURECUBE 5
54#define SVGA3D_RESOURCE_TYPE_DX10_MAX 6
55#define SVGA3D_RESOURCE_BUFFEREX 6
56#define SVGA3D_RESOURCE_TYPE_MAX 7
57typedef uint32 SVGA3dResourceType;
58
59#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0
60#define SVGA3D_DEPTH_WRITE_MASK_ALL 1
61typedef uint8 SVGA3dDepthWriteMask;
62
63#define SVGA3D_FILTER_MIP_LINEAR (1 << 0)
64#define SVGA3D_FILTER_MAG_LINEAR (1 << 2)
65#define SVGA3D_FILTER_MIN_LINEAR (1 << 4)
66#define SVGA3D_FILTER_ANISOTROPIC (1 << 6)
67#define SVGA3D_FILTER_COMPARE (1 << 7)
68typedef uint32 SVGA3dFilter;
69
70#define SVGA3D_CULL_INVALID 0
71#define SVGA3D_CULL_MIN 1
72#define SVGA3D_CULL_NONE 1
73#define SVGA3D_CULL_FRONT 2
74#define SVGA3D_CULL_BACK 3
75#define SVGA3D_CULL_MAX 4
76typedef uint8 SVGA3dCullMode;
77
78#define SVGA3D_COMPARISON_INVALID 0
79#define SVGA3D_COMPARISON_MIN 1
80#define SVGA3D_COMPARISON_NEVER 1
81#define SVGA3D_COMPARISON_LESS 2
82#define SVGA3D_COMPARISON_EQUAL 3
83#define SVGA3D_COMPARISON_LESS_EQUAL 4
84#define SVGA3D_COMPARISON_GREATER 5
85#define SVGA3D_COMPARISON_NOT_EQUAL 6
86#define SVGA3D_COMPARISON_GREATER_EQUAL 7
87#define SVGA3D_COMPARISON_ALWAYS 8
88#define SVGA3D_COMPARISON_MAX 9
89typedef uint8 SVGA3dComparisonFunc;
90
91#define SVGA3D_DX_MAX_VERTEXBUFFERS 32
92#define SVGA3D_DX_MAX_SOTARGETS 4
93#define SVGA3D_DX_MAX_SRVIEWS 128
94#define SVGA3D_DX_MAX_CONSTBUFFERS 16
95#define SVGA3D_DX_MAX_SAMPLERS 16
96
97/* Id limits */
98static const uint32 SVGA3dBlendObjectCountPerContext = 4096;
99static const uint32 SVGA3dDepthStencilObjectCountPerContext = 4096;
100
101typedef uint32 SVGA3dSurfaceId;
102typedef uint32 SVGA3dShaderResourceViewId;
103typedef uint32 SVGA3dRenderTargetViewId;
104typedef uint32 SVGA3dDepthStencilViewId;
105
106typedef uint32 SVGA3dShaderId;
107typedef uint32 SVGA3dElementLayoutId;
108typedef uint32 SVGA3dSamplerId;
109typedef uint32 SVGA3dBlendStateId;
110typedef uint32 SVGA3dDepthStencilStateId;
111typedef uint32 SVGA3dRasterizerStateId;
112typedef uint32 SVGA3dQueryId;
113typedef uint32 SVGA3dStreamOutputId;
114
115typedef union {
116 struct {
117 float r;
118 float g;
119 float b;
120 float a;
121 };
122
123 float value[4];
124} SVGA3dRGBAFloat;
125
126typedef
127#include "vmware_pack_begin.h"
128struct {
129 uint32 cid;
130 SVGAMobId mobid;
131}
132#include "vmware_pack_end.h"
133SVGAOTableDXContextEntry;
134
135typedef
136#include "vmware_pack_begin.h"
137struct SVGA3dCmdDXDefineContext {
138 uint32 cid;
139}
140#include "vmware_pack_end.h"
141SVGA3dCmdDXDefineContext; /* SVGA_3D_CMD_DX_DEFINE_CONTEXT */
142
143typedef
144#include "vmware_pack_begin.h"
145struct SVGA3dCmdDXDestroyContext {
146 uint32 cid;
147}
148#include "vmware_pack_end.h"
149SVGA3dCmdDXDestroyContext; /* SVGA_3D_CMD_DX_DESTROY_CONTEXT */
150
151/*
152 * Bind a DX context.
153 *
154 * validContents should be set to 0 for new contexts,
155 * and 1 if this is an old context which is getting paged
156 * back on to the device.
157 *
158 * For new contexts, it is recommended that the driver
159 * issue commands to initialize all interesting state
160 * prior to rendering.
161 */
162typedef
163#include "vmware_pack_begin.h"
164struct SVGA3dCmdDXBindContext {
165 uint32 cid;
166 SVGAMobId mobid;
167 uint32 validContents;
168}
169#include "vmware_pack_end.h"
170SVGA3dCmdDXBindContext; /* SVGA_3D_CMD_DX_BIND_CONTEXT */
171
172/*
173 * Readback a DX context.
174 * (Request that the device flush the contents back into guest memory.)
175 */
176typedef
177#include "vmware_pack_begin.h"
178struct SVGA3dCmdDXReadbackContext {
179 uint32 cid;
180}
181#include "vmware_pack_end.h"
182SVGA3dCmdDXReadbackContext; /* SVGA_3D_CMD_DX_READBACK_CONTEXT */
183
184/*
185 * Invalidate a guest-backed context.
186 */
187typedef
188#include "vmware_pack_begin.h"
189struct SVGA3dCmdDXInvalidateContext {
190 uint32 cid;
191}
192#include "vmware_pack_end.h"
193SVGA3dCmdDXInvalidateContext; /* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT */
194
195typedef
196#include "vmware_pack_begin.h"
197struct SVGA3dReplyFormatData {
198 uint32 formatSupport;
199 uint32 msaa2xQualityLevels:5;
200 uint32 msaa4xQualityLevels:5;
201 uint32 msaa8xQualityLevels:5;
202 uint32 msaa16xQualityLevels:5;
203 uint32 msaa32xQualityLevels:5;
204 uint32 pad:7;
205}
206#include "vmware_pack_end.h"
207SVGA3dReplyFormatData;
208
209typedef
210#include "vmware_pack_begin.h"
211struct SVGA3dCmdDXSetSingleConstantBuffer {
212 uint32 slot;
213 SVGA3dShaderType type;
214 SVGA3dSurfaceId sid;
215 uint32 offsetInBytes;
216 uint32 sizeInBytes;
217}
218#include "vmware_pack_end.h"
219SVGA3dCmdDXSetSingleConstantBuffer;
220/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER */
221
222typedef
223#include "vmware_pack_begin.h"
224struct SVGA3dCmdDXSetShaderResources {
225 uint32 startView;
226 SVGA3dShaderType type;
227
228 /*
229 * Followed by a variable number of SVGA3dShaderResourceViewId's.
230 */
231}
232#include "vmware_pack_end.h"
233SVGA3dCmdDXSetShaderResources; /* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES */
234
235typedef
236#include "vmware_pack_begin.h"
237struct SVGA3dCmdDXSetShader {
238 SVGA3dShaderId shaderId;
239 SVGA3dShaderType type;
240}
241#include "vmware_pack_end.h"
242SVGA3dCmdDXSetShader; /* SVGA_3D_CMD_DX_SET_SHADER */
243
244typedef
245#include "vmware_pack_begin.h"
246struct SVGA3dCmdDXSetSamplers {
247 uint32 startSampler;
248 SVGA3dShaderType type;
249
250 /*
251 * Followed by a variable number of SVGA3dSamplerId's.
252 */
253}
254#include "vmware_pack_end.h"
255SVGA3dCmdDXSetSamplers; /* SVGA_3D_CMD_DX_SET_SAMPLERS */
256
257typedef
258#include "vmware_pack_begin.h"
259struct SVGA3dCmdDXDraw {
260 uint32 vertexCount;
261 uint32 startVertexLocation;
262}
263#include "vmware_pack_end.h"
264SVGA3dCmdDXDraw; /* SVGA_3D_CMD_DX_DRAW */
265
266typedef
267#include "vmware_pack_begin.h"
268struct SVGA3dCmdDXDrawIndexed {
269 uint32 indexCount;
270 uint32 startIndexLocation;
271 int32 baseVertexLocation;
272}
273#include "vmware_pack_end.h"
274SVGA3dCmdDXDrawIndexed; /* SVGA_3D_CMD_DX_DRAW_INDEXED */
275
276typedef
277#include "vmware_pack_begin.h"
278struct SVGA3dCmdDXDrawInstanced {
279 uint32 vertexCountPerInstance;
280 uint32 instanceCount;
281 uint32 startVertexLocation;
282 uint32 startInstanceLocation;
283}
284#include "vmware_pack_end.h"
285SVGA3dCmdDXDrawInstanced; /* SVGA_3D_CMD_DX_DRAW_INSTANCED */
286
287typedef
288#include "vmware_pack_begin.h"
289struct SVGA3dCmdDXDrawIndexedInstanced {
290 uint32 indexCountPerInstance;
291 uint32 instanceCount;
292 uint32 startIndexLocation;
293 int32 baseVertexLocation;
294 uint32 startInstanceLocation;
295}
296#include "vmware_pack_end.h"
297SVGA3dCmdDXDrawIndexedInstanced; /* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED */
298
299typedef
300#include "vmware_pack_begin.h"
301struct SVGA3dCmdDXDrawAuto {
302 uint32 pad0;
303}
304#include "vmware_pack_end.h"
305SVGA3dCmdDXDrawAuto; /* SVGA_3D_CMD_DX_DRAW_AUTO */
306
307typedef
308#include "vmware_pack_begin.h"
309struct SVGA3dCmdDXSetInputLayout {
310 SVGA3dElementLayoutId elementLayoutId;
311}
312#include "vmware_pack_end.h"
313SVGA3dCmdDXSetInputLayout; /* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT */
314
315typedef
316#include "vmware_pack_begin.h"
317struct SVGA3dVertexBuffer {
318 SVGA3dSurfaceId sid;
319 uint32 stride;
320 uint32 offset;
321}
322#include "vmware_pack_end.h"
323SVGA3dVertexBuffer;
324
325typedef
326#include "vmware_pack_begin.h"
327struct SVGA3dCmdDXSetVertexBuffers {
328 uint32 startBuffer;
329 /* Followed by a variable number of SVGA3dVertexBuffer's. */
330}
331#include "vmware_pack_end.h"
332SVGA3dCmdDXSetVertexBuffers; /* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS */
333
334typedef
335#include "vmware_pack_begin.h"
336struct SVGA3dCmdDXSetIndexBuffer {
337 SVGA3dSurfaceId sid;
338 SVGA3dSurfaceFormat format;
339 uint32 offset;
340}
341#include "vmware_pack_end.h"
342SVGA3dCmdDXSetIndexBuffer; /* SVGA_3D_CMD_DX_SET_INDEX_BUFFER */
343
344typedef
345#include "vmware_pack_begin.h"
346struct SVGA3dCmdDXSetTopology {
347 SVGA3dPrimitiveType topology;
348}
349#include "vmware_pack_end.h"
350SVGA3dCmdDXSetTopology; /* SVGA_3D_CMD_DX_SET_TOPOLOGY */
351
352typedef
353#include "vmware_pack_begin.h"
354struct SVGA3dCmdDXSetRenderTargets {
355 SVGA3dDepthStencilViewId depthStencilViewId;
356 /* Followed by a variable number of SVGA3dRenderTargetViewId's. */
357}
358#include "vmware_pack_end.h"
359SVGA3dCmdDXSetRenderTargets; /* SVGA_3D_CMD_DX_SET_RENDERTARGETS */
360
361typedef
362#include "vmware_pack_begin.h"
363struct SVGA3dCmdDXSetBlendState {
364 SVGA3dBlendStateId blendId;
365 float blendFactor[4];
366 uint32 sampleMask;
367}
368#include "vmware_pack_end.h"
369SVGA3dCmdDXSetBlendState; /* SVGA_3D_CMD_DX_SET_BLEND_STATE */
370
371typedef
372#include "vmware_pack_begin.h"
373struct SVGA3dCmdDXSetDepthStencilState {
374 SVGA3dDepthStencilStateId depthStencilId;
375 uint32 stencilRef;
376}
377#include "vmware_pack_end.h"
378SVGA3dCmdDXSetDepthStencilState; /* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE */
379
380typedef
381#include "vmware_pack_begin.h"
382struct SVGA3dCmdDXSetRasterizerState {
383 SVGA3dRasterizerStateId rasterizerId;
384}
385#include "vmware_pack_end.h"
386SVGA3dCmdDXSetRasterizerState; /* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE */
387
388#define SVGA3D_DXQUERY_FLAG_PREDICATEHINT (1 << 0)
389typedef uint32 SVGA3dDXQueryFlags;
390
391/*
392 * The SVGADXQueryDeviceState and SVGADXQueryDeviceBits are used by the device
393 * to track query state transitions, but are not intended to be used by the
394 * driver.
395 */
396#define SVGADX_QDSTATE_INVALID ((uint8)-1) /* Query has no state */
397#define SVGADX_QDSTATE_MIN 0
398#define SVGADX_QDSTATE_IDLE 0 /* Query hasn't started yet */
399#define SVGADX_QDSTATE_ACTIVE 1 /* Query is actively gathering data */
400#define SVGADX_QDSTATE_PENDING 2 /* Query is waiting for results */
401#define SVGADX_QDSTATE_FINISHED 3 /* Query has completed */
402#define SVGADX_QDSTATE_MAX 4
403typedef uint8 SVGADXQueryDeviceState;
404
405typedef
406#include "vmware_pack_begin.h"
407struct {
408 SVGA3dQueryTypeUint8 type;
409 uint16 pad0;
410 SVGADXQueryDeviceState state;
411 SVGA3dDXQueryFlags flags;
412 SVGAMobId mobid;
413 uint32 offset;
414}
415#include "vmware_pack_end.h"
416SVGACOTableDXQueryEntry;
417
418typedef
419#include "vmware_pack_begin.h"
420struct SVGA3dCmdDXDefineQuery {
421 SVGA3dQueryId queryId;
422 SVGA3dQueryType type;
423 SVGA3dDXQueryFlags flags;
424}
425#include "vmware_pack_end.h"
426SVGA3dCmdDXDefineQuery; /* SVGA_3D_CMD_DX_DEFINE_QUERY */
427
428typedef
429#include "vmware_pack_begin.h"
430struct SVGA3dCmdDXDestroyQuery {
431 SVGA3dQueryId queryId;
432}
433#include "vmware_pack_end.h"
434SVGA3dCmdDXDestroyQuery; /* SVGA_3D_CMD_DX_DESTROY_QUERY */
435
436typedef
437#include "vmware_pack_begin.h"
438struct SVGA3dCmdDXBindQuery {
439 SVGA3dQueryId queryId;
440 SVGAMobId mobid;
441}
442#include "vmware_pack_end.h"
443SVGA3dCmdDXBindQuery; /* SVGA_3D_CMD_DX_BIND_QUERY */
444
445typedef
446#include "vmware_pack_begin.h"
447struct SVGA3dCmdDXSetQueryOffset {
448 SVGA3dQueryId queryId;
449 uint32 mobOffset;
450}
451#include "vmware_pack_end.h"
452SVGA3dCmdDXSetQueryOffset; /* SVGA_3D_CMD_DX_SET_QUERY_OFFSET */
453
454typedef
455#include "vmware_pack_begin.h"
456struct SVGA3dCmdDXBeginQuery {
457 SVGA3dQueryId queryId;
458}
459#include "vmware_pack_end.h"
460SVGA3dCmdDXBeginQuery; /* SVGA_3D_CMD_DX_QUERY_BEGIN */
461
462typedef
463#include "vmware_pack_begin.h"
464struct SVGA3dCmdDXEndQuery {
465 SVGA3dQueryId queryId;
466}
467#include "vmware_pack_end.h"
468SVGA3dCmdDXEndQuery; /* SVGA_3D_CMD_DX_QUERY_END */
469
470typedef
471#include "vmware_pack_begin.h"
472struct SVGA3dCmdDXReadbackQuery {
473 SVGA3dQueryId queryId;
474}
475#include "vmware_pack_end.h"
476SVGA3dCmdDXReadbackQuery; /* SVGA_3D_CMD_DX_READBACK_QUERY */
477
478typedef
479#include "vmware_pack_begin.h"
480struct SVGA3dCmdDXMoveQuery {
481 SVGA3dQueryId queryId;
482 SVGAMobId mobid;
483 uint32 mobOffset;
484}
485#include "vmware_pack_end.h"
486SVGA3dCmdDXMoveQuery; /* SVGA_3D_CMD_DX_MOVE_QUERY */
487
488typedef
489#include "vmware_pack_begin.h"
490struct SVGA3dCmdDXBindAllQuery {
491 uint32 cid;
492 SVGAMobId mobid;
493}
494#include "vmware_pack_end.h"
495SVGA3dCmdDXBindAllQuery; /* SVGA_3D_CMD_DX_BIND_ALL_QUERY */
496
497typedef
498#include "vmware_pack_begin.h"
499struct SVGA3dCmdDXReadbackAllQuery {
500 uint32 cid;
501}
502#include "vmware_pack_end.h"
503SVGA3dCmdDXReadbackAllQuery; /* SVGA_3D_CMD_DX_READBACK_ALL_QUERY */
504
505typedef
506#include "vmware_pack_begin.h"
507struct SVGA3dCmdDXSetPredication {
508 SVGA3dQueryId queryId;
509 uint32 predicateValue;
510}
511#include "vmware_pack_end.h"
512SVGA3dCmdDXSetPredication; /* SVGA_3D_CMD_DX_SET_PREDICATION */
513
514typedef
515#include "vmware_pack_begin.h"
516struct MKS3dDXSOState {
517 uint32 offset; /* Starting offset */
518 uint32 intOffset; /* Internal offset */
519 uint32 vertexCount; /* vertices written */
520 uint32 sizeInBytes; /* max bytes to write */
521}
522#include "vmware_pack_end.h"
523SVGA3dDXSOState;
524
525/* Set the offset field to this value to append SO values to the buffer */
526#define SVGA3D_DX_SO_OFFSET_APPEND ((uint32) ~0u)
527
528typedef
529#include "vmware_pack_begin.h"
530struct SVGA3dSoTarget {
531 SVGA3dSurfaceId sid;
532 uint32 offset;
533 uint32 sizeInBytes;
534}
535#include "vmware_pack_end.h"
536SVGA3dSoTarget;
537
538typedef
539#include "vmware_pack_begin.h"
540struct SVGA3dCmdDXSetSOTargets {
541 uint32 pad0;
542 /* Followed by a variable number of SVGA3dSOTarget's. */
543}
544#include "vmware_pack_end.h"
545SVGA3dCmdDXSetSOTargets; /* SVGA_3D_CMD_DX_SET_SOTARGETS */
546
547typedef
548#include "vmware_pack_begin.h"
549struct SVGA3dViewport
550{
551 float x;
552 float y;
553 float width;
554 float height;
555 float minDepth;
556 float maxDepth;
557}
558#include "vmware_pack_end.h"
559SVGA3dViewport;
560
561typedef
562#include "vmware_pack_begin.h"
563struct SVGA3dCmdDXSetViewports {
564 uint32 pad0;
565 /* Followed by a variable number of SVGA3dViewport's. */
566}
567#include "vmware_pack_end.h"
568SVGA3dCmdDXSetViewports; /* SVGA_3D_CMD_DX_SET_VIEWPORTS */
569
570#define SVGA3D_DX_MAX_VIEWPORTS 16
571
572typedef
573#include "vmware_pack_begin.h"
574struct SVGA3dCmdDXSetScissorRects {
575 uint32 pad0;
576 /* Followed by a variable number of SVGASignedRect's. */
577}
578#include "vmware_pack_end.h"
579SVGA3dCmdDXSetScissorRects; /* SVGA_3D_CMD_DX_SET_SCISSORRECTS */
580
581#define SVGA3D_DX_MAX_SCISSORRECTS 16
582
583typedef
584#include "vmware_pack_begin.h"
585struct SVGA3dCmdDXClearRenderTargetView {
586 SVGA3dRenderTargetViewId renderTargetViewId;
587 SVGA3dRGBAFloat rgba;
588}
589#include "vmware_pack_end.h"
590SVGA3dCmdDXClearRenderTargetView; /* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW */
591
592typedef
593#include "vmware_pack_begin.h"
594struct SVGA3dCmdDXClearDepthStencilView {
595 uint16 flags;
596 uint16 stencil;
597 SVGA3dDepthStencilViewId depthStencilViewId;
598 float depth;
599}
600#include "vmware_pack_end.h"
601SVGA3dCmdDXClearDepthStencilView; /* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW */
602
603typedef
604#include "vmware_pack_begin.h"
605struct SVGA3dCmdDXPredCopyRegion {
606 SVGA3dSurfaceId dstSid;
607 uint32 dstSubResource;
608 SVGA3dSurfaceId srcSid;
609 uint32 srcSubResource;
610 SVGA3dCopyBox box;
611}
612#include "vmware_pack_end.h"
613SVGA3dCmdDXPredCopyRegion;
614/* SVGA_3D_CMD_DX_PRED_COPY_REGION */
615
616typedef
617#include "vmware_pack_begin.h"
618struct SVGA3dCmdDXPredCopy {
619 SVGA3dSurfaceId dstSid;
620 SVGA3dSurfaceId srcSid;
621}
622#include "vmware_pack_end.h"
623SVGA3dCmdDXPredCopy; /* SVGA_3D_CMD_DX_PRED_COPY */
624
625typedef
626#include "vmware_pack_begin.h"
627struct SVGA3dCmdDXBufferCopy {
628 SVGA3dSurfaceId dest;
629 SVGA3dSurfaceId src;
630 uint32 destX;
631 uint32 srcX;
632 uint32 width;
633}
634#include "vmware_pack_end.h"
635SVGA3dCmdDXBufferCopy;
636/* SVGA_3D_CMD_DX_BUFFER_COPY */
637
638typedef uint32 SVGA3dDXStretchBltMode;
639#define SVGADX_STRETCHBLT_LINEAR (1 << 0)
640#define SVGADX_STRETCHBLT_FORCE_SRC_SRGB (1 << 1)
641
642typedef
643#include "vmware_pack_begin.h"
644struct SVGA3dCmdDXStretchBlt {
645 SVGA3dSurfaceId srcSid;
646 uint32 srcSubResource;
647 SVGA3dSurfaceId dstSid;
648 uint32 destSubResource;
649 SVGA3dBox boxSrc;
650 SVGA3dBox boxDest;
651 SVGA3dDXStretchBltMode mode;
652}
653#include "vmware_pack_end.h"
654SVGA3dCmdDXStretchBlt; /* SVGA_3D_CMD_DX_STRETCHBLT */
655
656typedef
657#include "vmware_pack_begin.h"
658struct SVGA3dCmdDXGenMips {
659 SVGA3dShaderResourceViewId shaderResourceViewId;
660}
661#include "vmware_pack_end.h"
662SVGA3dCmdDXGenMips; /* SVGA_3D_CMD_DX_GENMIPS */
663
664/*
665 * Defines a resource/DX surface. Resources share the surfaceId namespace.
666 *
667 */
668typedef
669#include "vmware_pack_begin.h"
670struct SVGA3dCmdDefineGBSurface_v2 {
671 uint32 sid;
672 SVGA3dSurfaceFlags surfaceFlags;
673 SVGA3dSurfaceFormat format;
674 uint32 numMipLevels;
675 uint32 multisampleCount;
676 SVGA3dTextureFilter autogenFilter;
677 SVGA3dSize size;
678 uint32 arraySize;
679 uint32 pad;
680}
681#include "vmware_pack_end.h"
682SVGA3dCmdDefineGBSurface_v2; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 */
683
684/*
685 * Update a sub-resource in a guest-backed resource.
686 * (Inform the device that the guest-contents have been updated.)
687 */
688typedef
689#include "vmware_pack_begin.h"
690struct SVGA3dCmdDXUpdateSubResource {
691 SVGA3dSurfaceId sid;
692 uint32 subResource;
693 SVGA3dBox box;
694}
695#include "vmware_pack_end.h"
696SVGA3dCmdDXUpdateSubResource; /* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE */
697
698/*
699 * Readback a subresource in a guest-backed resource.
700 * (Request the device to flush the dirty contents into the guest.)
701 */
702typedef
703#include "vmware_pack_begin.h"
704struct SVGA3dCmdDXReadbackSubResource {
705 SVGA3dSurfaceId sid;
706 uint32 subResource;
707}
708#include "vmware_pack_end.h"
709SVGA3dCmdDXReadbackSubResource; /* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE */
710
711/*
712 * Invalidate an image in a guest-backed surface.
713 * (Notify the device that the contents can be lost.)
714 */
715typedef
716#include "vmware_pack_begin.h"
717struct SVGA3dCmdDXInvalidateSubResource {
718 SVGA3dSurfaceId sid;
719 uint32 subResource;
720}
721#include "vmware_pack_end.h"
722SVGA3dCmdDXInvalidateSubResource; /* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE */
723
724
725/*
726 * Raw byte wise transfer from a buffer surface into another surface
727 * of the requested box.
728 */
729typedef
730#include "vmware_pack_begin.h"
731struct SVGA3dCmdDXTransferFromBuffer {
732 SVGA3dSurfaceId srcSid;
733 uint32 srcOffset;
734 uint32 srcPitch;
735 uint32 srcSlicePitch;
736 SVGA3dSurfaceId destSid;
737 uint32 destSubResource;
738 SVGA3dBox destBox;
739}
740#include "vmware_pack_end.h"
741SVGA3dCmdDXTransferFromBuffer; /* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER */
742
743
744/*
745 * Raw byte wise transfer from a buffer surface into another surface
746 * of the requested box. Supported if SVGA3D_DEVCAP_DXCONTEXT is set.
747 * The context is implied from the command buffer header.
748 */
749typedef
750#include "vmware_pack_begin.h"
751struct SVGA3dCmdDXPredTransferFromBuffer {
752 SVGA3dSurfaceId srcSid;
753 uint32 srcOffset;
754 uint32 srcPitch;
755 uint32 srcSlicePitch;
756 SVGA3dSurfaceId destSid;
757 uint32 destSubResource;
758 SVGA3dBox destBox;
759}
760#include "vmware_pack_end.h"
761SVGA3dCmdDXPredTransferFromBuffer;
762/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER */
763
764
765typedef
766#include "vmware_pack_begin.h"
767struct SVGA3dCmdDXSurfaceCopyAndReadback {
768 SVGA3dSurfaceId srcSid;
769 SVGA3dSurfaceId destSid;
770 SVGA3dCopyBox box;
771}
772#include "vmware_pack_end.h"
773SVGA3dCmdDXSurfaceCopyAndReadback;
774/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK */
775
776
777typedef
778#include "vmware_pack_begin.h"
779struct {
780 union {
781 struct {
782 uint32 firstElement;
783 uint32 numElements;
784 uint32 pad0;
785 uint32 pad1;
786 } buffer;
787 struct {
788 uint32 mostDetailedMip;
789 uint32 firstArraySlice;
790 uint32 mipLevels;
791 uint32 arraySize;
792 } tex;
793 struct {
794 uint32 firstElement;
795 uint32 numElements;
796 uint32 flags;
797 uint32 pad0;
798 } bufferex;
799 };
800}
801#include "vmware_pack_end.h"
802SVGA3dShaderResourceViewDesc;
803
804typedef
805#include "vmware_pack_begin.h"
806struct {
807 SVGA3dSurfaceId sid;
808 SVGA3dSurfaceFormat format;
809 SVGA3dResourceType resourceDimension;
810 SVGA3dShaderResourceViewDesc desc;
811 uint32 pad;
812}
813#include "vmware_pack_end.h"
814SVGACOTableDXSRViewEntry;
815
816typedef
817#include "vmware_pack_begin.h"
818struct SVGA3dCmdDXDefineShaderResourceView {
819 SVGA3dShaderResourceViewId shaderResourceViewId;
820
821 SVGA3dSurfaceId sid;
822 SVGA3dSurfaceFormat format;
823 SVGA3dResourceType resourceDimension;
824
825 SVGA3dShaderResourceViewDesc desc;
826}
827#include "vmware_pack_end.h"
828SVGA3dCmdDXDefineShaderResourceView;
829/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW */
830
831typedef
832#include "vmware_pack_begin.h"
833struct SVGA3dCmdDXDestroyShaderResourceView {
834 SVGA3dShaderResourceViewId shaderResourceViewId;
835}
836#include "vmware_pack_end.h"
837SVGA3dCmdDXDestroyShaderResourceView;
838/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW */
839
840typedef
841#include "vmware_pack_begin.h"
842struct SVGA3dRenderTargetViewDesc {
843 union {
844 struct {
845 uint32 firstElement;
846 uint32 numElements;
847 } buffer;
848 struct {
849 uint32 mipSlice;
850 uint32 firstArraySlice;
851 uint32 arraySize;
852 } tex; /* 1d, 2d, cube */
853 struct {
854 uint32 mipSlice;
855 uint32 firstW;
856 uint32 wSize;
857 } tex3D;
858 };
859}
860#include "vmware_pack_end.h"
861SVGA3dRenderTargetViewDesc;
862
863typedef
864#include "vmware_pack_begin.h"
865struct {
866 SVGA3dSurfaceId sid;
867 SVGA3dSurfaceFormat format;
868 SVGA3dResourceType resourceDimension;
869 SVGA3dRenderTargetViewDesc desc;
870 uint32 pad[2];
871}
872#include "vmware_pack_end.h"
873SVGACOTableDXRTViewEntry;
874
875typedef
876#include "vmware_pack_begin.h"
877struct SVGA3dCmdDXDefineRenderTargetView {
878 SVGA3dRenderTargetViewId renderTargetViewId;
879
880 SVGA3dSurfaceId sid;
881 SVGA3dSurfaceFormat format;
882 SVGA3dResourceType resourceDimension;
883
884 SVGA3dRenderTargetViewDesc desc;
885}
886#include "vmware_pack_end.h"
887SVGA3dCmdDXDefineRenderTargetView;
888/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW */
889
890typedef
891#include "vmware_pack_begin.h"
892struct SVGA3dCmdDXDestroyRenderTargetView {
893 SVGA3dRenderTargetViewId renderTargetViewId;
894}
895#include "vmware_pack_end.h"
896SVGA3dCmdDXDestroyRenderTargetView;
897/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW */
898
899/*
900 */
901#define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_DEPTH 0x01
902#define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_STENCIL 0x02
903#define SVGA3D_DXDSVIEW_CREATE_FLAG_MASK 0x03
904typedef uint8 SVGA3DCreateDSViewFlags;
905
906typedef
907#include "vmware_pack_begin.h"
908struct {
909 SVGA3dSurfaceId sid;
910 SVGA3dSurfaceFormat format;
911 SVGA3dResourceType resourceDimension;
912 uint32 mipSlice;
913 uint32 firstArraySlice;
914 uint32 arraySize;
915 SVGA3DCreateDSViewFlags flags;
916 uint8 pad0;
917 uint16 pad1;
918 uint32 pad2;
919}
920#include "vmware_pack_end.h"
921SVGACOTableDXDSViewEntry;
922
923typedef
924#include "vmware_pack_begin.h"
925struct SVGA3dCmdDXDefineDepthStencilView {
926 SVGA3dDepthStencilViewId depthStencilViewId;
927
928 SVGA3dSurfaceId sid;
929 SVGA3dSurfaceFormat format;
930 SVGA3dResourceType resourceDimension;
931 uint32 mipSlice;
932 uint32 firstArraySlice;
933 uint32 arraySize;
934 SVGA3DCreateDSViewFlags flags;
935 uint8 pad0;
936 uint16 pad1;
937}
938#include "vmware_pack_end.h"
939SVGA3dCmdDXDefineDepthStencilView;
940/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW */
941
942typedef
943#include "vmware_pack_begin.h"
944struct SVGA3dCmdDXDestroyDepthStencilView {
945 SVGA3dDepthStencilViewId depthStencilViewId;
946}
947#include "vmware_pack_end.h"
948SVGA3dCmdDXDestroyDepthStencilView;
949/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW */
950
951typedef
952#include "vmware_pack_begin.h"
953struct SVGA3dInputElementDesc {
954 uint32 inputSlot;
955 uint32 alignedByteOffset;
956 SVGA3dSurfaceFormat format;
957 SVGA3dInputClassification inputSlotClass;
958 uint32 instanceDataStepRate;
959 uint32 inputRegister;
960}
961#include "vmware_pack_end.h"
962SVGA3dInputElementDesc;
963
964typedef
965#include "vmware_pack_begin.h"
966struct {
967 /*
968 * XXX: How many of these can there be?
969 */
970 uint32 elid;
971 uint32 numDescs;
972 SVGA3dInputElementDesc desc[32];
973 uint32 pad[62];
974}
975#include "vmware_pack_end.h"
976SVGACOTableDXElementLayoutEntry;
977
978typedef
979#include "vmware_pack_begin.h"
980struct SVGA3dCmdDXDefineElementLayout {
981 SVGA3dElementLayoutId elementLayoutId;
982 /* Followed by a variable number of SVGA3dInputElementDesc's. */
983}
984#include "vmware_pack_end.h"
985SVGA3dCmdDXDefineElementLayout;
986/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT */
987
988typedef
989#include "vmware_pack_begin.h"
990struct SVGA3dCmdDXDestroyElementLayout {
991 SVGA3dElementLayoutId elementLayoutId;
992}
993#include "vmware_pack_end.h"
994SVGA3dCmdDXDestroyElementLayout;
995/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT */
996
997
998#define SVGA3D_DX_MAX_RENDER_TARGETS 8
999
1000typedef
1001#include "vmware_pack_begin.h"
1002struct SVGA3dDXBlendStatePerRT {
1003 uint8 blendEnable;
1004 uint8 srcBlend;
1005 uint8 destBlend;
1006 uint8 blendOp;
1007 uint8 srcBlendAlpha;
1008 uint8 destBlendAlpha;
1009 uint8 blendOpAlpha;
1010 uint8 renderTargetWriteMask;
1011 uint8 logicOpEnable;
1012 uint8 logicOp;
1013 uint16 pad0;
1014}
1015#include "vmware_pack_end.h"
1016SVGA3dDXBlendStatePerRT;
1017
1018typedef
1019#include "vmware_pack_begin.h"
1020struct {
1021 uint8 alphaToCoverageEnable;
1022 uint8 independentBlendEnable;
1023 uint16 pad0;
1024 SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS];
1025 uint32 pad1[7];
1026}
1027#include "vmware_pack_end.h"
1028SVGACOTableDXBlendStateEntry;
1029
1030/*
1031 */
1032typedef
1033#include "vmware_pack_begin.h"
1034struct SVGA3dCmdDXDefineBlendState {
1035 SVGA3dBlendStateId blendId;
1036 uint8 alphaToCoverageEnable;
1037 uint8 independentBlendEnable;
1038 uint16 pad0;
1039 SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS];
1040}
1041#include "vmware_pack_end.h"
1042SVGA3dCmdDXDefineBlendState; /* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE */
1043
1044typedef
1045#include "vmware_pack_begin.h"
1046struct SVGA3dCmdDXDestroyBlendState {
1047 SVGA3dBlendStateId blendId;
1048}
1049#include "vmware_pack_end.h"
1050SVGA3dCmdDXDestroyBlendState; /* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE */
1051
1052typedef
1053#include "vmware_pack_begin.h"
1054struct {
1055 uint8 depthEnable;
1056 SVGA3dDepthWriteMask depthWriteMask;
1057 SVGA3dComparisonFunc depthFunc;
1058 uint8 stencilEnable;
1059 uint8 frontEnable;
1060 uint8 backEnable;
1061 uint8 stencilReadMask;
1062 uint8 stencilWriteMask;
1063
1064 uint8 frontStencilFailOp;
1065 uint8 frontStencilDepthFailOp;
1066 uint8 frontStencilPassOp;
1067 SVGA3dComparisonFunc frontStencilFunc;
1068
1069 uint8 backStencilFailOp;
1070 uint8 backStencilDepthFailOp;
1071 uint8 backStencilPassOp;
1072 SVGA3dComparisonFunc backStencilFunc;
1073}
1074#include "vmware_pack_end.h"
1075SVGACOTableDXDepthStencilEntry;
1076
1077/*
1078 */
1079typedef
1080#include "vmware_pack_begin.h"
1081struct SVGA3dCmdDXDefineDepthStencilState {
1082 SVGA3dDepthStencilStateId depthStencilId;
1083
1084 uint8 depthEnable;
1085 SVGA3dDepthWriteMask depthWriteMask;
1086 SVGA3dComparisonFunc depthFunc;
1087 uint8 stencilEnable;
1088 uint8 frontEnable;
1089 uint8 backEnable;
1090 uint8 stencilReadMask;
1091 uint8 stencilWriteMask;
1092
1093 uint8 frontStencilFailOp;
1094 uint8 frontStencilDepthFailOp;
1095 uint8 frontStencilPassOp;
1096 SVGA3dComparisonFunc frontStencilFunc;
1097
1098 uint8 backStencilFailOp;
1099 uint8 backStencilDepthFailOp;
1100 uint8 backStencilPassOp;
1101 SVGA3dComparisonFunc backStencilFunc;
1102}
1103#include "vmware_pack_end.h"
1104SVGA3dCmdDXDefineDepthStencilState;
1105/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE */
1106
1107typedef
1108#include "vmware_pack_begin.h"
1109struct SVGA3dCmdDXDestroyDepthStencilState {
1110 SVGA3dDepthStencilStateId depthStencilId;
1111}
1112#include "vmware_pack_end.h"
1113SVGA3dCmdDXDestroyDepthStencilState;
1114/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE */
1115
1116typedef
1117#include "vmware_pack_begin.h"
1118struct {
1119 uint8 fillMode;
1120 SVGA3dCullMode cullMode;
1121 uint8 frontCounterClockwise;
1122 uint8 provokingVertexLast;
1123 int32 depthBias;
1124 float depthBiasClamp;
1125 float slopeScaledDepthBias;
1126 uint8 depthClipEnable;
1127 uint8 scissorEnable;
1128 uint8 multisampleEnable;
1129 uint8 antialiasedLineEnable;
1130 float lineWidth;
1131 uint8 lineStippleEnable;
1132 uint8 lineStippleFactor;
1133 uint16 lineStipplePattern;
1134 uint32 forcedSampleCount;
1135}
1136#include "vmware_pack_end.h"
1137SVGACOTableDXRasterizerStateEntry;
1138
1139/*
1140 */
1141typedef
1142#include "vmware_pack_begin.h"
1143struct SVGA3dCmdDXDefineRasterizerState {
1144 SVGA3dRasterizerStateId rasterizerId;
1145
1146 uint8 fillMode;
1147 SVGA3dCullMode cullMode;
1148 uint8 frontCounterClockwise;
1149 uint8 provokingVertexLast;
1150 int32 depthBias;
1151 float depthBiasClamp;
1152 float slopeScaledDepthBias;
1153 uint8 depthClipEnable;
1154 uint8 scissorEnable;
1155 uint8 multisampleEnable;
1156 uint8 antialiasedLineEnable;
1157 float lineWidth;
1158 uint8 lineStippleEnable;
1159 uint8 lineStippleFactor;
1160 uint16 lineStipplePattern;
1161}
1162#include "vmware_pack_end.h"
1163SVGA3dCmdDXDefineRasterizerState;
1164/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE */
1165
1166typedef
1167#include "vmware_pack_begin.h"
1168struct SVGA3dCmdDXDestroyRasterizerState {
1169 SVGA3dRasterizerStateId rasterizerId;
1170}
1171#include "vmware_pack_end.h"
1172SVGA3dCmdDXDestroyRasterizerState;
1173/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE */
1174
1175typedef
1176#include "vmware_pack_begin.h"
1177struct {
1178 SVGA3dFilter filter;
1179 uint8 addressU;
1180 uint8 addressV;
1181 uint8 addressW;
1182 uint8 pad0;
1183 float mipLODBias;
1184 uint8 maxAnisotropy;
1185 SVGA3dComparisonFunc comparisonFunc;
1186 uint16 pad1;
1187 SVGA3dRGBAFloat borderColor;
1188 float minLOD;
1189 float maxLOD;
1190 uint32 pad2[6];
1191}
1192#include "vmware_pack_end.h"
1193SVGACOTableDXSamplerEntry;
1194
1195/*
1196 */
1197typedef
1198#include "vmware_pack_begin.h"
1199struct SVGA3dCmdDXDefineSamplerState {
1200 SVGA3dSamplerId samplerId;
1201 SVGA3dFilter filter;
1202 uint8 addressU;
1203 uint8 addressV;
1204 uint8 addressW;
1205 uint8 pad0;
1206 float mipLODBias;
1207 uint8 maxAnisotropy;
1208 SVGA3dComparisonFunc comparisonFunc;
1209 uint16 pad1;
1210 SVGA3dRGBAFloat borderColor;
1211 float minLOD;
1212 float maxLOD;
1213}
1214#include "vmware_pack_end.h"
1215SVGA3dCmdDXDefineSamplerState; /* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE */
1216
1217typedef
1218#include "vmware_pack_begin.h"
1219struct SVGA3dCmdDXDestroySamplerState {
1220 SVGA3dSamplerId samplerId;
1221}
1222#include "vmware_pack_end.h"
1223SVGA3dCmdDXDestroySamplerState; /* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE */
1224
1225/*
1226 */
1227typedef
1228#include "vmware_pack_begin.h"
1229struct SVGA3dSignatureEntry {
1230 uint8 systemValue;
1231 uint8 reg; /* register is a reserved word */
1232 uint16 mask;
1233 uint8 registerComponentType;
1234 uint8 minPrecision;
1235 uint16 pad0;
1236}
1237#include "vmware_pack_end.h"
1238SVGA3dSignatureEntry;
1239
1240typedef
1241#include "vmware_pack_begin.h"
1242struct SVGA3dCmdDXDefineShader {
1243 SVGA3dShaderId shaderId;
1244 SVGA3dShaderType type;
1245 uint32 sizeInBytes; /* Number of bytes of shader text. */
1246}
1247#include "vmware_pack_end.h"
1248SVGA3dCmdDXDefineShader; /* SVGA_3D_CMD_DX_DEFINE_SHADER */
1249
1250typedef
1251#include "vmware_pack_begin.h"
1252struct SVGACOTableDXShaderEntry {
1253 SVGA3dShaderType type;
1254 uint32 sizeInBytes;
1255 uint32 offsetInBytes;
1256 SVGAMobId mobid;
1257 uint32 numInputSignatureEntries;
1258 uint32 numOutputSignatureEntries;
1259
1260 uint32 numPatchConstantSignatureEntries;
1261
1262 uint32 pad;
1263}
1264#include "vmware_pack_end.h"
1265SVGACOTableDXShaderEntry;
1266
1267typedef
1268#include "vmware_pack_begin.h"
1269struct SVGA3dCmdDXDestroyShader {
1270 SVGA3dShaderId shaderId;
1271}
1272#include "vmware_pack_end.h"
1273SVGA3dCmdDXDestroyShader; /* SVGA_3D_CMD_DX_DESTROY_SHADER */
1274
1275typedef
1276#include "vmware_pack_begin.h"
1277struct SVGA3dCmdDXBindShader {
1278 uint32 cid;
1279 uint32 shid;
1280 SVGAMobId mobid;
1281 uint32 offsetInBytes;
1282}
1283#include "vmware_pack_end.h"
1284SVGA3dCmdDXBindShader; /* SVGA_3D_CMD_DX_BIND_SHADER */
1285
1286/*
1287 * The maximum number of streamout decl's in each streamout entry.
1288 */
1289#define SVGA3D_MAX_STREAMOUT_DECLS 64
1290
1291typedef
1292#include "vmware_pack_begin.h"
1293struct SVGA3dStreamOutputDeclarationEntry {
1294 uint32 outputSlot;
1295 uint32 registerIndex;
1296 uint8 registerMask;
1297 uint8 pad0;
1298 uint16 pad1;
1299 uint32 stream;
1300}
1301#include "vmware_pack_end.h"
1302SVGA3dStreamOutputDeclarationEntry;
1303
1304typedef
1305#include "vmware_pack_begin.h"
1306struct SVGAOTableStreamOutputEntry {
1307 uint32 numOutputStreamEntries;
1308 SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_STREAMOUT_DECLS];
1309 uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
1310 uint32 rasterizedStream;
1311 uint32 pad[250];
1312}
1313#include "vmware_pack_end.h"
1314SVGACOTableDXStreamOutputEntry;
1315
1316typedef
1317#include "vmware_pack_begin.h"
1318struct SVGA3dCmdDXDefineStreamOutput {
1319 SVGA3dStreamOutputId soid;
1320 uint32 numOutputStreamEntries;
1321 SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_STREAMOUT_DECLS];
1322 uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
1323 uint32 rasterizedStream;
1324}
1325#include "vmware_pack_end.h"
1326SVGA3dCmdDXDefineStreamOutput; /* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT */
1327
1328typedef
1329#include "vmware_pack_begin.h"
1330struct SVGA3dCmdDXDestroyStreamOutput {
1331 SVGA3dStreamOutputId soid;
1332}
1333#include "vmware_pack_end.h"
1334SVGA3dCmdDXDestroyStreamOutput; /* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT */
1335
1336typedef
1337#include "vmware_pack_begin.h"
1338struct SVGA3dCmdDXSetStreamOutput {
1339 SVGA3dStreamOutputId soid;
1340}
1341#include "vmware_pack_end.h"
1342SVGA3dCmdDXSetStreamOutput; /* SVGA_3D_CMD_DX_SET_STREAMOUTPUT */
1343
1344typedef
1345#include "vmware_pack_begin.h"
1346struct {
1347 uint64 value;
1348 uint32 mobId;
1349 uint32 mobOffset;
1350}
1351#include "vmware_pack_end.h"
1352SVGA3dCmdDXMobFence64; /* SVGA_3D_CMD_DX_MOB_FENCE_64 */
1353
1354/*
1355 * SVGA3dCmdSetCOTable --
1356 *
1357 * This command allows the guest to bind a mob to a context-object table.
1358 */
1359
1360typedef
1361#include "vmware_pack_begin.h"
1362struct SVGA3dCmdDXSetCOTable {
1363 uint32 cid;
1364 uint32 mobid;
1365 SVGACOTableType type;
1366 uint32 validSizeInBytes;
1367}
1368#include "vmware_pack_end.h"
1369SVGA3dCmdDXSetCOTable; /* SVGA_3D_CMD_DX_SET_COTABLE */
1370
1371typedef
1372#include "vmware_pack_begin.h"
1373struct SVGA3dCmdDXReadbackCOTable {
1374 uint32 cid;
1375 SVGACOTableType type;
1376}
1377#include "vmware_pack_end.h"
1378SVGA3dCmdDXReadbackCOTable; /* SVGA_3D_CMD_DX_READBACK_COTABLE */
1379
1380typedef
1381#include "vmware_pack_begin.h"
1382struct SVGA3dCOTableData {
1383 uint32 mobid;
1384}
1385#include "vmware_pack_end.h"
1386SVGA3dCOTableData;
1387
1388typedef
1389#include "vmware_pack_begin.h"
1390struct SVGA3dBufferBinding {
1391 uint32 bufferId;
1392 uint32 stride;
1393 uint32 offset;
1394}
1395#include "vmware_pack_end.h"
1396SVGA3dBufferBinding;
1397
1398typedef
1399#include "vmware_pack_begin.h"
1400struct SVGA3dConstantBufferBinding {
1401 uint32 sid;
1402 uint32 offsetInBytes;
1403 uint32 sizeInBytes;
1404}
1405#include "vmware_pack_end.h"
1406SVGA3dConstantBufferBinding;
1407
1408typedef
1409#include "vmware_pack_begin.h"
1410struct SVGADXInputAssemblyMobFormat {
1411 uint32 layoutId;
1412 SVGA3dBufferBinding vertexBuffers[SVGA3D_DX_MAX_VERTEXBUFFERS];
1413 uint32 indexBufferSid;
1414 uint32 pad;
1415 uint32 indexBufferOffset;
1416 uint32 indexBufferFormat;
1417 uint32 topology;
1418}
1419#include "vmware_pack_end.h"
1420SVGADXInputAssemblyMobFormat;
1421
1422typedef
1423#include "vmware_pack_begin.h"
1424struct SVGADXContextMobFormat {
1425 SVGADXInputAssemblyMobFormat inputAssembly;
1426
1427 struct {
1428 uint32 blendStateId;
1429 uint32 blendFactor[4];
1430 uint32 sampleMask;
1431 uint32 depthStencilStateId;
1432 uint32 stencilRef;
1433 uint32 rasterizerStateId;
1434 uint32 depthStencilViewId;
1435 uint32 renderTargetViewIds[SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS];
1436 uint32 unorderedAccessViewIds[SVGA3D_MAX_UAVIEWS];
1437 } renderState;
1438
1439 struct {
1440 uint32 targets[SVGA3D_DX_MAX_SOTARGETS];
1441 uint32 soid;
1442 } streamOut;
1443 uint32 pad0[11];
1444
1445 uint8 numViewports;
1446 uint8 numScissorRects;
1447 uint16 pad1[1];
1448
1449 uint32 pad2[3];
1450
1451 SVGA3dViewport viewports[SVGA3D_DX_MAX_VIEWPORTS];
1452 uint32 pad3[32];
1453
1454 SVGASignedRect scissorRects[SVGA3D_DX_MAX_SCISSORRECTS];
1455 uint32 pad4[64];
1456
1457 struct {
1458 uint32 queryID;
1459 uint32 value;
1460 } predication;
1461 uint32 pad5[2];
1462
1463 struct {
1464 uint32 shaderId;
1465 SVGA3dConstantBufferBinding constantBuffers[SVGA3D_DX_MAX_CONSTBUFFERS];
1466 uint32 shaderResources[SVGA3D_DX_MAX_SRVIEWS];
1467 uint32 samplers[SVGA3D_DX_MAX_SAMPLERS];
1468 } shaderState[SVGA3D_NUM_SHADERTYPE];
1469 uint32 pad6[26];
1470
1471 SVGA3dQueryId queryID[SVGA3D_MAX_QUERY];
1472
1473 SVGA3dCOTableData cotables[SVGA_COTABLE_MAX];
1474 uint32 pad7[381];
1475}
1476#include "vmware_pack_end.h"
1477SVGADXContextMobFormat;
1478
1479typedef
1480#include "vmware_pack_begin.h"
1481struct SVGA3dCmdDXTempSetContext {
1482 uint32 dxcid;
1483}
1484#include "vmware_pack_end.h"
1485SVGA3dCmdDXTempSetContext; /* SVGA_3D_CMD_DX_TEMP_SET_CONTEXT */
1486
1487#endif /* _SVGA3D_DX_H_ */
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
new file mode 100644
index 000000000000..a1c36877ad55
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
@@ -0,0 +1,99 @@
1/**********************************************************
2 * Copyright 2007-2015 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_limits.h --
28 *
29 * SVGA 3d hardware limits
30 */
31
32#ifndef _SVGA3D_LIMITS_H_
33#define _SVGA3D_LIMITS_H_
34
35#define INCLUDE_ALLOW_MODULE
36#define INCLUDE_ALLOW_USERLEVEL
37#define INCLUDE_ALLOW_VMCORE
38
39#include "includeCheck.h"
40
41#define SVGA3D_NUM_CLIPPLANES 6
42#define SVGA3D_MAX_RENDER_TARGETS 8
43#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS (SVGA3D_MAX_RENDER_TARGETS)
44#define SVGA3D_MAX_UAVIEWS 8
45#define SVGA3D_MAX_CONTEXT_IDS 256
46#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
47
48/*
49 * Maximum ID a shader can be assigned on a given context.
50 */
51#define SVGA3D_MAX_SHADERIDS 5000
52/*
53 * Maximum number of shaders of a given type that can be defined
54 * (including all contexts).
55 */
56#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000
57
58#define SVGA3D_NUM_TEXTURE_UNITS 32
59#define SVGA3D_NUM_LIGHTS 8
60
61/*
62 * Maximum size in dwords of shader text the SVGA device will allow.
63 * Currently 8 MB.
64 */
65#define SVGA3D_MAX_SHADER_MEMORY (8 * 1024 * 1024 / sizeof(uint32))
66
67#define SVGA3D_MAX_CLIP_PLANES 6
68
69/*
70 * This is the limit to the number of fixed-function texture
71 * transforms and texture coordinates we can support. It does *not*
72 * correspond to the number of texture image units (samplers) we
73 * support!
74 */
75#define SVGA3D_MAX_TEXTURE_COORDS 8
76
77/*
78 * Number of faces in a cubemap.
79 */
80#define SVGA3D_MAX_SURFACE_FACES 6
81
82/*
83 * Maximum number of array indexes in a GB surface (with DX enabled).
84 */
85#define SVGA3D_MAX_SURFACE_ARRAYSIZE 512
86
87/*
88 * The maximum number of vertex arrays we're guaranteed to support in
89 * SVGA_3D_CMD_DRAWPRIMITIVES.
90 */
91#define SVGA3D_MAX_VERTEX_ARRAYS 32
92
93/*
94 * The maximum number of primitive ranges we're guaranteed to support
95 * in SVGA_3D_CMD_DRAWPRIMITIVES.
96 */
97#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
98
99#endif /* _SVGA3D_LIMITS_H_ */
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h
new file mode 100644
index 000000000000..b44ce648f592
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h
@@ -0,0 +1,50 @@
1/**********************************************************
2 * Copyright 1998-2015 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_reg.h --
28 *
29 * SVGA 3d hardware definitions
30 */
31
32#ifndef _SVGA3D_REG_H_
33#define _SVGA3D_REG_H_
34
35#define INCLUDE_ALLOW_MODULE
36#define INCLUDE_ALLOW_USERLEVEL
37#define INCLUDE_ALLOW_VMCORE
38
39#include "includeCheck.h"
40
41#include "svga_reg.h"
42
43#include "svga3d_types.h"
44#include "svga3d_limits.h"
45#include "svga3d_cmd.h"
46#include "svga3d_dx.h"
47#include "svga3d_devcaps.h"
48
49
50#endif /* _SVGA3D_REG_H_ */
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
new file mode 100644
index 000000000000..58704f0a4607
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
@@ -0,0 +1,1204 @@
1/**************************************************************************
2 *
3 * Copyright © 2008-2015 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#ifdef __KERNEL__
29
30#include <drm/vmwgfx_drm.h>
31#define surf_size_struct struct drm_vmw_size
32
33#else /* __KERNEL__ */
34
35#ifndef ARRAY_SIZE
36#define ARRAY_SIZE(_A) (sizeof(_A) / sizeof((_A)[0]))
37#endif /* ARRAY_SIZE */
38
39#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
40#define max_t(type, x, y) ((x) > (y) ? (x) : (y))
41#define surf_size_struct SVGA3dSize
42#define u32 uint32
43
44#endif /* __KERNEL__ */
45
46#include "svga3d_reg.h"
47
48/*
49 * enum svga3d_block_desc describes the active data channels in a block.
50 *
51 * There can be at-most four active channels in a block:
52 * 1. Red, bump W, luminance and depth are stored in the first channel.
53 * 2. Green, bump V and stencil are stored in the second channel.
54 * 3. Blue and bump U are stored in the third channel.
55 * 4. Alpha and bump Q are stored in the fourth channel.
56 *
57 * Block channels can be used to store compressed and buffer data:
58 * 1. For compressed formats, only the data channel is used and its size
59 * is equal to that of a singular block in the compression scheme.
60 * 2. For buffer formats, only the data channel is used and its size is
61 * exactly one byte in length.
62 * 3. In each case the bit depth represent the size of a singular block.
63 *
64 * Note: Compressed and IEEE formats do not use the bitMask structure.
65 */
66
67enum svga3d_block_desc {
68 SVGA3DBLOCKDESC_NONE = 0, /* No channels are active */
69 SVGA3DBLOCKDESC_BLUE = 1 << 0, /* Block with red channel
70 data */
71 SVGA3DBLOCKDESC_U = 1 << 0, /* Block with bump U channel
72 data */
73 SVGA3DBLOCKDESC_UV_VIDEO = 1 << 7, /* Block with alternating video
74 U and V */
75 SVGA3DBLOCKDESC_GREEN = 1 << 1, /* Block with green channel
76 data */
77 SVGA3DBLOCKDESC_V = 1 << 1, /* Block with bump V channel
78 data */
79 SVGA3DBLOCKDESC_STENCIL = 1 << 1, /* Block with a stencil
80 channel */
81 SVGA3DBLOCKDESC_RED = 1 << 2, /* Block with blue channel
82 data */
83 SVGA3DBLOCKDESC_W = 1 << 2, /* Block with bump W channel
84 data */
85 SVGA3DBLOCKDESC_LUMINANCE = 1 << 2, /* Block with luminance channel
86 data */
87 SVGA3DBLOCKDESC_Y = 1 << 2, /* Block with video luminance
88 data */
89 SVGA3DBLOCKDESC_DEPTH = 1 << 2, /* Block with depth channel */
90 SVGA3DBLOCKDESC_ALPHA = 1 << 3, /* Block with an alpha
91 channel */
92 SVGA3DBLOCKDESC_Q = 1 << 3, /* Block with bump Q channel
93 data */
94 SVGA3DBLOCKDESC_BUFFER = 1 << 4, /* Block stores 1 byte of
95 data */
96 SVGA3DBLOCKDESC_COMPRESSED = 1 << 5, /* Block stores n bytes of
97 data depending on the
98 compression method used */
99 SVGA3DBLOCKDESC_IEEE_FP = 1 << 6, /* Block stores data in an IEEE
100 floating point
101 representation in
102 all channels */
103 SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 8, /* Three separate blocks store
104 data. */
105 SVGA3DBLOCKDESC_U_VIDEO = 1 << 9, /* Block with U video data */
106 SVGA3DBLOCKDESC_V_VIDEO = 1 << 10, /* Block with V video data */
107 SVGA3DBLOCKDESC_EXP = 1 << 11, /* Shared exponent */
108 SVGA3DBLOCKDESC_SRGB = 1 << 12, /* Data is in sRGB format */
109 SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 13, /* 2 planes of Y, UV,
110 e.g., NV12. */
111 SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 14, /* 3 planes of separate
112 Y, U, V, e.g., YV12. */
113
114 SVGA3DBLOCKDESC_RG = SVGA3DBLOCKDESC_RED |
115 SVGA3DBLOCKDESC_GREEN,
116 SVGA3DBLOCKDESC_RGB = SVGA3DBLOCKDESC_RG |
117 SVGA3DBLOCKDESC_BLUE,
118 SVGA3DBLOCKDESC_RGB_SRGB = SVGA3DBLOCKDESC_RGB |
119 SVGA3DBLOCKDESC_SRGB,
120 SVGA3DBLOCKDESC_RGBA = SVGA3DBLOCKDESC_RGB |
121 SVGA3DBLOCKDESC_ALPHA,
122 SVGA3DBLOCKDESC_RGBA_SRGB = SVGA3DBLOCKDESC_RGBA |
123 SVGA3DBLOCKDESC_SRGB,
124 SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U |
125 SVGA3DBLOCKDESC_V,
126 SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV |
127 SVGA3DBLOCKDESC_LUMINANCE,
128 SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV |
129 SVGA3DBLOCKDESC_W,
130 SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW |
131 SVGA3DBLOCKDESC_ALPHA,
132 SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U |
133 SVGA3DBLOCKDESC_V |
134 SVGA3DBLOCKDESC_W |
135 SVGA3DBLOCKDESC_Q,
136 SVGA3DBLOCKDESC_LA = SVGA3DBLOCKDESC_LUMINANCE |
137 SVGA3DBLOCKDESC_ALPHA,
138 SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED |
139 SVGA3DBLOCKDESC_IEEE_FP,
140 SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP |
141 SVGA3DBLOCKDESC_GREEN,
142 SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP |
143 SVGA3DBLOCKDESC_BLUE,
144 SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RGB_FP |
145 SVGA3DBLOCKDESC_ALPHA,
146 SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH |
147 SVGA3DBLOCKDESC_STENCIL,
148 SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_UV_VIDEO |
149 SVGA3DBLOCKDESC_Y,
150 SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA |
151 SVGA3DBLOCKDESC_Y |
152 SVGA3DBLOCKDESC_U_VIDEO |
153 SVGA3DBLOCKDESC_V_VIDEO,
154 SVGA3DBLOCKDESC_RGBE = SVGA3DBLOCKDESC_RGB |
155 SVGA3DBLOCKDESC_EXP,
156 SVGA3DBLOCKDESC_COMPRESSED_SRGB = SVGA3DBLOCKDESC_COMPRESSED |
157 SVGA3DBLOCKDESC_SRGB,
158 SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_PLANAR_YUV |
159 SVGA3DBLOCKDESC_2PLANAR_YUV,
160 SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_PLANAR_YUV |
161 SVGA3DBLOCKDESC_3PLANAR_YUV,
162};
163
164/*
165 * SVGA3dSurfaceDesc describes the actual pixel data.
166 *
167 * This structure provides the following information:
168 * 1. Block description.
169 * 2. Dimensions of a block in the surface.
170 * 3. Size of block in bytes.
171 * 4. Bit depth of the pixel data.
172 * 5. Channel bit depths and masks (if applicable).
173 */
174struct svga3d_channel_def {
175 union {
176 u8 blue;
177 u8 u;
178 u8 uv_video;
179 u8 u_video;
180 };
181 union {
182 u8 green;
183 u8 v;
184 u8 stencil;
185 u8 v_video;
186 };
187 union {
188 u8 red;
189 u8 w;
190 u8 luminance;
191 u8 y;
192 u8 depth;
193 u8 data;
194 };
195 union {
196 u8 alpha;
197 u8 q;
198 u8 exp;
199 };
200};
201
202struct svga3d_surface_desc {
203 SVGA3dSurfaceFormat format;
204 enum svga3d_block_desc block_desc;
205 surf_size_struct block_size;
206 u32 bytes_per_block;
207 u32 pitch_bytes_per_block;
208
209 u32 total_bit_depth;
210 struct svga3d_channel_def bit_depth;
211 struct svga3d_channel_def bit_offset;
212};
213
214static const struct svga3d_surface_desc svga3d_surface_descs[] = {
215 {SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE,
216 {1, 1, 1}, 0, 0,
217 0, {{0}, {0}, {0}, {0}},
218 {{0}, {0}, {0}, {0}}},
219
220 {SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB,
221 {1, 1, 1}, 4, 4,
222 24, {{8}, {8}, {8}, {0}},
223 {{0}, {8}, {16}, {24}}},
224
225 {SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA,
226 {1, 1, 1}, 4, 4,
227 32, {{8}, {8}, {8}, {8}},
228 {{0}, {8}, {16}, {24}}},
229
230 {SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB,
231 {1, 1, 1}, 2, 2,
232 16, {{5}, {6}, {5}, {0}},
233 {{0}, {5}, {11}, {0}}},
234
235 {SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB,
236 {1, 1, 1}, 2, 2,
237 15, {{5}, {5}, {5}, {0}},
238 {{0}, {5}, {10}, {0}}},
239
240 {SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA,
241 {1, 1, 1}, 2, 2,
242 16, {{5}, {5}, {5}, {1}},
243 {{0}, {5}, {10}, {15}}},
244
245 {SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA,
246 {1, 1, 1}, 2, 2,
247 16, {{4}, {4}, {4}, {4}},
248 {{0}, {4}, {8}, {12}}},
249
250 {SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH,
251 {1, 1, 1}, 4, 4,
252 32, {{0}, {0}, {32}, {0}},
253 {{0}, {0}, {0}, {0}}},
254
255 {SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH,
256 {1, 1, 1}, 2, 2,
257 16, {{0}, {0}, {16}, {0}},
258 {{0}, {0}, {0}, {0}}},
259
260 {SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS,
261 {1, 1, 1}, 4, 4,
262 32, {{0}, {8}, {24}, {0}},
263 {{0}, {24}, {0}, {0}}},
264
265 {SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS,
266 {1, 1, 1}, 2, 2,
267 16, {{0}, {1}, {15}, {0}},
268 {{0}, {15}, {0}, {0}}},
269
270 {SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_LUMINANCE,
271 {1, 1, 1}, 1, 1,
272 8, {{0}, {0}, {8}, {0}},
273 {{0}, {0}, {0}, {0}}},
274
275 {SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA,
276 {1 , 1, 1}, 1, 1,
277 8, {{0}, {0}, {4}, {4}},
278 {{0}, {0}, {0}, {4}}},
279
280 {SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_LUMINANCE,
281 {1, 1, 1}, 2, 2,
282 16, {{0}, {0}, {16}, {0}},
283 {{0}, {0}, {0}, {0}}},
284
285 {SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA,
286 {1, 1, 1}, 2, 2,
287 16, {{0}, {0}, {8}, {8}},
288 {{0}, {0}, {0}, {8}}},
289
290 {SVGA3D_DXT1, SVGA3DBLOCKDESC_COMPRESSED,
291 {4, 4, 1}, 8, 8,
292 64, {{0}, {0}, {64}, {0}},
293 {{0}, {0}, {0}, {0}}},
294
295 {SVGA3D_DXT2, SVGA3DBLOCKDESC_COMPRESSED,
296 {4, 4, 1}, 16, 16,
297 128, {{0}, {0}, {128}, {0}},
298 {{0}, {0}, {0}, {0}}},
299
300 {SVGA3D_DXT3, SVGA3DBLOCKDESC_COMPRESSED,
301 {4, 4, 1}, 16, 16,
302 128, {{0}, {0}, {128}, {0}},
303 {{0}, {0}, {0}, {0}}},
304
305 {SVGA3D_DXT4, SVGA3DBLOCKDESC_COMPRESSED,
306 {4, 4, 1}, 16, 16,
307 128, {{0}, {0}, {128}, {0}},
308 {{0}, {0}, {0}, {0}}},
309
310 {SVGA3D_DXT5, SVGA3DBLOCKDESC_COMPRESSED,
311 {4, 4, 1}, 16, 16,
312 128, {{0}, {0}, {128}, {0}},
313 {{0}, {0}, {0}, {0}}},
314
315 {SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV,
316 {1, 1, 1}, 2, 2,
317 16, {{0}, {0}, {8}, {8}},
318 {{0}, {0}, {0}, {8}}},
319
320 {SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL,
321 {1, 1, 1}, 2, 2,
322 16, {{5}, {5}, {6}, {0}},
323 {{11}, {6}, {0}, {0}}},
324
325 {SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL,
326 {1, 1, 1}, 4, 4,
327 32, {{8}, {8}, {8}, {0}},
328 {{16}, {8}, {0}, {0}}},
329
330 {SVGA3D_BUMPL8V8U8, SVGA3DBLOCKDESC_UVL,
331 {1, 1, 1}, 3, 3,
332 24, {{8}, {8}, {8}, {0}},
333 {{16}, {8}, {0}, {0}}},
334
335 {SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP,
336 {1, 1, 1}, 8, 8,
337 64, {{16}, {16}, {16}, {16}},
338 {{32}, {16}, {0}, {48}}},
339
340 {SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP,
341 {1, 1, 1}, 16, 16,
342 128, {{32}, {32}, {32}, {32}},
343 {{64}, {32}, {0}, {96}}},
344
345 {SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA,
346 {1, 1, 1}, 4, 4,
347 32, {{10}, {10}, {10}, {2}},
348 {{0}, {10}, {20}, {30}}},
349
350 {SVGA3D_V8U8, SVGA3DBLOCKDESC_UV,
351 {1, 1, 1}, 2, 2,
352 16, {{8}, {8}, {0}, {0}},
353 {{8}, {0}, {0}, {0}}},
354
355 {SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ,
356 {1, 1, 1}, 4, 4,
357 32, {{8}, {8}, {8}, {8}},
358 {{24}, {16}, {8}, {0}}},
359
360 {SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UV,
361 {1, 1, 1}, 2, 2,
362 16, {{8}, {8}, {0}, {0}},
363 {{8}, {0}, {0}, {0}}},
364
365 {SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL,
366 {1, 1, 1}, 4, 4,
367 24, {{8}, {8}, {8}, {0}},
368 {{16}, {8}, {0}, {0}}},
369
370 {SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA,
371 {1, 1, 1}, 4, 4,
372 32, {{10}, {10}, {10}, {2}},
373 {{0}, {10}, {20}, {30}}},
374
375 {SVGA3D_ALPHA8, SVGA3DBLOCKDESC_ALPHA,
376 {1, 1, 1}, 1, 1,
377 8, {{0}, {0}, {0}, {8}},
378 {{0}, {0}, {0}, {0}}},
379
380 {SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP,
381 {1, 1, 1}, 2, 2,
382 16, {{0}, {0}, {16}, {0}},
383 {{0}, {0}, {0}, {0}}},
384
385 {SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP,
386 {1, 1, 1}, 4, 4,
387 32, {{0}, {0}, {32}, {0}},
388 {{0}, {0}, {0}, {0}}},
389
390 {SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP,
391 {1, 1, 1}, 4, 4,
392 32, {{0}, {16}, {16}, {0}},
393 {{0}, {16}, {0}, {0}}},
394
395 {SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP,
396 {1, 1, 1}, 8, 8,
397 64, {{0}, {32}, {32}, {0}},
398 {{0}, {32}, {0}, {0}}},
399
400 {SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER,
401 {1, 1, 1}, 1, 1,
402 8, {{0}, {0}, {8}, {0}},
403 {{0}, {0}, {0}, {0}}},
404
405 {SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH,
406 {1, 1, 1}, 4, 4,
407 32, {{0}, {0}, {24}, {0}},
408 {{0}, {24}, {0}, {0}}},
409
410 {SVGA3D_V16U16, SVGA3DBLOCKDESC_UV,
411 {1, 1, 1}, 4, 4,
412 32, {{16}, {16}, {0}, {0}},
413 {{16}, {0}, {0}, {0}}},
414
415 {SVGA3D_G16R16, SVGA3DBLOCKDESC_RG,
416 {1, 1, 1}, 4, 4,
417 32, {{0}, {16}, {16}, {0}},
418 {{0}, {0}, {16}, {0}}},
419
420 {SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA,
421 {1, 1, 1}, 8, 8,
422 64, {{16}, {16}, {16}, {16}},
423 {{32}, {16}, {0}, {48}}},
424
425 {SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV,
426 {1, 1, 1}, 2, 2,
427 16, {{8}, {0}, {8}, {0}},
428 {{0}, {0}, {8}, {0}}},
429
430 {SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV,
431 {1, 1, 1}, 2, 2,
432 16, {{8}, {0}, {8}, {0}},
433 {{8}, {0}, {0}, {0}}},
434
435 {SVGA3D_NV12, SVGA3DBLOCKDESC_NV12,
436 {2, 2, 1}, 6, 2,
437 48, {{0}, {0}, {48}, {0}},
438 {{0}, {0}, {0}, {0}}},
439
440 {SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV,
441 {1, 1, 1}, 4, 4,
442 32, {{8}, {8}, {8}, {8}},
443 {{0}, {8}, {16}, {24}}},
444
445 {SVGA3D_R32G32B32A32_TYPELESS, SVGA3DBLOCKDESC_RGBA,
446 {1, 1, 1}, 16, 16,
447 128, {{32}, {32}, {32}, {32}},
448 {{64}, {32}, {0}, {96}}},
449
450 {SVGA3D_R32G32B32A32_UINT, SVGA3DBLOCKDESC_RGBA,
451 {1, 1, 1}, 16, 16,
452 128, {{32}, {32}, {32}, {32}},
453 {{64}, {32}, {0}, {96}}},
454
455 {SVGA3D_R32G32B32A32_SINT, SVGA3DBLOCKDESC_UVWQ,
456 {1, 1, 1}, 16, 16,
457 128, {{32}, {32}, {32}, {32}},
458 {{64}, {32}, {0}, {96}}},
459
460 {SVGA3D_R32G32B32_TYPELESS, SVGA3DBLOCKDESC_RGB,
461 {1, 1, 1}, 12, 12,
462 96, {{32}, {32}, {32}, {0}},
463 {{64}, {32}, {0}, {0}}},
464
465 {SVGA3D_R32G32B32_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
466 {1, 1, 1}, 12, 12,
467 96, {{32}, {32}, {32}, {0}},
468 {{64}, {32}, {0}, {0}}},
469
470 {SVGA3D_R32G32B32_UINT, SVGA3DBLOCKDESC_RGB,
471 {1, 1, 1}, 12, 12,
472 96, {{32}, {32}, {32}, {0}},
473 {{64}, {32}, {0}, {0}}},
474
475 {SVGA3D_R32G32B32_SINT, SVGA3DBLOCKDESC_UVW,
476 {1, 1, 1}, 12, 12,
477 96, {{32}, {32}, {32}, {0}},
478 {{64}, {32}, {0}, {0}}},
479
480 {SVGA3D_R16G16B16A16_TYPELESS, SVGA3DBLOCKDESC_RGBA,
481 {1, 1, 1}, 8, 8,
482 64, {{16}, {16}, {16}, {16}},
483 {{32}, {16}, {0}, {48}}},
484
485 {SVGA3D_R16G16B16A16_UINT, SVGA3DBLOCKDESC_RGBA,
486 {1, 1, 1}, 8, 8,
487 64, {{16}, {16}, {16}, {16}},
488 {{32}, {16}, {0}, {48}}},
489
490 {SVGA3D_R16G16B16A16_SNORM, SVGA3DBLOCKDESC_UVWQ,
491 {1, 1, 1}, 8, 8,
492 64, {{16}, {16}, {16}, {16}},
493 {{32}, {16}, {0}, {48}}},
494
495 {SVGA3D_R16G16B16A16_SINT, SVGA3DBLOCKDESC_UVWQ,
496 {1, 1, 1}, 8, 8,
497 64, {{16}, {16}, {16}, {16}},
498 {{32}, {16}, {0}, {48}}},
499
500 {SVGA3D_R32G32_TYPELESS, SVGA3DBLOCKDESC_RG,
501 {1, 1, 1}, 8, 8,
502 64, {{0}, {32}, {32}, {0}},
503 {{0}, {32}, {0}, {0}}},
504
505 {SVGA3D_R32G32_UINT, SVGA3DBLOCKDESC_RG,
506 {1, 1, 1}, 8, 8,
507 64, {{0}, {32}, {32}, {0}},
508 {{0}, {32}, {0}, {0}}},
509
510 {SVGA3D_R32G32_SINT, SVGA3DBLOCKDESC_UV,
511 {1, 1, 1}, 8, 8,
512 64, {{0}, {32}, {32}, {0}},
513 {{0}, {32}, {0}, {0}}},
514
515 {SVGA3D_R32G8X24_TYPELESS, SVGA3DBLOCKDESC_RG,
516 {1, 1, 1}, 8, 8,
517 64, {{0}, {8}, {32}, {0}},
518 {{0}, {32}, {0}, {0}}},
519
520 {SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3DBLOCKDESC_DS,
521 {1, 1, 1}, 8, 8,
522 64, {{0}, {8}, {32}, {0}},
523 {{0}, {32}, {0}, {0}}},
524
525 {SVGA3D_R32_FLOAT_X8X24_TYPELESS, SVGA3DBLOCKDESC_R_FP,
526 {1, 1, 1}, 8, 8,
527 64, {{0}, {0}, {32}, {0}},
528 {{0}, {0}, {0}, {0}}},
529
530 {SVGA3D_X32_TYPELESS_G8X24_UINT, SVGA3DBLOCKDESC_GREEN,
531 {1, 1, 1}, 8, 8,
532 64, {{0}, {8}, {0}, {0}},
533 {{0}, {32}, {0}, {0}}},
534
535 {SVGA3D_R10G10B10A2_TYPELESS, SVGA3DBLOCKDESC_RGBA,
536 {1, 1, 1}, 4, 4,
537 32, {{10}, {10}, {10}, {2}},
538 {{0}, {10}, {20}, {30}}},
539
540 {SVGA3D_R10G10B10A2_UINT, SVGA3DBLOCKDESC_RGBA,
541 {1, 1, 1}, 4, 4,
542 32, {{10}, {10}, {10}, {2}},
543 {{0}, {10}, {20}, {30}}},
544
545 {SVGA3D_R11G11B10_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
546 {1, 1, 1}, 4, 4,
547 32, {{10}, {11}, {11}, {0}},
548 {{0}, {10}, {21}, {0}}},
549
550 {SVGA3D_R8G8B8A8_TYPELESS, SVGA3DBLOCKDESC_RGBA,
551 {1, 1, 1}, 4, 4,
552 32, {{8}, {8}, {8}, {8}},
553 {{16}, {8}, {0}, {24}}},
554
555 {SVGA3D_R8G8B8A8_UNORM, SVGA3DBLOCKDESC_RGBA,
556 {1, 1, 1}, 4, 4,
557 32, {{8}, {8}, {8}, {8}},
558 {{16}, {8}, {0}, {24}}},
559
560 {SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_SRGB,
561 {1, 1, 1}, 4, 4,
562 32, {{8}, {8}, {8}, {8}},
563 {{16}, {8}, {0}, {24}}},
564
565 {SVGA3D_R8G8B8A8_UINT, SVGA3DBLOCKDESC_RGBA,
566 {1, 1, 1}, 4, 4,
567 32, {{8}, {8}, {8}, {8}},
568 {{16}, {8}, {0}, {24}}},
569
570 {SVGA3D_R8G8B8A8_SINT, SVGA3DBLOCKDESC_RGBA,
571 {1, 1, 1}, 4, 4,
572 32, {{8}, {8}, {8}, {8}},
573 {{16}, {8}, {0}, {24}}},
574
575 {SVGA3D_R16G16_TYPELESS, SVGA3DBLOCKDESC_RG,
576 {1, 1, 1}, 4, 4,
577 32, {{0}, {16}, {16}, {0}},
578 {{0}, {16}, {0}, {0}}},
579
580 {SVGA3D_R16G16_UINT, SVGA3DBLOCKDESC_RG_FP,
581 {1, 1, 1}, 4, 4,
582 32, {{0}, {16}, {16}, {0}},
583 {{0}, {16}, {0}, {0}}},
584
585 {SVGA3D_R16G16_SINT, SVGA3DBLOCKDESC_UV,
586 {1, 1, 1}, 4, 4,
587 32, {{0}, {16}, {16}, {0}},
588 {{0}, {16}, {0}, {0}}},
589
590 {SVGA3D_R32_TYPELESS, SVGA3DBLOCKDESC_RED,
591 {1, 1, 1}, 4, 4,
592 32, {{0}, {0}, {32}, {0}},
593 {{0}, {0}, {0}, {0}}},
594
595 {SVGA3D_D32_FLOAT, SVGA3DBLOCKDESC_DEPTH,
596 {1, 1, 1}, 4, 4,
597 32, {{0}, {0}, {32}, {0}},
598 {{0}, {0}, {0}, {0}}},
599
600 {SVGA3D_R32_UINT, SVGA3DBLOCKDESC_RED,
601 {1, 1, 1}, 4, 4,
602 32, {{0}, {0}, {32}, {0}},
603 {{0}, {0}, {0}, {0}}},
604
605 {SVGA3D_R32_SINT, SVGA3DBLOCKDESC_RED,
606 {1, 1, 1}, 4, 4,
607 32, {{0}, {0}, {32}, {0}},
608 {{0}, {0}, {0}, {0}}},
609
610 {SVGA3D_R24G8_TYPELESS, SVGA3DBLOCKDESC_RG,
611 {1, 1, 1}, 4, 4,
612 32, {{0}, {8}, {24}, {0}},
613 {{0}, {24}, {0}, {0}}},
614
615 {SVGA3D_D24_UNORM_S8_UINT, SVGA3DBLOCKDESC_DS,
616 {1, 1, 1}, 4, 4,
617 32, {{0}, {8}, {24}, {0}},
618 {{0}, {24}, {0}, {0}}},
619
620 {SVGA3D_R24_UNORM_X8_TYPELESS, SVGA3DBLOCKDESC_RED,
621 {1, 1, 1}, 4, 4,
622 32, {{0}, {0}, {24}, {0}},
623 {{0}, {0}, {0}, {0}}},
624
625 {SVGA3D_X24_TYPELESS_G8_UINT, SVGA3DBLOCKDESC_GREEN,
626 {1, 1, 1}, 4, 4,
627 32, {{0}, {8}, {0}, {0}},
628 {{0}, {24}, {0}, {0}}},
629
630 {SVGA3D_R8G8_TYPELESS, SVGA3DBLOCKDESC_RG,
631 {1, 1, 1}, 2, 2,
632 16, {{0}, {8}, {8}, {0}},
633 {{0}, {8}, {0}, {0}}},
634
635 {SVGA3D_R8G8_UNORM, SVGA3DBLOCKDESC_RG,
636 {1, 1, 1}, 2, 2,
637 16, {{0}, {8}, {8}, {0}},
638 {{0}, {8}, {0}, {0}}},
639
640 {SVGA3D_R8G8_UINT, SVGA3DBLOCKDESC_RG,
641 {1, 1, 1}, 2, 2,
642 16, {{0}, {8}, {8}, {0}},
643 {{0}, {8}, {0}, {0}}},
644
645 {SVGA3D_R8G8_SINT, SVGA3DBLOCKDESC_UV,
646 {1, 1, 1}, 2, 2,
647 16, {{0}, {8}, {8}, {0}},
648 {{0}, {8}, {0}, {0}}},
649
650 {SVGA3D_R16_TYPELESS, SVGA3DBLOCKDESC_RED,
651 {1, 1, 1}, 2, 2,
652 16, {{0}, {0}, {16}, {0}},
653 {{0}, {0}, {0}, {0}}},
654
655 {SVGA3D_R16_UNORM, SVGA3DBLOCKDESC_RED,
656 {1, 1, 1}, 2, 2,
657 16, {{0}, {0}, {16}, {0}},
658 {{0}, {0}, {0}, {0}}},
659
660 {SVGA3D_R16_UINT, SVGA3DBLOCKDESC_RED,
661 {1, 1, 1}, 2, 2,
662 16, {{0}, {0}, {16}, {0}},
663 {{0}, {0}, {0}, {0}}},
664
665 {SVGA3D_R16_SNORM, SVGA3DBLOCKDESC_U,
666 {1, 1, 1}, 2, 2,
667 16, {{0}, {0}, {16}, {0}},
668 {{0}, {0}, {0}, {0}}},
669
670 {SVGA3D_R16_SINT, SVGA3DBLOCKDESC_U,
671 {1, 1, 1}, 2, 2,
672 16, {{0}, {0}, {16}, {0}},
673 {{0}, {0}, {0}, {0}}},
674
675 {SVGA3D_R8_TYPELESS, SVGA3DBLOCKDESC_RED,
676 {1, 1, 1}, 1, 1,
677 8, {{0}, {0}, {8}, {0}},
678 {{0}, {0}, {0}, {0}}},
679
680 {SVGA3D_R8_UNORM, SVGA3DBLOCKDESC_RED,
681 {1, 1, 1}, 1, 1,
682 8, {{0}, {0}, {8}, {0}},
683 {{0}, {0}, {0}, {0}}},
684
685 {SVGA3D_R8_UINT, SVGA3DBLOCKDESC_RED,
686 {1, 1, 1}, 1, 1,
687 8, {{0}, {0}, {8}, {0}},
688 {{0}, {0}, {0}, {0}}},
689
690 {SVGA3D_R8_SNORM, SVGA3DBLOCKDESC_U,
691 {1, 1, 1}, 1, 1,
692 8, {{0}, {0}, {8}, {0}},
693 {{0}, {0}, {0}, {0}}},
694
695 {SVGA3D_R8_SINT, SVGA3DBLOCKDESC_U,
696 {1, 1, 1}, 1, 1,
697 8, {{0}, {0}, {8}, {0}},
698 {{0}, {0}, {0}, {0}}},
699
700 {SVGA3D_P8, SVGA3DBLOCKDESC_RED,
701 {1, 1, 1}, 1, 1,
702 8, {{0}, {0}, {8}, {0}},
703 {{0}, {0}, {0}, {0}}},
704
705 {SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3DBLOCKDESC_RGBE,
706 {1, 1, 1}, 4, 4,
707 32, {{9}, {9}, {9}, {5}},
708 {{18}, {9}, {0}, {27}}},
709
710 {SVGA3D_R8G8_B8G8_UNORM, SVGA3DBLOCKDESC_RG,
711 {1, 1, 1}, 2, 2,
712 16, {{0}, {8}, {8}, {0}},
713 {{0}, {8}, {0}, {0}}},
714
715 {SVGA3D_G8R8_G8B8_UNORM, SVGA3DBLOCKDESC_RG,
716 {1, 1, 1}, 2, 2,
717 16, {{0}, {8}, {8}, {0}},
718 {{0}, {8}, {0}, {0}}},
719
720 {SVGA3D_BC1_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED,
721 {4, 4, 1}, 8, 8,
722 64, {{0}, {0}, {64}, {0}},
723 {{0}, {0}, {0}, {0}}},
724
725 {SVGA3D_BC1_UNORM_SRGB, SVGA3DBLOCKDESC_COMPRESSED_SRGB,
726 {4, 4, 1}, 8, 8,
727 64, {{0}, {0}, {64}, {0}},
728 {{0}, {0}, {0}, {0}}},
729
730 {SVGA3D_BC2_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED,
731 {4, 4, 1}, 16, 16,
732 128, {{0}, {0}, {128}, {0}},
733 {{0}, {0}, {0}, {0}}},
734
735 {SVGA3D_BC2_UNORM_SRGB, SVGA3DBLOCKDESC_COMPRESSED_SRGB,
736 {4, 4, 1}, 16, 16,
737 128, {{0}, {0}, {128}, {0}},
738 {{0}, {0}, {0}, {0}}},
739
740 {SVGA3D_BC3_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED,
741 {4, 4, 1}, 16, 16,
742 128, {{0}, {0}, {128}, {0}},
743 {{0}, {0}, {0}, {0}}},
744
745 {SVGA3D_BC3_UNORM_SRGB, SVGA3DBLOCKDESC_COMPRESSED_SRGB,
746 {4, 4, 1}, 16, 16,
747 128, {{0}, {0}, {128}, {0}},
748 {{0}, {0}, {0}, {0}}},
749
750 {SVGA3D_BC4_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED,
751 {4, 4, 1}, 8, 8,
752 64, {{0}, {0}, {64}, {0}},
753 {{0}, {0}, {0}, {0}}},
754
755 {SVGA3D_ATI1, SVGA3DBLOCKDESC_COMPRESSED,
756 {4, 4, 1}, 8, 8,
757 64, {{0}, {0}, {64}, {0}},
758 {{0}, {0}, {0}, {0}}},
759
760 {SVGA3D_BC4_SNORM, SVGA3DBLOCKDESC_COMPRESSED,
761 {4, 4, 1}, 8, 8,
762 64, {{0}, {0}, {64}, {0}},
763 {{0}, {0}, {0}, {0}}},
764
765 {SVGA3D_BC5_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED,
766 {4, 4, 1}, 16, 16,
767 128, {{0}, {0}, {128}, {0}},
768 {{0}, {0}, {0}, {0}}},
769
770 {SVGA3D_ATI2, SVGA3DBLOCKDESC_COMPRESSED,
771 {4, 4, 1}, 16, 16,
772 128, {{0}, {0}, {128}, {0}},
773 {{0}, {0}, {0}, {0}}},
774
775 {SVGA3D_BC5_SNORM, SVGA3DBLOCKDESC_COMPRESSED,
776 {4, 4, 1}, 16, 16,
777 128, {{0}, {0}, {128}, {0}},
778 {{0}, {0}, {0}, {0}}},
779
780 {SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, SVGA3DBLOCKDESC_RGBA,
781 {1, 1, 1}, 4, 4,
782 32, {{10}, {10}, {10}, {2}},
783 {{0}, {10}, {20}, {30}}},
784
785 {SVGA3D_B8G8R8A8_TYPELESS, SVGA3DBLOCKDESC_RGBA,
786 {1, 1, 1}, 4, 4,
787 32, {{8}, {8}, {8}, {8}},
788 {{0}, {8}, {16}, {24}}},
789
790 {SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_SRGB,
791 {1, 1, 1}, 4, 4,
792 32, {{8}, {8}, {8}, {8}},
793 {{0}, {8}, {16}, {24}}},
794
795 {SVGA3D_B8G8R8X8_TYPELESS, SVGA3DBLOCKDESC_RGB,
796 {1, 1, 1}, 4, 4,
797 24, {{8}, {8}, {8}, {0}},
798 {{0}, {8}, {16}, {24}}},
799
800 {SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3DBLOCKDESC_RGB_SRGB,
801 {1, 1, 1}, 4, 4,
802 24, {{8}, {8}, {8}, {0}},
803 {{0}, {8}, {16}, {24}}},
804
805 {SVGA3D_Z_DF16, SVGA3DBLOCKDESC_DEPTH,
806 {1, 1, 1}, 2, 2,
807 16, {{0}, {0}, {16}, {0}},
808 {{0}, {0}, {0}, {0}}},
809
810 {SVGA3D_Z_DF24, SVGA3DBLOCKDESC_DEPTH,
811 {1, 1, 1}, 4, 4,
812 32, {{0}, {8}, {24}, {0}},
813 {{0}, {24}, {0}, {0}}},
814
815 {SVGA3D_Z_D24S8_INT, SVGA3DBLOCKDESC_DS,
816 {1, 1, 1}, 4, 4,
817 32, {{0}, {8}, {24}, {0}},
818 {{0}, {24}, {0}, {0}}},
819
820 {SVGA3D_YV12, SVGA3DBLOCKDESC_YV12,
821 {2, 2, 1}, 6, 2,
822 48, {{0}, {0}, {48}, {0}},
823 {{0}, {0}, {0}, {0}}},
824
825 {SVGA3D_R32G32B32A32_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
826 {1, 1, 1}, 16, 16,
827 128, {{32}, {32}, {32}, {32}},
828 {{64}, {32}, {0}, {96}}},
829
830 {SVGA3D_R16G16B16A16_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
831 {1, 1, 1}, 8, 8,
832 64, {{16}, {16}, {16}, {16}},
833 {{32}, {16}, {0}, {48}}},
834
835 {SVGA3D_R16G16B16A16_UNORM, SVGA3DBLOCKDESC_RGBA,
836 {1, 1, 1}, 8, 8,
837 64, {{16}, {16}, {16}, {16}},
838 {{32}, {16}, {0}, {48}}},
839
840 {SVGA3D_R32G32_FLOAT, SVGA3DBLOCKDESC_RG_FP,
841 {1, 1, 1}, 8, 8,
842 64, {{0}, {32}, {32}, {0}},
843 {{0}, {32}, {0}, {0}}},
844
845 {SVGA3D_R10G10B10A2_UNORM, SVGA3DBLOCKDESC_RGBA,
846 {1, 1, 1}, 4, 4,
847 32, {{10}, {10}, {10}, {2}},
848 {{0}, {10}, {20}, {30}}},
849
850 {SVGA3D_R8G8B8A8_SNORM, SVGA3DBLOCKDESC_RGBA,
851 {1, 1, 1}, 4, 4,
852 32, {{8}, {8}, {8}, {8}},
853 {{24}, {16}, {8}, {0}}},
854
855 {SVGA3D_R16G16_FLOAT, SVGA3DBLOCKDESC_RG_FP,
856 {1, 1, 1}, 4, 4,
857 32, {{0}, {16}, {16}, {0}},
858 {{0}, {16}, {0}, {0}}},
859
860 {SVGA3D_R16G16_UNORM, SVGA3DBLOCKDESC_RG,
861 {1, 1, 1}, 4, 4,
862 32, {{0}, {16}, {16}, {0}},
863 {{0}, {0}, {16}, {0}}},
864
865 {SVGA3D_R16G16_SNORM, SVGA3DBLOCKDESC_RG,
866 {1, 1, 1}, 4, 4,
867 32, {{16}, {16}, {0}, {0}},
868 {{16}, {0}, {0}, {0}}},
869
870 {SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP,
871 {1, 1, 1}, 4, 4,
872 32, {{0}, {0}, {32}, {0}},
873 {{0}, {0}, {0}, {0}}},
874
875 {SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG,
876 {1, 1, 1}, 2, 2,
877 16, {{8}, {8}, {0}, {0}},
878 {{8}, {0}, {0}, {0}}},
879
880 {SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP,
881 {1, 1, 1}, 2, 2,
882 16, {{0}, {0}, {16}, {0}},
883 {{0}, {0}, {0}, {0}}},
884
885 {SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH,
886 {1, 1, 1}, 2, 2,
887 16, {{0}, {0}, {16}, {0}},
888 {{0}, {0}, {0}, {0}}},
889
890 {SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_ALPHA,
891 {1, 1, 1}, 1, 1,
892 8, {{0}, {0}, {0}, {8}},
893 {{0}, {0}, {0}, {0}}},
894
895 {SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_COMPRESSED,
896 {4, 4, 1}, 8, 8,
897 64, {{0}, {0}, {64}, {0}},
898 {{0}, {0}, {0}, {0}}},
899
900 {SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_COMPRESSED,
901 {4, 4, 1}, 16, 16,
902 128, {{0}, {0}, {128}, {0}},
903 {{0}, {0}, {0}, {0}}},
904
905 {SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_COMPRESSED,
906 {4, 4, 1}, 16, 16,
907 128, {{0}, {0}, {128}, {0}},
908 {{0}, {0}, {0}, {0}}},
909
910 {SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB,
911 {1, 1, 1}, 2, 2,
912 16, {{5}, {6}, {5}, {0}},
913 {{0}, {5}, {11}, {0}}},
914
915 {SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA,
916 {1, 1, 1}, 2, 2,
917 16, {{5}, {5}, {5}, {1}},
918 {{0}, {5}, {10}, {15}}},
919
920 {SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA,
921 {1, 1, 1}, 4, 4,
922 32, {{8}, {8}, {8}, {8}},
923 {{0}, {8}, {16}, {24}}},
924
925 {SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB,
926 {1, 1, 1}, 4, 4,
927 24, {{8}, {8}, {8}, {0}},
928 {{0}, {8}, {16}, {24}}},
929
930 {SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_COMPRESSED,
931 {4, 4, 1}, 8, 8,
932 64, {{0}, {0}, {64}, {0}},
933 {{0}, {0}, {0}, {0}}},
934
935 {SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_COMPRESSED,
936 {4, 4, 1}, 16, 16,
937 128, {{0}, {0}, {128}, {0}},
938 {{0}, {0}, {0}, {0}}},
939
940};
941
942static inline u32 clamped_umul32(u32 a, u32 b)
943{
944 uint64_t tmp = (uint64_t) a*b;
945 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp;
946}
947
948static inline const struct svga3d_surface_desc *
949svga3dsurface_get_desc(SVGA3dSurfaceFormat format)
950{
951 if (format < ARRAY_SIZE(svga3d_surface_descs))
952 return &svga3d_surface_descs[format];
953
954 return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID];
955}
956
957/*
958 *----------------------------------------------------------------------
959 *
960 * svga3dsurface_get_mip_size --
961 *
962 * Given a base level size and the mip level, compute the size of
963 * the mip level.
964 *
965 * Results:
966 * See above.
967 *
968 * Side effects:
969 * None.
970 *
971 *----------------------------------------------------------------------
972 */
973
974static inline surf_size_struct
975svga3dsurface_get_mip_size(surf_size_struct base_level, u32 mip_level)
976{
977 surf_size_struct size;
978
979 size.width = max_t(u32, base_level.width >> mip_level, 1);
980 size.height = max_t(u32, base_level.height >> mip_level, 1);
981 size.depth = max_t(u32, base_level.depth >> mip_level, 1);
982 return size;
983}
984
985static inline void
986svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc,
987 const surf_size_struct *pixel_size,
988 surf_size_struct *block_size)
989{
990 block_size->width = DIV_ROUND_UP(pixel_size->width,
991 desc->block_size.width);
992 block_size->height = DIV_ROUND_UP(pixel_size->height,
993 desc->block_size.height);
994 block_size->depth = DIV_ROUND_UP(pixel_size->depth,
995 desc->block_size.depth);
996}
997
998static inline bool
999svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc)
1000{
1001 return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0;
1002}
1003
1004static inline u32
1005svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc,
1006 const surf_size_struct *size)
1007{
1008 u32 pitch;
1009 surf_size_struct blocks;
1010
1011 svga3dsurface_get_size_in_blocks(desc, size, &blocks);
1012
1013 pitch = blocks.width * desc->pitch_bytes_per_block;
1014
1015 return pitch;
1016}
1017
1018/*
1019 *-----------------------------------------------------------------------------
1020 *
1021 * svga3dsurface_get_image_buffer_size --
1022 *
1023 * Return the number of bytes of buffer space required to store
1024 * one image of a surface, optionally using the specified pitch.
1025 *
1026 * If pitch is zero, it is assumed that rows are tightly packed.
1027 *
1028 * This function is overflow-safe. If the result would have
1029 * overflowed, instead we return MAX_UINT32.
1030 *
1031 * Results:
1032 * Byte count.
1033 *
1034 * Side effects:
1035 * None.
1036 *
1037 *-----------------------------------------------------------------------------
1038 */
1039
1040static inline u32
1041svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc,
1042 const surf_size_struct *size,
1043 u32 pitch)
1044{
1045 surf_size_struct image_blocks;
1046 u32 slice_size, total_size;
1047
1048 svga3dsurface_get_size_in_blocks(desc, size, &image_blocks);
1049
1050 if (svga3dsurface_is_planar_surface(desc)) {
1051 total_size = clamped_umul32(image_blocks.width,
1052 image_blocks.height);
1053 total_size = clamped_umul32(total_size, image_blocks.depth);
1054 total_size = clamped_umul32(total_size, desc->bytes_per_block);
1055 return total_size;
1056 }
1057
1058 if (pitch == 0)
1059 pitch = svga3dsurface_calculate_pitch(desc, size);
1060
1061 slice_size = clamped_umul32(image_blocks.height, pitch);
1062 total_size = clamped_umul32(slice_size, image_blocks.depth);
1063
1064 return total_size;
1065}
1066
1067static inline u32
1068svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
1069 surf_size_struct base_level_size,
1070 u32 num_mip_levels,
1071 u32 num_layers)
1072{
1073 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
1074 u32 total_size = 0;
1075 u32 mip;
1076
1077 for (mip = 0; mip < num_mip_levels; mip++) {
1078 surf_size_struct size =
1079 svga3dsurface_get_mip_size(base_level_size, mip);
1080 total_size += svga3dsurface_get_image_buffer_size(desc,
1081 &size, 0);
1082 }
1083
1084 return total_size * num_layers;
1085}
1086
1087
1088/**
1089 * svga3dsurface_get_pixel_offset - Compute the offset (in bytes) to a pixel
1090 * in an image (or volume).
1091 *
1092 * @width: The image width in pixels.
1093 * @height: The image height in pixels
1094 */
1095static inline u32
1096svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format,
1097 u32 width, u32 height,
1098 u32 x, u32 y, u32 z)
1099{
1100 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
1101 const u32 bw = desc->block_size.width, bh = desc->block_size.height;
1102 const u32 bd = desc->block_size.depth;
1103 const u32 rowstride = DIV_ROUND_UP(width, bw) * desc->bytes_per_block;
1104 const u32 imgstride = DIV_ROUND_UP(height, bh) * rowstride;
1105 const u32 offset = (z / bd * imgstride +
1106 y / bh * rowstride +
1107 x / bw * desc->bytes_per_block);
1108 return offset;
1109}
1110
1111
1112static inline u32
1113svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format,
1114 surf_size_struct baseLevelSize,
1115 u32 numMipLevels,
1116 u32 face,
1117 u32 mip)
1118
1119{
1120 u32 offset;
1121 u32 mipChainBytes;
1122 u32 mipChainBytesToLevel;
1123 u32 i;
1124 const struct svga3d_surface_desc *desc;
1125 surf_size_struct mipSize;
1126 u32 bytes;
1127
1128 desc = svga3dsurface_get_desc(format);
1129
1130 mipChainBytes = 0;
1131 mipChainBytesToLevel = 0;
1132 for (i = 0; i < numMipLevels; i++) {
1133 mipSize = svga3dsurface_get_mip_size(baseLevelSize, i);
1134 bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0);
1135 mipChainBytes += bytes;
1136 if (i < mip)
1137 mipChainBytesToLevel += bytes;
1138 }
1139
1140 offset = mipChainBytes * face + mipChainBytesToLevel;
1141
1142 return offset;
1143}
1144
1145
1146/**
1147 * svga3dsurface_is_gb_screen_target_format - Is the specified format usable as
1148 * a ScreenTarget?
1149 * (with just the GBObjects cap-bit
1150 * set)
1151 * @format: format to queried
1152 *
1153 * RETURNS:
1154 * true if queried format is valid for screen targets
1155 */
1156static inline bool
1157svga3dsurface_is_gb_screen_target_format(SVGA3dSurfaceFormat format)
1158{
1159 return (format == SVGA3D_X8R8G8B8 ||
1160 format == SVGA3D_A8R8G8B8 ||
1161 format == SVGA3D_R5G6B5 ||
1162 format == SVGA3D_X1R5G5B5 ||
1163 format == SVGA3D_A1R5G5B5 ||
1164 format == SVGA3D_P8);
1165}
1166
1167
1168/**
1169 * svga3dsurface_is_dx_screen_target_format - Is the specified format usable as
1170 * a ScreenTarget?
1171 * (with DX10 enabled)
1172 *
1173 * @format: format to queried
1174 *
1175 * Results:
1176 * true if queried format is valid for screen targets
1177 */
1178static inline bool
1179svga3dsurface_is_dx_screen_target_format(SVGA3dSurfaceFormat format)
1180{
1181 return (format == SVGA3D_R8G8B8A8_UNORM ||
1182 format == SVGA3D_B8G8R8A8_UNORM ||
1183 format == SVGA3D_B8G8R8X8_UNORM);
1184}
1185
1186
1187/**
1188 * svga3dsurface_is_screen_target_format - Is the specified format usable as a
1189 * ScreenTarget?
1190 * (for some combination of caps)
1191 *
1192 * @format: format to queried
1193 *
1194 * Results:
1195 * true if queried format is valid for screen targets
1196 */
1197static inline bool
1198svga3dsurface_is_screen_target_format(SVGA3dSurfaceFormat format)
1199{
1200 if (svga3dsurface_is_gb_screen_target_format(format)) {
1201 return true;
1202 }
1203 return svga3dsurface_is_dx_screen_target_format(format);
1204}
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
new file mode 100644
index 000000000000..27b33ba88430
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
@@ -0,0 +1,1633 @@
1/**********************************************************
2 * Copyright 2012-2015 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_types.h --
28 *
29 * SVGA 3d hardware definitions for basic types
30 */
31
32#ifndef _SVGA3D_TYPES_H_
33#define _SVGA3D_TYPES_H_
34
35#define INCLUDE_ALLOW_MODULE
36#define INCLUDE_ALLOW_USERLEVEL
37#define INCLUDE_ALLOW_VMCORE
38
39#include "includeCheck.h"
40
41/*
42 * Generic Types
43 */
44
45#define SVGA3D_INVALID_ID ((uint32)-1)
46
47typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
48typedef uint32 SVGA3dColor; /* a, r, g, b */
49
50typedef
51#include "vmware_pack_begin.h"
52struct SVGA3dCopyRect {
53 uint32 x;
54 uint32 y;
55 uint32 w;
56 uint32 h;
57 uint32 srcx;
58 uint32 srcy;
59}
60#include "vmware_pack_end.h"
61SVGA3dCopyRect;
62
63typedef
64#include "vmware_pack_begin.h"
65struct SVGA3dCopyBox {
66 uint32 x;
67 uint32 y;
68 uint32 z;
69 uint32 w;
70 uint32 h;
71 uint32 d;
72 uint32 srcx;
73 uint32 srcy;
74 uint32 srcz;
75}
76#include "vmware_pack_end.h"
77SVGA3dCopyBox;
78
79typedef
80#include "vmware_pack_begin.h"
81struct SVGA3dRect {
82 uint32 x;
83 uint32 y;
84 uint32 w;
85 uint32 h;
86}
87#include "vmware_pack_end.h"
88SVGA3dRect;
89
90typedef
91#include "vmware_pack_begin.h"
92struct {
93 uint32 x;
94 uint32 y;
95 uint32 z;
96 uint32 w;
97 uint32 h;
98 uint32 d;
99}
100#include "vmware_pack_end.h"
101SVGA3dBox;
102
103typedef
104#include "vmware_pack_begin.h"
105struct {
106 uint32 x;
107 uint32 y;
108 uint32 z;
109}
110#include "vmware_pack_end.h"
111SVGA3dPoint;
112
113/*
114 * Surface formats.
115 */
116typedef enum SVGA3dSurfaceFormat {
117 SVGA3D_FORMAT_INVALID = 0,
118
119 SVGA3D_X8R8G8B8 = 1,
120 SVGA3D_FORMAT_MIN = 1,
121
122 SVGA3D_A8R8G8B8 = 2,
123
124 SVGA3D_R5G6B5 = 3,
125 SVGA3D_X1R5G5B5 = 4,
126 SVGA3D_A1R5G5B5 = 5,
127 SVGA3D_A4R4G4B4 = 6,
128
129 SVGA3D_Z_D32 = 7,
130 SVGA3D_Z_D16 = 8,
131 SVGA3D_Z_D24S8 = 9,
132 SVGA3D_Z_D15S1 = 10,
133
134 SVGA3D_LUMINANCE8 = 11,
135 SVGA3D_LUMINANCE4_ALPHA4 = 12,
136 SVGA3D_LUMINANCE16 = 13,
137 SVGA3D_LUMINANCE8_ALPHA8 = 14,
138
139 SVGA3D_DXT1 = 15,
140 SVGA3D_DXT2 = 16,
141 SVGA3D_DXT3 = 17,
142 SVGA3D_DXT4 = 18,
143 SVGA3D_DXT5 = 19,
144
145 SVGA3D_BUMPU8V8 = 20,
146 SVGA3D_BUMPL6V5U5 = 21,
147 SVGA3D_BUMPX8L8V8U8 = 22,
148 SVGA3D_BUMPL8V8U8 = 23,
149
150 SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
151 SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
152
153 SVGA3D_A2R10G10B10 = 26,
154
155 /* signed formats */
156 SVGA3D_V8U8 = 27,
157 SVGA3D_Q8W8V8U8 = 28,
158 SVGA3D_CxV8U8 = 29,
159
160 /* mixed formats */
161 SVGA3D_X8L8V8U8 = 30,
162 SVGA3D_A2W10V10U10 = 31,
163
164 SVGA3D_ALPHA8 = 32,
165
166 /* Single- and dual-component floating point formats */
167 SVGA3D_R_S10E5 = 33,
168 SVGA3D_R_S23E8 = 34,
169 SVGA3D_RG_S10E5 = 35,
170 SVGA3D_RG_S23E8 = 36,
171
172 SVGA3D_BUFFER = 37,
173
174 SVGA3D_Z_D24X8 = 38,
175
176 SVGA3D_V16U16 = 39,
177
178 SVGA3D_G16R16 = 40,
179 SVGA3D_A16B16G16R16 = 41,
180
181 /* Packed Video formats */
182 SVGA3D_UYVY = 42,
183 SVGA3D_YUY2 = 43,
184
185 /* Planar video formats */
186 SVGA3D_NV12 = 44,
187
188 /* Video format with alpha */
189 SVGA3D_AYUV = 45,
190
191 SVGA3D_R32G32B32A32_TYPELESS = 46,
192 SVGA3D_R32G32B32A32_UINT = 47,
193 SVGA3D_R32G32B32A32_SINT = 48,
194 SVGA3D_R32G32B32_TYPELESS = 49,
195 SVGA3D_R32G32B32_FLOAT = 50,
196 SVGA3D_R32G32B32_UINT = 51,
197 SVGA3D_R32G32B32_SINT = 52,
198 SVGA3D_R16G16B16A16_TYPELESS = 53,
199 SVGA3D_R16G16B16A16_UINT = 54,
200 SVGA3D_R16G16B16A16_SNORM = 55,
201 SVGA3D_R16G16B16A16_SINT = 56,
202 SVGA3D_R32G32_TYPELESS = 57,
203 SVGA3D_R32G32_UINT = 58,
204 SVGA3D_R32G32_SINT = 59,
205 SVGA3D_R32G8X24_TYPELESS = 60,
206 SVGA3D_D32_FLOAT_S8X24_UINT = 61,
207 SVGA3D_R32_FLOAT_X8X24_TYPELESS = 62,
208 SVGA3D_X32_TYPELESS_G8X24_UINT = 63,
209 SVGA3D_R10G10B10A2_TYPELESS = 64,
210 SVGA3D_R10G10B10A2_UINT = 65,
211 SVGA3D_R11G11B10_FLOAT = 66,
212 SVGA3D_R8G8B8A8_TYPELESS = 67,
213 SVGA3D_R8G8B8A8_UNORM = 68,
214 SVGA3D_R8G8B8A8_UNORM_SRGB = 69,
215 SVGA3D_R8G8B8A8_UINT = 70,
216 SVGA3D_R8G8B8A8_SINT = 71,
217 SVGA3D_R16G16_TYPELESS = 72,
218 SVGA3D_R16G16_UINT = 73,
219 SVGA3D_R16G16_SINT = 74,
220 SVGA3D_R32_TYPELESS = 75,
221 SVGA3D_D32_FLOAT = 76,
222 SVGA3D_R32_UINT = 77,
223 SVGA3D_R32_SINT = 78,
224 SVGA3D_R24G8_TYPELESS = 79,
225 SVGA3D_D24_UNORM_S8_UINT = 80,
226 SVGA3D_R24_UNORM_X8_TYPELESS = 81,
227 SVGA3D_X24_TYPELESS_G8_UINT = 82,
228 SVGA3D_R8G8_TYPELESS = 83,
229 SVGA3D_R8G8_UNORM = 84,
230 SVGA3D_R8G8_UINT = 85,
231 SVGA3D_R8G8_SINT = 86,
232 SVGA3D_R16_TYPELESS = 87,
233 SVGA3D_R16_UNORM = 88,
234 SVGA3D_R16_UINT = 89,
235 SVGA3D_R16_SNORM = 90,
236 SVGA3D_R16_SINT = 91,
237 SVGA3D_R8_TYPELESS = 92,
238 SVGA3D_R8_UNORM = 93,
239 SVGA3D_R8_UINT = 94,
240 SVGA3D_R8_SNORM = 95,
241 SVGA3D_R8_SINT = 96,
242 SVGA3D_P8 = 97,
243 SVGA3D_R9G9B9E5_SHAREDEXP = 98,
244 SVGA3D_R8G8_B8G8_UNORM = 99,
245 SVGA3D_G8R8_G8B8_UNORM = 100,
246 SVGA3D_BC1_TYPELESS = 101,
247 SVGA3D_BC1_UNORM_SRGB = 102,
248 SVGA3D_BC2_TYPELESS = 103,
249 SVGA3D_BC2_UNORM_SRGB = 104,
250 SVGA3D_BC3_TYPELESS = 105,
251 SVGA3D_BC3_UNORM_SRGB = 106,
252 SVGA3D_BC4_TYPELESS = 107,
253 SVGA3D_ATI1 = 108, /* DX9-specific BC4_UNORM */
254 SVGA3D_BC4_SNORM = 109,
255 SVGA3D_BC5_TYPELESS = 110,
256 SVGA3D_ATI2 = 111, /* DX9-specific BC5_UNORM */
257 SVGA3D_BC5_SNORM = 112,
258 SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113,
259 SVGA3D_B8G8R8A8_TYPELESS = 114,
260 SVGA3D_B8G8R8A8_UNORM_SRGB = 115,
261 SVGA3D_B8G8R8X8_TYPELESS = 116,
262 SVGA3D_B8G8R8X8_UNORM_SRGB = 117,
263
264 /* Advanced depth formats. */
265 SVGA3D_Z_DF16 = 118,
266 SVGA3D_Z_DF24 = 119,
267 SVGA3D_Z_D24S8_INT = 120,
268
269 /* Planar video formats. */
270 SVGA3D_YV12 = 121,
271
272 SVGA3D_R32G32B32A32_FLOAT = 122,
273 SVGA3D_R16G16B16A16_FLOAT = 123,
274 SVGA3D_R16G16B16A16_UNORM = 124,
275 SVGA3D_R32G32_FLOAT = 125,
276 SVGA3D_R10G10B10A2_UNORM = 126,
277 SVGA3D_R8G8B8A8_SNORM = 127,
278 SVGA3D_R16G16_FLOAT = 128,
279 SVGA3D_R16G16_UNORM = 129,
280 SVGA3D_R16G16_SNORM = 130,
281 SVGA3D_R32_FLOAT = 131,
282 SVGA3D_R8G8_SNORM = 132,
283 SVGA3D_R16_FLOAT = 133,
284 SVGA3D_D16_UNORM = 134,
285 SVGA3D_A8_UNORM = 135,
286 SVGA3D_BC1_UNORM = 136,
287 SVGA3D_BC2_UNORM = 137,
288 SVGA3D_BC3_UNORM = 138,
289 SVGA3D_B5G6R5_UNORM = 139,
290 SVGA3D_B5G5R5A1_UNORM = 140,
291 SVGA3D_B8G8R8A8_UNORM = 141,
292 SVGA3D_B8G8R8X8_UNORM = 142,
293 SVGA3D_BC4_UNORM = 143,
294 SVGA3D_BC5_UNORM = 144,
295
296 SVGA3D_FORMAT_MAX
297} SVGA3dSurfaceFormat;
298
299typedef enum SVGA3dSurfaceFlags {
300 SVGA3D_SURFACE_CUBEMAP = (1 << 0),
301
302 /*
303 * HINT flags are not enforced by the device but are useful for
304 * performance.
305 */
306 SVGA3D_SURFACE_HINT_STATIC = (1 << 1),
307 SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2),
308 SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3),
309 SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4),
310 SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5),
311 SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6),
312 SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7),
313 SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8),
314 SVGA3D_SURFACE_MASKABLE_ANTIALIAS = (1 << 9),
315 SVGA3D_SURFACE_AUTOGENMIPMAPS = (1 << 10),
316 SVGA3D_SURFACE_DECODE_RENDERTARGET = (1 << 11),
317
318 /*
319 * Is this surface using a base-level pitch for it's mob backing?
320 *
321 * This flag is not intended to be set by guest-drivers, but is instead
322 * set by the device when the surface is bound to a mob with a specified
323 * pitch.
324 */
325 SVGA3D_SURFACE_MOB_PITCH = (1 << 12),
326
327 SVGA3D_SURFACE_INACTIVE = (1 << 13),
328 SVGA3D_SURFACE_HINT_RT_LOCKABLE = (1 << 14),
329 SVGA3D_SURFACE_VOLUME = (1 << 15),
330
331 /*
332 * Required to be set on a surface to bind it to a screen target.
333 */
334 SVGA3D_SURFACE_SCREENTARGET = (1 << 16),
335
336 /*
337 * Align images in the guest-backing mob to 16-bytes.
338 */
339 SVGA3D_SURFACE_ALIGN16 = (1 << 17),
340
341 SVGA3D_SURFACE_1D = (1 << 18),
342 SVGA3D_SURFACE_ARRAY = (1 << 19),
343
344 /*
345 * Bind flags.
346 * These are enforced for any surface defined with DefineGBSurface_v2.
347 */
348 SVGA3D_SURFACE_BIND_VERTEX_BUFFER = (1 << 20),
349 SVGA3D_SURFACE_BIND_INDEX_BUFFER = (1 << 21),
350 SVGA3D_SURFACE_BIND_CONSTANT_BUFFER = (1 << 22),
351 SVGA3D_SURFACE_BIND_SHADER_RESOURCE = (1 << 23),
352 SVGA3D_SURFACE_BIND_RENDER_TARGET = (1 << 24),
353 SVGA3D_SURFACE_BIND_DEPTH_STENCIL = (1 << 25),
354 SVGA3D_SURFACE_BIND_STREAM_OUTPUT = (1 << 26),
355
356 /*
357 * A note on staging flags:
358 *
359 * The STAGING flags notes that the surface will not be used directly by the
360 * drawing pipeline, i.e. that it will not be bound to any bind point.
361 * Staging surfaces may be used by copy operations to move data in and out
362 * of other surfaces.
363 *
364 * The HINT_INDIRECT_UPDATE flag suggests that the surface will receive
365 * updates indirectly, i.e. the surface will not be updated directly, but
366 * will receive copies from staging surfaces.
367 */
368 SVGA3D_SURFACE_STAGING_UPLOAD = (1 << 27),
369 SVGA3D_SURFACE_STAGING_DOWNLOAD = (1 << 28),
370 SVGA3D_SURFACE_HINT_INDIRECT_UPDATE = (1 << 29),
371
372 /*
373 * Setting this flag allow this surface to be used with the
374 * SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER command. It is only valid for
375 * buffer surfaces, an no bind flags are allowed to be set on surfaces
376 * with this flag.
377 */
378 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER = (1 << 30),
379
380 /*
381 * Marker for the last defined bit.
382 */
383 SVGA3D_SURFACE_FLAG_MAX = (1 << 31),
384} SVGA3dSurfaceFlags;
385
386#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \
387 ( SVGA3D_SURFACE_MOB_PITCH | \
388 SVGA3D_SURFACE_SCREENTARGET | \
389 SVGA3D_SURFACE_ALIGN16 | \
390 SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
391 SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
392 SVGA3D_SURFACE_STAGING_UPLOAD | \
393 SVGA3D_SURFACE_STAGING_DOWNLOAD | \
394 SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
395 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
396 )
397
398#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \
399 ( SVGA3D_SURFACE_CUBEMAP | \
400 SVGA3D_SURFACE_MASKABLE_ANTIALIAS | \
401 SVGA3D_SURFACE_AUTOGENMIPMAPS | \
402 SVGA3D_SURFACE_DECODE_RENDERTARGET | \
403 SVGA3D_SURFACE_VOLUME | \
404 SVGA3D_SURFACE_1D | \
405 SVGA3D_SURFACE_ARRAY | \
406 SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
407 SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
408 SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
409 SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
410 SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
411 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
412 )
413
414#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \
415 ( SVGA3D_SURFACE_CUBEMAP | \
416 SVGA3D_SURFACE_AUTOGENMIPMAPS | \
417 SVGA3D_SURFACE_DECODE_RENDERTARGET | \
418 SVGA3D_SURFACE_VOLUME | \
419 SVGA3D_SURFACE_1D | \
420 SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
421 SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
422 SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
423 SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
424 SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
425 SVGA3D_SURFACE_INACTIVE | \
426 SVGA3D_SURFACE_STAGING_UPLOAD | \
427 SVGA3D_SURFACE_STAGING_DOWNLOAD | \
428 SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
429 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
430 )
431
432#define SVGA3D_SURFACE_DX_ONLY_MASK \
433 ( SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
434 SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
435
436#define SVGA3D_SURFACE_STAGING_MASK \
437 ( SVGA3D_SURFACE_STAGING_UPLOAD | \
438 SVGA3D_SURFACE_STAGING_DOWNLOAD \
439 )
440
441#define SVGA3D_SURFACE_BIND_MASK \
442 ( SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
443 SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
444 SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
445 SVGA3D_SURFACE_BIND_SHADER_RESOURCE | \
446 SVGA3D_SURFACE_BIND_RENDER_TARGET | \
447 SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
448 SVGA3D_SURFACE_BIND_STREAM_OUTPUT \
449 )
450
451typedef enum {
452 SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
453 SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
454 SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
455 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
456 SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
457 SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
458 SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
459
460/*
461 * This format can be used as a render target if the current display mode
462 * is the same depth if the alpha channel is ignored. e.g. if the device
463 * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
464 * format op list entry for A8R8G8B8 should have this cap.
465 */
466 SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
467
468/*
469 * This format contains DirectDraw support (including Flip). This flag
470 * should not to be set on alpha formats.
471 */
472 SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
473
474/*
475 * The rasterizer can support some level of Direct3D support in this format
476 * and implies that the driver can create a Context in this mode (for some
477 * render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
478 * flag must also be set.
479 */
480 SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
481
482/*
483 * This is set for a private format when the driver has put the bpp in
484 * the structure.
485 */
486 SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
487
488/*
489 * Indicates that this format can be converted to any RGB format for which
490 * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified
491 */
492 SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
493
494/*
495 * Indicates that this format can be used to create offscreen plain surfaces.
496 */
497 SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
498
499/*
500 * Indicated that this format can be read as an SRGB texture (meaning that the
501 * sampler will linearize the looked up data)
502 */
503 SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
504
505/*
506 * Indicates that this format can be used in the bumpmap instructions
507 */
508 SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
509
510/*
511 * Indicates that this format can be sampled by the displacement map sampler
512 */
513 SVGA3DFORMAT_OP_DMAP = 0x00020000,
514
515/*
516 * Indicates that this format cannot be used with texture filtering
517 */
518 SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
519
520/*
521 * Indicates that format conversions are supported to this RGB format if
522 * SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
523 */
524 SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
525
526/*
527 * Indicated that this format can be written as an SRGB target
528 * (meaning that the pixel pipe will DE-linearize data on output to format)
529 */
530 SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
531
532/*
533 * Indicates that this format cannot be used with alpha blending
534 */
535 SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
536
537/*
538 * Indicates that the device can auto-generated sublevels for resources
539 * of this format
540 */
541 SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
542
543/*
544 * Indicates that this format can be used by vertex texture sampler
545 */
546 SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
547
548/*
549 * Indicates that this format supports neither texture coordinate
550 * wrap modes, nor mipmapping.
551 */
552 SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
553} SVGA3dFormatOp;
554
555#define SVGA3D_FORMAT_POSITIVE \
556 (SVGA3DFORMAT_OP_TEXTURE | \
557 SVGA3DFORMAT_OP_VOLUMETEXTURE | \
558 SVGA3DFORMAT_OP_CUBETEXTURE | \
559 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET | \
560 SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET | \
561 SVGA3DFORMAT_OP_ZSTENCIL | \
562 SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH | \
563 SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET | \
564 SVGA3DFORMAT_OP_DISPLAYMODE | \
565 SVGA3DFORMAT_OP_3DACCELERATION | \
566 SVGA3DFORMAT_OP_PIXELSIZE | \
567 SVGA3DFORMAT_OP_CONVERT_TO_ARGB | \
568 SVGA3DFORMAT_OP_OFFSCREENPLAIN | \
569 SVGA3DFORMAT_OP_SRGBREAD | \
570 SVGA3DFORMAT_OP_BUMPMAP | \
571 SVGA3DFORMAT_OP_DMAP | \
572 SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB | \
573 SVGA3DFORMAT_OP_SRGBWRITE | \
574 SVGA3DFORMAT_OP_AUTOGENMIPMAP | \
575 SVGA3DFORMAT_OP_VERTEXTEXTURE)
576
577#define SVGA3D_FORMAT_NEGATIVE \
578 (SVGA3DFORMAT_OP_NOFILTER | \
579 SVGA3DFORMAT_OP_NOALPHABLEND | \
580 SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP)
581
582/*
583 * This structure is a conversion of SVGA3DFORMAT_OP_*
584 * Entries must be located at the same position.
585 */
586typedef union {
587 uint32 value;
588 struct {
589 uint32 texture : 1;
590 uint32 volumeTexture : 1;
591 uint32 cubeTexture : 1;
592 uint32 offscreenRenderTarget : 1;
593 uint32 sameFormatRenderTarget : 1;
594 uint32 unknown1 : 1;
595 uint32 zStencil : 1;
596 uint32 zStencilArbitraryDepth : 1;
597 uint32 sameFormatUpToAlpha : 1;
598 uint32 unknown2 : 1;
599 uint32 displayMode : 1;
600 uint32 acceleration3d : 1;
601 uint32 pixelSize : 1;
602 uint32 convertToARGB : 1;
603 uint32 offscreenPlain : 1;
604 uint32 sRGBRead : 1;
605 uint32 bumpMap : 1;
606 uint32 dmap : 1;
607 uint32 noFilter : 1;
608 uint32 memberOfGroupARGB : 1;
609 uint32 sRGBWrite : 1;
610 uint32 noAlphaBlend : 1;
611 uint32 autoGenMipMap : 1;
612 uint32 vertexTexture : 1;
613 uint32 noTexCoordWrapNorMip : 1;
614 };
615} SVGA3dSurfaceFormatCaps;
616
617/*
618 * SVGA_3D_CMD_SETRENDERSTATE Types. All value types
619 * must fit in a uint32.
620 */
621
622typedef enum {
623 SVGA3D_RS_INVALID = 0,
624 SVGA3D_RS_MIN = 1,
625 SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */
626 SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */
627 SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */
628 SVGA3D_RS_DITHERENABLE = 4, /* SVGA3dBool */
629 SVGA3D_RS_BLENDENABLE = 5, /* SVGA3dBool */
630 SVGA3D_RS_FOGENABLE = 6, /* SVGA3dBool */
631 SVGA3D_RS_SPECULARENABLE = 7, /* SVGA3dBool */
632 SVGA3D_RS_STENCILENABLE = 8, /* SVGA3dBool */
633 SVGA3D_RS_LIGHTINGENABLE = 9, /* SVGA3dBool */
634 SVGA3D_RS_NORMALIZENORMALS = 10, /* SVGA3dBool */
635 SVGA3D_RS_POINTSPRITEENABLE = 11, /* SVGA3dBool */
636 SVGA3D_RS_POINTSCALEENABLE = 12, /* SVGA3dBool */
637 SVGA3D_RS_STENCILREF = 13, /* uint32 */
638 SVGA3D_RS_STENCILMASK = 14, /* uint32 */
639 SVGA3D_RS_STENCILWRITEMASK = 15, /* uint32 */
640 SVGA3D_RS_FOGSTART = 16, /* float */
641 SVGA3D_RS_FOGEND = 17, /* float */
642 SVGA3D_RS_FOGDENSITY = 18, /* float */
643 SVGA3D_RS_POINTSIZE = 19, /* float */
644 SVGA3D_RS_POINTSIZEMIN = 20, /* float */
645 SVGA3D_RS_POINTSIZEMAX = 21, /* float */
646 SVGA3D_RS_POINTSCALE_A = 22, /* float */
647 SVGA3D_RS_POINTSCALE_B = 23, /* float */
648 SVGA3D_RS_POINTSCALE_C = 24, /* float */
649 SVGA3D_RS_FOGCOLOR = 25, /* SVGA3dColor */
650 SVGA3D_RS_AMBIENT = 26, /* SVGA3dColor */
651 SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */
652 SVGA3D_RS_FOGMODE = 28, /* SVGA3dFogMode */
653 SVGA3D_RS_FILLMODE = 29, /* SVGA3dFillMode */
654 SVGA3D_RS_SHADEMODE = 30, /* SVGA3dShadeMode */
655 SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */
656 SVGA3D_RS_SRCBLEND = 32, /* SVGA3dBlendOp */
657 SVGA3D_RS_DSTBLEND = 33, /* SVGA3dBlendOp */
658 SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */
659 SVGA3D_RS_CULLMODE = 35, /* SVGA3dFace */
660 SVGA3D_RS_ZFUNC = 36, /* SVGA3dCmpFunc */
661 SVGA3D_RS_ALPHAFUNC = 37, /* SVGA3dCmpFunc */
662 SVGA3D_RS_STENCILFUNC = 38, /* SVGA3dCmpFunc */
663 SVGA3D_RS_STENCILFAIL = 39, /* SVGA3dStencilOp */
664 SVGA3D_RS_STENCILZFAIL = 40, /* SVGA3dStencilOp */
665 SVGA3D_RS_STENCILPASS = 41, /* SVGA3dStencilOp */
666 SVGA3D_RS_ALPHAREF = 42, /* float (0.0 .. 1.0) */
667 SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */
668 SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */
669 SVGA3D_RS_ZBIAS = 45, /* float */
670 SVGA3D_RS_RANGEFOGENABLE = 46, /* SVGA3dBool */
671 SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */
672 SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */
673 SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */
674 SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */
675 SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */
676 SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */
677 SVGA3D_RS_TEXTUREFACTOR = 53, /* SVGA3dColor */
678 SVGA3D_RS_LOCALVIEWER = 54, /* SVGA3dBool */
679 SVGA3D_RS_SCISSORTESTENABLE = 55, /* SVGA3dBool */
680 SVGA3D_RS_BLENDCOLOR = 56, /* SVGA3dColor */
681 SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */
682 SVGA3D_RS_CCWSTENCILFUNC = 58, /* SVGA3dCmpFunc */
683 SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */
684 SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */
685 SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */
686 SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */
687 SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, /* float */
688 SVGA3D_RS_DEPTHBIAS = 64, /* float */
689
690
691 /*
692 * Output Gamma Level
693 *
694 * Output gamma effects the gamma curve of colors that are output from the
695 * rendering pipeline. A value of 1.0 specifies a linear color space. If the
696 * value is <= 0.0, gamma correction is ignored and linear color space is
697 * used.
698 */
699
700 SVGA3D_RS_OUTPUTGAMMA = 65, /* float */
701 SVGA3D_RS_ZVISIBLE = 66, /* SVGA3dBool */
702 SVGA3D_RS_LASTPIXEL = 67, /* SVGA3dBool */
703 SVGA3D_RS_CLIPPING = 68, /* SVGA3dBool */
704 SVGA3D_RS_WRAP0 = 69, /* SVGA3dWrapFlags */
705 SVGA3D_RS_WRAP1 = 70, /* SVGA3dWrapFlags */
706 SVGA3D_RS_WRAP2 = 71, /* SVGA3dWrapFlags */
707 SVGA3D_RS_WRAP3 = 72, /* SVGA3dWrapFlags */
708 SVGA3D_RS_WRAP4 = 73, /* SVGA3dWrapFlags */
709 SVGA3D_RS_WRAP5 = 74, /* SVGA3dWrapFlags */
710 SVGA3D_RS_WRAP6 = 75, /* SVGA3dWrapFlags */
711 SVGA3D_RS_WRAP7 = 76, /* SVGA3dWrapFlags */
712 SVGA3D_RS_WRAP8 = 77, /* SVGA3dWrapFlags */
713 SVGA3D_RS_WRAP9 = 78, /* SVGA3dWrapFlags */
714 SVGA3D_RS_WRAP10 = 79, /* SVGA3dWrapFlags */
715 SVGA3D_RS_WRAP11 = 80, /* SVGA3dWrapFlags */
716 SVGA3D_RS_WRAP12 = 81, /* SVGA3dWrapFlags */
717 SVGA3D_RS_WRAP13 = 82, /* SVGA3dWrapFlags */
718 SVGA3D_RS_WRAP14 = 83, /* SVGA3dWrapFlags */
719 SVGA3D_RS_WRAP15 = 84, /* SVGA3dWrapFlags */
720 SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */
721 SVGA3D_RS_MULTISAMPLEMASK = 86, /* uint32 */
722 SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */
723 SVGA3D_RS_TWEENFACTOR = 88, /* float */
724 SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */
725 SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */
726 SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */
727 SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */
728 SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */
729 SVGA3D_RS_SRCBLENDALPHA = 94, /* SVGA3dBlendOp */
730 SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */
731 SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
732 SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, /* SVGA3dTransparencyAntialiasType */
733 SVGA3D_RS_LINEWIDTH = 98, /* float */
734 SVGA3D_RS_MAX
735} SVGA3dRenderStateName;
736
737typedef enum {
738 SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0,
739 SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1,
740 SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2,
741 SVGA3D_TRANSPARENCYANTIALIAS_MAX
742} SVGA3dTransparencyAntialiasType;
743
744typedef enum {
745 SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
746 SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
747 SVGA3D_VERTEXMATERIAL_SPECULAR = 2, /* Use the value in the specular component */
748 SVGA3D_VERTEXMATERIAL_MAX = 3,
749} SVGA3dVertexMaterial;
750
751typedef enum {
752 SVGA3D_FILLMODE_INVALID = 0,
753 SVGA3D_FILLMODE_MIN = 1,
754 SVGA3D_FILLMODE_POINT = 1,
755 SVGA3D_FILLMODE_LINE = 2,
756 SVGA3D_FILLMODE_FILL = 3,
757 SVGA3D_FILLMODE_MAX
758} SVGA3dFillModeType;
759
760
761typedef
762#include "vmware_pack_begin.h"
763union {
764 struct {
765 uint16 mode; /* SVGA3dFillModeType */
766 uint16 face; /* SVGA3dFace */
767 };
768 uint32 uintValue;
769}
770#include "vmware_pack_end.h"
771SVGA3dFillMode;
772
773typedef enum {
774 SVGA3D_SHADEMODE_INVALID = 0,
775 SVGA3D_SHADEMODE_FLAT = 1,
776 SVGA3D_SHADEMODE_SMOOTH = 2,
777 SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */
778 SVGA3D_SHADEMODE_MAX
779} SVGA3dShadeMode;
780
781typedef
782#include "vmware_pack_begin.h"
783union {
784 struct {
785 uint16 repeat;
786 uint16 pattern;
787 };
788 uint32 uintValue;
789}
790#include "vmware_pack_end.h"
791SVGA3dLinePattern;
792
793typedef enum {
794 SVGA3D_BLENDOP_INVALID = 0,
795 SVGA3D_BLENDOP_MIN = 1,
796 SVGA3D_BLENDOP_ZERO = 1,
797 SVGA3D_BLENDOP_ONE = 2,
798 SVGA3D_BLENDOP_SRCCOLOR = 3,
799 SVGA3D_BLENDOP_INVSRCCOLOR = 4,
800 SVGA3D_BLENDOP_SRCALPHA = 5,
801 SVGA3D_BLENDOP_INVSRCALPHA = 6,
802 SVGA3D_BLENDOP_DESTALPHA = 7,
803 SVGA3D_BLENDOP_INVDESTALPHA = 8,
804 SVGA3D_BLENDOP_DESTCOLOR = 9,
805 SVGA3D_BLENDOP_INVDESTCOLOR = 10,
806 SVGA3D_BLENDOP_SRCALPHASAT = 11,
807 SVGA3D_BLENDOP_BLENDFACTOR = 12,
808 SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
809 SVGA3D_BLENDOP_SRC1COLOR = 14,
810 SVGA3D_BLENDOP_INVSRC1COLOR = 15,
811 SVGA3D_BLENDOP_SRC1ALPHA = 16,
812 SVGA3D_BLENDOP_INVSRC1ALPHA = 17,
813 SVGA3D_BLENDOP_BLENDFACTORALPHA = 18,
814 SVGA3D_BLENDOP_INVBLENDFACTORALPHA = 19,
815 SVGA3D_BLENDOP_MAX
816} SVGA3dBlendOp;
817
818typedef enum {
819 SVGA3D_BLENDEQ_INVALID = 0,
820 SVGA3D_BLENDEQ_MIN = 1,
821 SVGA3D_BLENDEQ_ADD = 1,
822 SVGA3D_BLENDEQ_SUBTRACT = 2,
823 SVGA3D_BLENDEQ_REVSUBTRACT = 3,
824 SVGA3D_BLENDEQ_MINIMUM = 4,
825 SVGA3D_BLENDEQ_MAXIMUM = 5,
826 SVGA3D_BLENDEQ_MAX
827} SVGA3dBlendEquation;
828
829typedef enum {
830 SVGA3D_DX11_LOGICOP_MIN = 0,
831 SVGA3D_DX11_LOGICOP_CLEAR = 0,
832 SVGA3D_DX11_LOGICOP_SET = 1,
833 SVGA3D_DX11_LOGICOP_COPY = 2,
834 SVGA3D_DX11_LOGICOP_COPY_INVERTED = 3,
835 SVGA3D_DX11_LOGICOP_NOOP = 4,
836 SVGA3D_DX11_LOGICOP_INVERT = 5,
837 SVGA3D_DX11_LOGICOP_AND = 6,
838 SVGA3D_DX11_LOGICOP_NAND = 7,
839 SVGA3D_DX11_LOGICOP_OR = 8,
840 SVGA3D_DX11_LOGICOP_NOR = 9,
841 SVGA3D_DX11_LOGICOP_XOR = 10,
842 SVGA3D_DX11_LOGICOP_EQUIV = 11,
843 SVGA3D_DX11_LOGICOP_AND_REVERSE = 12,
844 SVGA3D_DX11_LOGICOP_AND_INVERTED = 13,
845 SVGA3D_DX11_LOGICOP_OR_REVERSE = 14,
846 SVGA3D_DX11_LOGICOP_OR_INVERTED = 15,
847 SVGA3D_DX11_LOGICOP_MAX
848} SVGA3dDX11LogicOp;
849
850typedef enum {
851 SVGA3D_FRONTWINDING_INVALID = 0,
852 SVGA3D_FRONTWINDING_CW = 1,
853 SVGA3D_FRONTWINDING_CCW = 2,
854 SVGA3D_FRONTWINDING_MAX
855} SVGA3dFrontWinding;
856
857typedef enum {
858 SVGA3D_FACE_INVALID = 0,
859 SVGA3D_FACE_NONE = 1,
860 SVGA3D_FACE_MIN = 1,
861 SVGA3D_FACE_FRONT = 2,
862 SVGA3D_FACE_BACK = 3,
863 SVGA3D_FACE_FRONT_BACK = 4,
864 SVGA3D_FACE_MAX
865} SVGA3dFace;
866
867/*
868 * The order and the values should not be changed
869 */
870
871typedef enum {
872 SVGA3D_CMP_INVALID = 0,
873 SVGA3D_CMP_NEVER = 1,
874 SVGA3D_CMP_LESS = 2,
875 SVGA3D_CMP_EQUAL = 3,
876 SVGA3D_CMP_LESSEQUAL = 4,
877 SVGA3D_CMP_GREATER = 5,
878 SVGA3D_CMP_NOTEQUAL = 6,
879 SVGA3D_CMP_GREATEREQUAL = 7,
880 SVGA3D_CMP_ALWAYS = 8,
881 SVGA3D_CMP_MAX
882} SVGA3dCmpFunc;
883
884/*
885 * SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
886 * the fog factor to be specified in the alpha component of the specular
887 * (a.k.a. secondary) vertex color.
888 */
889typedef enum {
890 SVGA3D_FOGFUNC_INVALID = 0,
891 SVGA3D_FOGFUNC_EXP = 1,
892 SVGA3D_FOGFUNC_EXP2 = 2,
893 SVGA3D_FOGFUNC_LINEAR = 3,
894 SVGA3D_FOGFUNC_PER_VERTEX = 4
895} SVGA3dFogFunction;
896
897/*
898 * SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
899 * or per-pixel basis.
900 */
901typedef enum {
902 SVGA3D_FOGTYPE_INVALID = 0,
903 SVGA3D_FOGTYPE_VERTEX = 1,
904 SVGA3D_FOGTYPE_PIXEL = 2,
905 SVGA3D_FOGTYPE_MAX = 3
906} SVGA3dFogType;
907
908/*
909 * SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
910 * computed using the eye Z value of each pixel (or vertex), whereas range-
911 * based fog is computed using the actual distance (range) to the eye.
912 */
913typedef enum {
914 SVGA3D_FOGBASE_INVALID = 0,
915 SVGA3D_FOGBASE_DEPTHBASED = 1,
916 SVGA3D_FOGBASE_RANGEBASED = 2,
917 SVGA3D_FOGBASE_MAX = 3
918} SVGA3dFogBase;
919
920typedef enum {
921 SVGA3D_STENCILOP_INVALID = 0,
922 SVGA3D_STENCILOP_MIN = 1,
923 SVGA3D_STENCILOP_KEEP = 1,
924 SVGA3D_STENCILOP_ZERO = 2,
925 SVGA3D_STENCILOP_REPLACE = 3,
926 SVGA3D_STENCILOP_INCRSAT = 4,
927 SVGA3D_STENCILOP_DECRSAT = 5,
928 SVGA3D_STENCILOP_INVERT = 6,
929 SVGA3D_STENCILOP_INCR = 7,
930 SVGA3D_STENCILOP_DECR = 8,
931 SVGA3D_STENCILOP_MAX
932} SVGA3dStencilOp;
933
934typedef enum {
935 SVGA3D_CLIPPLANE_0 = (1 << 0),
936 SVGA3D_CLIPPLANE_1 = (1 << 1),
937 SVGA3D_CLIPPLANE_2 = (1 << 2),
938 SVGA3D_CLIPPLANE_3 = (1 << 3),
939 SVGA3D_CLIPPLANE_4 = (1 << 4),
940 SVGA3D_CLIPPLANE_5 = (1 << 5),
941} SVGA3dClipPlanes;
942
943typedef enum {
944 SVGA3D_CLEAR_COLOR = 0x1,
945 SVGA3D_CLEAR_DEPTH = 0x2,
946 SVGA3D_CLEAR_STENCIL = 0x4,
947
948 /*
949 * Hint only, must be used together with SVGA3D_CLEAR_COLOR. If
950 * SVGA3D_CLEAR_DEPTH or SVGA3D_CLEAR_STENCIL bit is set, this
951 * bit will be ignored.
952 */
953 SVGA3D_CLEAR_COLORFILL = 0x8
954} SVGA3dClearFlag;
955
956typedef enum {
957 SVGA3D_RT_DEPTH = 0,
958 SVGA3D_RT_MIN = 0,
959 SVGA3D_RT_STENCIL = 1,
960 SVGA3D_RT_COLOR0 = 2,
961 SVGA3D_RT_COLOR1 = 3,
962 SVGA3D_RT_COLOR2 = 4,
963 SVGA3D_RT_COLOR3 = 5,
964 SVGA3D_RT_COLOR4 = 6,
965 SVGA3D_RT_COLOR5 = 7,
966 SVGA3D_RT_COLOR6 = 8,
967 SVGA3D_RT_COLOR7 = 9,
968 SVGA3D_RT_MAX,
969 SVGA3D_RT_INVALID = ((uint32)-1),
970} SVGA3dRenderTargetType;
971
972#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
973
974typedef
975#include "vmware_pack_begin.h"
976union {
977 struct {
978 uint32 red : 1;
979 uint32 green : 1;
980 uint32 blue : 1;
981 uint32 alpha : 1;
982 };
983 uint32 uintValue;
984}
985#include "vmware_pack_end.h"
986SVGA3dColorMask;
987
988typedef enum {
989 SVGA3D_VBLEND_DISABLE = 0,
990 SVGA3D_VBLEND_1WEIGHT = 1,
991 SVGA3D_VBLEND_2WEIGHT = 2,
992 SVGA3D_VBLEND_3WEIGHT = 3,
993 SVGA3D_VBLEND_MAX = 4,
994} SVGA3dVertexBlendFlags;
995
996typedef enum {
997 SVGA3D_WRAPCOORD_0 = 1 << 0,
998 SVGA3D_WRAPCOORD_1 = 1 << 1,
999 SVGA3D_WRAPCOORD_2 = 1 << 2,
1000 SVGA3D_WRAPCOORD_3 = 1 << 3,
1001 SVGA3D_WRAPCOORD_ALL = 0xF,
1002} SVGA3dWrapFlags;
1003
1004/*
1005 * SVGA_3D_CMD_TEXTURESTATE Types. All value types
1006 * must fit in a uint32.
1007 */
1008
1009typedef enum {
1010 SVGA3D_TS_INVALID = 0,
1011 SVGA3D_TS_MIN = 1,
1012 SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */
1013 SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */
1014 SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
1015 SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */
1016 SVGA3D_TS_ALPHAOP = 5, /* SVGA3dTextureCombiner */
1017 SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */
1018 SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */
1019 SVGA3D_TS_ADDRESSU = 8, /* SVGA3dTextureAddress */
1020 SVGA3D_TS_ADDRESSV = 9, /* SVGA3dTextureAddress */
1021 SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */
1022 SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */
1023 SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */
1024 SVGA3D_TS_BORDERCOLOR = 13, /* SVGA3dColor */
1025 SVGA3D_TS_TEXCOORDINDEX = 14, /* uint32 */
1026 SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */
1027 SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */
1028 SVGA3D_TS_BUMPENVMAT00 = 17, /* float */
1029 SVGA3D_TS_BUMPENVMAT01 = 18, /* float */
1030 SVGA3D_TS_BUMPENVMAT10 = 19, /* float */
1031 SVGA3D_TS_BUMPENVMAT11 = 20, /* float */
1032 SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32 */
1033 SVGA3D_TS_TEXTURE_LOD_BIAS = 22, /* float */
1034 SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32 */
1035 SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */
1036
1037
1038 /*
1039 * Sampler Gamma Level
1040 *
1041 * Sampler gamma effects the color of samples taken from the sampler. A
1042 * value of 1.0 will produce linear samples. If the value is <= 0.0 the
1043 * gamma value is ignored and a linear space is used.
1044 */
1045
1046 SVGA3D_TS_GAMMA = 25, /* float */
1047 SVGA3D_TS_BUMPENVLSCALE = 26, /* float */
1048 SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */
1049 SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
1050 SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
1051 SVGA3D_TS_PREGB_MAX = 30, /* Max value before GBObjects */
1052 SVGA3D_TS_CONSTANT = 30, /* SVGA3dColor */
1053 SVGA3D_TS_COLOR_KEY_ENABLE = 31, /* SVGA3dBool */
1054 SVGA3D_TS_COLOR_KEY = 32, /* SVGA3dColor */
1055 SVGA3D_TS_MAX
1056} SVGA3dTextureStateName;
1057
1058typedef enum {
1059 SVGA3D_TC_INVALID = 0,
1060 SVGA3D_TC_DISABLE = 1,
1061 SVGA3D_TC_SELECTARG1 = 2,
1062 SVGA3D_TC_SELECTARG2 = 3,
1063 SVGA3D_TC_MODULATE = 4,
1064 SVGA3D_TC_ADD = 5,
1065 SVGA3D_TC_ADDSIGNED = 6,
1066 SVGA3D_TC_SUBTRACT = 7,
1067 SVGA3D_TC_BLENDTEXTUREALPHA = 8,
1068 SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
1069 SVGA3D_TC_BLENDCURRENTALPHA = 10,
1070 SVGA3D_TC_BLENDFACTORALPHA = 11,
1071 SVGA3D_TC_MODULATE2X = 12,
1072 SVGA3D_TC_MODULATE4X = 13,
1073 SVGA3D_TC_DSDT = 14,
1074 SVGA3D_TC_DOTPRODUCT3 = 15,
1075 SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
1076 SVGA3D_TC_ADDSIGNED2X = 17,
1077 SVGA3D_TC_ADDSMOOTH = 18,
1078 SVGA3D_TC_PREMODULATE = 19,
1079 SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
1080 SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
1081 SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
1082 SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
1083 SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
1084 SVGA3D_TC_MULTIPLYADD = 25,
1085 SVGA3D_TC_LERP = 26,
1086 SVGA3D_TC_MAX
1087} SVGA3dTextureCombiner;
1088
1089#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
1090
1091typedef enum {
1092 SVGA3D_TEX_ADDRESS_INVALID = 0,
1093 SVGA3D_TEX_ADDRESS_MIN = 1,
1094 SVGA3D_TEX_ADDRESS_WRAP = 1,
1095 SVGA3D_TEX_ADDRESS_MIRROR = 2,
1096 SVGA3D_TEX_ADDRESS_CLAMP = 3,
1097 SVGA3D_TEX_ADDRESS_BORDER = 4,
1098 SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
1099 SVGA3D_TEX_ADDRESS_EDGE = 6,
1100 SVGA3D_TEX_ADDRESS_MAX
1101} SVGA3dTextureAddress;
1102
1103/*
1104 * SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
1105 * disabled, and the rasterizer should use the magnification filter instead.
1106 */
1107typedef enum {
1108 SVGA3D_TEX_FILTER_NONE = 0,
1109 SVGA3D_TEX_FILTER_MIN = 0,
1110 SVGA3D_TEX_FILTER_NEAREST = 1,
1111 SVGA3D_TEX_FILTER_LINEAR = 2,
1112 SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
1113 SVGA3D_TEX_FILTER_FLATCUBIC = 4, /* Deprecated, not implemented */
1114 SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, /* Deprecated, not implemented */
1115 SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, /* Not currently implemented */
1116 SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, /* Not currently implemented */
1117 SVGA3D_TEX_FILTER_MAX
1118} SVGA3dTextureFilter;
1119
1120typedef enum {
1121 SVGA3D_TEX_TRANSFORM_OFF = 0,
1122 SVGA3D_TEX_TRANSFORM_S = (1 << 0),
1123 SVGA3D_TEX_TRANSFORM_T = (1 << 1),
1124 SVGA3D_TEX_TRANSFORM_R = (1 << 2),
1125 SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
1126 SVGA3D_TEX_PROJECTED = (1 << 15),
1127} SVGA3dTexTransformFlags;
1128
1129typedef enum {
1130 SVGA3D_TEXCOORD_GEN_OFF = 0,
1131 SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
1132 SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
1133 SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
1134 SVGA3D_TEXCOORD_GEN_SPHERE = 4,
1135 SVGA3D_TEXCOORD_GEN_MAX
1136} SVGA3dTextureCoordGen;
1137
1138/*
1139 * Texture argument constants for texture combiner
1140 */
1141typedef enum {
1142 SVGA3D_TA_INVALID = 0,
1143 SVGA3D_TA_TFACTOR = 1,
1144 SVGA3D_TA_PREVIOUS = 2,
1145 SVGA3D_TA_DIFFUSE = 3,
1146 SVGA3D_TA_TEXTURE = 4,
1147 SVGA3D_TA_SPECULAR = 5,
1148 SVGA3D_TA_CONSTANT = 6,
1149 SVGA3D_TA_MAX
1150} SVGA3dTextureArgData;
1151
1152#define SVGA3D_TM_MASK_LEN 4
1153
1154/* Modifiers for texture argument constants defined above. */
1155typedef enum {
1156 SVGA3D_TM_NONE = 0,
1157 SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
1158 SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN),
1159} SVGA3dTextureArgModifier;
1160
1161/*
1162 * Vertex declarations
1163 *
1164 * Notes:
1165 *
1166 * SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
1167 * draw with any POSITIONT vertex arrays, the programmable vertex
1168 * pipeline will be implicitly disabled. Drawing will take place as if
1169 * no vertex shader was bound.
1170 */
1171
1172typedef enum {
1173 SVGA3D_DECLUSAGE_POSITION = 0,
1174 SVGA3D_DECLUSAGE_BLENDWEIGHT,
1175 SVGA3D_DECLUSAGE_BLENDINDICES,
1176 SVGA3D_DECLUSAGE_NORMAL,
1177 SVGA3D_DECLUSAGE_PSIZE,
1178 SVGA3D_DECLUSAGE_TEXCOORD,
1179 SVGA3D_DECLUSAGE_TANGENT,
1180 SVGA3D_DECLUSAGE_BINORMAL,
1181 SVGA3D_DECLUSAGE_TESSFACTOR,
1182 SVGA3D_DECLUSAGE_POSITIONT,
1183 SVGA3D_DECLUSAGE_COLOR,
1184 SVGA3D_DECLUSAGE_FOG,
1185 SVGA3D_DECLUSAGE_DEPTH,
1186 SVGA3D_DECLUSAGE_SAMPLE,
1187 SVGA3D_DECLUSAGE_MAX
1188} SVGA3dDeclUsage;
1189
1190typedef enum {
1191 SVGA3D_DECLMETHOD_DEFAULT = 0,
1192 SVGA3D_DECLMETHOD_PARTIALU,
1193 SVGA3D_DECLMETHOD_PARTIALV,
1194 SVGA3D_DECLMETHOD_CROSSUV, /* Normal */
1195 SVGA3D_DECLMETHOD_UV,
1196 SVGA3D_DECLMETHOD_LOOKUP, /* Lookup a displacement map */
1197 SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED, /* Lookup a pre-sampled displacement */
1198 /* map */
1199} SVGA3dDeclMethod;
1200
1201typedef enum {
1202 SVGA3D_DECLTYPE_FLOAT1 = 0,
1203 SVGA3D_DECLTYPE_FLOAT2 = 1,
1204 SVGA3D_DECLTYPE_FLOAT3 = 2,
1205 SVGA3D_DECLTYPE_FLOAT4 = 3,
1206 SVGA3D_DECLTYPE_D3DCOLOR = 4,
1207 SVGA3D_DECLTYPE_UBYTE4 = 5,
1208 SVGA3D_DECLTYPE_SHORT2 = 6,
1209 SVGA3D_DECLTYPE_SHORT4 = 7,
1210 SVGA3D_DECLTYPE_UBYTE4N = 8,
1211 SVGA3D_DECLTYPE_SHORT2N = 9,
1212 SVGA3D_DECLTYPE_SHORT4N = 10,
1213 SVGA3D_DECLTYPE_USHORT2N = 11,
1214 SVGA3D_DECLTYPE_USHORT4N = 12,
1215 SVGA3D_DECLTYPE_UDEC3 = 13,
1216 SVGA3D_DECLTYPE_DEC3N = 14,
1217 SVGA3D_DECLTYPE_FLOAT16_2 = 15,
1218 SVGA3D_DECLTYPE_FLOAT16_4 = 16,
1219 SVGA3D_DECLTYPE_MAX,
1220} SVGA3dDeclType;
1221
1222/*
1223 * This structure is used for the divisor for geometry instancing;
1224 * it's a direct translation of the Direct3D equivalent.
1225 */
1226typedef union {
1227 struct {
1228 /*
1229 * For index data, this number represents the number of instances to draw.
1230 * For instance data, this number represents the number of
1231 * instances/vertex in this stream
1232 */
1233 uint32 count : 30;
1234
1235 /*
1236 * This is 1 if this is supposed to be the data that is repeated for
1237 * every instance.
1238 */
1239 uint32 indexedData : 1;
1240
1241 /*
1242 * This is 1 if this is supposed to be the per-instance data.
1243 */
1244 uint32 instanceData : 1;
1245 };
1246
1247 uint32 value;
1248} SVGA3dVertexDivisor;
1249
1250typedef enum {
1251 /*
1252 * SVGA3D_PRIMITIVE_INVALID is a valid primitive type.
1253 *
1254 * List MIN second so debuggers will think INVALID is
1255 * the correct name.
1256 */
1257 SVGA3D_PRIMITIVE_INVALID = 0,
1258 SVGA3D_PRIMITIVE_MIN = 0,
1259 SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
1260 SVGA3D_PRIMITIVE_POINTLIST = 2,
1261 SVGA3D_PRIMITIVE_LINELIST = 3,
1262 SVGA3D_PRIMITIVE_LINESTRIP = 4,
1263 SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
1264 SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
1265 SVGA3D_PRIMITIVE_LINELIST_ADJ = 7,
1266 SVGA3D_PRIMITIVE_PREDX_MAX = 7,
1267 SVGA3D_PRIMITIVE_LINESTRIP_ADJ = 8,
1268 SVGA3D_PRIMITIVE_TRIANGLELIST_ADJ = 9,
1269 SVGA3D_PRIMITIVE_TRIANGLESTRIP_ADJ = 10,
1270 SVGA3D_PRIMITIVE_MAX
1271} SVGA3dPrimitiveType;
1272
1273typedef enum {
1274 SVGA3D_COORDINATE_INVALID = 0,
1275 SVGA3D_COORDINATE_LEFTHANDED = 1,
1276 SVGA3D_COORDINATE_RIGHTHANDED = 2,
1277 SVGA3D_COORDINATE_MAX
1278} SVGA3dCoordinateType;
1279
1280typedef enum {
1281 SVGA3D_TRANSFORM_INVALID = 0,
1282 SVGA3D_TRANSFORM_WORLD = 1,
1283 SVGA3D_TRANSFORM_MIN = 1,
1284 SVGA3D_TRANSFORM_VIEW = 2,
1285 SVGA3D_TRANSFORM_PROJECTION = 3,
1286 SVGA3D_TRANSFORM_TEXTURE0 = 4,
1287 SVGA3D_TRANSFORM_TEXTURE1 = 5,
1288 SVGA3D_TRANSFORM_TEXTURE2 = 6,
1289 SVGA3D_TRANSFORM_TEXTURE3 = 7,
1290 SVGA3D_TRANSFORM_TEXTURE4 = 8,
1291 SVGA3D_TRANSFORM_TEXTURE5 = 9,
1292 SVGA3D_TRANSFORM_TEXTURE6 = 10,
1293 SVGA3D_TRANSFORM_TEXTURE7 = 11,
1294 SVGA3D_TRANSFORM_WORLD1 = 12,
1295 SVGA3D_TRANSFORM_WORLD2 = 13,
1296 SVGA3D_TRANSFORM_WORLD3 = 14,
1297 SVGA3D_TRANSFORM_MAX
1298} SVGA3dTransformType;
1299
1300typedef enum {
1301 SVGA3D_LIGHTTYPE_INVALID = 0,
1302 SVGA3D_LIGHTTYPE_MIN = 1,
1303 SVGA3D_LIGHTTYPE_POINT = 1,
1304 SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
1305 SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
1306 SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
1307 SVGA3D_LIGHTTYPE_MAX
1308} SVGA3dLightType;
1309
1310typedef enum {
1311 SVGA3D_CUBEFACE_POSX = 0,
1312 SVGA3D_CUBEFACE_NEGX = 1,
1313 SVGA3D_CUBEFACE_POSY = 2,
1314 SVGA3D_CUBEFACE_NEGY = 3,
1315 SVGA3D_CUBEFACE_POSZ = 4,
1316 SVGA3D_CUBEFACE_NEGZ = 5,
1317} SVGA3dCubeFace;
1318
1319typedef enum {
1320 SVGA3D_SHADERTYPE_INVALID = 0,
1321 SVGA3D_SHADERTYPE_MIN = 1,
1322 SVGA3D_SHADERTYPE_VS = 1,
1323 SVGA3D_SHADERTYPE_PS = 2,
1324 SVGA3D_SHADERTYPE_PREDX_MAX = 3,
1325 SVGA3D_SHADERTYPE_GS = 3,
1326 SVGA3D_SHADERTYPE_DX10_MAX = 4,
1327 SVGA3D_SHADERTYPE_HS = 4,
1328 SVGA3D_SHADERTYPE_DS = 5,
1329 SVGA3D_SHADERTYPE_CS = 6,
1330 SVGA3D_SHADERTYPE_MAX = 7
1331} SVGA3dShaderType;
1332
1333#define SVGA3D_NUM_SHADERTYPE_PREDX \
1334 (SVGA3D_SHADERTYPE_PREDX_MAX - SVGA3D_SHADERTYPE_MIN)
1335
1336#define SVGA3D_NUM_SHADERTYPE_DX10 \
1337 (SVGA3D_SHADERTYPE_DX10_MAX - SVGA3D_SHADERTYPE_MIN)
1338
1339#define SVGA3D_NUM_SHADERTYPE \
1340 (SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN)
1341
1342typedef enum {
1343 SVGA3D_CONST_TYPE_MIN = 0,
1344 SVGA3D_CONST_TYPE_FLOAT = 0,
1345 SVGA3D_CONST_TYPE_INT = 1,
1346 SVGA3D_CONST_TYPE_BOOL = 2,
1347 SVGA3D_CONST_TYPE_MAX = 3,
1348} SVGA3dShaderConstType;
1349
1350/*
1351 * Register limits for shader consts.
1352 */
1353#define SVGA3D_CONSTREG_MAX 256
1354#define SVGA3D_CONSTINTREG_MAX 16
1355#define SVGA3D_CONSTBOOLREG_MAX 16
1356
1357typedef enum {
1358 SVGA3D_STRETCH_BLT_POINT = 0,
1359 SVGA3D_STRETCH_BLT_LINEAR = 1,
1360 SVGA3D_STRETCH_BLT_MAX
1361} SVGA3dStretchBltMode;
1362
1363typedef enum {
1364 SVGA3D_QUERYTYPE_INVALID = ((uint8)-1),
1365 SVGA3D_QUERYTYPE_MIN = 0,
1366 SVGA3D_QUERYTYPE_OCCLUSION = 0,
1367 SVGA3D_QUERYTYPE_TIMESTAMP = 1,
1368 SVGA3D_QUERYTYPE_TIMESTAMPDISJOINT = 2,
1369 SVGA3D_QUERYTYPE_PIPELINESTATS = 3,
1370 SVGA3D_QUERYTYPE_OCCLUSIONPREDICATE = 4,
1371 SVGA3D_QUERYTYPE_STREAMOUTPUTSTATS = 5,
1372 SVGA3D_QUERYTYPE_STREAMOVERFLOWPREDICATE = 6,
1373 SVGA3D_QUERYTYPE_OCCLUSION64 = 7,
1374 SVGA3D_QUERYTYPE_EVENT = 8,
1375 SVGA3D_QUERYTYPE_DX10_MAX = 9,
1376 SVGA3D_QUERYTYPE_SOSTATS_STREAM0 = 9,
1377 SVGA3D_QUERYTYPE_SOSTATS_STREAM1 = 10,
1378 SVGA3D_QUERYTYPE_SOSTATS_STREAM2 = 11,
1379 SVGA3D_QUERYTYPE_SOSTATS_STREAM3 = 12,
1380 SVGA3D_QUERYTYPE_SOP_STREAM0 = 13,
1381 SVGA3D_QUERYTYPE_SOP_STREAM1 = 14,
1382 SVGA3D_QUERYTYPE_SOP_STREAM2 = 15,
1383 SVGA3D_QUERYTYPE_SOP_STREAM3 = 16,
1384 SVGA3D_QUERYTYPE_MAX
1385} SVGA3dQueryType;
1386
1387typedef uint8 SVGA3dQueryTypeUint8;
1388
1389#define SVGA3D_NUM_QUERYTYPE (SVGA3D_QUERYTYPE_MAX - SVGA3D_QUERYTYPE_MIN)
1390
1391/*
1392 * This is the maximum number of queries per context that can be active
1393 * simultaneously between a beginQuery and endQuery.
1394 */
1395#define SVGA3D_MAX_QUERY 64
1396
1397/*
1398 * Query result buffer formats
1399 */
1400typedef
1401#include "vmware_pack_begin.h"
1402struct {
1403 uint32 samplesRendered;
1404}
1405#include "vmware_pack_end.h"
1406SVGADXOcclusionQueryResult;
1407
1408typedef
1409#include "vmware_pack_begin.h"
1410struct {
1411 uint32 passed;
1412}
1413#include "vmware_pack_end.h"
1414SVGADXEventQueryResult;
1415
1416typedef
1417#include "vmware_pack_begin.h"
1418struct {
1419 uint64 timestamp;
1420}
1421#include "vmware_pack_end.h"
1422SVGADXTimestampQueryResult;
1423
1424typedef
1425#include "vmware_pack_begin.h"
1426struct {
1427 uint64 realFrequency;
1428 uint32 disjoint;
1429}
1430#include "vmware_pack_end.h"
1431SVGADXTimestampDisjointQueryResult;
1432
1433typedef
1434#include "vmware_pack_begin.h"
1435struct {
1436 uint64 inputAssemblyVertices;
1437 uint64 inputAssemblyPrimitives;
1438 uint64 vertexShaderInvocations;
1439 uint64 geometryShaderInvocations;
1440 uint64 geometryShaderPrimitives;
1441 uint64 clipperInvocations;
1442 uint64 clipperPrimitives;
1443 uint64 pixelShaderInvocations;
1444 uint64 hullShaderInvocations;
1445 uint64 domainShaderInvocations;
1446 uint64 computeShaderInvocations;
1447}
1448#include "vmware_pack_end.h"
1449SVGADXPipelineStatisticsQueryResult;
1450
1451typedef
1452#include "vmware_pack_begin.h"
1453struct {
1454 uint32 anySamplesRendered;
1455}
1456#include "vmware_pack_end.h"
1457SVGADXOcclusionPredicateQueryResult;
1458
1459typedef
1460#include "vmware_pack_begin.h"
1461struct {
1462 uint64 numPrimitivesWritten;
1463 uint64 numPrimitivesRequired;
1464}
1465#include "vmware_pack_end.h"
1466SVGADXStreamOutStatisticsQueryResult;
1467
1468typedef
1469#include "vmware_pack_begin.h"
1470struct {
1471 uint32 overflowed;
1472}
1473#include "vmware_pack_end.h"
1474SVGADXStreamOutPredicateQueryResult;
1475
1476typedef
1477#include "vmware_pack_begin.h"
1478struct {
1479 uint64 samplesRendered;
1480}
1481#include "vmware_pack_end.h"
1482SVGADXOcclusion64QueryResult;
1483
1484/*
1485 * SVGADXQueryResultUnion is not intended for use in the protocol, but is
1486 * very helpful when working with queries generically.
1487 */
1488typedef
1489#include "vmware_pack_begin.h"
1490union SVGADXQueryResultUnion {
1491 SVGADXOcclusionQueryResult occ;
1492 SVGADXEventQueryResult event;
1493 SVGADXTimestampQueryResult ts;
1494 SVGADXTimestampDisjointQueryResult tsDisjoint;
1495 SVGADXPipelineStatisticsQueryResult pipelineStats;
1496 SVGADXOcclusionPredicateQueryResult occPred;
1497 SVGADXStreamOutStatisticsQueryResult soStats;
1498 SVGADXStreamOutPredicateQueryResult soPred;
1499 SVGADXOcclusion64QueryResult occ64;
1500}
1501#include "vmware_pack_end.h"
1502SVGADXQueryResultUnion;
1503
1504
1505typedef enum {
1506 SVGA3D_QUERYSTATE_PENDING = 0, /* Query is not finished yet */
1507 SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully */
1508 SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully */
1509 SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (guest only) */
1510} SVGA3dQueryState;
1511
1512typedef enum {
1513 SVGA3D_WRITE_HOST_VRAM = 1,
1514 SVGA3D_READ_HOST_VRAM = 2,
1515} SVGA3dTransferType;
1516
1517typedef enum {
1518 SVGA3D_LOGICOP_INVALID = 0,
1519 SVGA3D_LOGICOP_MIN = 1,
1520 SVGA3D_LOGICOP_COPY = 1,
1521 SVGA3D_LOGICOP_NOT = 2,
1522 SVGA3D_LOGICOP_AND = 3,
1523 SVGA3D_LOGICOP_OR = 4,
1524 SVGA3D_LOGICOP_XOR = 5,
1525 SVGA3D_LOGICOP_NXOR = 6,
1526 SVGA3D_LOGICOP_ROP3MIN = 30, /* 7-29 are reserved for future logic ops. */
1527 SVGA3D_LOGICOP_ROP3MAX = (SVGA3D_LOGICOP_ROP3MIN + 255),
1528 SVGA3D_LOGICOP_MAX = (SVGA3D_LOGICOP_ROP3MAX + 1),
1529} SVGA3dLogicOp;
1530
1531typedef
1532#include "vmware_pack_begin.h"
1533struct {
1534 union {
1535 struct {
1536 uint16 function; /* SVGA3dFogFunction */
1537 uint8 type; /* SVGA3dFogType */
1538 uint8 base; /* SVGA3dFogBase */
1539 };
1540 uint32 uintValue;
1541 };
1542}
1543#include "vmware_pack_end.h"
1544SVGA3dFogMode;
1545
1546/*
1547 * Uniquely identify one image (a 1D/2D/3D array) from a surface. This
1548 * is a surface ID as well as face/mipmap indices.
1549 */
1550
1551typedef
1552#include "vmware_pack_begin.h"
1553struct SVGA3dSurfaceImageId {
1554 uint32 sid;
1555 uint32 face;
1556 uint32 mipmap;
1557}
1558#include "vmware_pack_end.h"
1559SVGA3dSurfaceImageId;
1560
1561typedef
1562#include "vmware_pack_begin.h"
1563struct {
1564 uint32 width;
1565 uint32 height;
1566 uint32 depth;
1567}
1568#include "vmware_pack_end.h"
1569SVGA3dSize;
1570
1571/*
1572 * Guest-backed objects definitions.
1573 */
1574typedef enum {
1575 SVGA_OTABLE_MOB = 0,
1576 SVGA_OTABLE_MIN = 0,
1577 SVGA_OTABLE_SURFACE = 1,
1578 SVGA_OTABLE_CONTEXT = 2,
1579 SVGA_OTABLE_SHADER = 3,
1580 SVGA_OTABLE_SCREENTARGET = 4,
1581
1582 SVGA_OTABLE_DX9_MAX = 5,
1583
1584 SVGA_OTABLE_DXCONTEXT = 5,
1585 SVGA_OTABLE_MAX = 6
1586} SVGAOTableType;
1587
1588/*
1589 * Deprecated.
1590 */
1591#define SVGA_OTABLE_COUNT 4
1592
1593typedef enum {
1594 SVGA_COTABLE_MIN = 0,
1595 SVGA_COTABLE_RTVIEW = 0,
1596 SVGA_COTABLE_DSVIEW = 1,
1597 SVGA_COTABLE_SRVIEW = 2,
1598 SVGA_COTABLE_ELEMENTLAYOUT = 3,
1599 SVGA_COTABLE_BLENDSTATE = 4,
1600 SVGA_COTABLE_DEPTHSTENCIL = 5,
1601 SVGA_COTABLE_RASTERIZERSTATE = 6,
1602 SVGA_COTABLE_SAMPLER = 7,
1603 SVGA_COTABLE_STREAMOUTPUT = 8,
1604 SVGA_COTABLE_DXQUERY = 9,
1605 SVGA_COTABLE_DXSHADER = 10,
1606 SVGA_COTABLE_DX10_MAX = 11,
1607 SVGA_COTABLE_UAVIEW = 11,
1608 SVGA_COTABLE_MAX
1609} SVGACOTableType;
1610
1611/*
1612 * The largest size (number of entries) allowed in a COTable.
1613 */
1614#define SVGA_COTABLE_MAX_IDS (MAX_UINT16 - 2)
1615
1616typedef enum SVGAMobFormat {
1617 SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID,
1618 SVGA3D_MOBFMT_PTDEPTH_0 = 0,
1619 SVGA3D_MOBFMT_MIN = 0,
1620 SVGA3D_MOBFMT_PTDEPTH_1 = 1,
1621 SVGA3D_MOBFMT_PTDEPTH_2 = 2,
1622 SVGA3D_MOBFMT_RANGE = 3,
1623 SVGA3D_MOBFMT_PTDEPTH64_0 = 4,
1624 SVGA3D_MOBFMT_PTDEPTH64_1 = 5,
1625 SVGA3D_MOBFMT_PTDEPTH64_2 = 6,
1626 SVGA3D_MOBFMT_PREDX_MAX = 7,
1627 SVGA3D_MOBFMT_EMPTY = 7,
1628 SVGA3D_MOBFMT_MAX,
1629} SVGAMobFormat;
1630
1631#define SVGA3D_MOB_EMPTY_BASE 1
1632
1633#endif /* _SVGA3D_TYPES_H_ */
diff --git a/drivers/gpu/drm/vmwgfx/svga_escape.h b/drivers/gpu/drm/vmwgfx/device_include/svga_escape.h
index 8e8d9682e018..884b1d1fb85f 100644
--- a/drivers/gpu/drm/vmwgfx/svga_escape.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga_escape.h
@@ -1,5 +1,5 @@
1/********************************************************** 1/**********************************************************
2 * Copyright 2007-2009 VMware, Inc. All rights reserved. 2 * Copyright 2007-2015 VMware, Inc. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person 4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation 5 * obtaining a copy of this software and associated documentation
diff --git a/drivers/gpu/drm/vmwgfx/svga_overlay.h b/drivers/gpu/drm/vmwgfx/device_include/svga_overlay.h
index f38416fcb046..faf6d9b2b891 100644
--- a/drivers/gpu/drm/vmwgfx/svga_overlay.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga_overlay.h
@@ -1,5 +1,5 @@
1/********************************************************** 1/**********************************************************
2 * Copyright 2007-2009 VMware, Inc. All rights reserved. 2 * Copyright 2007-2015 VMware, Inc. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person 4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation 5 * obtaining a copy of this software and associated documentation
@@ -152,19 +152,17 @@ VMwareVideoGetAttributes(const SVGAOverlayFormat format, /* IN */
152 switch (format) { 152 switch (format) {
153 case VMWARE_FOURCC_YV12: 153 case VMWARE_FOURCC_YV12:
154 *height = (*height + 1) & ~1; 154 *height = (*height + 1) & ~1;
155 *size = (*width + 3) & ~3; 155 *size = (*width) * (*height);
156 156
157 if (pitches) { 157 if (pitches) {
158 pitches[0] = *size; 158 pitches[0] = *width;
159 } 159 }
160 160
161 *size *= *height;
162
163 if (offsets) { 161 if (offsets) {
164 offsets[1] = *size; 162 offsets[1] = *size;
165 } 163 }
166 164
167 tmp = ((*width >> 1) + 3) & ~3; 165 tmp = *width >> 1;
168 166
169 if (pitches) { 167 if (pitches) {
170 pitches[1] = pitches[2] = tmp; 168 pitches[1] = pitches[2] = tmp;
diff --git a/drivers/gpu/drm/vmwgfx/svga_reg.h b/drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
index 3763d5bac47b..6e0ccb70a700 100644
--- a/drivers/gpu/drm/vmwgfx/svga_reg.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
@@ -1,5 +1,5 @@
1/********************************************************** 1/**********************************************************
2 * Copyright 1998-2009 VMware, Inc. All rights reserved. 2 * Copyright 1998-2015 VMware, Inc. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person 4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation 5 * obtaining a copy of this software and associated documentation
@@ -31,20 +31,38 @@
31 31
32#ifndef _SVGA_REG_H_ 32#ifndef _SVGA_REG_H_
33#define _SVGA_REG_H_ 33#define _SVGA_REG_H_
34#include <linux/pci_ids.h>
35
36#define INCLUDE_ALLOW_MODULE
37#define INCLUDE_ALLOW_USERLEVEL
38
39#define INCLUDE_ALLOW_VMCORE
40#include "includeCheck.h"
41
42#include "svga_types.h"
34 43
35/* 44/*
36 * PCI device IDs. 45 * SVGA_REG_ENABLE bit definitions.
37 */ 46 */
38#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 47typedef enum {
48 SVGA_REG_ENABLE_DISABLE = 0,
49 SVGA_REG_ENABLE_ENABLE = (1 << 0),
50 SVGA_REG_ENABLE_HIDE = (1 << 1),
51} SvgaRegEnable;
52
53typedef uint32 SVGAMobId;
39 54
40/* 55/*
41 * SVGA_REG_ENABLE bit definitions. 56 * Arbitrary and meaningless limits. Please ignore these when writing
57 * new drivers.
42 */ 58 */
43#define SVGA_REG_ENABLE_DISABLE 0 59#define SVGA_MAX_WIDTH 2560
44#define SVGA_REG_ENABLE_ENABLE 1 60#define SVGA_MAX_HEIGHT 1600
45#define SVGA_REG_ENABLE_HIDE 2 61
46#define SVGA_REG_ENABLE_ENABLE_HIDE (SVGA_REG_ENABLE_ENABLE |\ 62
47 SVGA_REG_ENABLE_HIDE) 63#define SVGA_MAX_BITS_PER_PIXEL 32
64#define SVGA_MAX_DEPTH 24
65#define SVGA_MAX_DISPLAYS 10
48 66
49/* 67/*
50 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned 68 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
@@ -57,14 +75,9 @@
57#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */ 75#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */
58 76
59/* 77/*
60 * The maximum framebuffer size that can traced for e.g. guests in VESA mode. 78 * The maximum framebuffer size that can traced for guests unless the
61 * The changeMap in the monitor is proportional to this number. Therefore, we'd 79 * SVGA_CAP_GBOBJECTS is set in SVGA_REG_CAPABILITIES. In that case
62 * like to keep it as small as possible to reduce monitor overhead (using 80 * the full framebuffer can be traced independent of this limit.
63 * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over
64 * 4k!).
65 *
66 * NB: For compatibility reasons, this value must be greater than 0xff0000.
67 * See bug 335072.
68 */ 81 */
69#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000 82#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000
70 83
@@ -133,6 +146,7 @@ enum {
133 SVGA_REG_FB_SIZE = 16, 146 SVGA_REG_FB_SIZE = 16,
134 147
135 /* ID 0 implementation only had the above registers, then the palette */ 148 /* ID 0 implementation only had the above registers, then the palette */
149 SVGA_REG_ID_0_TOP = 17,
136 150
137 SVGA_REG_CAPABILITIES = 17, 151 SVGA_REG_CAPABILITIES = 17,
138 SVGA_REG_MEM_START = 18, /* (Deprecated) */ 152 SVGA_REG_MEM_START = 18, /* (Deprecated) */
@@ -173,7 +187,7 @@ enum {
173 SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */ 187 SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
174 SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */ 188 SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
175 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */ 189 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */
176 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */ 190 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */
177 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */ 191 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
178 SVGA_REG_CMD_PREPEND_LOW = 53, 192 SVGA_REG_CMD_PREPEND_LOW = 53,
179 SVGA_REG_CMD_PREPEND_HIGH = 54, 193 SVGA_REG_CMD_PREPEND_HIGH = 54,
@@ -184,7 +198,6 @@ enum {
184 198
185 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 199 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
186 /* Next 768 (== 256*3) registers exist for colormap */ 200 /* Next 768 (== 256*3) registers exist for colormap */
187
188 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS 201 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
189 /* Base of scratch registers */ 202 /* Base of scratch registers */
190 /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage: 203 /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
@@ -192,7 +205,6 @@ enum {
192 the use of the current SVGA driver. */ 205 the use of the current SVGA driver. */
193}; 206};
194 207
195
196/* 208/*
197 * Guest memory regions (GMRs): 209 * Guest memory regions (GMRs):
198 * 210 *
@@ -290,16 +302,22 @@ enum {
290#define SVGA_GMR_FRAMEBUFFER ((uint32) -2) /* Guest Framebuffer (GFB) */ 302#define SVGA_GMR_FRAMEBUFFER ((uint32) -2) /* Guest Framebuffer (GFB) */
291 303
292typedef 304typedef
305#include "vmware_pack_begin.h"
293struct SVGAGuestMemDescriptor { 306struct SVGAGuestMemDescriptor {
294 uint32 ppn; 307 uint32 ppn;
295 uint32 numPages; 308 uint32 numPages;
296} SVGAGuestMemDescriptor; 309}
310#include "vmware_pack_end.h"
311SVGAGuestMemDescriptor;
297 312
298typedef 313typedef
314#include "vmware_pack_begin.h"
299struct SVGAGuestPtr { 315struct SVGAGuestPtr {
300 uint32 gmrId; 316 uint32 gmrId;
301 uint32 offset; 317 uint32 offset;
302} SVGAGuestPtr; 318}
319#include "vmware_pack_end.h"
320SVGAGuestPtr;
303 321
304/* 322/*
305 * Register based command buffers -- 323 * Register based command buffers --
@@ -356,9 +374,9 @@ struct SVGAGuestPtr {
356 * what it will set to. 374 * what it will set to.
357 */ 375 */
358 376
359#define SVGA_CB_MAX_SIZE (512 * 1024) // 512 KB 377#define SVGA_CB_MAX_SIZE (512 * 1024) /* 512 KB */
360#define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32 378#define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32
361#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB 379#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) /* 32 KB */
362 380
363#define SVGA_CB_CONTEXT_MASK 0x3f 381#define SVGA_CB_CONTEXT_MASK 0x3f
364typedef enum { 382typedef enum {
@@ -431,9 +449,10 @@ typedef enum {
431} SVGACBFlags; 449} SVGACBFlags;
432 450
433typedef 451typedef
452#include "vmware_pack_begin.h"
434struct { 453struct {
435 volatile SVGACBStatus status; /* Modified by device. */ 454 volatile SVGACBStatus status;
436 volatile uint32 errorOffset; /* Modified by device. */ 455 volatile uint32 errorOffset;
437 uint64 id; 456 uint64 id;
438 SVGACBFlags flags; 457 SVGACBFlags flags;
439 uint32 length; 458 uint32 length;
@@ -444,13 +463,11 @@ struct {
444 uint32 mobOffset; 463 uint32 mobOffset;
445 } mob; 464 } mob;
446 } ptr; 465 } ptr;
447 uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise, 466 uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise */
448 * modified by device.
449 */
450 uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */ 467 uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */
451 uint32 mustBeZero[6]; 468 uint32 mustBeZero[6];
452} 469}
453__attribute__((__packed__)) 470#include "vmware_pack_end.h"
454SVGACBHeader; 471SVGACBHeader;
455 472
456typedef enum { 473typedef enum {
@@ -458,9 +475,9 @@ typedef enum {
458 SVGA_DC_CMD_START_STOP_CONTEXT = 1, 475 SVGA_DC_CMD_START_STOP_CONTEXT = 1,
459 SVGA_DC_CMD_PREEMPT = 2, 476 SVGA_DC_CMD_PREEMPT = 2,
460 SVGA_DC_CMD_MAX = 3, 477 SVGA_DC_CMD_MAX = 3,
478 SVGA_DC_CMD_FORCE_UINT = MAX_UINT32,
461} SVGADeviceContextCmdId; 479} SVGADeviceContextCmdId;
462 480
463
464typedef struct { 481typedef struct {
465 uint32 enable; 482 uint32 enable;
466 SVGACBContext context; 483 SVGACBContext context;
@@ -485,7 +502,6 @@ typedef struct {
485 uint32 ignoreIDZero; 502 uint32 ignoreIDZero;
486} SVGADCCmdPreempt; 503} SVGADCCmdPreempt;
487 504
488
489/* 505/*
490 * SVGAGMRImageFormat -- 506 * SVGAGMRImageFormat --
491 * 507 *
@@ -506,13 +522,12 @@ typedef struct {
506 * 522 *
507 */ 523 */
508 524
509typedef 525typedef struct SVGAGMRImageFormat {
510struct SVGAGMRImageFormat {
511 union { 526 union {
512 struct { 527 struct {
513 uint32 bitsPerPixel : 8; 528 uint32 bitsPerPixel : 8;
514 uint32 colorDepth : 8; 529 uint32 colorDepth : 8;
515 uint32 reserved : 16; /* Must be zero */ 530 uint32 reserved : 16; /* Must be zero */
516 }; 531 };
517 532
518 uint32 value; 533 uint32 value;
@@ -520,6 +535,7 @@ struct SVGAGMRImageFormat {
520} SVGAGMRImageFormat; 535} SVGAGMRImageFormat;
521 536
522typedef 537typedef
538#include "vmware_pack_begin.h"
523struct SVGAGuestImage { 539struct SVGAGuestImage {
524 SVGAGuestPtr ptr; 540 SVGAGuestPtr ptr;
525 541
@@ -539,7 +555,9 @@ struct SVGAGuestImage {
539 * assuming each row of blocks is tightly packed. 555 * assuming each row of blocks is tightly packed.
540 */ 556 */
541 uint32 pitch; 557 uint32 pitch;
542} SVGAGuestImage; 558}
559#include "vmware_pack_end.h"
560SVGAGuestImage;
543 561
544/* 562/*
545 * SVGAColorBGRX -- 563 * SVGAColorBGRX --
@@ -549,14 +567,13 @@ struct SVGAGuestImage {
549 * GMRFB state. 567 * GMRFB state.
550 */ 568 */
551 569
552typedef 570typedef struct SVGAColorBGRX {
553struct SVGAColorBGRX {
554 union { 571 union {
555 struct { 572 struct {
556 uint32 b : 8; 573 uint32 b : 8;
557 uint32 g : 8; 574 uint32 g : 8;
558 uint32 r : 8; 575 uint32 r : 8;
559 uint32 x : 8; /* Unused */ 576 uint32 x : 8; /* Unused */
560 }; 577 };
561 578
562 uint32 value; 579 uint32 value;
@@ -578,26 +595,49 @@ struct SVGAColorBGRX {
578 */ 595 */
579 596
580typedef 597typedef
581struct SVGASignedRect { 598#include "vmware_pack_begin.h"
599struct {
582 int32 left; 600 int32 left;
583 int32 top; 601 int32 top;
584 int32 right; 602 int32 right;
585 int32 bottom; 603 int32 bottom;
586} SVGASignedRect; 604}
605#include "vmware_pack_end.h"
606SVGASignedRect;
587 607
588typedef 608typedef
589struct SVGASignedPoint { 609#include "vmware_pack_begin.h"
610struct {
590 int32 x; 611 int32 x;
591 int32 y; 612 int32 y;
592} SVGASignedPoint; 613}
614#include "vmware_pack_end.h"
615SVGASignedPoint;
593 616
594 617
595/* 618/*
596 * Capabilities 619 * SVGA Device Capabilities
597 * 620 *
598 * Note the holes in the bitfield. Missing bits have been deprecated, 621 * Note the holes in the bitfield. Missing bits have been deprecated,
599 * and must not be reused. Those capabilities will never be reported 622 * and must not be reused. Those capabilities will never be reported
600 * by new versions of the SVGA device. 623 * by new versions of the SVGA device.
624 *
625 * XXX: Add longer descriptions for each capability, including a list
626 * of the new features that each capability provides.
627 *
628 * SVGA_CAP_IRQMASK --
629 * Provides device interrupts. Adds device register SVGA_REG_IRQMASK
630 * to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
631 * set/clear pending interrupts.
632 *
633 * SVGA_CAP_GMR --
634 * Provides synchronous mapping of guest memory regions (GMR).
635 * Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR,
636 * SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH.
637 *
638 * SVGA_CAP_TRACES --
639 * Allows framebuffer trace-based updates even when FIFO is enabled.
640 * Adds device register SVGA_REG_TRACES.
601 * 641 *
602 * SVGA_CAP_GMR2 -- 642 * SVGA_CAP_GMR2 --
603 * Provides asynchronous commands to define and remap guest memory 643 * Provides asynchronous commands to define and remap guest memory
@@ -607,21 +647,39 @@ struct SVGASignedPoint {
607 * SVGA_CAP_SCREEN_OBJECT_2 -- 647 * SVGA_CAP_SCREEN_OBJECT_2 --
608 * Allow screen object support, and require backing stores from the 648 * Allow screen object support, and require backing stores from the
609 * guest for each screen object. 649 * guest for each screen object.
650 *
651 * SVGA_CAP_COMMAND_BUFFERS --
652 * Enable register based command buffer submission.
653 *
654 * SVGA_CAP_DEAD1 --
655 * This cap was incorrectly used by old drivers and should not be
656 * reused.
657 *
658 * SVGA_CAP_CMD_BUFFERS_2 --
659 * Enable support for the prepend command buffer submision
660 * registers. SVGA_REG_CMD_PREPEND_LOW and
661 * SVGA_REG_CMD_PREPEND_HIGH.
662 *
663 * SVGA_CAP_GBOBJECTS --
664 * Enable guest-backed objects and surfaces.
665 *
666 * SVGA_CAP_CMD_BUFFERS_3 --
667 * Enable support for command buffers in a mob.
610 */ 668 */
611 669
612#define SVGA_CAP_NONE 0x00000000 670#define SVGA_CAP_NONE 0x00000000
613#define SVGA_CAP_RECT_COPY 0x00000002 671#define SVGA_CAP_RECT_COPY 0x00000002
614#define SVGA_CAP_CURSOR 0x00000020 672#define SVGA_CAP_CURSOR 0x00000020
615#define SVGA_CAP_CURSOR_BYPASS 0x00000040 /* Legacy (Use Cursor Bypass 3 instead) */ 673#define SVGA_CAP_CURSOR_BYPASS 0x00000040
616#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 /* Legacy (Use Cursor Bypass 3 instead) */ 674#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080
617#define SVGA_CAP_8BIT_EMULATION 0x00000100 675#define SVGA_CAP_8BIT_EMULATION 0x00000100
618#define SVGA_CAP_ALPHA_CURSOR 0x00000200 676#define SVGA_CAP_ALPHA_CURSOR 0x00000200
619#define SVGA_CAP_3D 0x00004000 677#define SVGA_CAP_3D 0x00004000
620#define SVGA_CAP_EXTENDED_FIFO 0x00008000 678#define SVGA_CAP_EXTENDED_FIFO 0x00008000
621#define SVGA_CAP_MULTIMON 0x00010000 /* Legacy multi-monitor support */ 679#define SVGA_CAP_MULTIMON 0x00010000
622#define SVGA_CAP_PITCHLOCK 0x00020000 680#define SVGA_CAP_PITCHLOCK 0x00020000
623#define SVGA_CAP_IRQMASK 0x00040000 681#define SVGA_CAP_IRQMASK 0x00040000
624#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 /* Legacy multi-monitor support */ 682#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000
625#define SVGA_CAP_GMR 0x00100000 683#define SVGA_CAP_GMR 0x00100000
626#define SVGA_CAP_TRACES 0x00200000 684#define SVGA_CAP_TRACES 0x00200000
627#define SVGA_CAP_GMR2 0x00400000 685#define SVGA_CAP_GMR2 0x00400000
@@ -630,7 +688,33 @@ struct SVGASignedPoint {
630#define SVGA_CAP_DEAD1 0x02000000 688#define SVGA_CAP_DEAD1 0x02000000
631#define SVGA_CAP_CMD_BUFFERS_2 0x04000000 689#define SVGA_CAP_CMD_BUFFERS_2 0x04000000
632#define SVGA_CAP_GBOBJECTS 0x08000000 690#define SVGA_CAP_GBOBJECTS 0x08000000
633#define SVGA_CAP_CMD_BUFFERS_3 0x10000000 691#define SVGA_CAP_DX 0x10000000
692
693#define SVGA_CAP_CMD_RESERVED 0x80000000
694
695
696/*
697 * The Guest can optionally read some SVGA device capabilities through
698 * the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before
699 * the SVGA device is initialized. The type of capability the guest
700 * is requesting from the SVGABackdoorCapType enum should be placed in
701 * the upper 16 bits of the backdoor command id (ECX). On success the
702 * the value of EBX will be set to BDOOR_MAGIC and EAX will be set to
703 * the requested capability. If the command is not supported then EBX
704 * will be left unchanged and EAX will be set to -1. Because it is
705 * possible that -1 is the value of the requested cap the correct way
706 * to check if the command was successful is to check if EBX was changed
707 * to BDOOR_MAGIC making sure to initialize the register to something
708 * else first.
709 */
710
711typedef enum {
712 SVGABackdoorCapDeviceCaps = 0,
713 SVGABackdoorCapFifoCaps = 1,
714 SVGABackdoorCap3dHWVersion = 2,
715 SVGABackdoorCapMax = 3,
716} SVGABackdoorCapType;
717
634 718
635/* 719/*
636 * FIFO register indices. 720 * FIFO register indices.
@@ -1070,7 +1154,8 @@ enum {
1070 SVGA_VIDEO_PITCH_2, 1154 SVGA_VIDEO_PITCH_2,
1071 SVGA_VIDEO_PITCH_3, 1155 SVGA_VIDEO_PITCH_3,
1072 SVGA_VIDEO_DATA_GMRID, /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */ 1156 SVGA_VIDEO_DATA_GMRID, /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */
1073 SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords (SVGA_ID_INVALID) */ 1157 SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords */
1158 /* (SVGA_ID_INVALID) */
1074 SVGA_VIDEO_NUM_REGS 1159 SVGA_VIDEO_NUM_REGS
1075}; 1160};
1076 1161
@@ -1083,7 +1168,9 @@ enum {
1083 * video frame to be displayed. 1168 * video frame to be displayed.
1084 */ 1169 */
1085 1170
1086typedef struct SVGAOverlayUnit { 1171typedef
1172#include "vmware_pack_begin.h"
1173struct SVGAOverlayUnit {
1087 uint32 enabled; 1174 uint32 enabled;
1088 uint32 flags; 1175 uint32 flags;
1089 uint32 dataOffset; 1176 uint32 dataOffset;
@@ -1103,7 +1190,27 @@ typedef struct SVGAOverlayUnit {
1103 uint32 pitches[3]; 1190 uint32 pitches[3];
1104 uint32 dataGMRId; 1191 uint32 dataGMRId;
1105 uint32 dstScreenId; 1192 uint32 dstScreenId;
1106} SVGAOverlayUnit; 1193}
1194#include "vmware_pack_end.h"
1195SVGAOverlayUnit;
1196
1197
1198/*
1199 * Guest display topology
1200 *
1201 * XXX: This structure is not part of the SVGA device's interface, and
1202 * doesn't really belong here.
1203 */
1204#define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
1205
1206typedef struct SVGADisplayTopology {
1207 uint16 displayId;
1208 uint16 isPrimary;
1209 uint32 width;
1210 uint32 height;
1211 uint32 positionX;
1212 uint32 positionY;
1213} SVGADisplayTopology;
1107 1214
1108 1215
1109/* 1216/*
@@ -1138,10 +1245,10 @@ typedef struct SVGAOverlayUnit {
1138 * value of zero means no cloning should happen. 1245 * value of zero means no cloning should happen.
1139 */ 1246 */
1140 1247
1141#define SVGA_SCREEN_MUST_BE_SET (1 << 0) /* Must be set or results undefined */ 1248#define SVGA_SCREEN_MUST_BE_SET (1 << 0)
1142#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */ 1249#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */
1143#define SVGA_SCREEN_IS_PRIMARY (1 << 1) /* Guest considers this screen to be 'primary' */ 1250#define SVGA_SCREEN_IS_PRIMARY (1 << 1)
1144#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) /* Guest is running a fullscreen app here */ 1251#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2)
1145 1252
1146/* 1253/*
1147 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is 1254 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is
@@ -1164,7 +1271,8 @@ typedef struct SVGAOverlayUnit {
1164#define SVGA_SCREEN_BLANKING (1 << 4) 1271#define SVGA_SCREEN_BLANKING (1 << 4)
1165 1272
1166typedef 1273typedef
1167struct SVGAScreenObject { 1274#include "vmware_pack_begin.h"
1275struct {
1168 uint32 structSize; /* sizeof(SVGAScreenObject) */ 1276 uint32 structSize; /* sizeof(SVGAScreenObject) */
1169 uint32 id; 1277 uint32 id;
1170 uint32 flags; 1278 uint32 flags;
@@ -1182,8 +1290,17 @@ struct SVGAScreenObject {
1182 * with SVGA_FIFO_CAP_SCREEN_OBJECT. 1290 * with SVGA_FIFO_CAP_SCREEN_OBJECT.
1183 */ 1291 */
1184 SVGAGuestImage backingStore; 1292 SVGAGuestImage backingStore;
1293
1294 /*
1295 * The cloneCount field is treated as a hint from the guest that
1296 * the user wants this display to be cloned, cloneCount times.
1297 *
1298 * A value of zero means no cloning should happen.
1299 */
1185 uint32 cloneCount; 1300 uint32 cloneCount;
1186} SVGAScreenObject; 1301}
1302#include "vmware_pack_end.h"
1303SVGAScreenObject;
1187 1304
1188 1305
1189/* 1306/*
@@ -1196,7 +1313,7 @@ struct SVGAScreenObject {
1196 * Note the holes in the command ID numbers: These commands have been 1313 * Note the holes in the command ID numbers: These commands have been
1197 * deprecated, and the old IDs must not be reused. 1314 * deprecated, and the old IDs must not be reused.
1198 * 1315 *
1199 * Command IDs from 1000 to 1999 are reserved for use by the SVGA3D 1316 * Command IDs from 1000 to 2999 are reserved for use by the SVGA3D
1200 * protocol. 1317 * protocol.
1201 * 1318 *
1202 * Each command's parameters are described by the comments and 1319 * Each command's parameters are described by the comments and
@@ -1207,6 +1324,7 @@ typedef enum {
1207 SVGA_CMD_INVALID_CMD = 0, 1324 SVGA_CMD_INVALID_CMD = 0,
1208 SVGA_CMD_UPDATE = 1, 1325 SVGA_CMD_UPDATE = 1,
1209 SVGA_CMD_RECT_COPY = 3, 1326 SVGA_CMD_RECT_COPY = 3,
1327 SVGA_CMD_RECT_ROP_COPY = 14,
1210 SVGA_CMD_DEFINE_CURSOR = 19, 1328 SVGA_CMD_DEFINE_CURSOR = 19,
1211 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 1329 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
1212 SVGA_CMD_UPDATE_VERBOSE = 25, 1330 SVGA_CMD_UPDATE_VERBOSE = 25,
@@ -1222,9 +1340,14 @@ typedef enum {
1222 SVGA_CMD_ANNOTATION_COPY = 40, 1340 SVGA_CMD_ANNOTATION_COPY = 40,
1223 SVGA_CMD_DEFINE_GMR2 = 41, 1341 SVGA_CMD_DEFINE_GMR2 = 41,
1224 SVGA_CMD_REMAP_GMR2 = 42, 1342 SVGA_CMD_REMAP_GMR2 = 42,
1343 SVGA_CMD_DEAD = 43,
1344 SVGA_CMD_DEAD_2 = 44,
1345 SVGA_CMD_NOP = 45,
1346 SVGA_CMD_NOP_ERROR = 46,
1225 SVGA_CMD_MAX 1347 SVGA_CMD_MAX
1226} SVGAFifoCmdId; 1348} SVGAFifoCmdId;
1227 1349
1350#define SVGA_CMD_MAX_DATASIZE (256 * 1024)
1228#define SVGA_CMD_MAX_ARGS 64 1351#define SVGA_CMD_MAX_ARGS 64
1229 1352
1230 1353
@@ -1257,12 +1380,15 @@ typedef enum {
1257 */ 1380 */
1258 1381
1259typedef 1382typedef
1260struct SVGAFifoCmdUpdate { 1383#include "vmware_pack_begin.h"
1384struct {
1261 uint32 x; 1385 uint32 x;
1262 uint32 y; 1386 uint32 y;
1263 uint32 width; 1387 uint32 width;
1264 uint32 height; 1388 uint32 height;
1265} SVGAFifoCmdUpdate; 1389}
1390#include "vmware_pack_end.h"
1391SVGAFifoCmdUpdate;
1266 1392
1267 1393
1268/* 1394/*
@@ -1276,14 +1402,44 @@ struct SVGAFifoCmdUpdate {
1276 */ 1402 */
1277 1403
1278typedef 1404typedef
1279struct SVGAFifoCmdRectCopy { 1405#include "vmware_pack_begin.h"
1406struct {
1407 uint32 srcX;
1408 uint32 srcY;
1409 uint32 destX;
1410 uint32 destY;
1411 uint32 width;
1412 uint32 height;
1413}
1414#include "vmware_pack_end.h"
1415SVGAFifoCmdRectCopy;
1416
1417
1418/*
1419 * SVGA_CMD_RECT_ROP_COPY --
1420 *
1421 * Perform a rectangular DMA transfer from one area of the GFB to
1422 * another, and copy the result to any screens which intersect it.
1423 * The value of ROP may only be SVGA_ROP_COPY, and this command is
1424 * only supported for backwards compatibility reasons.
1425 *
1426 * Availability:
1427 * SVGA_CAP_RECT_COPY
1428 */
1429
1430typedef
1431#include "vmware_pack_begin.h"
1432struct {
1280 uint32 srcX; 1433 uint32 srcX;
1281 uint32 srcY; 1434 uint32 srcY;
1282 uint32 destX; 1435 uint32 destX;
1283 uint32 destY; 1436 uint32 destY;
1284 uint32 width; 1437 uint32 width;
1285 uint32 height; 1438 uint32 height;
1286} SVGAFifoCmdRectCopy; 1439 uint32 rop;
1440}
1441#include "vmware_pack_end.h"
1442SVGAFifoCmdRectRopCopy;
1287 1443
1288 1444
1289/* 1445/*
@@ -1300,7 +1456,8 @@ struct SVGAFifoCmdRectCopy {
1300 */ 1456 */
1301 1457
1302typedef 1458typedef
1303struct SVGAFifoCmdDefineCursor { 1459#include "vmware_pack_begin.h"
1460struct {
1304 uint32 id; /* Reserved, must be zero. */ 1461 uint32 id; /* Reserved, must be zero. */
1305 uint32 hotspotX; 1462 uint32 hotspotX;
1306 uint32 hotspotY; 1463 uint32 hotspotY;
@@ -1312,7 +1469,9 @@ struct SVGAFifoCmdDefineCursor {
1312 * Followed by scanline data for AND mask, then XOR mask. 1469 * Followed by scanline data for AND mask, then XOR mask.
1313 * Each scanline is padded to a 32-bit boundary. 1470 * Each scanline is padded to a 32-bit boundary.
1314 */ 1471 */
1315} SVGAFifoCmdDefineCursor; 1472}
1473#include "vmware_pack_end.h"
1474SVGAFifoCmdDefineCursor;
1316 1475
1317 1476
1318/* 1477/*
@@ -1329,14 +1488,17 @@ struct SVGAFifoCmdDefineCursor {
1329 */ 1488 */
1330 1489
1331typedef 1490typedef
1332struct SVGAFifoCmdDefineAlphaCursor { 1491#include "vmware_pack_begin.h"
1492struct {
1333 uint32 id; /* Reserved, must be zero. */ 1493 uint32 id; /* Reserved, must be zero. */
1334 uint32 hotspotX; 1494 uint32 hotspotX;
1335 uint32 hotspotY; 1495 uint32 hotspotY;
1336 uint32 width; 1496 uint32 width;
1337 uint32 height; 1497 uint32 height;
1338 /* Followed by scanline data */ 1498 /* Followed by scanline data */
1339} SVGAFifoCmdDefineAlphaCursor; 1499}
1500#include "vmware_pack_end.h"
1501SVGAFifoCmdDefineAlphaCursor;
1340 1502
1341 1503
1342/* 1504/*
@@ -1352,13 +1514,16 @@ struct SVGAFifoCmdDefineAlphaCursor {
1352 */ 1514 */
1353 1515
1354typedef 1516typedef
1355struct SVGAFifoCmdUpdateVerbose { 1517#include "vmware_pack_begin.h"
1518struct {
1356 uint32 x; 1519 uint32 x;
1357 uint32 y; 1520 uint32 y;
1358 uint32 width; 1521 uint32 width;
1359 uint32 height; 1522 uint32 height;
1360 uint32 reason; 1523 uint32 reason;
1361} SVGAFifoCmdUpdateVerbose; 1524}
1525#include "vmware_pack_end.h"
1526SVGAFifoCmdUpdateVerbose;
1362 1527
1363 1528
1364/* 1529/*
@@ -1377,14 +1542,17 @@ struct SVGAFifoCmdUpdateVerbose {
1377#define SVGA_ROP_COPY 0x03 1542#define SVGA_ROP_COPY 0x03
1378 1543
1379typedef 1544typedef
1380struct SVGAFifoCmdFrontRopFill { 1545#include "vmware_pack_begin.h"
1546struct {
1381 uint32 color; /* In the same format as the GFB */ 1547 uint32 color; /* In the same format as the GFB */
1382 uint32 x; 1548 uint32 x;
1383 uint32 y; 1549 uint32 y;
1384 uint32 width; 1550 uint32 width;
1385 uint32 height; 1551 uint32 height;
1386 uint32 rop; /* Must be SVGA_ROP_COPY */ 1552 uint32 rop; /* Must be SVGA_ROP_COPY */
1387} SVGAFifoCmdFrontRopFill; 1553}
1554#include "vmware_pack_end.h"
1555SVGAFifoCmdFrontRopFill;
1388 1556
1389 1557
1390/* 1558/*
@@ -1403,9 +1571,12 @@ struct SVGAFifoCmdFrontRopFill {
1403 */ 1571 */
1404 1572
1405typedef 1573typedef
1574#include "vmware_pack_begin.h"
1406struct { 1575struct {
1407 uint32 fence; 1576 uint32 fence;
1408} SVGAFifoCmdFence; 1577}
1578#include "vmware_pack_end.h"
1579SVGAFifoCmdFence;
1409 1580
1410 1581
1411/* 1582/*
@@ -1420,11 +1591,14 @@ struct {
1420 */ 1591 */
1421 1592
1422typedef 1593typedef
1423struct SVGAFifoCmdEscape { 1594#include "vmware_pack_begin.h"
1595struct {
1424 uint32 nsid; 1596 uint32 nsid;
1425 uint32 size; 1597 uint32 size;
1426 /* followed by 'size' bytes of data */ 1598 /* followed by 'size' bytes of data */
1427} SVGAFifoCmdEscape; 1599}
1600#include "vmware_pack_end.h"
1601SVGAFifoCmdEscape;
1428 1602
1429 1603
1430/* 1604/*
@@ -1454,9 +1628,12 @@ struct SVGAFifoCmdEscape {
1454 */ 1628 */
1455 1629
1456typedef 1630typedef
1631#include "vmware_pack_begin.h"
1457struct { 1632struct {
1458 SVGAScreenObject screen; /* Variable-length according to version */ 1633 SVGAScreenObject screen; /* Variable-length according to version */
1459} SVGAFifoCmdDefineScreen; 1634}
1635#include "vmware_pack_end.h"
1636SVGAFifoCmdDefineScreen;
1460 1637
1461 1638
1462/* 1639/*
@@ -1470,9 +1647,12 @@ struct {
1470 */ 1647 */
1471 1648
1472typedef 1649typedef
1650#include "vmware_pack_begin.h"
1473struct { 1651struct {
1474 uint32 screenId; 1652 uint32 screenId;
1475} SVGAFifoCmdDestroyScreen; 1653}
1654#include "vmware_pack_end.h"
1655SVGAFifoCmdDestroyScreen;
1476 1656
1477 1657
1478/* 1658/*
@@ -1523,11 +1703,14 @@ struct {
1523 */ 1703 */
1524 1704
1525typedef 1705typedef
1706#include "vmware_pack_begin.h"
1526struct { 1707struct {
1527 SVGAGuestPtr ptr; 1708 SVGAGuestPtr ptr;
1528 uint32 bytesPerLine; 1709 uint32 bytesPerLine;
1529 SVGAGMRImageFormat format; 1710 SVGAGMRImageFormat format;
1530} SVGAFifoCmdDefineGMRFB; 1711}
1712#include "vmware_pack_end.h"
1713SVGAFifoCmdDefineGMRFB;
1531 1714
1532 1715
1533/* 1716/*
@@ -1535,19 +1718,10 @@ struct {
1535 * 1718 *
1536 * This is a guest-to-host blit. It performs a DMA operation to 1719 * This is a guest-to-host blit. It performs a DMA operation to
1537 * copy a rectangular region of pixels from the current GMRFB to 1720 * copy a rectangular region of pixels from the current GMRFB to
1538 * one or more Screen Objects. 1721 * a ScreenObject.
1539 * 1722 *
1540 * The destination coordinate may be specified relative to a 1723 * The destination coordinate may be specified relative to a
1541 * screen's origin (if a screen ID is specified) or relative to the 1724 * screen's origin. The provided screen ID must be valid.
1542 * virtual coordinate system's origin (if the screen ID is
1543 * SVGA_ID_INVALID). The actual destination may span zero or more
1544 * screens, in the case of a virtual destination rect or a rect
1545 * which extends off the edge of the specified screen.
1546 *
1547 * This command writes to the screen's "base layer": the underlying
1548 * framebuffer which exists below any cursor or video overlays. No
1549 * action is necessary to explicitly hide or update any overlays
1550 * which exist on top of the updated region.
1551 * 1725 *
1552 * The SVGA device is guaranteed to finish reading from the GMRFB 1726 * The SVGA device is guaranteed to finish reading from the GMRFB
1553 * by the time any subsequent FENCE commands are reached. 1727 * by the time any subsequent FENCE commands are reached.
@@ -1560,46 +1734,27 @@ struct {
1560 */ 1734 */
1561 1735
1562typedef 1736typedef
1737#include "vmware_pack_begin.h"
1563struct { 1738struct {
1564 SVGASignedPoint srcOrigin; 1739 SVGASignedPoint srcOrigin;
1565 SVGASignedRect destRect; 1740 SVGASignedRect destRect;
1566 uint32 destScreenId; 1741 uint32 destScreenId;
1567} SVGAFifoCmdBlitGMRFBToScreen; 1742}
1743#include "vmware_pack_end.h"
1744SVGAFifoCmdBlitGMRFBToScreen;
1568 1745
1569 1746
1570/* 1747/*
1571 * SVGA_CMD_BLIT_SCREEN_TO_GMRFB -- 1748 * SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
1572 * 1749 *
1573 * This is a host-to-guest blit. It performs a DMA operation to 1750 * This is a host-to-guest blit. It performs a DMA operation to
1574 * copy a rectangular region of pixels from a single Screen Object 1751 * copy a rectangular region of pixels from a single ScreenObject
1575 * back to the current GMRFB. 1752 * back to the current GMRFB.
1576 * 1753 *
1577 * Usage note: This command should be used rarely. It will
1578 * typically be inefficient, but it is necessary for some types of
1579 * synchronization between 3D (GPU) and 2D (CPU) rendering into
1580 * overlapping areas of a screen.
1581 *
1582 * The source coordinate is specified relative to a screen's 1754 * The source coordinate is specified relative to a screen's
1583 * origin. The provided screen ID must be valid. If any parameters 1755 * origin. The provided screen ID must be valid. If any parameters
1584 * are invalid, the resulting pixel values are undefined. 1756 * are invalid, the resulting pixel values are undefined.
1585 * 1757 *
1586 * This command reads the screen's "base layer". Overlays like
1587 * video and cursor are not included, but any data which was sent
1588 * using a blit-to-screen primitive will be available, no matter
1589 * whether the data's original source was the GMRFB or the 3D
1590 * acceleration hardware.
1591 *
1592 * Note that our guest-to-host blits and host-to-guest blits aren't
1593 * symmetric in their current implementation. While the parameters
1594 * are identical, host-to-guest blits are a lot less featureful.
1595 * They do not support clipping: If the source parameters don't
1596 * fully fit within a screen, the blit fails. They must originate
1597 * from exactly one screen. Virtual coordinates are not directly
1598 * supported.
1599 *
1600 * Host-to-guest blits do support the same set of GMRFB formats
1601 * offered by guest-to-host blits.
1602 *
1603 * The SVGA device is guaranteed to finish writing to the GMRFB by 1758 * The SVGA device is guaranteed to finish writing to the GMRFB by
1604 * the time any subsequent FENCE commands are reached. 1759 * the time any subsequent FENCE commands are reached.
1605 * 1760 *
@@ -1608,77 +1763,57 @@ struct {
1608 */ 1763 */
1609 1764
1610typedef 1765typedef
1766#include "vmware_pack_begin.h"
1611struct { 1767struct {
1612 SVGASignedPoint destOrigin; 1768 SVGASignedPoint destOrigin;
1613 SVGASignedRect srcRect; 1769 SVGASignedRect srcRect;
1614 uint32 srcScreenId; 1770 uint32 srcScreenId;
1615} SVGAFifoCmdBlitScreenToGMRFB; 1771}
1772#include "vmware_pack_end.h"
1773SVGAFifoCmdBlitScreenToGMRFB;
1616 1774
1617 1775
1618/* 1776/*
1619 * SVGA_CMD_ANNOTATION_FILL -- 1777 * SVGA_CMD_ANNOTATION_FILL --
1620 * 1778 *
1621 * This is a blit annotation. This command stores a small piece of 1779 * The annotation commands have been deprecated, should not be used
1622 * device state which is consumed by the next blit-to-screen 1780 * by new drivers. They used to provide performance hints to the SVGA
1623 * command. The state is only cleared by commands which are 1781 * device about the content of screen updates, but newer SVGA devices
1624 * specifically documented as consuming an annotation. Other 1782 * ignore these.
1625 * commands (such as ESCAPEs for debugging) may intervene between
1626 * the annotation and its associated blit.
1627 *
1628 * This annotation is a promise about the contents of the next
1629 * blit: The video driver is guaranteeing that all pixels in that
1630 * blit will have the same value, specified here as a color in
1631 * SVGAColorBGRX format.
1632 *
1633 * The SVGA device can still render the blit correctly even if it
1634 * ignores this annotation, but the annotation may allow it to
1635 * perform the blit more efficiently, for example by ignoring the
1636 * source data and performing a fill in hardware.
1637 *
1638 * This annotation is most important for performance when the
1639 * user's display is being remoted over a network connection.
1640 * 1783 *
1641 * Availability: 1784 * Availability:
1642 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1785 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1643 */ 1786 */
1644 1787
1645typedef 1788typedef
1789#include "vmware_pack_begin.h"
1646struct { 1790struct {
1647 SVGAColorBGRX color; 1791 SVGAColorBGRX color;
1648} SVGAFifoCmdAnnotationFill; 1792}
1793#include "vmware_pack_end.h"
1794SVGAFifoCmdAnnotationFill;
1649 1795
1650 1796
1651/* 1797/*
1652 * SVGA_CMD_ANNOTATION_COPY -- 1798 * SVGA_CMD_ANNOTATION_COPY --
1653 * 1799 *
1654 * This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more 1800 * The annotation commands have been deprecated, should not be used
1655 * information about annotations. 1801 * by new drivers. They used to provide performance hints to the SVGA
1656 * 1802 * device about the content of screen updates, but newer SVGA devices
1657 * This annotation is a promise about the contents of the next 1803 * ignore these.
1658 * blit: The video driver is guaranteeing that all pixels in that
1659 * blit will have the same value as those which already exist at an
1660 * identically-sized region on the same or a different screen.
1661 *
1662 * Note that the source pixels for the COPY in this annotation are
1663 * sampled before applying the anqnotation's associated blit. They
1664 * are allowed to overlap with the blit's destination pixels.
1665 *
1666 * The copy source rectangle is specified the same way as the blit
1667 * destination: it can be a rectangle which spans zero or more
1668 * screens, specified relative to either a screen or to the virtual
1669 * coordinate system's origin. If the source rectangle includes
1670 * pixels which are not from exactly one screen, the results are
1671 * undefined.
1672 * 1804 *
1673 * Availability: 1805 * Availability:
1674 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1806 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1675 */ 1807 */
1676 1808
1677typedef 1809typedef
1810#include "vmware_pack_begin.h"
1678struct { 1811struct {
1679 SVGASignedPoint srcOrigin; 1812 SVGASignedPoint srcOrigin;
1680 uint32 srcScreenId; 1813 uint32 srcScreenId;
1681} SVGAFifoCmdAnnotationCopy; 1814}
1815#include "vmware_pack_end.h"
1816SVGAFifoCmdAnnotationCopy;
1682 1817
1683 1818
1684/* 1819/*
@@ -1691,10 +1826,13 @@ struct {
1691 */ 1826 */
1692 1827
1693typedef 1828typedef
1829#include "vmware_pack_begin.h"
1694struct { 1830struct {
1695 uint32 gmrId; 1831 uint32 gmrId;
1696 uint32 numPages; 1832 uint32 numPages;
1697} SVGAFifoCmdDefineGMR2; 1833}
1834#include "vmware_pack_end.h"
1835SVGAFifoCmdDefineGMR2;
1698 1836
1699 1837
1700/* 1838/*
@@ -1733,6 +1871,7 @@ typedef enum {
1733} SVGARemapGMR2Flags; 1871} SVGARemapGMR2Flags;
1734 1872
1735typedef 1873typedef
1874#include "vmware_pack_begin.h"
1736struct { 1875struct {
1737 uint32 gmrId; 1876 uint32 gmrId;
1738 SVGARemapGMR2Flags flags; 1877 SVGARemapGMR2Flags flags;
@@ -1746,6 +1885,52 @@ struct {
1746 * (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag 1885 * (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag
1747 * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry. 1886 * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.
1748 */ 1887 */
1749} SVGAFifoCmdRemapGMR2; 1888}
1889#include "vmware_pack_end.h"
1890SVGAFifoCmdRemapGMR2;
1891
1892
1893/*
1894 * Size of SVGA device memory such as frame buffer and FIFO.
1895 */
1896#define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) /* bytes */
1897#define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024)
1898#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024)
1899#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024)
1900#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024)
1901#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
1902#define SVGA_GRAPHICS_MEMORY_KB_MAX (2 * 1024 * 1024)
1903#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024)
1904
1905#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */
1906
1907/*
1908 * To simplify autoDetect display configuration, support a minimum of
1909 * two 1920x1200 monitors, 32bpp, side-by-side, optionally rotated:
1910 * numDisplays = 2
1911 * maxWidth = numDisplay * 1920 = 3840
1912 * maxHeight = rotated width of single monitor = 1920
1913 * vramSize = maxWidth * maxHeight * 4 = 29491200
1914 */
1915#define SVGA_VRAM_SIZE_AUTODETECT (32 * 1024 * 1024)
1916
1917#if defined(VMX86_SERVER)
1918#define SVGA_VRAM_SIZE (4 * 1024 * 1024)
1919#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
1920#define SVGA_FIFO_SIZE (256 * 1024)
1921#define SVGA_FIFO_SIZE_3D (516 * 1024)
1922#define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024)
1923#define SVGA_AUTODETECT_DEFAULT FALSE
1924#else
1925#define SVGA_VRAM_SIZE (16 * 1024 * 1024)
1926#define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE
1927#define SVGA_FIFO_SIZE (2 * 1024 * 1024)
1928#define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE
1929#define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024)
1930#define SVGA_AUTODETECT_DEFAULT TRUE
1931#endif
1932
1933#define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024)
1934#define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024)
1750 1935
1751#endif 1936#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga_types.h b/drivers/gpu/drm/vmwgfx/device_include/svga_types.h
new file mode 100644
index 000000000000..2e8ba4df8de9
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga_types.h
@@ -0,0 +1,46 @@
1/**********************************************************
2 * Copyright 2015 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25#ifndef _VM_BASIC_TYPES_H_
26#define _VM_BASIC_TYPES_H_
27#include <linux/kernel.h>
28
29typedef u32 uint32;
30typedef s32 int32;
31typedef u64 uint64;
32typedef u16 uint16;
33typedef s16 int16;
34typedef u8 uint8;
35typedef s8 int8;
36
37typedef uint64 PA;
38typedef uint32 PPN;
39typedef uint64 PPN64;
40
41typedef bool Bool;
42
43#define MAX_UINT32 U32_MAX
44#define MAX_UINT16 U16_MAX
45
46#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/vm_basic_types.h b/drivers/gpu/drm/vmwgfx/device_include/vm_basic_types.h
new file mode 100644
index 000000000000..120eab830eaf
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/vm_basic_types.h
@@ -0,0 +1,21 @@
1#ifndef _VM_BASIC_TYPES_H_
2#define _VM_BASIC_TYPES_H_
3#include <linux/kernel.h>
4
5typedef u32 uint32;
6typedef s32 int32;
7typedef u64 uint64;
8typedef u16 uint16;
9typedef s16 int16;
10typedef u8 uint8;
11typedef s8 int8;
12
13typedef uint64 PA;
14typedef uint32 PPN;
15typedef uint64 PPN64;
16
17typedef bool Bool;
18
19#define MAX_UINT32 U32_MAX
20
21#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_begin.h b/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_begin.h
new file mode 100644
index 000000000000..7e7b0ce34aa2
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_begin.h
@@ -0,0 +1,25 @@
1/**********************************************************
2 * Copyright 2015 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25#include <linux/compiler.h>
diff --git a/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_end.h b/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_end.h
new file mode 100644
index 000000000000..e2e440ed3d44
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_end.h
@@ -0,0 +1,25 @@
1/**********************************************************
2 * Copyright 2015 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25__packed
diff --git a/drivers/gpu/drm/vmwgfx/svga3d_reg.h b/drivers/gpu/drm/vmwgfx/svga3d_reg.h
deleted file mode 100644
index f4af9f1ef9be..000000000000
--- a/drivers/gpu/drm/vmwgfx/svga3d_reg.h
+++ /dev/null
@@ -1,2675 +0,0 @@
1/**********************************************************
2 * Copyright 1998-2014 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_reg.h --
28 *
29 * SVGA 3D hardware definitions
30 */
31
32#ifndef _SVGA3D_REG_H_
33#define _SVGA3D_REG_H_
34
35#include "svga_reg.h"
36
37typedef uint32 PPN;
38typedef u64 PPN64;
39
40/*
41 * 3D Hardware Version
42 *
43 * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
44 * register. Is set by the host and read by the guest. This lets
45 * us make new guest drivers which are backwards-compatible with old
46 * SVGA hardware revisions. It does not let us support old guest
47 * drivers. Good enough for now.
48 *
49 */
50
51#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
52#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
53#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
54
55typedef enum {
56 SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
57 SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
58 SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
59 SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
60 SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
61 SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
62 SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
63 SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
64} SVGA3dHardwareVersion;
65
66/*
67 * Generic Types
68 */
69
70typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
71#define SVGA3D_NUM_CLIPPLANES 6
72#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS 8
73#define SVGA3D_MAX_CONTEXT_IDS 256
74#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
75
76#define SVGA3D_NUM_TEXTURE_UNITS 32
77#define SVGA3D_NUM_LIGHTS 8
78
79/*
80 * Surface formats.
81 *
82 * If you modify this list, be sure to keep GLUtil.c in sync. It
83 * includes the internal format definition of each surface in
84 * GLUtil_ConvertSurfaceFormat, and it contains a table of
85 * human-readable names in GLUtil_GetFormatName.
86 */
87
88typedef enum SVGA3dSurfaceFormat {
89 SVGA3D_FORMAT_MIN = 0,
90 SVGA3D_FORMAT_INVALID = 0,
91
92 SVGA3D_X8R8G8B8 = 1,
93 SVGA3D_A8R8G8B8 = 2,
94
95 SVGA3D_R5G6B5 = 3,
96 SVGA3D_X1R5G5B5 = 4,
97 SVGA3D_A1R5G5B5 = 5,
98 SVGA3D_A4R4G4B4 = 6,
99
100 SVGA3D_Z_D32 = 7,
101 SVGA3D_Z_D16 = 8,
102 SVGA3D_Z_D24S8 = 9,
103 SVGA3D_Z_D15S1 = 10,
104
105 SVGA3D_LUMINANCE8 = 11,
106 SVGA3D_LUMINANCE4_ALPHA4 = 12,
107 SVGA3D_LUMINANCE16 = 13,
108 SVGA3D_LUMINANCE8_ALPHA8 = 14,
109
110 SVGA3D_DXT1 = 15,
111 SVGA3D_DXT2 = 16,
112 SVGA3D_DXT3 = 17,
113 SVGA3D_DXT4 = 18,
114 SVGA3D_DXT5 = 19,
115
116 SVGA3D_BUMPU8V8 = 20,
117 SVGA3D_BUMPL6V5U5 = 21,
118 SVGA3D_BUMPX8L8V8U8 = 22,
119 SVGA3D_BUMPL8V8U8 = 23,
120
121 SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
122 SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
123
124 SVGA3D_A2R10G10B10 = 26,
125
126 /* signed formats */
127 SVGA3D_V8U8 = 27,
128 SVGA3D_Q8W8V8U8 = 28,
129 SVGA3D_CxV8U8 = 29,
130
131 /* mixed formats */
132 SVGA3D_X8L8V8U8 = 30,
133 SVGA3D_A2W10V10U10 = 31,
134
135 SVGA3D_ALPHA8 = 32,
136
137 /* Single- and dual-component floating point formats */
138 SVGA3D_R_S10E5 = 33,
139 SVGA3D_R_S23E8 = 34,
140 SVGA3D_RG_S10E5 = 35,
141 SVGA3D_RG_S23E8 = 36,
142
143 SVGA3D_BUFFER = 37,
144
145 SVGA3D_Z_D24X8 = 38,
146
147 SVGA3D_V16U16 = 39,
148
149 SVGA3D_G16R16 = 40,
150 SVGA3D_A16B16G16R16 = 41,
151
152 /* Packed Video formats */
153 SVGA3D_UYVY = 42,
154 SVGA3D_YUY2 = 43,
155
156 /* Planar video formats */
157 SVGA3D_NV12 = 44,
158
159 /* Video format with alpha */
160 SVGA3D_AYUV = 45,
161
162 SVGA3D_R32G32B32A32_TYPELESS = 46,
163 SVGA3D_R32G32B32A32_FLOAT = 25,
164 SVGA3D_R32G32B32A32_UINT = 47,
165 SVGA3D_R32G32B32A32_SINT = 48,
166 SVGA3D_R32G32B32_TYPELESS = 49,
167 SVGA3D_R32G32B32_FLOAT = 50,
168 SVGA3D_R32G32B32_UINT = 51,
169 SVGA3D_R32G32B32_SINT = 52,
170 SVGA3D_R16G16B16A16_TYPELESS = 53,
171 SVGA3D_R16G16B16A16_FLOAT = 24,
172 SVGA3D_R16G16B16A16_UNORM = 41,
173 SVGA3D_R16G16B16A16_UINT = 54,
174 SVGA3D_R16G16B16A16_SNORM = 55,
175 SVGA3D_R16G16B16A16_SINT = 56,
176 SVGA3D_R32G32_TYPELESS = 57,
177 SVGA3D_R32G32_FLOAT = 36,
178 SVGA3D_R32G32_UINT = 58,
179 SVGA3D_R32G32_SINT = 59,
180 SVGA3D_R32G8X24_TYPELESS = 60,
181 SVGA3D_D32_FLOAT_S8X24_UINT = 61,
182 SVGA3D_R32_FLOAT_X8X24_TYPELESS = 62,
183 SVGA3D_X32_TYPELESS_G8X24_UINT = 63,
184 SVGA3D_R10G10B10A2_TYPELESS = 64,
185 SVGA3D_R10G10B10A2_UNORM = 26,
186 SVGA3D_R10G10B10A2_UINT = 65,
187 SVGA3D_R11G11B10_FLOAT = 66,
188 SVGA3D_R8G8B8A8_TYPELESS = 67,
189 SVGA3D_R8G8B8A8_UNORM = 68,
190 SVGA3D_R8G8B8A8_UNORM_SRGB = 69,
191 SVGA3D_R8G8B8A8_UINT = 70,
192 SVGA3D_R8G8B8A8_SNORM = 28,
193 SVGA3D_R8G8B8A8_SINT = 71,
194 SVGA3D_R16G16_TYPELESS = 72,
195 SVGA3D_R16G16_FLOAT = 35,
196 SVGA3D_R16G16_UNORM = 40,
197 SVGA3D_R16G16_UINT = 73,
198 SVGA3D_R16G16_SNORM = 39,
199 SVGA3D_R16G16_SINT = 74,
200 SVGA3D_R32_TYPELESS = 75,
201 SVGA3D_D32_FLOAT = 76,
202 SVGA3D_R32_FLOAT = 34,
203 SVGA3D_R32_UINT = 77,
204 SVGA3D_R32_SINT = 78,
205 SVGA3D_R24G8_TYPELESS = 79,
206 SVGA3D_D24_UNORM_S8_UINT = 80,
207 SVGA3D_R24_UNORM_X8_TYPELESS = 81,
208 SVGA3D_X24_TYPELESS_G8_UINT = 82,
209 SVGA3D_R8G8_TYPELESS = 83,
210 SVGA3D_R8G8_UNORM = 84,
211 SVGA3D_R8G8_UINT = 85,
212 SVGA3D_R8G8_SNORM = 27,
213 SVGA3D_R8G8_SINT = 86,
214 SVGA3D_R16_TYPELESS = 87,
215 SVGA3D_R16_FLOAT = 33,
216 SVGA3D_D16_UNORM = 8,
217 SVGA3D_R16_UNORM = 88,
218 SVGA3D_R16_UINT = 89,
219 SVGA3D_R16_SNORM = 90,
220 SVGA3D_R16_SINT = 91,
221 SVGA3D_R8_TYPELESS = 92,
222 SVGA3D_R8_UNORM = 93,
223 SVGA3D_R8_UINT = 94,
224 SVGA3D_R8_SNORM = 95,
225 SVGA3D_R8_SINT = 96,
226 SVGA3D_A8_UNORM = 32,
227 SVGA3D_P8 = 97,
228 SVGA3D_R9G9B9E5_SHAREDEXP = 98,
229 SVGA3D_R8G8_B8G8_UNORM = 99,
230 SVGA3D_G8R8_G8B8_UNORM = 100,
231 SVGA3D_BC1_TYPELESS = 101,
232 SVGA3D_BC1_UNORM = 15,
233 SVGA3D_BC1_UNORM_SRGB = 102,
234 SVGA3D_BC2_TYPELESS = 103,
235 SVGA3D_BC2_UNORM = 17,
236 SVGA3D_BC2_UNORM_SRGB = 104,
237 SVGA3D_BC3_TYPELESS = 105,
238 SVGA3D_BC3_UNORM = 19,
239 SVGA3D_BC3_UNORM_SRGB = 106,
240 SVGA3D_BC4_TYPELESS = 107,
241 SVGA3D_BC4_UNORM = 108,
242 SVGA3D_BC4_SNORM = 109,
243 SVGA3D_BC5_TYPELESS = 110,
244 SVGA3D_BC5_UNORM = 111,
245 SVGA3D_BC5_SNORM = 112,
246 SVGA3D_B5G6R5_UNORM = 3,
247 SVGA3D_B5G5R5A1_UNORM = 5,
248 SVGA3D_B8G8R8A8_UNORM = 2,
249 SVGA3D_B8G8R8X8_UNORM = 1,
250 SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113,
251 SVGA3D_B8G8R8A8_TYPELESS = 114,
252 SVGA3D_B8G8R8A8_UNORM_SRGB = 115,
253 SVGA3D_B8G8R8X8_TYPELESS = 116,
254 SVGA3D_B8G8R8X8_UNORM_SRGB = 117,
255
256 /* Advanced D3D9 depth formats. */
257 SVGA3D_Z_DF16 = 118,
258 SVGA3D_Z_DF24 = 119,
259 SVGA3D_Z_D24S8_INT = 120,
260
261 /* Planar video formats. */
262 SVGA3D_YV12 = 121,
263
264 SVGA3D_FORMAT_MAX = 122,
265} SVGA3dSurfaceFormat;
266
267typedef uint32 SVGA3dColor; /* a, r, g, b */
268
269/*
270 * These match the D3DFORMAT_OP definitions used by Direct3D. We need
271 * them so that we can query the host for what the supported surface
272 * operations are (when we're using the D3D backend, in particular),
273 * and so we can send those operations to the guest.
274 */
275typedef enum {
276 SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
277 SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
278 SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
279 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
280 SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
281 SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
282 SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
283
284/*
285 * This format can be used as a render target if the current display mode
286 * is the same depth if the alpha channel is ignored. e.g. if the device
287 * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
288 * format op list entry for A8R8G8B8 should have this cap.
289 */
290 SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
291
292/*
293 * This format contains DirectDraw support (including Flip). This flag
294 * should not to be set on alpha formats.
295 */
296 SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
297
298/*
299 * The rasterizer can support some level of Direct3D support in this format
300 * and implies that the driver can create a Context in this mode (for some
301 * render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
302 * flag must also be set.
303 */
304 SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
305
306/*
307 * This is set for a private format when the driver has put the bpp in
308 * the structure.
309 */
310 SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
311
312/*
313 * Indicates that this format can be converted to any RGB format for which
314 * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified
315 */
316 SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
317
318/*
319 * Indicates that this format can be used to create offscreen plain surfaces.
320 */
321 SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
322
323/*
324 * Indicated that this format can be read as an SRGB texture (meaning that the
325 * sampler will linearize the looked up data)
326 */
327 SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
328
329/*
330 * Indicates that this format can be used in the bumpmap instructions
331 */
332 SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
333
334/*
335 * Indicates that this format can be sampled by the displacement map sampler
336 */
337 SVGA3DFORMAT_OP_DMAP = 0x00020000,
338
339/*
340 * Indicates that this format cannot be used with texture filtering
341 */
342 SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
343
344/*
345 * Indicates that format conversions are supported to this RGB format if
346 * SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
347 */
348 SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
349
350/*
351 * Indicated that this format can be written as an SRGB target (meaning that the
352 * pixel pipe will DE-linearize data on output to format)
353 */
354 SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
355
356/*
357 * Indicates that this format cannot be used with alpha blending
358 */
359 SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
360
361/*
362 * Indicates that the device can auto-generated sublevels for resources
363 * of this format
364 */
365 SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
366
367/*
368 * Indicates that this format can be used by vertex texture sampler
369 */
370 SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
371
372/*
373 * Indicates that this format supports neither texture coordinate wrap
374 * modes, nor mipmapping
375 */
376 SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
377} SVGA3dFormatOp;
378
379/*
380 * This structure is a conversion of SVGA3DFORMAT_OP_*.
381 * Entries must be located at the same position.
382 */
383typedef union {
384 uint32 value;
385 struct {
386 uint32 texture : 1;
387 uint32 volumeTexture : 1;
388 uint32 cubeTexture : 1;
389 uint32 offscreenRenderTarget : 1;
390 uint32 sameFormatRenderTarget : 1;
391 uint32 unknown1 : 1;
392 uint32 zStencil : 1;
393 uint32 zStencilArbitraryDepth : 1;
394 uint32 sameFormatUpToAlpha : 1;
395 uint32 unknown2 : 1;
396 uint32 displayMode : 1;
397 uint32 acceleration3d : 1;
398 uint32 pixelSize : 1;
399 uint32 convertToARGB : 1;
400 uint32 offscreenPlain : 1;
401 uint32 sRGBRead : 1;
402 uint32 bumpMap : 1;
403 uint32 dmap : 1;
404 uint32 noFilter : 1;
405 uint32 memberOfGroupARGB : 1;
406 uint32 sRGBWrite : 1;
407 uint32 noAlphaBlend : 1;
408 uint32 autoGenMipMap : 1;
409 uint32 vertexTexture : 1;
410 uint32 noTexCoordWrapNorMip : 1;
411 };
412} SVGA3dSurfaceFormatCaps;
413
414/*
415 * SVGA_3D_CMD_SETRENDERSTATE Types. All value types
416 * must fit in a uint32.
417 */
418
419typedef enum {
420 SVGA3D_RS_INVALID = 0,
421 SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */
422 SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */
423 SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */
424 SVGA3D_RS_DITHERENABLE = 4, /* SVGA3dBool */
425 SVGA3D_RS_BLENDENABLE = 5, /* SVGA3dBool */
426 SVGA3D_RS_FOGENABLE = 6, /* SVGA3dBool */
427 SVGA3D_RS_SPECULARENABLE = 7, /* SVGA3dBool */
428 SVGA3D_RS_STENCILENABLE = 8, /* SVGA3dBool */
429 SVGA3D_RS_LIGHTINGENABLE = 9, /* SVGA3dBool */
430 SVGA3D_RS_NORMALIZENORMALS = 10, /* SVGA3dBool */
431 SVGA3D_RS_POINTSPRITEENABLE = 11, /* SVGA3dBool */
432 SVGA3D_RS_POINTSCALEENABLE = 12, /* SVGA3dBool */
433 SVGA3D_RS_STENCILREF = 13, /* uint32 */
434 SVGA3D_RS_STENCILMASK = 14, /* uint32 */
435 SVGA3D_RS_STENCILWRITEMASK = 15, /* uint32 */
436 SVGA3D_RS_FOGSTART = 16, /* float */
437 SVGA3D_RS_FOGEND = 17, /* float */
438 SVGA3D_RS_FOGDENSITY = 18, /* float */
439 SVGA3D_RS_POINTSIZE = 19, /* float */
440 SVGA3D_RS_POINTSIZEMIN = 20, /* float */
441 SVGA3D_RS_POINTSIZEMAX = 21, /* float */
442 SVGA3D_RS_POINTSCALE_A = 22, /* float */
443 SVGA3D_RS_POINTSCALE_B = 23, /* float */
444 SVGA3D_RS_POINTSCALE_C = 24, /* float */
445 SVGA3D_RS_FOGCOLOR = 25, /* SVGA3dColor */
446 SVGA3D_RS_AMBIENT = 26, /* SVGA3dColor */
447 SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */
448 SVGA3D_RS_FOGMODE = 28, /* SVGA3dFogMode */
449 SVGA3D_RS_FILLMODE = 29, /* SVGA3dFillMode */
450 SVGA3D_RS_SHADEMODE = 30, /* SVGA3dShadeMode */
451 SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */
452 SVGA3D_RS_SRCBLEND = 32, /* SVGA3dBlendOp */
453 SVGA3D_RS_DSTBLEND = 33, /* SVGA3dBlendOp */
454 SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */
455 SVGA3D_RS_CULLMODE = 35, /* SVGA3dFace */
456 SVGA3D_RS_ZFUNC = 36, /* SVGA3dCmpFunc */
457 SVGA3D_RS_ALPHAFUNC = 37, /* SVGA3dCmpFunc */
458 SVGA3D_RS_STENCILFUNC = 38, /* SVGA3dCmpFunc */
459 SVGA3D_RS_STENCILFAIL = 39, /* SVGA3dStencilOp */
460 SVGA3D_RS_STENCILZFAIL = 40, /* SVGA3dStencilOp */
461 SVGA3D_RS_STENCILPASS = 41, /* SVGA3dStencilOp */
462 SVGA3D_RS_ALPHAREF = 42, /* float (0.0 .. 1.0) */
463 SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */
464 SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */
465 SVGA3D_RS_ZBIAS = 45, /* float */
466 SVGA3D_RS_RANGEFOGENABLE = 46, /* SVGA3dBool */
467 SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */
468 SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */
469 SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */
470 SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */
471 SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */
472 SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */
473 SVGA3D_RS_TEXTUREFACTOR = 53, /* SVGA3dColor */
474 SVGA3D_RS_LOCALVIEWER = 54, /* SVGA3dBool */
475 SVGA3D_RS_SCISSORTESTENABLE = 55, /* SVGA3dBool */
476 SVGA3D_RS_BLENDCOLOR = 56, /* SVGA3dColor */
477 SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */
478 SVGA3D_RS_CCWSTENCILFUNC = 58, /* SVGA3dCmpFunc */
479 SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */
480 SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */
481 SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */
482 SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */
483 SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, /* float */
484 SVGA3D_RS_DEPTHBIAS = 64, /* float */
485
486
487 /*
488 * Output Gamma Level
489 *
490 * Output gamma effects the gamma curve of colors that are output from the
491 * rendering pipeline. A value of 1.0 specifies a linear color space. If the
492 * value is <= 0.0, gamma correction is ignored and linear color space is
493 * used.
494 */
495
496 SVGA3D_RS_OUTPUTGAMMA = 65, /* float */
497 SVGA3D_RS_ZVISIBLE = 66, /* SVGA3dBool */
498 SVGA3D_RS_LASTPIXEL = 67, /* SVGA3dBool */
499 SVGA3D_RS_CLIPPING = 68, /* SVGA3dBool */
500 SVGA3D_RS_WRAP0 = 69, /* SVGA3dWrapFlags */
501 SVGA3D_RS_WRAP1 = 70, /* SVGA3dWrapFlags */
502 SVGA3D_RS_WRAP2 = 71, /* SVGA3dWrapFlags */
503 SVGA3D_RS_WRAP3 = 72, /* SVGA3dWrapFlags */
504 SVGA3D_RS_WRAP4 = 73, /* SVGA3dWrapFlags */
505 SVGA3D_RS_WRAP5 = 74, /* SVGA3dWrapFlags */
506 SVGA3D_RS_WRAP6 = 75, /* SVGA3dWrapFlags */
507 SVGA3D_RS_WRAP7 = 76, /* SVGA3dWrapFlags */
508 SVGA3D_RS_WRAP8 = 77, /* SVGA3dWrapFlags */
509 SVGA3D_RS_WRAP9 = 78, /* SVGA3dWrapFlags */
510 SVGA3D_RS_WRAP10 = 79, /* SVGA3dWrapFlags */
511 SVGA3D_RS_WRAP11 = 80, /* SVGA3dWrapFlags */
512 SVGA3D_RS_WRAP12 = 81, /* SVGA3dWrapFlags */
513 SVGA3D_RS_WRAP13 = 82, /* SVGA3dWrapFlags */
514 SVGA3D_RS_WRAP14 = 83, /* SVGA3dWrapFlags */
515 SVGA3D_RS_WRAP15 = 84, /* SVGA3dWrapFlags */
516 SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */
517 SVGA3D_RS_MULTISAMPLEMASK = 86, /* uint32 */
518 SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */
519 SVGA3D_RS_TWEENFACTOR = 88, /* float */
520 SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */
521 SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */
522 SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */
523 SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */
524 SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */
525 SVGA3D_RS_SRCBLENDALPHA = 94, /* SVGA3dBlendOp */
526 SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */
527 SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
528 SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, /* SVGA3dTransparencyAntialiasType */
529 SVGA3D_RS_LINEAA = 98, /* SVGA3dBool */
530 SVGA3D_RS_LINEWIDTH = 99, /* float */
531 SVGA3D_RS_MAX
532} SVGA3dRenderStateName;
533
534typedef enum {
535 SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0,
536 SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1,
537 SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2,
538 SVGA3D_TRANSPARENCYANTIALIAS_MAX
539} SVGA3dTransparencyAntialiasType;
540
541typedef enum {
542 SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
543 SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
544 SVGA3D_VERTEXMATERIAL_SPECULAR = 2, /* Use the value in the specular component */
545} SVGA3dVertexMaterial;
546
547typedef enum {
548 SVGA3D_FILLMODE_INVALID = 0,
549 SVGA3D_FILLMODE_POINT = 1,
550 SVGA3D_FILLMODE_LINE = 2,
551 SVGA3D_FILLMODE_FILL = 3,
552 SVGA3D_FILLMODE_MAX
553} SVGA3dFillModeType;
554
555
556typedef
557union {
558 struct {
559 uint16 mode; /* SVGA3dFillModeType */
560 uint16 face; /* SVGA3dFace */
561 };
562 uint32 uintValue;
563} SVGA3dFillMode;
564
565typedef enum {
566 SVGA3D_SHADEMODE_INVALID = 0,
567 SVGA3D_SHADEMODE_FLAT = 1,
568 SVGA3D_SHADEMODE_SMOOTH = 2,
569 SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */
570 SVGA3D_SHADEMODE_MAX
571} SVGA3dShadeMode;
572
573typedef
574union {
575 struct {
576 uint16 repeat;
577 uint16 pattern;
578 };
579 uint32 uintValue;
580} SVGA3dLinePattern;
581
582typedef enum {
583 SVGA3D_BLENDOP_INVALID = 0,
584 SVGA3D_BLENDOP_ZERO = 1,
585 SVGA3D_BLENDOP_ONE = 2,
586 SVGA3D_BLENDOP_SRCCOLOR = 3,
587 SVGA3D_BLENDOP_INVSRCCOLOR = 4,
588 SVGA3D_BLENDOP_SRCALPHA = 5,
589 SVGA3D_BLENDOP_INVSRCALPHA = 6,
590 SVGA3D_BLENDOP_DESTALPHA = 7,
591 SVGA3D_BLENDOP_INVDESTALPHA = 8,
592 SVGA3D_BLENDOP_DESTCOLOR = 9,
593 SVGA3D_BLENDOP_INVDESTCOLOR = 10,
594 SVGA3D_BLENDOP_SRCALPHASAT = 11,
595 SVGA3D_BLENDOP_BLENDFACTOR = 12,
596 SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
597 SVGA3D_BLENDOP_MAX
598} SVGA3dBlendOp;
599
600typedef enum {
601 SVGA3D_BLENDEQ_INVALID = 0,
602 SVGA3D_BLENDEQ_ADD = 1,
603 SVGA3D_BLENDEQ_SUBTRACT = 2,
604 SVGA3D_BLENDEQ_REVSUBTRACT = 3,
605 SVGA3D_BLENDEQ_MINIMUM = 4,
606 SVGA3D_BLENDEQ_MAXIMUM = 5,
607 SVGA3D_BLENDEQ_MAX
608} SVGA3dBlendEquation;
609
610typedef enum {
611 SVGA3D_FRONTWINDING_INVALID = 0,
612 SVGA3D_FRONTWINDING_CW = 1,
613 SVGA3D_FRONTWINDING_CCW = 2,
614 SVGA3D_FRONTWINDING_MAX
615} SVGA3dFrontWinding;
616
617typedef enum {
618 SVGA3D_FACE_INVALID = 0,
619 SVGA3D_FACE_NONE = 1,
620 SVGA3D_FACE_FRONT = 2,
621 SVGA3D_FACE_BACK = 3,
622 SVGA3D_FACE_FRONT_BACK = 4,
623 SVGA3D_FACE_MAX
624} SVGA3dFace;
625
626/*
627 * The order and the values should not be changed
628 */
629
630typedef enum {
631 SVGA3D_CMP_INVALID = 0,
632 SVGA3D_CMP_NEVER = 1,
633 SVGA3D_CMP_LESS = 2,
634 SVGA3D_CMP_EQUAL = 3,
635 SVGA3D_CMP_LESSEQUAL = 4,
636 SVGA3D_CMP_GREATER = 5,
637 SVGA3D_CMP_NOTEQUAL = 6,
638 SVGA3D_CMP_GREATEREQUAL = 7,
639 SVGA3D_CMP_ALWAYS = 8,
640 SVGA3D_CMP_MAX
641} SVGA3dCmpFunc;
642
643/*
644 * SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
645 * the fog factor to be specified in the alpha component of the specular
646 * (a.k.a. secondary) vertex color.
647 */
648typedef enum {
649 SVGA3D_FOGFUNC_INVALID = 0,
650 SVGA3D_FOGFUNC_EXP = 1,
651 SVGA3D_FOGFUNC_EXP2 = 2,
652 SVGA3D_FOGFUNC_LINEAR = 3,
653 SVGA3D_FOGFUNC_PER_VERTEX = 4
654} SVGA3dFogFunction;
655
656/*
657 * SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
658 * or per-pixel basis.
659 */
660typedef enum {
661 SVGA3D_FOGTYPE_INVALID = 0,
662 SVGA3D_FOGTYPE_VERTEX = 1,
663 SVGA3D_FOGTYPE_PIXEL = 2,
664 SVGA3D_FOGTYPE_MAX = 3
665} SVGA3dFogType;
666
667/*
668 * SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
669 * computed using the eye Z value of each pixel (or vertex), whereas range-
670 * based fog is computed using the actual distance (range) to the eye.
671 */
672typedef enum {
673 SVGA3D_FOGBASE_INVALID = 0,
674 SVGA3D_FOGBASE_DEPTHBASED = 1,
675 SVGA3D_FOGBASE_RANGEBASED = 2,
676 SVGA3D_FOGBASE_MAX = 3
677} SVGA3dFogBase;
678
679typedef enum {
680 SVGA3D_STENCILOP_INVALID = 0,
681 SVGA3D_STENCILOP_KEEP = 1,
682 SVGA3D_STENCILOP_ZERO = 2,
683 SVGA3D_STENCILOP_REPLACE = 3,
684 SVGA3D_STENCILOP_INCRSAT = 4,
685 SVGA3D_STENCILOP_DECRSAT = 5,
686 SVGA3D_STENCILOP_INVERT = 6,
687 SVGA3D_STENCILOP_INCR = 7,
688 SVGA3D_STENCILOP_DECR = 8,
689 SVGA3D_STENCILOP_MAX
690} SVGA3dStencilOp;
691
692typedef enum {
693 SVGA3D_CLIPPLANE_0 = (1 << 0),
694 SVGA3D_CLIPPLANE_1 = (1 << 1),
695 SVGA3D_CLIPPLANE_2 = (1 << 2),
696 SVGA3D_CLIPPLANE_3 = (1 << 3),
697 SVGA3D_CLIPPLANE_4 = (1 << 4),
698 SVGA3D_CLIPPLANE_5 = (1 << 5),
699} SVGA3dClipPlanes;
700
701typedef enum {
702 SVGA3D_CLEAR_COLOR = 0x1,
703 SVGA3D_CLEAR_DEPTH = 0x2,
704 SVGA3D_CLEAR_STENCIL = 0x4
705} SVGA3dClearFlag;
706
707typedef enum {
708 SVGA3D_RT_DEPTH = 0,
709 SVGA3D_RT_STENCIL = 1,
710 SVGA3D_RT_COLOR0 = 2,
711 SVGA3D_RT_COLOR1 = 3,
712 SVGA3D_RT_COLOR2 = 4,
713 SVGA3D_RT_COLOR3 = 5,
714 SVGA3D_RT_COLOR4 = 6,
715 SVGA3D_RT_COLOR5 = 7,
716 SVGA3D_RT_COLOR6 = 8,
717 SVGA3D_RT_COLOR7 = 9,
718 SVGA3D_RT_MAX,
719 SVGA3D_RT_INVALID = ((uint32)-1),
720} SVGA3dRenderTargetType;
721
722#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
723
724typedef
725union {
726 struct {
727 uint32 red : 1;
728 uint32 green : 1;
729 uint32 blue : 1;
730 uint32 alpha : 1;
731 };
732 uint32 uintValue;
733} SVGA3dColorMask;
734
735typedef enum {
736 SVGA3D_VBLEND_DISABLE = 0,
737 SVGA3D_VBLEND_1WEIGHT = 1,
738 SVGA3D_VBLEND_2WEIGHT = 2,
739 SVGA3D_VBLEND_3WEIGHT = 3,
740} SVGA3dVertexBlendFlags;
741
742typedef enum {
743 SVGA3D_WRAPCOORD_0 = 1 << 0,
744 SVGA3D_WRAPCOORD_1 = 1 << 1,
745 SVGA3D_WRAPCOORD_2 = 1 << 2,
746 SVGA3D_WRAPCOORD_3 = 1 << 3,
747 SVGA3D_WRAPCOORD_ALL = 0xF,
748} SVGA3dWrapFlags;
749
750/*
751 * SVGA_3D_CMD_TEXTURESTATE Types. All value types
752 * must fit in a uint32.
753 */
754
755typedef enum {
756 SVGA3D_TS_INVALID = 0,
757 SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */
758 SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */
759 SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
760 SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */
761 SVGA3D_TS_ALPHAOP = 5, /* SVGA3dTextureCombiner */
762 SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */
763 SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */
764 SVGA3D_TS_ADDRESSU = 8, /* SVGA3dTextureAddress */
765 SVGA3D_TS_ADDRESSV = 9, /* SVGA3dTextureAddress */
766 SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */
767 SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */
768 SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */
769 SVGA3D_TS_BORDERCOLOR = 13, /* SVGA3dColor */
770 SVGA3D_TS_TEXCOORDINDEX = 14, /* uint32 */
771 SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */
772 SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */
773 SVGA3D_TS_BUMPENVMAT00 = 17, /* float */
774 SVGA3D_TS_BUMPENVMAT01 = 18, /* float */
775 SVGA3D_TS_BUMPENVMAT10 = 19, /* float */
776 SVGA3D_TS_BUMPENVMAT11 = 20, /* float */
777 SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32 */
778 SVGA3D_TS_TEXTURE_LOD_BIAS = 22, /* float */
779 SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32 */
780 SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */
781
782
783 /*
784 * Sampler Gamma Level
785 *
786 * Sampler gamma effects the color of samples taken from the sampler. A
787 * value of 1.0 will produce linear samples. If the value is <= 0.0 the
788 * gamma value is ignored and a linear space is used.
789 */
790
791 SVGA3D_TS_GAMMA = 25, /* float */
792 SVGA3D_TS_BUMPENVLSCALE = 26, /* float */
793 SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */
794 SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
795 SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
796 SVGA3D_TS_MAX
797} SVGA3dTextureStateName;
798
799typedef enum {
800 SVGA3D_TC_INVALID = 0,
801 SVGA3D_TC_DISABLE = 1,
802 SVGA3D_TC_SELECTARG1 = 2,
803 SVGA3D_TC_SELECTARG2 = 3,
804 SVGA3D_TC_MODULATE = 4,
805 SVGA3D_TC_ADD = 5,
806 SVGA3D_TC_ADDSIGNED = 6,
807 SVGA3D_TC_SUBTRACT = 7,
808 SVGA3D_TC_BLENDTEXTUREALPHA = 8,
809 SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
810 SVGA3D_TC_BLENDCURRENTALPHA = 10,
811 SVGA3D_TC_BLENDFACTORALPHA = 11,
812 SVGA3D_TC_MODULATE2X = 12,
813 SVGA3D_TC_MODULATE4X = 13,
814 SVGA3D_TC_DSDT = 14,
815 SVGA3D_TC_DOTPRODUCT3 = 15,
816 SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
817 SVGA3D_TC_ADDSIGNED2X = 17,
818 SVGA3D_TC_ADDSMOOTH = 18,
819 SVGA3D_TC_PREMODULATE = 19,
820 SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
821 SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
822 SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
823 SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
824 SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
825 SVGA3D_TC_MULTIPLYADD = 25,
826 SVGA3D_TC_LERP = 26,
827 SVGA3D_TC_MAX
828} SVGA3dTextureCombiner;
829
830#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
831
832typedef enum {
833 SVGA3D_TEX_ADDRESS_INVALID = 0,
834 SVGA3D_TEX_ADDRESS_WRAP = 1,
835 SVGA3D_TEX_ADDRESS_MIRROR = 2,
836 SVGA3D_TEX_ADDRESS_CLAMP = 3,
837 SVGA3D_TEX_ADDRESS_BORDER = 4,
838 SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
839 SVGA3D_TEX_ADDRESS_EDGE = 6,
840 SVGA3D_TEX_ADDRESS_MAX
841} SVGA3dTextureAddress;
842
843/*
844 * SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
845 * disabled, and the rasterizer should use the magnification filter instead.
846 */
847typedef enum {
848 SVGA3D_TEX_FILTER_NONE = 0,
849 SVGA3D_TEX_FILTER_NEAREST = 1,
850 SVGA3D_TEX_FILTER_LINEAR = 2,
851 SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
852 SVGA3D_TEX_FILTER_FLATCUBIC = 4, /* Deprecated, not implemented */
853 SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, /* Deprecated, not implemented */
854 SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, /* Not currently implemented */
855 SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, /* Not currently implemented */
856 SVGA3D_TEX_FILTER_MAX
857} SVGA3dTextureFilter;
858
859typedef enum {
860 SVGA3D_TEX_TRANSFORM_OFF = 0,
861 SVGA3D_TEX_TRANSFORM_S = (1 << 0),
862 SVGA3D_TEX_TRANSFORM_T = (1 << 1),
863 SVGA3D_TEX_TRANSFORM_R = (1 << 2),
864 SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
865 SVGA3D_TEX_PROJECTED = (1 << 15),
866} SVGA3dTexTransformFlags;
867
868typedef enum {
869 SVGA3D_TEXCOORD_GEN_OFF = 0,
870 SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
871 SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
872 SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
873 SVGA3D_TEXCOORD_GEN_SPHERE = 4,
874 SVGA3D_TEXCOORD_GEN_MAX
875} SVGA3dTextureCoordGen;
876
877/*
878 * Texture argument constants for texture combiner
879 */
880typedef enum {
881 SVGA3D_TA_INVALID = 0,
882 SVGA3D_TA_CONSTANT = 1,
883 SVGA3D_TA_PREVIOUS = 2,
884 SVGA3D_TA_DIFFUSE = 3,
885 SVGA3D_TA_TEXTURE = 4,
886 SVGA3D_TA_SPECULAR = 5,
887 SVGA3D_TA_MAX
888} SVGA3dTextureArgData;
889
890#define SVGA3D_TM_MASK_LEN 4
891
892/* Modifiers for texture argument constants defined above. */
893typedef enum {
894 SVGA3D_TM_NONE = 0,
895 SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
896 SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN),
897} SVGA3dTextureArgModifier;
898
899#define SVGA3D_INVALID_ID ((uint32)-1)
900#define SVGA3D_MAX_CLIP_PLANES 6
901
902/*
903 * This is the limit to the number of fixed-function texture
904 * transforms and texture coordinates we can support. It does *not*
905 * correspond to the number of texture image units (samplers) we
906 * support!
907 */
908#define SVGA3D_MAX_TEXTURE_COORDS 8
909
910/*
911 * Vertex declarations
912 *
913 * Notes:
914 *
915 * SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
916 * draw with any POSITIONT vertex arrays, the programmable vertex
917 * pipeline will be implicitly disabled. Drawing will take place as if
918 * no vertex shader was bound.
919 */
920
921typedef enum {
922 SVGA3D_DECLUSAGE_POSITION = 0,
923 SVGA3D_DECLUSAGE_BLENDWEIGHT, /* 1 */
924 SVGA3D_DECLUSAGE_BLENDINDICES, /* 2 */
925 SVGA3D_DECLUSAGE_NORMAL, /* 3 */
926 SVGA3D_DECLUSAGE_PSIZE, /* 4 */
927 SVGA3D_DECLUSAGE_TEXCOORD, /* 5 */
928 SVGA3D_DECLUSAGE_TANGENT, /* 6 */
929 SVGA3D_DECLUSAGE_BINORMAL, /* 7 */
930 SVGA3D_DECLUSAGE_TESSFACTOR, /* 8 */
931 SVGA3D_DECLUSAGE_POSITIONT, /* 9 */
932 SVGA3D_DECLUSAGE_COLOR, /* 10 */
933 SVGA3D_DECLUSAGE_FOG, /* 11 */
934 SVGA3D_DECLUSAGE_DEPTH, /* 12 */
935 SVGA3D_DECLUSAGE_SAMPLE, /* 13 */
936 SVGA3D_DECLUSAGE_MAX
937} SVGA3dDeclUsage;
938
939typedef enum {
940 SVGA3D_DECLMETHOD_DEFAULT = 0,
941 SVGA3D_DECLMETHOD_PARTIALU,
942 SVGA3D_DECLMETHOD_PARTIALV,
943 SVGA3D_DECLMETHOD_CROSSUV, /* Normal */
944 SVGA3D_DECLMETHOD_UV,
945 SVGA3D_DECLMETHOD_LOOKUP, /* Lookup a displacement map */
946 SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED, /* Lookup a pre-sampled displacement map */
947} SVGA3dDeclMethod;
948
949typedef enum {
950 SVGA3D_DECLTYPE_FLOAT1 = 0,
951 SVGA3D_DECLTYPE_FLOAT2 = 1,
952 SVGA3D_DECLTYPE_FLOAT3 = 2,
953 SVGA3D_DECLTYPE_FLOAT4 = 3,
954 SVGA3D_DECLTYPE_D3DCOLOR = 4,
955 SVGA3D_DECLTYPE_UBYTE4 = 5,
956 SVGA3D_DECLTYPE_SHORT2 = 6,
957 SVGA3D_DECLTYPE_SHORT4 = 7,
958 SVGA3D_DECLTYPE_UBYTE4N = 8,
959 SVGA3D_DECLTYPE_SHORT2N = 9,
960 SVGA3D_DECLTYPE_SHORT4N = 10,
961 SVGA3D_DECLTYPE_USHORT2N = 11,
962 SVGA3D_DECLTYPE_USHORT4N = 12,
963 SVGA3D_DECLTYPE_UDEC3 = 13,
964 SVGA3D_DECLTYPE_DEC3N = 14,
965 SVGA3D_DECLTYPE_FLOAT16_2 = 15,
966 SVGA3D_DECLTYPE_FLOAT16_4 = 16,
967 SVGA3D_DECLTYPE_MAX,
968} SVGA3dDeclType;
969
970/*
971 * This structure is used for the divisor for geometry instancing;
972 * it's a direct translation of the Direct3D equivalent.
973 */
974typedef union {
975 struct {
976 /*
977 * For index data, this number represents the number of instances to draw.
978 * For instance data, this number represents the number of
979 * instances/vertex in this stream
980 */
981 uint32 count : 30;
982
983 /*
984 * This is 1 if this is supposed to be the data that is repeated for
985 * every instance.
986 */
987 uint32 indexedData : 1;
988
989 /*
990 * This is 1 if this is supposed to be the per-instance data.
991 */
992 uint32 instanceData : 1;
993 };
994
995 uint32 value;
996} SVGA3dVertexDivisor;
997
998typedef enum {
999 SVGA3D_PRIMITIVE_INVALID = 0,
1000 SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
1001 SVGA3D_PRIMITIVE_POINTLIST = 2,
1002 SVGA3D_PRIMITIVE_LINELIST = 3,
1003 SVGA3D_PRIMITIVE_LINESTRIP = 4,
1004 SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
1005 SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
1006 SVGA3D_PRIMITIVE_MAX
1007} SVGA3dPrimitiveType;
1008
1009typedef enum {
1010 SVGA3D_COORDINATE_INVALID = 0,
1011 SVGA3D_COORDINATE_LEFTHANDED = 1,
1012 SVGA3D_COORDINATE_RIGHTHANDED = 2,
1013 SVGA3D_COORDINATE_MAX
1014} SVGA3dCoordinateType;
1015
1016typedef enum {
1017 SVGA3D_TRANSFORM_INVALID = 0,
1018 SVGA3D_TRANSFORM_WORLD = 1,
1019 SVGA3D_TRANSFORM_VIEW = 2,
1020 SVGA3D_TRANSFORM_PROJECTION = 3,
1021 SVGA3D_TRANSFORM_TEXTURE0 = 4,
1022 SVGA3D_TRANSFORM_TEXTURE1 = 5,
1023 SVGA3D_TRANSFORM_TEXTURE2 = 6,
1024 SVGA3D_TRANSFORM_TEXTURE3 = 7,
1025 SVGA3D_TRANSFORM_TEXTURE4 = 8,
1026 SVGA3D_TRANSFORM_TEXTURE5 = 9,
1027 SVGA3D_TRANSFORM_TEXTURE6 = 10,
1028 SVGA3D_TRANSFORM_TEXTURE7 = 11,
1029 SVGA3D_TRANSFORM_WORLD1 = 12,
1030 SVGA3D_TRANSFORM_WORLD2 = 13,
1031 SVGA3D_TRANSFORM_WORLD3 = 14,
1032 SVGA3D_TRANSFORM_MAX
1033} SVGA3dTransformType;
1034
1035typedef enum {
1036 SVGA3D_LIGHTTYPE_INVALID = 0,
1037 SVGA3D_LIGHTTYPE_POINT = 1,
1038 SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
1039 SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
1040 SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
1041 SVGA3D_LIGHTTYPE_MAX
1042} SVGA3dLightType;
1043
1044typedef enum {
1045 SVGA3D_CUBEFACE_POSX = 0,
1046 SVGA3D_CUBEFACE_NEGX = 1,
1047 SVGA3D_CUBEFACE_POSY = 2,
1048 SVGA3D_CUBEFACE_NEGY = 3,
1049 SVGA3D_CUBEFACE_POSZ = 4,
1050 SVGA3D_CUBEFACE_NEGZ = 5,
1051} SVGA3dCubeFace;
1052
1053typedef enum {
1054 SVGA3D_SHADERTYPE_INVALID = 0,
1055 SVGA3D_SHADERTYPE_MIN = 1,
1056 SVGA3D_SHADERTYPE_VS = 1,
1057 SVGA3D_SHADERTYPE_PS = 2,
1058 SVGA3D_SHADERTYPE_MAX = 3,
1059 SVGA3D_SHADERTYPE_GS = 3,
1060} SVGA3dShaderType;
1061
1062#define SVGA3D_NUM_SHADERTYPE (SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN)
1063
1064typedef enum {
1065 SVGA3D_CONST_TYPE_FLOAT = 0,
1066 SVGA3D_CONST_TYPE_INT = 1,
1067 SVGA3D_CONST_TYPE_BOOL = 2,
1068 SVGA3D_CONST_TYPE_MAX
1069} SVGA3dShaderConstType;
1070
1071#define SVGA3D_MAX_SURFACE_FACES 6
1072
1073typedef enum {
1074 SVGA3D_STRETCH_BLT_POINT = 0,
1075 SVGA3D_STRETCH_BLT_LINEAR = 1,
1076 SVGA3D_STRETCH_BLT_MAX
1077} SVGA3dStretchBltMode;
1078
1079typedef enum {
1080 SVGA3D_QUERYTYPE_OCCLUSION = 0,
1081 SVGA3D_QUERYTYPE_MAX
1082} SVGA3dQueryType;
1083
1084typedef enum {
1085 SVGA3D_QUERYSTATE_PENDING = 0, /* Waiting on the host (set by guest) */
1086 SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully (set by host) */
1087 SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully (set by host) */
1088 SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (For guest use only) */
1089} SVGA3dQueryState;
1090
1091typedef enum {
1092 SVGA3D_WRITE_HOST_VRAM = 1,
1093 SVGA3D_READ_HOST_VRAM = 2,
1094} SVGA3dTransferType;
1095
1096/*
1097 * The maximum number of vertex arrays we're guaranteed to support in
1098 * SVGA_3D_CMD_DRAWPRIMITIVES.
1099 */
1100#define SVGA3D_MAX_VERTEX_ARRAYS 32
1101
1102/*
1103 * The maximum number of primitive ranges we're guaranteed to support
1104 * in SVGA_3D_CMD_DRAWPRIMITIVES.
1105 */
1106#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
1107
1108/*
1109 * Identifiers for commands in the command FIFO.
1110 *
1111 * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
1112 * the SVGA3D protocol and remain reserved; they should not be used in the
1113 * future.
1114 *
1115 * IDs between 1040 and 1999 (inclusive) are available for use by the
1116 * current SVGA3D protocol.
1117 *
1118 * FIFO clients other than SVGA3D should stay below 1000, or at 2000
1119 * and up.
1120 */
1121
1122#define SVGA_3D_CMD_LEGACY_BASE 1000
1123#define SVGA_3D_CMD_BASE 1040
1124
1125#define SVGA_3D_CMD_SURFACE_DEFINE SVGA_3D_CMD_BASE + 0 /* Deprecated */
1126#define SVGA_3D_CMD_SURFACE_DESTROY SVGA_3D_CMD_BASE + 1
1127#define SVGA_3D_CMD_SURFACE_COPY SVGA_3D_CMD_BASE + 2
1128#define SVGA_3D_CMD_SURFACE_STRETCHBLT SVGA_3D_CMD_BASE + 3
1129#define SVGA_3D_CMD_SURFACE_DMA SVGA_3D_CMD_BASE + 4
1130#define SVGA_3D_CMD_CONTEXT_DEFINE SVGA_3D_CMD_BASE + 5
1131#define SVGA_3D_CMD_CONTEXT_DESTROY SVGA_3D_CMD_BASE + 6
1132#define SVGA_3D_CMD_SETTRANSFORM SVGA_3D_CMD_BASE + 7
1133#define SVGA_3D_CMD_SETZRANGE SVGA_3D_CMD_BASE + 8
1134#define SVGA_3D_CMD_SETRENDERSTATE SVGA_3D_CMD_BASE + 9
1135#define SVGA_3D_CMD_SETRENDERTARGET SVGA_3D_CMD_BASE + 10
1136#define SVGA_3D_CMD_SETTEXTURESTATE SVGA_3D_CMD_BASE + 11
1137#define SVGA_3D_CMD_SETMATERIAL SVGA_3D_CMD_BASE + 12
1138#define SVGA_3D_CMD_SETLIGHTDATA SVGA_3D_CMD_BASE + 13
1139#define SVGA_3D_CMD_SETLIGHTENABLED SVGA_3D_CMD_BASE + 14
1140#define SVGA_3D_CMD_SETVIEWPORT SVGA_3D_CMD_BASE + 15
1141#define SVGA_3D_CMD_SETCLIPPLANE SVGA_3D_CMD_BASE + 16
1142#define SVGA_3D_CMD_CLEAR SVGA_3D_CMD_BASE + 17
1143#define SVGA_3D_CMD_PRESENT SVGA_3D_CMD_BASE + 18 /* Deprecated */
1144#define SVGA_3D_CMD_SHADER_DEFINE SVGA_3D_CMD_BASE + 19
1145#define SVGA_3D_CMD_SHADER_DESTROY SVGA_3D_CMD_BASE + 20
1146#define SVGA_3D_CMD_SET_SHADER SVGA_3D_CMD_BASE + 21
1147#define SVGA_3D_CMD_SET_SHADER_CONST SVGA_3D_CMD_BASE + 22
1148#define SVGA_3D_CMD_DRAW_PRIMITIVES SVGA_3D_CMD_BASE + 23
1149#define SVGA_3D_CMD_SETSCISSORRECT SVGA_3D_CMD_BASE + 24
1150#define SVGA_3D_CMD_BEGIN_QUERY SVGA_3D_CMD_BASE + 25
1151#define SVGA_3D_CMD_END_QUERY SVGA_3D_CMD_BASE + 26
1152#define SVGA_3D_CMD_WAIT_FOR_QUERY SVGA_3D_CMD_BASE + 27
1153#define SVGA_3D_CMD_PRESENT_READBACK SVGA_3D_CMD_BASE + 28 /* Deprecated */
1154#define SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN SVGA_3D_CMD_BASE + 29
1155#define SVGA_3D_CMD_SURFACE_DEFINE_V2 SVGA_3D_CMD_BASE + 30
1156#define SVGA_3D_CMD_GENERATE_MIPMAPS SVGA_3D_CMD_BASE + 31
1157#define SVGA_3D_CMD_ACTIVATE_SURFACE SVGA_3D_CMD_BASE + 40
1158#define SVGA_3D_CMD_DEACTIVATE_SURFACE SVGA_3D_CMD_BASE + 41
1159#define SVGA_3D_CMD_SCREEN_DMA 1082
1160#define SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE 1083
1161#define SVGA_3D_CMD_OPEN_CONTEXT_SURFACE 1084
1162
1163#define SVGA_3D_CMD_LOGICOPS_BITBLT 1085
1164#define SVGA_3D_CMD_LOGICOPS_TRANSBLT 1086
1165#define SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1087
1166#define SVGA_3D_CMD_LOGICOPS_COLORFILL 1088
1167#define SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1089
1168#define SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1090
1169
1170#define SVGA_3D_CMD_SET_OTABLE_BASE 1091
1171#define SVGA_3D_CMD_READBACK_OTABLE 1092
1172
1173#define SVGA_3D_CMD_DEFINE_GB_MOB 1093
1174#define SVGA_3D_CMD_DESTROY_GB_MOB 1094
1175#define SVGA_3D_CMD_REDEFINE_GB_MOB 1095
1176#define SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING 1096
1177
1178#define SVGA_3D_CMD_DEFINE_GB_SURFACE 1097
1179#define SVGA_3D_CMD_DESTROY_GB_SURFACE 1098
1180#define SVGA_3D_CMD_BIND_GB_SURFACE 1099
1181#define SVGA_3D_CMD_COND_BIND_GB_SURFACE 1100
1182#define SVGA_3D_CMD_UPDATE_GB_IMAGE 1101
1183#define SVGA_3D_CMD_UPDATE_GB_SURFACE 1102
1184#define SVGA_3D_CMD_READBACK_GB_IMAGE 1103
1185#define SVGA_3D_CMD_READBACK_GB_SURFACE 1104
1186#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105
1187#define SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106
1188
1189#define SVGA_3D_CMD_DEFINE_GB_CONTEXT 1107
1190#define SVGA_3D_CMD_DESTROY_GB_CONTEXT 1108
1191#define SVGA_3D_CMD_BIND_GB_CONTEXT 1109
1192#define SVGA_3D_CMD_READBACK_GB_CONTEXT 1110
1193#define SVGA_3D_CMD_INVALIDATE_GB_CONTEXT 1111
1194
1195#define SVGA_3D_CMD_DEFINE_GB_SHADER 1112
1196#define SVGA_3D_CMD_DESTROY_GB_SHADER 1113
1197#define SVGA_3D_CMD_BIND_GB_SHADER 1114
1198
1199#define SVGA_3D_CMD_SET_OTABLE_BASE64 1115
1200
1201#define SVGA_3D_CMD_BEGIN_GB_QUERY 1116
1202#define SVGA_3D_CMD_END_GB_QUERY 1117
1203#define SVGA_3D_CMD_WAIT_FOR_GB_QUERY 1118
1204
1205#define SVGA_3D_CMD_NOP 1119
1206
1207#define SVGA_3D_CMD_ENABLE_GART 1120
1208#define SVGA_3D_CMD_DISABLE_GART 1121
1209#define SVGA_3D_CMD_MAP_MOB_INTO_GART 1122
1210#define SVGA_3D_CMD_UNMAP_GART_RANGE 1123
1211
1212#define SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124
1213#define SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125
1214#define SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126
1215#define SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127
1216
1217#define SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL 1128
1218#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL 1129
1219
1220#define SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE 1130
1221#define SVGA_3D_CMD_GB_SCREEN_DMA 1131
1222#define SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH 1132
1223#define SVGA_3D_CMD_GB_MOB_FENCE 1133
1224#define SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134
1225#define SVGA_3D_CMD_DEFINE_GB_MOB64 1135
1226#define SVGA_3D_CMD_REDEFINE_GB_MOB64 1136
1227#define SVGA_3D_CMD_NOP_ERROR 1137
1228
1229#define SVGA_3D_CMD_RESERVED1 1138
1230#define SVGA_3D_CMD_RESERVED2 1139
1231#define SVGA_3D_CMD_RESERVED3 1140
1232#define SVGA_3D_CMD_RESERVED4 1141
1233#define SVGA_3D_CMD_RESERVED5 1142
1234
1235#define SVGA_3D_CMD_MAX 1142
1236#define SVGA_3D_CMD_FUTURE_MAX 3000
1237
1238/*
1239 * Common substructures used in multiple FIFO commands:
1240 */
1241
1242typedef struct {
1243 union {
1244 struct {
1245 uint16 function; /* SVGA3dFogFunction */
1246 uint8 type; /* SVGA3dFogType */
1247 uint8 base; /* SVGA3dFogBase */
1248 };
1249 uint32 uintValue;
1250 };
1251} SVGA3dFogMode;
1252
1253/*
1254 * Uniquely identify one image (a 1D/2D/3D array) from a surface. This
1255 * is a surface ID as well as face/mipmap indices.
1256 */
1257
1258typedef
1259struct SVGA3dSurfaceImageId {
1260 uint32 sid;
1261 uint32 face;
1262 uint32 mipmap;
1263} SVGA3dSurfaceImageId;
1264
1265typedef
1266struct SVGA3dGuestImage {
1267 SVGAGuestPtr ptr;
1268
1269 /*
1270 * A note on interpretation of pitch: This value of pitch is the
1271 * number of bytes between vertically adjacent image
1272 * blocks. Normally this is the number of bytes between the first
1273 * pixel of two adjacent scanlines. With compressed textures,
1274 * however, this may represent the number of bytes between
1275 * compression blocks rather than between rows of pixels.
1276 *
1277 * XXX: Compressed textures currently must be tightly packed in guest memory.
1278 *
1279 * If the image is 1-dimensional, pitch is ignored.
1280 *
1281 * If 'pitch' is zero, the SVGA3D device calculates a pitch value
1282 * assuming each row of blocks is tightly packed.
1283 */
1284 uint32 pitch;
1285} SVGA3dGuestImage;
1286
1287
1288/*
1289 * FIFO command format definitions:
1290 */
1291
1292/*
1293 * The data size header following cmdNum for every 3d command
1294 */
1295typedef
1296struct {
1297 uint32 id;
1298 uint32 size;
1299} SVGA3dCmdHeader;
1300
1301/*
1302 * A surface is a hierarchy of host VRAM surfaces: 1D, 2D, or 3D, with
1303 * optional mipmaps and cube faces.
1304 */
1305
1306typedef
1307struct {
1308 uint32 width;
1309 uint32 height;
1310 uint32 depth;
1311} SVGA3dSize;
1312
1313typedef enum {
1314 SVGA3D_SURFACE_CUBEMAP = (1 << 0),
1315
1316 /*
1317 * HINT flags are not enforced by the device but are useful for
1318 * performance.
1319 */
1320 SVGA3D_SURFACE_HINT_STATIC = (1 << 1),
1321 SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2),
1322 SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3),
1323 SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4),
1324 SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5),
1325 SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6),
1326 SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7),
1327 SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8),
1328 SVGA3D_SURFACE_MASKABLE_ANTIALIAS = (1 << 9),
1329 SVGA3D_SURFACE_AUTOGENMIPMAPS = (1 << 10),
1330 SVGA3D_SURFACE_DECODE_RENDERTARGET = (1 << 11),
1331
1332 /*
1333 * Is this surface using a base-level pitch for it's mob backing?
1334 *
1335 * This flag is not intended to be set by guest-drivers, but is instead
1336 * set by the device when the surface is bound to a mob with a specified
1337 * pitch.
1338 */
1339 SVGA3D_SURFACE_MOB_PITCH = (1 << 12),
1340
1341 SVGA3D_SURFACE_INACTIVE = (1 << 13),
1342 SVGA3D_SURFACE_HINT_RT_LOCKABLE = (1 << 14),
1343 SVGA3D_SURFACE_VOLUME = (1 << 15),
1344
1345 /*
1346 * Required to be set on a surface to bind it to a screen target.
1347 */
1348 SVGA3D_SURFACE_SCREENTARGET = (1 << 16),
1349
1350 /*
1351 * Align images in the guest-backing mob to 16-bytes.
1352 */
1353 SVGA3D_SURFACE_ALIGN16 = (1 << 17),
1354
1355 SVGA3D_SURFACE_1D = (1 << 18),
1356 SVGA3D_SURFACE_ARRAY = (1 << 19),
1357
1358 /*
1359 * Bind flags.
1360 * These are enforced for any surface defined with DefineGBSurface_v2.
1361 */
1362 SVGA3D_SURFACE_BIND_VERTEX_BUFFER = (1 << 20),
1363 SVGA3D_SURFACE_BIND_INDEX_BUFFER = (1 << 21),
1364 SVGA3D_SURFACE_BIND_CONSTANT_BUFFER = (1 << 22),
1365 SVGA3D_SURFACE_BIND_SHADER_RESOURCE = (1 << 23),
1366 SVGA3D_SURFACE_BIND_RENDER_TARGET = (1 << 24),
1367 SVGA3D_SURFACE_BIND_DEPTH_STENCIL = (1 << 25),
1368 SVGA3D_SURFACE_BIND_STREAM_OUTPUT = (1 << 26),
1369
1370 /*
1371 * Marker for the last defined bit.
1372 */
1373 SVGA3D_SURFACE_FLAG_MAX = (1 << 27),
1374} SVGA3dSurfaceFlags;
1375
1376typedef
1377struct {
1378 uint32 numMipLevels;
1379} SVGA3dSurfaceFace;
1380
1381typedef
1382struct {
1383 uint32 sid;
1384 SVGA3dSurfaceFlags surfaceFlags;
1385 SVGA3dSurfaceFormat format;
1386 /*
1387 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
1388 * structures must have the same value of numMipLevels field.
1389 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
1390 * numMipLevels set to 0.
1391 */
1392 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
1393 /*
1394 * Followed by an SVGA3dSize structure for each mip level in each face.
1395 *
1396 * A note on surface sizes: Sizes are always specified in pixels,
1397 * even if the true surface size is not a multiple of the minimum
1398 * block size of the surface's format. For example, a 3x3x1 DXT1
1399 * compressed texture would actually be stored as a 4x4x1 image in
1400 * memory.
1401 */
1402} SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
1403
1404typedef
1405struct {
1406 uint32 sid;
1407 SVGA3dSurfaceFlags surfaceFlags;
1408 SVGA3dSurfaceFormat format;
1409 /*
1410 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
1411 * structures must have the same value of numMipLevels field.
1412 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
1413 * numMipLevels set to 0.
1414 */
1415 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
1416 uint32 multisampleCount;
1417 SVGA3dTextureFilter autogenFilter;
1418 /*
1419 * Followed by an SVGA3dSize structure for each mip level in each face.
1420 *
1421 * A note on surface sizes: Sizes are always specified in pixels,
1422 * even if the true surface size is not a multiple of the minimum
1423 * block size of the surface's format. For example, a 3x3x1 DXT1
1424 * compressed texture would actually be stored as a 4x4x1 image in
1425 * memory.
1426 */
1427} SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
1428
1429typedef
1430struct {
1431 uint32 sid;
1432} SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
1433
1434typedef
1435struct {
1436 uint32 cid;
1437} SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
1438
1439typedef
1440struct {
1441 uint32 cid;
1442} SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
1443
1444typedef
1445struct {
1446 uint32 cid;
1447 SVGA3dClearFlag clearFlag;
1448 uint32 color;
1449 float depth;
1450 uint32 stencil;
1451 /* Followed by variable number of SVGA3dRect structures */
1452} SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
1453
1454typedef
1455struct SVGA3dCopyRect {
1456 uint32 x;
1457 uint32 y;
1458 uint32 w;
1459 uint32 h;
1460 uint32 srcx;
1461 uint32 srcy;
1462} SVGA3dCopyRect;
1463
1464typedef
1465struct SVGA3dCopyBox {
1466 uint32 x;
1467 uint32 y;
1468 uint32 z;
1469 uint32 w;
1470 uint32 h;
1471 uint32 d;
1472 uint32 srcx;
1473 uint32 srcy;
1474 uint32 srcz;
1475} SVGA3dCopyBox;
1476
1477typedef
1478struct {
1479 uint32 x;
1480 uint32 y;
1481 uint32 w;
1482 uint32 h;
1483} SVGA3dRect;
1484
1485typedef
1486struct {
1487 uint32 x;
1488 uint32 y;
1489 uint32 z;
1490 uint32 w;
1491 uint32 h;
1492 uint32 d;
1493} SVGA3dBox;
1494
1495typedef
1496struct {
1497 uint32 x;
1498 uint32 y;
1499 uint32 z;
1500} SVGA3dPoint;
1501
1502typedef
1503struct {
1504 SVGA3dLightType type;
1505 SVGA3dBool inWorldSpace;
1506 float diffuse[4];
1507 float specular[4];
1508 float ambient[4];
1509 float position[4];
1510 float direction[4];
1511 float range;
1512 float falloff;
1513 float attenuation0;
1514 float attenuation1;
1515 float attenuation2;
1516 float theta;
1517 float phi;
1518} SVGA3dLightData;
1519
1520typedef
1521struct {
1522 uint32 sid;
1523 /* Followed by variable number of SVGA3dCopyRect structures */
1524} SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
1525
1526typedef
1527struct {
1528 SVGA3dRenderStateName state;
1529 union {
1530 uint32 uintValue;
1531 float floatValue;
1532 };
1533} SVGA3dRenderState;
1534
1535typedef
1536struct {
1537 uint32 cid;
1538 /* Followed by variable number of SVGA3dRenderState structures */
1539} SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
1540
1541typedef
1542struct {
1543 uint32 cid;
1544 SVGA3dRenderTargetType type;
1545 SVGA3dSurfaceImageId target;
1546} SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
1547
1548typedef
1549struct {
1550 SVGA3dSurfaceImageId src;
1551 SVGA3dSurfaceImageId dest;
1552 /* Followed by variable number of SVGA3dCopyBox structures */
1553} SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
1554
1555typedef
1556struct {
1557 SVGA3dSurfaceImageId src;
1558 SVGA3dSurfaceImageId dest;
1559 SVGA3dBox boxSrc;
1560 SVGA3dBox boxDest;
1561 SVGA3dStretchBltMode mode;
1562} SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
1563
1564typedef
1565struct {
1566 /*
1567 * If the discard flag is present in a surface DMA operation, the host may
1568 * discard the contents of the current mipmap level and face of the target
1569 * surface before applying the surface DMA contents.
1570 */
1571 uint32 discard : 1;
1572
1573 /*
1574 * If the unsynchronized flag is present, the host may perform this upload
1575 * without syncing to pending reads on this surface.
1576 */
1577 uint32 unsynchronized : 1;
1578
1579 /*
1580 * Guests *MUST* set the reserved bits to 0 before submitting the command
1581 * suffix as future flags may occupy these bits.
1582 */
1583 uint32 reserved : 30;
1584} SVGA3dSurfaceDMAFlags;
1585
1586typedef
1587struct {
1588 SVGA3dGuestImage guest;
1589 SVGA3dSurfaceImageId host;
1590 SVGA3dTransferType transfer;
1591 /*
1592 * Followed by variable number of SVGA3dCopyBox structures. For consistency
1593 * in all clipping logic and coordinate translation, we define the
1594 * "source" in each copyBox as the guest image and the
1595 * "destination" as the host image, regardless of transfer
1596 * direction.
1597 *
1598 * For efficiency, the SVGA3D device is free to copy more data than
1599 * specified. For example, it may round copy boxes outwards such
1600 * that they lie on particular alignment boundaries.
1601 */
1602} SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
1603
1604/*
1605 * SVGA3dCmdSurfaceDMASuffix --
1606 *
1607 * This is a command suffix that will appear after a SurfaceDMA command in
1608 * the FIFO. It contains some extra information that hosts may use to
1609 * optimize performance or protect the guest. This suffix exists to preserve
1610 * backwards compatibility while also allowing for new functionality to be
1611 * implemented.
1612 */
1613
1614typedef
1615struct {
1616 uint32 suffixSize;
1617
1618 /*
1619 * The maximum offset is used to determine the maximum offset from the
1620 * guestPtr base address that will be accessed or written to during this
1621 * surfaceDMA. If the suffix is supported, the host will respect this
1622 * boundary while performing surface DMAs.
1623 *
1624 * Defaults to MAX_UINT32
1625 */
1626 uint32 maximumOffset;
1627
1628 /*
1629 * A set of flags that describes optimizations that the host may perform
1630 * while performing this surface DMA operation. The guest should never rely
1631 * on behaviour that is different when these flags are set for correctness.
1632 *
1633 * Defaults to 0
1634 */
1635 SVGA3dSurfaceDMAFlags flags;
1636} SVGA3dCmdSurfaceDMASuffix;
1637
1638/*
1639 * SVGA_3D_CMD_DRAW_PRIMITIVES --
1640 *
1641 * This command is the SVGA3D device's generic drawing entry point.
1642 * It can draw multiple ranges of primitives, optionally using an
1643 * index buffer, using an arbitrary collection of vertex buffers.
1644 *
1645 * Each SVGA3dVertexDecl defines a distinct vertex array to bind
1646 * during this draw call. The declarations specify which surface
1647 * the vertex data lives in, what that vertex data is used for,
1648 * and how to interpret it.
1649 *
1650 * Each SVGA3dPrimitiveRange defines a collection of primitives
1651 * to render using the same vertex arrays. An index buffer is
1652 * optional.
1653 */
1654
1655typedef
1656struct {
1657 /*
1658 * A range hint is an optional specification for the range of indices
1659 * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
1660 * that the entire array will be used.
1661 *
1662 * These are only hints. The SVGA3D device may use them for
1663 * performance optimization if possible, but it's also allowed to
1664 * ignore these values.
1665 */
1666 uint32 first;
1667 uint32 last;
1668} SVGA3dArrayRangeHint;
1669
1670typedef
1671struct {
1672 /*
1673 * Define the origin and shape of a vertex or index array. Both
1674 * 'offset' and 'stride' are in bytes. The provided surface will be
1675 * reinterpreted as a flat array of bytes in the same format used
1676 * by surface DMA operations. To avoid unnecessary conversions, the
1677 * surface should be created with the SVGA3D_BUFFER format.
1678 *
1679 * Index 0 in the array starts 'offset' bytes into the surface.
1680 * Index 1 begins at byte 'offset + stride', etc. Array indices may
1681 * not be negative.
1682 */
1683 uint32 surfaceId;
1684 uint32 offset;
1685 uint32 stride;
1686} SVGA3dArray;
1687
1688typedef
1689struct {
1690 /*
1691 * Describe a vertex array's data type, and define how it is to be
1692 * used by the fixed function pipeline or the vertex shader. It
1693 * isn't useful to have two VertexDecls with the same
1694 * VertexArrayIdentity in one draw call.
1695 */
1696 SVGA3dDeclType type;
1697 SVGA3dDeclMethod method;
1698 SVGA3dDeclUsage usage;
1699 uint32 usageIndex;
1700} SVGA3dVertexArrayIdentity;
1701
1702typedef
1703struct {
1704 SVGA3dVertexArrayIdentity identity;
1705 SVGA3dArray array;
1706 SVGA3dArrayRangeHint rangeHint;
1707} SVGA3dVertexDecl;
1708
1709typedef
1710struct {
1711 /*
1712 * Define a group of primitives to render, from sequential indices.
1713 *
1714 * The value of 'primitiveType' and 'primitiveCount' imply the
1715 * total number of vertices that will be rendered.
1716 */
1717 SVGA3dPrimitiveType primType;
1718 uint32 primitiveCount;
1719
1720 /*
1721 * Optional index buffer. If indexArray.surfaceId is
1722 * SVGA3D_INVALID_ID, we render without an index buffer. Rendering
1723 * without an index buffer is identical to rendering with an index
1724 * buffer containing the sequence [0, 1, 2, 3, ...].
1725 *
1726 * If an index buffer is in use, indexWidth specifies the width in
1727 * bytes of each index value. It must be less than or equal to
1728 * indexArray.stride.
1729 *
1730 * (Currently, the SVGA3D device requires index buffers to be tightly
1731 * packed. In other words, indexWidth == indexArray.stride)
1732 */
1733 SVGA3dArray indexArray;
1734 uint32 indexWidth;
1735
1736 /*
1737 * Optional index bias. This number is added to all indices from
1738 * indexArray before they are used as vertex array indices. This
1739 * can be used in multiple ways:
1740 *
1741 * - When not using an indexArray, this bias can be used to
1742 * specify where in the vertex arrays to begin rendering.
1743 *
1744 * - A positive number here is equivalent to increasing the
1745 * offset in each vertex array.
1746 *
1747 * - A negative number can be used to render using a small
1748 * vertex array and an index buffer that contains large
1749 * values. This may be used by some applications that
1750 * crop a vertex buffer without modifying their index
1751 * buffer.
1752 *
1753 * Note that rendering with a negative bias value may be slower and
1754 * use more memory than rendering with a positive or zero bias.
1755 */
1756 int32 indexBias;
1757} SVGA3dPrimitiveRange;
1758
1759typedef
1760struct {
1761 uint32 cid;
1762 uint32 numVertexDecls;
1763 uint32 numRanges;
1764
1765 /*
1766 * There are two variable size arrays after the
1767 * SVGA3dCmdDrawPrimitives structure. In order,
1768 * they are:
1769 *
1770 * 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
1771 * SVGA3D_MAX_VERTEX_ARRAYS;
1772 * 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
1773 * SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
1774 * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
1775 * the frequency divisor for the corresponding vertex decl).
1776 */
1777} SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
1778
1779typedef
1780struct {
1781 uint32 stage;
1782 SVGA3dTextureStateName name;
1783 union {
1784 uint32 value;
1785 float floatValue;
1786 };
1787} SVGA3dTextureState;
1788
1789typedef
1790struct {
1791 uint32 cid;
1792 /* Followed by variable number of SVGA3dTextureState structures */
1793} SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
1794
1795typedef
1796struct {
1797 uint32 cid;
1798 SVGA3dTransformType type;
1799 float matrix[16];
1800} SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
1801
1802typedef
1803struct {
1804 float min;
1805 float max;
1806} SVGA3dZRange;
1807
1808typedef
1809struct {
1810 uint32 cid;
1811 SVGA3dZRange zRange;
1812} SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
1813
1814typedef
1815struct {
1816 float diffuse[4];
1817 float ambient[4];
1818 float specular[4];
1819 float emissive[4];
1820 float shininess;
1821} SVGA3dMaterial;
1822
1823typedef
1824struct {
1825 uint32 cid;
1826 SVGA3dFace face;
1827 SVGA3dMaterial material;
1828} SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
1829
1830typedef
1831struct {
1832 uint32 cid;
1833 uint32 index;
1834 SVGA3dLightData data;
1835} SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
1836
1837typedef
1838struct {
1839 uint32 cid;
1840 uint32 index;
1841 uint32 enabled;
1842} SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
1843
1844typedef
1845struct {
1846 uint32 cid;
1847 SVGA3dRect rect;
1848} SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
1849
1850typedef
1851struct {
1852 uint32 cid;
1853 SVGA3dRect rect;
1854} SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
1855
1856typedef
1857struct {
1858 uint32 cid;
1859 uint32 index;
1860 float plane[4];
1861} SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
1862
1863typedef
1864struct {
1865 uint32 cid;
1866 uint32 shid;
1867 SVGA3dShaderType type;
1868 /* Followed by variable number of DWORDs for shader bycode */
1869} SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
1870
1871typedef
1872struct {
1873 uint32 cid;
1874 uint32 shid;
1875 SVGA3dShaderType type;
1876} SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
1877
1878typedef
1879struct {
1880 uint32 cid;
1881 uint32 reg; /* register number */
1882 SVGA3dShaderType type;
1883 SVGA3dShaderConstType ctype;
1884 uint32 values[4];
1885} SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
1886
1887typedef
1888struct {
1889 uint32 cid;
1890 SVGA3dShaderType type;
1891 uint32 shid;
1892} SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
1893
1894typedef
1895struct {
1896 uint32 cid;
1897 SVGA3dQueryType type;
1898} SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
1899
1900typedef
1901struct {
1902 uint32 cid;
1903 SVGA3dQueryType type;
1904 SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
1905} SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
1906
1907typedef
1908struct {
1909 uint32 cid; /* Same parameters passed to END_QUERY */
1910 SVGA3dQueryType type;
1911 SVGAGuestPtr guestResult;
1912} SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
1913
1914typedef
1915struct {
1916 uint32 totalSize; /* Set by guest before query is ended. */
1917 SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
1918 union { /* Set by host on exit from PENDING state */
1919 uint32 result32;
1920 };
1921} SVGA3dQueryResult;
1922
1923/*
1924 * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
1925 *
1926 * This is a blit from an SVGA3D surface to a Screen Object. Just
1927 * like GMR-to-screen blits, this blit may be directed at a
1928 * specific screen or to the virtual coordinate space.
1929 *
1930 * The blit copies from a rectangular region of an SVGA3D surface
1931 * image to a rectangular region of a screen or screens.
1932 *
1933 * This command takes an optional variable-length list of clipping
1934 * rectangles after the body of the command. If no rectangles are
1935 * specified, there is no clipping region. The entire destRect is
1936 * drawn to. If one or more rectangles are included, they describe
1937 * a clipping region. The clip rectangle coordinates are measured
1938 * relative to the top-left corner of destRect.
1939 *
1940 * This clipping region serves multiple purposes:
1941 *
1942 * - It can be used to perform an irregularly shaped blit more
1943 * efficiently than by issuing many separate blit commands.
1944 *
1945 * - It is equivalent to allowing blits with non-integer
1946 * source coordinates. You could blit just one half-pixel
1947 * of a source, for example, by specifying a larger
1948 * destination rectangle than you need, then removing
1949 * part of it using a clip rectangle.
1950 *
1951 * Availability:
1952 * SVGA_FIFO_CAP_SCREEN_OBJECT
1953 *
1954 * Limitations:
1955 *
1956 * - Currently, no backend supports blits from a mipmap or face
1957 * other than the first one.
1958 */
1959
1960typedef
1961struct {
1962 SVGA3dSurfaceImageId srcImage;
1963 SVGASignedRect srcRect;
1964 uint32 destScreenId; /* Screen ID or SVGA_ID_INVALID for virt. coords */
1965 SVGASignedRect destRect; /* Supports scaling if src/rest different size */
1966 /* Clipping: zero or more SVGASignedRects follow */
1967} SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
1968
1969typedef
1970struct {
1971 uint32 sid;
1972 SVGA3dTextureFilter filter;
1973} SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
1974
1975
1976/*
1977 * Guest-backed surface definitions.
1978 */
1979
1980typedef enum SVGAMobFormat {
1981 SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID,
1982 SVGA3D_MOBFMT_PTDEPTH_0 = 0,
1983 SVGA3D_MOBFMT_PTDEPTH_1 = 1,
1984 SVGA3D_MOBFMT_PTDEPTH_2 = 2,
1985 SVGA3D_MOBFMT_RANGE = 3,
1986 SVGA3D_MOBFMT_PTDEPTH64_0 = 4,
1987 SVGA3D_MOBFMT_PTDEPTH64_1 = 5,
1988 SVGA3D_MOBFMT_PTDEPTH64_2 = 6,
1989 SVGA3D_MOBFMT_MAX,
1990} SVGAMobFormat;
1991
1992/*
1993 * Sizes of opaque types.
1994 */
1995
1996#define SVGA3D_OTABLE_MOB_ENTRY_SIZE 16
1997#define SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE 8
1998#define SVGA3D_OTABLE_SURFACE_ENTRY_SIZE 64
1999#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE 16
2000#define SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE 64
2001#define SVGA3D_CONTEXT_DATA_SIZE 16384
2002
2003/*
2004 * SVGA3dCmdSetOTableBase --
2005 *
2006 * This command allows the guest to specify the base PPN of the
2007 * specified object table.
2008 */
2009
2010typedef enum {
2011 SVGA_OTABLE_MOB = 0,
2012 SVGA_OTABLE_MIN = 0,
2013 SVGA_OTABLE_SURFACE = 1,
2014 SVGA_OTABLE_CONTEXT = 2,
2015 SVGA_OTABLE_SHADER = 3,
2016 SVGA_OTABLE_SCREEN_TARGET = 4,
2017 SVGA_OTABLE_DX9_MAX = 5,
2018 SVGA_OTABLE_MAX = 8
2019} SVGAOTableType;
2020
2021typedef
2022struct {
2023 SVGAOTableType type;
2024 PPN baseAddress;
2025 uint32 sizeInBytes;
2026 uint32 validSizeInBytes;
2027 SVGAMobFormat ptDepth;
2028} __packed
2029SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */
2030
2031typedef
2032struct {
2033 SVGAOTableType type;
2034 PPN64 baseAddress;
2035 uint32 sizeInBytes;
2036 uint32 validSizeInBytes;
2037 SVGAMobFormat ptDepth;
2038} __packed
2039SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
2040
2041typedef
2042struct {
2043 SVGAOTableType type;
2044} __packed
2045SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */
2046
2047/*
2048 * Define a memory object (Mob) in the OTable.
2049 */
2050
2051typedef
2052struct SVGA3dCmdDefineGBMob {
2053 SVGAMobId mobid;
2054 SVGAMobFormat ptDepth;
2055 PPN base;
2056 uint32 sizeInBytes;
2057} __packed
2058SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
2059
2060
2061/*
2062 * Destroys an object in the OTable.
2063 */
2064
2065typedef
2066struct SVGA3dCmdDestroyGBMob {
2067 SVGAMobId mobid;
2068} __packed
2069SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
2070
2071/*
2072 * Redefine an object in the OTable.
2073 */
2074
2075typedef
2076struct SVGA3dCmdRedefineGBMob {
2077 SVGAMobId mobid;
2078 SVGAMobFormat ptDepth;
2079 PPN base;
2080 uint32 sizeInBytes;
2081} __packed
2082SVGA3dCmdRedefineGBMob; /* SVGA_3D_CMD_REDEFINE_GB_MOB */
2083
2084/*
2085 * Define a memory object (Mob) in the OTable with a PPN64 base.
2086 */
2087
2088typedef
2089struct SVGA3dCmdDefineGBMob64 {
2090 SVGAMobId mobid;
2091 SVGAMobFormat ptDepth;
2092 PPN64 base;
2093 uint32 sizeInBytes;
2094} __packed
2095SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */
2096
2097/*
2098 * Redefine an object in the OTable with PPN64 base.
2099 */
2100
2101typedef
2102struct SVGA3dCmdRedefineGBMob64 {
2103 SVGAMobId mobid;
2104 SVGAMobFormat ptDepth;
2105 PPN64 base;
2106 uint32 sizeInBytes;
2107} __packed
2108SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
2109
2110/*
2111 * Notification that the page tables have been modified.
2112 */
2113
2114typedef
2115struct SVGA3dCmdUpdateGBMobMapping {
2116 SVGAMobId mobid;
2117} __packed
2118SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */
2119
2120/*
2121 * Define a guest-backed surface.
2122 */
2123
2124typedef
2125struct SVGA3dCmdDefineGBSurface {
2126 uint32 sid;
2127 SVGA3dSurfaceFlags surfaceFlags;
2128 SVGA3dSurfaceFormat format;
2129 uint32 numMipLevels;
2130 uint32 multisampleCount;
2131 SVGA3dTextureFilter autogenFilter;
2132 SVGA3dSize size;
2133} __packed
2134SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
2135
2136/*
2137 * Destroy a guest-backed surface.
2138 */
2139
2140typedef
2141struct SVGA3dCmdDestroyGBSurface {
2142 uint32 sid;
2143} __packed
2144SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
2145
2146/*
2147 * Bind a guest-backed surface to an object.
2148 */
2149
2150typedef
2151struct SVGA3dCmdBindGBSurface {
2152 uint32 sid;
2153 SVGAMobId mobid;
2154} __packed
2155SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
2156
2157/*
2158 * Conditionally bind a mob to a guest backed surface if testMobid
2159 * matches the currently bound mob. Optionally issue a readback on
2160 * the surface while it is still bound to the old mobid if the mobid
2161 * is changed by this command.
2162 */
2163
2164#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_READBACK (1 << 0)
2165
2166typedef
2167struct{
2168 uint32 sid;
2169 SVGAMobId testMobid;
2170 SVGAMobId mobid;
2171 uint32 flags;
2172} __packed
2173SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
2174
2175/*
2176 * Update an image in a guest-backed surface.
2177 * (Inform the device that the guest-contents have been updated.)
2178 */
2179
2180typedef
2181struct SVGA3dCmdUpdateGBImage {
2182 SVGA3dSurfaceImageId image;
2183 SVGA3dBox box;
2184} __packed
2185SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
2186
2187/*
2188 * Update an entire guest-backed surface.
2189 * (Inform the device that the guest-contents have been updated.)
2190 */
2191
2192typedef
2193struct SVGA3dCmdUpdateGBSurface {
2194 uint32 sid;
2195} __packed
2196SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
2197
2198/*
2199 * Readback an image in a guest-backed surface.
2200 * (Request the device to flush the dirty contents into the guest.)
2201 */
2202
2203typedef
2204struct SVGA3dCmdReadbackGBImage {
2205 SVGA3dSurfaceImageId image;
2206} __packed
2207SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE*/
2208
2209/*
2210 * Readback an entire guest-backed surface.
2211 * (Request the device to flush the dirty contents into the guest.)
2212 */
2213
2214typedef
2215struct SVGA3dCmdReadbackGBSurface {
2216 uint32 sid;
2217} __packed
2218SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
2219
2220/*
2221 * Readback a sub rect of an image in a guest-backed surface. After
2222 * issuing this command the driver is required to issue an update call
2223 * of the same region before issuing any other commands that reference
2224 * this surface or rendering is not guaranteed.
2225 */
2226
2227typedef
2228struct SVGA3dCmdReadbackGBImagePartial {
2229 SVGA3dSurfaceImageId image;
2230 SVGA3dBox box;
2231 uint32 invertBox;
2232} __packed
2233SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
2234
2235/*
2236 * Invalidate an image in a guest-backed surface.
2237 * (Notify the device that the contents can be lost.)
2238 */
2239
2240typedef
2241struct SVGA3dCmdInvalidateGBImage {
2242 SVGA3dSurfaceImageId image;
2243} __packed
2244SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
2245
2246/*
2247 * Invalidate an entire guest-backed surface.
2248 * (Notify the device that the contents if all images can be lost.)
2249 */
2250
2251typedef
2252struct SVGA3dCmdInvalidateGBSurface {
2253 uint32 sid;
2254} __packed
2255SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
2256
2257/*
2258 * Invalidate a sub rect of an image in a guest-backed surface. After
2259 * issuing this command the driver is required to issue an update call
2260 * of the same region before issuing any other commands that reference
2261 * this surface or rendering is not guaranteed.
2262 */
2263
2264typedef
2265struct SVGA3dCmdInvalidateGBImagePartial {
2266 SVGA3dSurfaceImageId image;
2267 SVGA3dBox box;
2268 uint32 invertBox;
2269} __packed
2270SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
2271
2272/*
2273 * Define a guest-backed context.
2274 */
2275
2276typedef
2277struct SVGA3dCmdDefineGBContext {
2278 uint32 cid;
2279} __packed
2280SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
2281
2282/*
2283 * Destroy a guest-backed context.
2284 */
2285
2286typedef
2287struct SVGA3dCmdDestroyGBContext {
2288 uint32 cid;
2289} __packed
2290SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
2291
2292/*
2293 * Bind a guest-backed context.
2294 *
2295 * validContents should be set to 0 for new contexts,
2296 * and 1 if this is an old context which is getting paged
2297 * back on to the device.
2298 *
2299 * For new contexts, it is recommended that the driver
2300 * issue commands to initialize all interesting state
2301 * prior to rendering.
2302 */
2303
2304typedef
2305struct SVGA3dCmdBindGBContext {
2306 uint32 cid;
2307 SVGAMobId mobid;
2308 uint32 validContents;
2309} __packed
2310SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
2311
2312/*
2313 * Readback a guest-backed context.
2314 * (Request that the device flush the contents back into guest memory.)
2315 */
2316
2317typedef
2318struct SVGA3dCmdReadbackGBContext {
2319 uint32 cid;
2320} __packed
2321SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
2322
2323/*
2324 * Invalidate a guest-backed context.
2325 */
2326typedef
2327struct SVGA3dCmdInvalidateGBContext {
2328 uint32 cid;
2329} __packed
2330SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
2331
2332/*
2333 * Define a guest-backed shader.
2334 */
2335
2336typedef
2337struct SVGA3dCmdDefineGBShader {
2338 uint32 shid;
2339 SVGA3dShaderType type;
2340 uint32 sizeInBytes;
2341} __packed
2342SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
2343
2344/*
2345 * Bind a guest-backed shader.
2346 */
2347
2348typedef struct SVGA3dCmdBindGBShader {
2349 uint32 shid;
2350 SVGAMobId mobid;
2351 uint32 offsetInBytes;
2352} __packed
2353SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
2354
2355/*
2356 * Destroy a guest-backed shader.
2357 */
2358
2359typedef struct SVGA3dCmdDestroyGBShader {
2360 uint32 shid;
2361} __packed
2362SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
2363
2364typedef
2365struct {
2366 uint32 cid;
2367 uint32 regStart;
2368 SVGA3dShaderType shaderType;
2369 SVGA3dShaderConstType constType;
2370
2371 /*
2372 * Followed by a variable number of shader constants.
2373 *
2374 * Note that FLOAT and INT constants are 4-dwords in length, while
2375 * BOOL constants are 1-dword in length.
2376 */
2377} __packed
2378SVGA3dCmdSetGBShaderConstInline;
2379/* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
2380
2381typedef
2382struct {
2383 uint32 cid;
2384 SVGA3dQueryType type;
2385} __packed
2386SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
2387
2388typedef
2389struct {
2390 uint32 cid;
2391 SVGA3dQueryType type;
2392 SVGAMobId mobid;
2393 uint32 offset;
2394} __packed
2395SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
2396
2397
2398/*
2399 * SVGA_3D_CMD_WAIT_FOR_GB_QUERY --
2400 *
2401 * The semantics of this command are identical to the
2402 * SVGA_3D_CMD_WAIT_FOR_QUERY except that the results are written
2403 * to a Mob instead of a GMR.
2404 */
2405
2406typedef
2407struct {
2408 uint32 cid;
2409 SVGA3dQueryType type;
2410 SVGAMobId mobid;
2411 uint32 offset;
2412} __packed
2413SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
2414
2415typedef
2416struct {
2417 SVGAMobId mobid;
2418 uint32 fbOffset;
2419 uint32 initalized;
2420} __packed
2421SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
2422
2423typedef
2424struct {
2425 SVGAMobId mobid;
2426 uint32 gartOffset;
2427} __packed
2428SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
2429
2430
2431typedef
2432struct {
2433 uint32 gartOffset;
2434 uint32 numPages;
2435} __packed
2436SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
2437
2438
2439/*
2440 * Screen Targets
2441 */
2442#define SVGA_STFLAG_PRIMARY (1 << 0)
2443
2444typedef
2445struct {
2446 uint32 stid;
2447 uint32 width;
2448 uint32 height;
2449 int32 xRoot;
2450 int32 yRoot;
2451 uint32 flags;
2452 uint32 dpi;
2453} __packed
2454SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
2455
2456typedef
2457struct {
2458 uint32 stid;
2459} __packed
2460SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
2461
2462typedef
2463struct {
2464 uint32 stid;
2465 SVGA3dSurfaceImageId image;
2466} __packed
2467SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
2468
2469typedef
2470struct {
2471 uint32 stid;
2472 SVGA3dRect rect;
2473} __packed
2474SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
2475
2476/*
2477 * Capability query index.
2478 *
2479 * Notes:
2480 *
2481 * 1. SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
2482 * fixed-function texture units available. Each of these units
2483 * work in both FFP and Shader modes, and they support texture
2484 * transforms and texture coordinates. The host may have additional
2485 * texture image units that are only usable with shaders.
2486 *
2487 * 2. The BUFFER_FORMAT capabilities are deprecated, and they always
2488 * return TRUE. Even on physical hardware that does not support
2489 * these formats natively, the SVGA3D device will provide an emulation
2490 * which should be invisible to the guest OS.
2491 *
2492 * In general, the SVGA3D device should support any operation on
2493 * any surface format, it just may perform some of these
2494 * operations in software depending on the capabilities of the
2495 * available physical hardware.
2496 *
2497 * XXX: In the future, we will add capabilities that describe in
2498 * detail what formats are supported in hardware for what kinds
2499 * of operations.
2500 */
2501
2502typedef enum {
2503 SVGA3D_DEVCAP_3D = 0,
2504 SVGA3D_DEVCAP_MAX_LIGHTS = 1,
2505 SVGA3D_DEVCAP_MAX_TEXTURES = 2, /* See note (1) */
2506 SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3,
2507 SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4,
2508 SVGA3D_DEVCAP_VERTEX_SHADER = 5,
2509 SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6,
2510 SVGA3D_DEVCAP_FRAGMENT_SHADER = 7,
2511 SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8,
2512 SVGA3D_DEVCAP_S23E8_TEXTURES = 9,
2513 SVGA3D_DEVCAP_S10E5_TEXTURES = 10,
2514 SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11,
2515 SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12, /* See note (2) */
2516 SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13, /* See note (2) */
2517 SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14, /* See note (2) */
2518 SVGA3D_DEVCAP_QUERY_TYPES = 15,
2519 SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16,
2520 SVGA3D_DEVCAP_MAX_POINT_SIZE = 17,
2521 SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18,
2522 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19,
2523 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20,
2524 SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21,
2525 SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22,
2526 SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23,
2527 SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24,
2528 SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25,
2529 SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26,
2530 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27,
2531 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
2532 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29,
2533 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30,
2534 SVGA3D_DEVCAP_TEXTURE_OPS = 31,
2535 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32,
2536 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33,
2537 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34,
2538 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35,
2539 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36,
2540 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37,
2541 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38,
2542 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39,
2543 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40,
2544 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41,
2545 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42,
2546 SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43,
2547 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44,
2548 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45,
2549 SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46,
2550 SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47,
2551 SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48,
2552 SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49,
2553 SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50,
2554 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51,
2555 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52,
2556 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53,
2557 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54,
2558 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55,
2559 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56,
2560 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57,
2561 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58,
2562 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59,
2563 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60,
2564 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61,
2565 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63,
2566
2567 /*
2568 * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
2569 * render targets. This does no include the depth or stencil targets.
2570 */
2571 SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
2572
2573 SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65,
2574 SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66,
2575 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67,
2576 SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68,
2577 SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69,
2578 SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = 70,
2579 SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = 71,
2580 SVGA3D_DEVCAP_ALPHATOCOVERAGE = 72,
2581 SVGA3D_DEVCAP_SUPERSAMPLE = 73,
2582 SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74,
2583 SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75,
2584 SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76,
2585
2586 /*
2587 * This is the maximum number of SVGA context IDs that the guest
2588 * can define using SVGA_3D_CMD_CONTEXT_DEFINE.
2589 */
2590 SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77,
2591
2592 /*
2593 * This is the maximum number of SVGA surface IDs that the guest
2594 * can define using SVGA_3D_CMD_SURFACE_DEFINE*.
2595 */
2596 SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78,
2597
2598 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79,
2599 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80,
2600 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81,
2601
2602 SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = 82,
2603 SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = 83,
2604
2605 /*
2606 * Deprecated.
2607 */
2608 SVGA3D_DEVCAP_VGPU10 = 84,
2609
2610 /*
2611 * This contains several SVGA_3D_CAPS_VIDEO_DECODE elements
2612 * ored together, one for every type of video decoding supported.
2613 */
2614 SVGA3D_DEVCAP_VIDEO_DECODE = 85,
2615
2616 /*
2617 * This contains several SVGA_3D_CAPS_VIDEO_PROCESS elements
2618 * ored together, one for every type of video processing supported.
2619 */
2620 SVGA3D_DEVCAP_VIDEO_PROCESS = 86,
2621
2622 SVGA3D_DEVCAP_LINE_AA = 87, /* boolean */
2623 SVGA3D_DEVCAP_LINE_STIPPLE = 88, /* boolean */
2624 SVGA3D_DEVCAP_MAX_LINE_WIDTH = 89, /* float */
2625 SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH = 90, /* float */
2626
2627 SVGA3D_DEVCAP_SURFACEFMT_YV12 = 91,
2628
2629 /*
2630 * Does the host support the SVGA logic ops commands?
2631 */
2632 SVGA3D_DEVCAP_LOGICOPS = 92,
2633
2634 /*
2635 * What support does the host have for screen targets?
2636 *
2637 * See the SVGA3D_SCREENTARGET_CAP bits below.
2638 */
2639 SVGA3D_DEVCAP_SCREENTARGETS = 93,
2640
2641 SVGA3D_DEVCAP_MAX /* This must be the last index. */
2642} SVGA3dDevCapIndex;
2643
2644typedef union {
2645 Bool b;
2646 uint32 u;
2647 int32 i;
2648 float f;
2649} SVGA3dDevCapResult;
2650
2651typedef enum {
2652 SVGA3DCAPS_RECORD_UNKNOWN = 0,
2653 SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
2654 SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
2655 SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff,
2656} SVGA3dCapsRecordType;
2657
2658typedef
2659struct SVGA3dCapsRecordHeader {
2660 uint32 length;
2661 SVGA3dCapsRecordType type;
2662}
2663SVGA3dCapsRecordHeader;
2664
2665typedef
2666struct SVGA3dCapsRecord {
2667 SVGA3dCapsRecordHeader header;
2668 uint32 data[1];
2669}
2670SVGA3dCapsRecord;
2671
2672
2673typedef uint32 SVGA3dCapPair[2];
2674
2675#endif /* _SVGA3D_REG_H_ */
diff --git a/drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h b/drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h
deleted file mode 100644
index d55ab01d4c45..000000000000
--- a/drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h
+++ /dev/null
@@ -1,973 +0,0 @@
1/**************************************************************************
2 *
3 * Copyright © 2008-2012 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#ifdef __KERNEL__
29
30#include <drm/vmwgfx_drm.h>
31#define surf_size_struct struct drm_vmw_size
32
33#else /* __KERNEL__ */
34
35#ifndef ARRAY_SIZE
36#define ARRAY_SIZE(_A) (sizeof(_A) / sizeof((_A)[0]))
37#endif /* ARRAY_SIZE */
38
39#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
40#define max_t(type, x, y) ((x) > (y) ? (x) : (y))
41#define min_t(type, x, y) ((x) < (y) ? (x) : (y))
42#define surf_size_struct SVGA3dSize
43#define u32 uint32
44#define u64 uint64_t
45#define U32_MAX ((u32)~0U)
46
47#endif /* __KERNEL__ */
48
49#include "svga3d_reg.h"
50
51/*
52 * enum svga3d_block_desc describes the active data channels in a block.
53 *
54 * There can be at-most four active channels in a block:
55 * 1. Red, bump W, luminance and depth are stored in the first channel.
56 * 2. Green, bump V and stencil are stored in the second channel.
57 * 3. Blue and bump U are stored in the third channel.
58 * 4. Alpha and bump Q are stored in the fourth channel.
59 *
60 * Block channels can be used to store compressed and buffer data:
61 * 1. For compressed formats, only the data channel is used and its size
62 * is equal to that of a singular block in the compression scheme.
63 * 2. For buffer formats, only the data channel is used and its size is
64 * exactly one byte in length.
65 * 3. In each case the bit depth represent the size of a singular block.
66 *
67 * Note: Compressed and IEEE formats do not use the bitMask structure.
68 */
69
70enum svga3d_block_desc {
71 SVGA3DBLOCKDESC_NONE = 0, /* No channels are active */
72 SVGA3DBLOCKDESC_BLUE = 1 << 0, /* Block with red channel
73 data */
74 SVGA3DBLOCKDESC_U = 1 << 0, /* Block with bump U channel
75 data */
76 SVGA3DBLOCKDESC_UV_VIDEO = 1 << 7, /* Block with alternating video
77 U and V */
78 SVGA3DBLOCKDESC_GREEN = 1 << 1, /* Block with green channel
79 data */
80 SVGA3DBLOCKDESC_V = 1 << 1, /* Block with bump V channel
81 data */
82 SVGA3DBLOCKDESC_STENCIL = 1 << 1, /* Block with a stencil
83 channel */
84 SVGA3DBLOCKDESC_RED = 1 << 2, /* Block with blue channel
85 data */
86 SVGA3DBLOCKDESC_W = 1 << 2, /* Block with bump W channel
87 data */
88 SVGA3DBLOCKDESC_LUMINANCE = 1 << 2, /* Block with luminance channel
89 data */
90 SVGA3DBLOCKDESC_Y = 1 << 2, /* Block with video luminance
91 data */
92 SVGA3DBLOCKDESC_DEPTH = 1 << 2, /* Block with depth channel */
93 SVGA3DBLOCKDESC_ALPHA = 1 << 3, /* Block with an alpha
94 channel */
95 SVGA3DBLOCKDESC_Q = 1 << 3, /* Block with bump Q channel
96 data */
97 SVGA3DBLOCKDESC_BUFFER = 1 << 4, /* Block stores 1 byte of
98 data */
99 SVGA3DBLOCKDESC_COMPRESSED = 1 << 5, /* Block stores n bytes of
100 data depending on the
101 compression method used */
102 SVGA3DBLOCKDESC_IEEE_FP = 1 << 6, /* Block stores data in an IEEE
103 floating point
104 representation in
105 all channels */
106 SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 8, /* Three separate blocks store
107 data. */
108 SVGA3DBLOCKDESC_U_VIDEO = 1 << 9, /* Block with U video data */
109 SVGA3DBLOCKDESC_V_VIDEO = 1 << 10, /* Block with V video data */
110 SVGA3DBLOCKDESC_EXP = 1 << 11, /* Shared exponent */
111 SVGA3DBLOCKDESC_SRGB = 1 << 12, /* Data is in sRGB format */
112 SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 13, /* 2 planes of Y, UV,
113 e.g., NV12. */
114 SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 14, /* 3 planes of separate
115 Y, U, V, e.g., YV12. */
116
117 SVGA3DBLOCKDESC_RG = SVGA3DBLOCKDESC_RED |
118 SVGA3DBLOCKDESC_GREEN,
119 SVGA3DBLOCKDESC_RGB = SVGA3DBLOCKDESC_RG |
120 SVGA3DBLOCKDESC_BLUE,
121 SVGA3DBLOCKDESC_RGB_SRGB = SVGA3DBLOCKDESC_RGB |
122 SVGA3DBLOCKDESC_SRGB,
123 SVGA3DBLOCKDESC_RGBA = SVGA3DBLOCKDESC_RGB |
124 SVGA3DBLOCKDESC_ALPHA,
125 SVGA3DBLOCKDESC_RGBA_SRGB = SVGA3DBLOCKDESC_RGBA |
126 SVGA3DBLOCKDESC_SRGB,
127 SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U |
128 SVGA3DBLOCKDESC_V,
129 SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV |
130 SVGA3DBLOCKDESC_LUMINANCE,
131 SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV |
132 SVGA3DBLOCKDESC_W,
133 SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW |
134 SVGA3DBLOCKDESC_ALPHA,
135 SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U |
136 SVGA3DBLOCKDESC_V |
137 SVGA3DBLOCKDESC_W |
138 SVGA3DBLOCKDESC_Q,
139 SVGA3DBLOCKDESC_LA = SVGA3DBLOCKDESC_LUMINANCE |
140 SVGA3DBLOCKDESC_ALPHA,
141 SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED |
142 SVGA3DBLOCKDESC_IEEE_FP,
143 SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP |
144 SVGA3DBLOCKDESC_GREEN,
145 SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP |
146 SVGA3DBLOCKDESC_BLUE,
147 SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RGB_FP |
148 SVGA3DBLOCKDESC_ALPHA,
149 SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH |
150 SVGA3DBLOCKDESC_STENCIL,
151 SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_UV_VIDEO |
152 SVGA3DBLOCKDESC_Y,
153 SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA |
154 SVGA3DBLOCKDESC_Y |
155 SVGA3DBLOCKDESC_U_VIDEO |
156 SVGA3DBLOCKDESC_V_VIDEO,
157 SVGA3DBLOCKDESC_RGBE = SVGA3DBLOCKDESC_RGB |
158 SVGA3DBLOCKDESC_EXP,
159 SVGA3DBLOCKDESC_COMPRESSED_SRGB = SVGA3DBLOCKDESC_COMPRESSED |
160 SVGA3DBLOCKDESC_SRGB,
161 SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_PLANAR_YUV |
162 SVGA3DBLOCKDESC_2PLANAR_YUV,
163 SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_PLANAR_YUV |
164 SVGA3DBLOCKDESC_3PLANAR_YUV,
165};
166
167/*
168 * SVGA3dSurfaceDesc describes the actual pixel data.
169 *
170 * This structure provides the following information:
171 * 1. Block description.
172 * 2. Dimensions of a block in the surface.
173 * 3. Size of block in bytes.
174 * 4. Bit depth of the pixel data.
175 * 5. Channel bit depths and masks (if applicable).
176 */
177#define SVGA3D_CHANNEL_DEF(type) \
178 struct { \
179 union { \
180 type blue; \
181 type u; \
182 type uv_video; \
183 type u_video; \
184 }; \
185 union { \
186 type green; \
187 type v; \
188 type stencil; \
189 type v_video; \
190 }; \
191 union { \
192 type red; \
193 type w; \
194 type luminance; \
195 type y; \
196 type depth; \
197 type data; \
198 }; \
199 union { \
200 type alpha; \
201 type q; \
202 type exp; \
203 }; \
204 }
205
206struct svga3d_surface_desc {
207 enum svga3d_block_desc block_desc;
208 surf_size_struct block_size;
209 u32 bytes_per_block;
210 u32 pitch_bytes_per_block;
211
212 struct {
213 u32 total;
214 SVGA3D_CHANNEL_DEF(uint8);
215 } bit_depth;
216
217 struct {
218 SVGA3D_CHANNEL_DEF(uint8);
219 } bit_offset;
220};
221
222static const struct svga3d_surface_desc svga3d_surface_descs[] = {
223 {SVGA3DBLOCKDESC_NONE,
224 {1, 1, 1}, 0, 0, {0, {{0}, {0}, {0}, {0} } },
225 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_FORMAT_INVALID */
226
227 {SVGA3DBLOCKDESC_RGB,
228 {1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
229 {{{0}, {8}, {16}, {24} } } }, /* SVGA3D_X8R8G8B8 */
230
231 {SVGA3DBLOCKDESC_RGBA,
232 {1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
233 {{{0}, {8}, {16}, {24} } } }, /* SVGA3D_A8R8G8B8 */
234
235 {SVGA3DBLOCKDESC_RGB,
236 {1, 1, 1}, 2, 2, {16, {{5}, {6}, {5}, {0} } },
237 {{{0}, {5}, {11}, {0} } } }, /* SVGA3D_R5G6B5 */
238
239 {SVGA3DBLOCKDESC_RGB,
240 {1, 1, 1}, 2, 2, {15, {{5}, {5}, {5}, {0} } },
241 {{{0}, {5}, {10}, {0} } } }, /* SVGA3D_X1R5G5B5 */
242
243 {SVGA3DBLOCKDESC_RGBA,
244 {1, 1, 1}, 2, 2, {16, {{5}, {5}, {5}, {1} } },
245 {{{0}, {5}, {10}, {15} } } }, /* SVGA3D_A1R5G5B5 */
246
247 {SVGA3DBLOCKDESC_RGBA,
248 {1, 1, 1}, 2, 2, {16, {{4}, {4}, {4}, {4} } },
249 {{{0}, {4}, {8}, {12} } } }, /* SVGA3D_A4R4G4B4 */
250
251 {SVGA3DBLOCKDESC_DEPTH,
252 {1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
253 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_D32 */
254
255 {SVGA3DBLOCKDESC_DEPTH,
256 {1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
257 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_D16 */
258
259 {SVGA3DBLOCKDESC_DS,
260 {1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
261 {{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24S8 */
262
263 {SVGA3DBLOCKDESC_DS,
264 {1, 1, 1}, 2, 2, {16, {{0}, {1}, {15}, {0} } },
265 {{{0}, {15}, {0}, {0} } } }, /* SVGA3D_Z_D15S1 */
266
267 {SVGA3DBLOCKDESC_LUMINANCE,
268 {1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
269 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_LUMINANCE8 */
270
271 {SVGA3DBLOCKDESC_LA,
272 {1, 1, 1}, 1, 1, {8, {{0}, {0}, {4}, {4} } },
273 {{{0}, {0}, {0}, {4} } } }, /* SVGA3D_LUMINANCE4_ALPHA4 */
274
275 {SVGA3DBLOCKDESC_LUMINANCE,
276 {1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
277 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_LUMINANCE16 */
278
279 {SVGA3DBLOCKDESC_LA,
280 {1, 1, 1}, 2, 2, {16, {{0}, {0}, {8}, {8} } },
281 {{{0}, {0}, {0}, {8} } } }, /* SVGA3D_LUMINANCE8_ALPHA8 */
282
283 {SVGA3DBLOCKDESC_COMPRESSED,
284 {4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
285 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT1 */
286
287 {SVGA3DBLOCKDESC_COMPRESSED,
288 {4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
289 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT2 */
290
291 {SVGA3DBLOCKDESC_COMPRESSED,
292 {4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
293 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT3 */
294
295 {SVGA3DBLOCKDESC_COMPRESSED,
296 {4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
297 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT4 */
298
299 {SVGA3DBLOCKDESC_COMPRESSED,
300 {4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
301 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT5 */
302
303 {SVGA3DBLOCKDESC_UV,
304 {1, 1, 1}, 2, 2, {16, {{0}, {0}, {8}, {8} } },
305 {{{0}, {0}, {0}, {8} } } }, /* SVGA3D_BUMPU8V8 */
306
307 {SVGA3DBLOCKDESC_UVL,
308 {1, 1, 1}, 2, 2, {16, {{5}, {5}, {6}, {0} } },
309 {{{11}, {6}, {0}, {0} } } }, /* SVGA3D_BUMPL6V5U5 */
310
311 {SVGA3DBLOCKDESC_UVL,
312 {1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {0} } },
313 {{{16}, {8}, {0}, {0} } } }, /* SVGA3D_BUMPX8L8V8U8 */
314
315 {SVGA3DBLOCKDESC_UVL,
316 {1, 1, 1}, 3, 3, {24, {{8}, {8}, {8}, {0} } },
317 {{{16}, {8}, {0}, {0} } } }, /* SVGA3D_BUMPL8V8U8 */
318
319 {SVGA3DBLOCKDESC_RGBA_FP,
320 {1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
321 {{{32}, {16}, {0}, {48} } } }, /* SVGA3D_ARGB_S10E5 */
322
323 {SVGA3DBLOCKDESC_RGBA_FP,
324 {1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
325 {{{64}, {32}, {0}, {96} } } }, /* SVGA3D_ARGB_S23E8 */
326
327 {SVGA3DBLOCKDESC_RGBA,
328 {1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
329 {{{0}, {10}, {20}, {30} } } }, /* SVGA3D_A2R10G10B10 */
330
331 {SVGA3DBLOCKDESC_UV,
332 {1, 1, 1}, 2, 2, {16, {{8}, {8}, {0}, {0} } },
333 {{{8}, {0}, {0}, {0} } } }, /* SVGA3D_V8U8 */
334
335 {SVGA3DBLOCKDESC_UVWQ,
336 {1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
337 {{{24}, {16}, {8}, {0} } } }, /* SVGA3D_Q8W8V8U8 */
338
339 {SVGA3DBLOCKDESC_UV,
340 {1, 1, 1}, 2, 2, {16, {{8}, {8}, {0}, {0} } },
341 {{{8}, {0}, {0}, {0} } } }, /* SVGA3D_CxV8U8 */
342
343 {SVGA3DBLOCKDESC_UVL,
344 {1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
345 {{{16}, {8}, {0}, {0} } } }, /* SVGA3D_X8L8V8U8 */
346
347 {SVGA3DBLOCKDESC_UVWA,
348 {1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
349 {{{0}, {10}, {20}, {30} } } }, /* SVGA3D_A2W10V10U10 */
350
351 {SVGA3DBLOCKDESC_ALPHA,
352 {1, 1, 1}, 1, 1, {8, {{0}, {0}, {0}, {8} } },
353 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_ALPHA8 */
354
355 {SVGA3DBLOCKDESC_R_FP,
356 {1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
357 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R_S10E5 */
358
359 {SVGA3DBLOCKDESC_R_FP,
360 {1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
361 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R_S23E8 */
362
363 {SVGA3DBLOCKDESC_RG_FP,
364 {1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
365 {{{0}, {16}, {0}, {0} } } }, /* SVGA3D_RG_S10E5 */
366
367 {SVGA3DBLOCKDESC_RG_FP,
368 {1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
369 {{{0}, {32}, {0}, {0} } } }, /* SVGA3D_RG_S23E8 */
370
371 {SVGA3DBLOCKDESC_BUFFER,
372 {1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
373 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BUFFER */
374
375 {SVGA3DBLOCKDESC_DEPTH,
376 {1, 1, 1}, 4, 4, {32, {{0}, {0}, {24}, {0} } },
377 {{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24X8 */
378
379 {SVGA3DBLOCKDESC_UV,
380 {1, 1, 1}, 4, 4, {32, {{16}, {16}, {0}, {0} } },
381 {{{16}, {0}, {0}, {0} } } }, /* SVGA3D_V16U16 */
382
383 {SVGA3DBLOCKDESC_RG,
384 {1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
385 {{{0}, {0}, {16}, {0} } } }, /* SVGA3D_G16R16 */
386
387 {SVGA3DBLOCKDESC_RGBA,
388 {1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
389 {{{32}, {16}, {0}, {48} } } }, /* SVGA3D_A16B16G16R16 */
390
391 {SVGA3DBLOCKDESC_YUV,
392 {1, 1, 1}, 2, 2, {16, {{8}, {0}, {8}, {0} } },
393 {{{0}, {0}, {8}, {0} } } }, /* SVGA3D_UYVY */
394
395 {SVGA3DBLOCKDESC_YUV,
396 {1, 1, 1}, 2, 2, {16, {{8}, {0}, {8}, {0} } },
397 {{{8}, {0}, {0}, {0} } } }, /* SVGA3D_YUY2 */
398
399 {SVGA3DBLOCKDESC_NV12,
400 {2, 2, 1}, 6, 2, {48, {{0}, {0}, {48}, {0} } },
401 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_NV12 */
402
403 {SVGA3DBLOCKDESC_AYUV,
404 {1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
405 {{{0}, {8}, {16}, {24} } } }, /* SVGA3D_AYUV */
406
407 {SVGA3DBLOCKDESC_RGBA,
408 {1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
409 {{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_TYPELESS */
410
411 {SVGA3DBLOCKDESC_RGBA,
412 {1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
413 {{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_UINT */
414
415 {SVGA3DBLOCKDESC_UVWQ,
416 {1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
417 {{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_SINT */
418
419 {SVGA3DBLOCKDESC_RGB,
420 {1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
421 {{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_TYPELESS */
422
423 {SVGA3DBLOCKDESC_RGB_FP,
424 {1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
425 {{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_FLOAT */
426
427 {SVGA3DBLOCKDESC_RGB,
428 {1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
429 {{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_UINT */
430
431 {SVGA3DBLOCKDESC_UVW,
432 {1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
433 {{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_SINT */
434
435 {SVGA3DBLOCKDESC_RGBA,
436 {1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
437 {{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_TYPELESS */
438
439 {SVGA3DBLOCKDESC_RGBA,
440 {1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
441 {{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_UINT */
442
443 {SVGA3DBLOCKDESC_UVWQ,
444 {1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
445 {{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_SNORM */
446
447 {SVGA3DBLOCKDESC_UVWQ,
448 {1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
449 {{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_SINT */
450
451 {SVGA3DBLOCKDESC_RG,
452 {1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
453 {{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_TYPELESS */
454
455 {SVGA3DBLOCKDESC_RG,
456 {1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
457 {{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_UINT */
458
459 {SVGA3DBLOCKDESC_UV,
460 {1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
461 {{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_SINT */
462
463 {SVGA3DBLOCKDESC_RG,
464 {1, 1, 1}, 8, 8, {64, {{0}, {8}, {32}, {0} } },
465 {{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G8X24_TYPELESS */
466
467 {SVGA3DBLOCKDESC_DS,
468 {1, 1, 1}, 8, 8, {64, {{0}, {8}, {32}, {0} } },
469 {{{0}, {32}, {0}, {0} } } }, /* SVGA3D_D32_FLOAT_S8X24_UINT */
470
471 {SVGA3DBLOCKDESC_R_FP,
472 {1, 1, 1}, 8, 8, {64, {{0}, {0}, {32}, {0} } },
473 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_FLOAT_X8_X24_TYPELESS */
474
475 {SVGA3DBLOCKDESC_GREEN,
476 {1, 1, 1}, 8, 8, {64, {{0}, {8}, {0}, {0} } },
477 {{{0}, {32}, {0}, {0} } } }, /* SVGA3D_X32_TYPELESS_G8X24_UINT */
478
479 {SVGA3DBLOCKDESC_RGBA,
480 {1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
481 {{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10A2_TYPELESS */
482
483 {SVGA3DBLOCKDESC_RGBA,
484 {1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
485 {{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10A2_UINT */
486
487 {SVGA3DBLOCKDESC_RGB_FP,
488 {1, 1, 1}, 4, 4, {32, {{10}, {11}, {11}, {0} } },
489 {{{0}, {10}, {21}, {0} } } }, /* SVGA3D_R11G11B10_FLOAT */
490
491 {SVGA3DBLOCKDESC_RGBA,
492 {1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
493 {{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_TYPELESS */
494
495 {SVGA3DBLOCKDESC_RGBA,
496 {1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
497 {{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UNORM */
498
499 {SVGA3DBLOCKDESC_RGBA_SRGB,
500 {1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
501 {{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UNORM_SRGB */
502
503 {SVGA3DBLOCKDESC_RGBA,
504 {1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
505 {{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UINT */
506
507 {SVGA3DBLOCKDESC_RGBA,
508 {1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
509 {{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_SINT */
510
511 {SVGA3DBLOCKDESC_RG,
512 {1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
513 {{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_TYPELESS */
514
515 {SVGA3DBLOCKDESC_RG_FP,
516 {1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
517 {{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_UINT */
518
519 {SVGA3DBLOCKDESC_UV,
520 {1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
521 {{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_SINT */
522
523 {SVGA3DBLOCKDESC_RED,
524 {1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
525 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_TYPELESS */
526
527 {SVGA3DBLOCKDESC_DEPTH,
528 {1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
529 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_D32_FLOAT */
530
531 {SVGA3DBLOCKDESC_RED,
532 {1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
533 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_UINT */
534
535 {SVGA3DBLOCKDESC_RED,
536 {1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
537 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_SINT */
538
539 {SVGA3DBLOCKDESC_RG,
540 {1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
541 {{{0}, {24}, {0}, {0} } } }, /* SVGA3D_R24G8_TYPELESS */
542
543 {SVGA3DBLOCKDESC_DS,
544 {1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
545 {{{0}, {24}, {0}, {0} } } }, /* SVGA3D_D24_UNORM_S8_UINT */
546
547 {SVGA3DBLOCKDESC_RED,
548 {1, 1, 1}, 4, 4, {32, {{0}, {0}, {24}, {0} } },
549 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R24_UNORM_X8_TYPELESS */
550
551 {SVGA3DBLOCKDESC_GREEN,
552 {1, 1, 1}, 4, 4, {32, {{0}, {8}, {0}, {0} } },
553 {{{0}, {24}, {0}, {0} } } }, /* SVGA3D_X24_TYPELESS_G8_UINT */
554
555 {SVGA3DBLOCKDESC_RG,
556 {1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
557 {{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_TYPELESS */
558
559 {SVGA3DBLOCKDESC_RG,
560 {1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
561 {{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_UNORM */
562
563 {SVGA3DBLOCKDESC_RG,
564 {1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
565 {{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_UINT */
566
567 {SVGA3DBLOCKDESC_UV,
568 {1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
569 {{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_SINT */
570
571 {SVGA3DBLOCKDESC_RED,
572 {1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
573 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_TYPELESS */
574
575 {SVGA3DBLOCKDESC_RED,
576 {1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
577 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_UNORM */
578
579 {SVGA3DBLOCKDESC_RED,
580 {1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
581 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_UINT */
582
583 {SVGA3DBLOCKDESC_U,
584 {1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
585 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_SNORM */
586
587 {SVGA3DBLOCKDESC_U,
588 {1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
589 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_SINT */
590
591 {SVGA3DBLOCKDESC_RED,
592 {1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
593 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_TYPELESS */
594
595 {SVGA3DBLOCKDESC_RED,
596 {1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
597 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_UNORM */
598
599 {SVGA3DBLOCKDESC_RED,
600 {1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
601 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_UINT */
602
603 {SVGA3DBLOCKDESC_U,
604 {1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
605 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_SNORM */
606
607 {SVGA3DBLOCKDESC_U,
608 {1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
609 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_SINT */
610
611 {SVGA3DBLOCKDESC_NONE,
612 {1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
613 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_P8 */
614
615 {SVGA3DBLOCKDESC_RGBE,
616 {1, 1, 1}, 4, 4, {32, {{9}, {9}, {9}, {5} } },
617 {{{18}, {9}, {0}, {27} } } }, /* SVGA3D_R9G9B9E5_SHAREDEXP */
618
619 {SVGA3DBLOCKDESC_RG,
620 {1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
621 {{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_B8G8_UNORM */
622
623 {SVGA3DBLOCKDESC_RG,
624 {1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
625 {{{0}, {8}, {0}, {0} } } }, /* SVGA3D_G8R8_G8B8_UNORM */
626
627 {SVGA3DBLOCKDESC_COMPRESSED,
628 {4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
629 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC1_TYPELESS */
630
631 {SVGA3DBLOCKDESC_COMPRESSED_SRGB,
632 {4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
633 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC1_UNORM_SRGB */
634
635 {SVGA3DBLOCKDESC_COMPRESSED,
636 {4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
637 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC2_TYPELESS */
638
639 {SVGA3DBLOCKDESC_COMPRESSED_SRGB,
640 {4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
641 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC2_UNORM_SRGB */
642
643 {SVGA3DBLOCKDESC_COMPRESSED,
644 {4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
645 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC3_TYPELESS */
646
647 {SVGA3DBLOCKDESC_COMPRESSED_SRGB,
648 {4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
649 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC3_UNORM_SRGB */
650
651 {SVGA3DBLOCKDESC_COMPRESSED,
652 {4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
653 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_TYPELESS */
654
655 {SVGA3DBLOCKDESC_COMPRESSED,
656 {4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
657 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_UNORM */
658
659 {SVGA3DBLOCKDESC_COMPRESSED,
660 {4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
661 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_SNORM */
662
663 {SVGA3DBLOCKDESC_COMPRESSED,
664 {4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
665 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_TYPELESS */
666
667 {SVGA3DBLOCKDESC_COMPRESSED,
668 {4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
669 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_UNORM */
670
671 {SVGA3DBLOCKDESC_COMPRESSED,
672 {4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
673 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_SNORM */
674
675 {SVGA3DBLOCKDESC_RGBA,
676 {1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
677 {{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10_XR_BIAS_A2_UNORM */
678
679 {SVGA3DBLOCKDESC_RGBA,
680 {1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
681 {{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8A8_TYPELESS */
682
683 {SVGA3DBLOCKDESC_RGBA_SRGB,
684 {1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
685 {{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8A8_UNORM_SRGB */
686
687 {SVGA3DBLOCKDESC_RGB,
688 {1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
689 {{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8X8_TYPELESS */
690
691 {SVGA3DBLOCKDESC_RGB_SRGB,
692 {1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
693 {{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8X8_UNORM_SRGB */
694
695 {SVGA3DBLOCKDESC_DEPTH,
696 {1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
697 {{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_DF16 */
698
699 {SVGA3DBLOCKDESC_DS,
700 {1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
701 {{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_DF24 */
702
703 {SVGA3DBLOCKDESC_DS,
704 {1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
705 {{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24S8_INT */
706};
707
708static inline u32 clamped_umul32(u32 a, u32 b)
709{
710 u64 tmp = (u64) a*b;
711 return (tmp > (u64) U32_MAX) ? U32_MAX : tmp;
712}
713
714static inline const struct svga3d_surface_desc *
715svga3dsurface_get_desc(SVGA3dSurfaceFormat format)
716{
717 if (format < ARRAY_SIZE(svga3d_surface_descs))
718 return &svga3d_surface_descs[format];
719
720 return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID];
721}
722
723/*
724 *----------------------------------------------------------------------
725 *
726 * svga3dsurface_get_mip_size --
727 *
728 * Given a base level size and the mip level, compute the size of
729 * the mip level.
730 *
731 * Results:
732 * See above.
733 *
734 * Side effects:
735 * None.
736 *
737 *----------------------------------------------------------------------
738 */
739
740static inline surf_size_struct
741svga3dsurface_get_mip_size(surf_size_struct base_level, u32 mip_level)
742{
743 surf_size_struct size;
744
745 size.width = max_t(u32, base_level.width >> mip_level, 1);
746 size.height = max_t(u32, base_level.height >> mip_level, 1);
747 size.depth = max_t(u32, base_level.depth >> mip_level, 1);
748 return size;
749}
750
751static inline void
752svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc,
753 const surf_size_struct *pixel_size,
754 surf_size_struct *block_size)
755{
756 block_size->width = DIV_ROUND_UP(pixel_size->width,
757 desc->block_size.width);
758 block_size->height = DIV_ROUND_UP(pixel_size->height,
759 desc->block_size.height);
760 block_size->depth = DIV_ROUND_UP(pixel_size->depth,
761 desc->block_size.depth);
762}
763
764static inline bool
765svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc)
766{
767 return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0;
768}
769
770static inline u32
771svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc,
772 const surf_size_struct *size)
773{
774 u32 pitch;
775 surf_size_struct blocks;
776
777 svga3dsurface_get_size_in_blocks(desc, size, &blocks);
778
779 pitch = blocks.width * desc->pitch_bytes_per_block;
780
781 return pitch;
782}
783
784/*
785 *-----------------------------------------------------------------------------
786 *
787 * svga3dsurface_get_image_buffer_size --
788 *
789 * Return the number of bytes of buffer space required to store
790 * one image of a surface, optionally using the specified pitch.
791 *
792 * If pitch is zero, it is assumed that rows are tightly packed.
793 *
794 * This function is overflow-safe. If the result would have
795 * overflowed, instead we return MAX_UINT32.
796 *
797 * Results:
798 * Byte count.
799 *
800 * Side effects:
801 * None.
802 *
803 *-----------------------------------------------------------------------------
804 */
805
806static inline u32
807svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc,
808 const surf_size_struct *size,
809 u32 pitch)
810{
811 surf_size_struct image_blocks;
812 u32 slice_size, total_size;
813
814 svga3dsurface_get_size_in_blocks(desc, size, &image_blocks);
815
816 if (svga3dsurface_is_planar_surface(desc)) {
817 total_size = clamped_umul32(image_blocks.width,
818 image_blocks.height);
819 total_size = clamped_umul32(total_size, image_blocks.depth);
820 total_size = clamped_umul32(total_size, desc->bytes_per_block);
821 return total_size;
822 }
823
824 if (pitch == 0)
825 pitch = svga3dsurface_calculate_pitch(desc, size);
826
827 slice_size = clamped_umul32(image_blocks.height, pitch);
828 total_size = clamped_umul32(slice_size, image_blocks.depth);
829
830 return total_size;
831}
832
833static inline u32
834svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
835 surf_size_struct base_level_size,
836 u32 num_mip_levels,
837 bool cubemap)
838{
839 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
840 u64 total_size = 0;
841 u32 mip;
842
843 for (mip = 0; mip < num_mip_levels; mip++) {
844 surf_size_struct size =
845 svga3dsurface_get_mip_size(base_level_size, mip);
846 total_size += svga3dsurface_get_image_buffer_size(desc,
847 &size, 0);
848 }
849
850 if (cubemap)
851 total_size *= SVGA3D_MAX_SURFACE_FACES;
852
853 return (u32) min_t(u64, total_size, (u64) U32_MAX);
854}
855
856
857/**
858 * svga3dsurface_get_pixel_offset - Compute the offset (in bytes) to a pixel
859 * in an image (or volume).
860 *
861 * @width: The image width in pixels.
862 * @height: The image height in pixels
863 */
864static inline u32
865svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format,
866 u32 width, u32 height,
867 u32 x, u32 y, u32 z)
868{
869 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
870 const u32 bw = desc->block_size.width, bh = desc->block_size.height;
871 const u32 bd = desc->block_size.depth;
872 const u32 rowstride = DIV_ROUND_UP(width, bw) * desc->bytes_per_block;
873 const u32 imgstride = DIV_ROUND_UP(height, bh) * rowstride;
874 const u32 offset = (z / bd * imgstride +
875 y / bh * rowstride +
876 x / bw * desc->bytes_per_block);
877 return offset;
878}
879
880
881static inline u32
882svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format,
883 surf_size_struct baseLevelSize,
884 u32 numMipLevels,
885 u32 face,
886 u32 mip)
887
888{
889 u32 offset;
890 u32 mipChainBytes;
891 u32 mipChainBytesToLevel;
892 u32 i;
893 const struct svga3d_surface_desc *desc;
894 surf_size_struct mipSize;
895 u32 bytes;
896
897 desc = svga3dsurface_get_desc(format);
898
899 mipChainBytes = 0;
900 mipChainBytesToLevel = 0;
901 for (i = 0; i < numMipLevels; i++) {
902 mipSize = svga3dsurface_get_mip_size(baseLevelSize, i);
903 bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0);
904 mipChainBytes += bytes;
905 if (i < mip)
906 mipChainBytesToLevel += bytes;
907 }
908
909 offset = mipChainBytes * face + mipChainBytesToLevel;
910
911 return offset;
912}
913
914
915/**
916 * svga3dsurface_is_gb_screen_target_format - Is the specified format usable as
917 * a ScreenTarget?
918 * (with just the GBObjects cap-bit
919 * set)
920 * @format: format to queried
921 *
922 * RETURNS:
923 * true if queried format is valid for screen targets
924 */
925static inline bool
926svga3dsurface_is_gb_screen_target_format(SVGA3dSurfaceFormat format)
927{
928 return (format == SVGA3D_X8R8G8B8 ||
929 format == SVGA3D_A8R8G8B8 ||
930 format == SVGA3D_R5G6B5 ||
931 format == SVGA3D_X1R5G5B5 ||
932 format == SVGA3D_A1R5G5B5 ||
933 format == SVGA3D_P8);
934}
935
936
937/**
938 * svga3dsurface_is_dx_screen_target_format - Is the specified format usable as
939 * a ScreenTarget?
940 * (with DX10 enabled)
941 *
942 * @format: format to queried
943 *
944 * Results:
945 * true if queried format is valid for screen targets
946 */
947static inline bool
948svga3dsurface_is_dx_screen_target_format(SVGA3dSurfaceFormat format)
949{
950 return (format == SVGA3D_R8G8B8A8_UNORM ||
951 format == SVGA3D_B8G8R8A8_UNORM ||
952 format == SVGA3D_B8G8R8X8_UNORM);
953}
954
955
956/**
957 * svga3dsurface_is_screen_target_format - Is the specified format usable as a
958 * ScreenTarget?
959 * (for some combination of caps)
960 *
961 * @format: format to queried
962 *
963 * Results:
964 * true if queried format is valid for screen targets
965 */
966static inline bool
967svga3dsurface_is_screen_target_format(SVGA3dSurfaceFormat format)
968{
969 if (svga3dsurface_is_gb_screen_target_format(format)) {
970 return true;
971 }
972 return svga3dsurface_is_dx_screen_target_format(format);
973}
diff --git a/drivers/gpu/drm/vmwgfx/svga_types.h b/drivers/gpu/drm/vmwgfx/svga_types.h
deleted file mode 100644
index 1186898208ed..000000000000
--- a/drivers/gpu/drm/vmwgfx/svga_types.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28/**
29 * Silly typedefs for the svga headers. Currently the headers are shared
30 * between all components that talk to svga. And as such the headers are
31 * are in a completely different style and use weird defines.
32 *
33 * This file lets all the ugly be prefixed with svga*.
34 */
35
36#ifndef _SVGA_TYPES_H_
37#define _SVGA_TYPES_H_
38
39typedef uint16_t uint16;
40typedef uint32_t uint32;
41typedef uint8_t uint8;
42typedef int32_t int32;
43typedef uint64_t uint64;
44typedef bool Bool;
45typedef uint64 PA;
46typedef uint32 SVGAMobId;
47
48#endif
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c
index 5667c134e409..04fa8526b55e 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c
@@ -1139,7 +1139,7 @@ int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man,
1139 * actually call into the already enabled manager, when 1139 * actually call into the already enabled manager, when
1140 * binding the MOB. 1140 * binding the MOB.
1141 */ 1141 */
1142 if (!(dev_priv->capabilities & SVGA_CAP_CMD_BUFFERS_3)) 1142 if (!(dev_priv->capabilities & SVGA_CAP_DX))
1143 return -ENOMEM; 1143 return -ENOMEM;
1144 1144
1145 ret = ttm_bo_create(&dev_priv->bdev, size, ttm_bo_type_device, 1145 ret = ttm_bo_create(&dev_priv->bdev, size, ttm_bo_type_device,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_context.c b/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
index 2aa8bb818739..15f954423e7c 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
@@ -696,7 +696,7 @@ int vmw_context_binding_add(struct vmw_ctx_binding_state *cbs,
696 break; 696 break;
697 case vmw_ctx_binding_shader: 697 case vmw_ctx_binding_shader:
698 if (unlikely((unsigned)bi->i1.shader_type >= 698 if (unlikely((unsigned)bi->i1.shader_type >=
699 SVGA3D_SHADERTYPE_MAX)) { 699 SVGA3D_SHADERTYPE_PREDX_MAX)) {
700 DRM_ERROR("Illegal shader type %u.\n", 700 DRM_ERROR("Illegal shader type %u.\n",
701 (unsigned) bi->i1.shader_type); 701 (unsigned) bi->i1.shader_type);
702 return -EINVAL; 702 return -EINVAL;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 65e35654f0f2..b83adea43f3a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -278,8 +278,8 @@ static void vmw_print_capabilities(uint32_t capabilities)
278 DRM_INFO(" Command Buffers 2.\n"); 278 DRM_INFO(" Command Buffers 2.\n");
279 if (capabilities & SVGA_CAP_GBOBJECTS) 279 if (capabilities & SVGA_CAP_GBOBJECTS)
280 DRM_INFO(" Guest Backed Resources.\n"); 280 DRM_INFO(" Guest Backed Resources.\n");
281 if (capabilities & SVGA_CAP_CMD_BUFFERS_3) 281 if (capabilities & SVGA_CAP_DX)
282 DRM_INFO(" Command Buffers 3.\n"); 282 DRM_INFO(" DX Features.\n");
283} 283}
284 284
285/** 285/**
@@ -1264,7 +1264,8 @@ static void __vmw_svga_disable(struct vmw_private *dev_priv)
1264 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1264 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1265 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1265 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1266 vmw_write(dev_priv, SVGA_REG_ENABLE, 1266 vmw_write(dev_priv, SVGA_REG_ENABLE,
1267 SVGA_REG_ENABLE_ENABLE_HIDE); 1267 SVGA_REG_ENABLE_HIDE |
1268 SVGA_REG_ENABLE_ENABLE);
1268 } 1269 }
1269 spin_unlock(&dev_priv->svga_lock); 1270 spin_unlock(&dev_priv->svga_lock);
1270} 1271}
@@ -1282,11 +1283,12 @@ void vmw_svga_disable(struct vmw_private *dev_priv)
1282 spin_lock(&dev_priv->svga_lock); 1283 spin_lock(&dev_priv->svga_lock);
1283 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1284 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1284 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1285 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1285 vmw_write(dev_priv, SVGA_REG_ENABLE,
1286 SVGA_REG_ENABLE_ENABLE_HIDE);
1287 spin_unlock(&dev_priv->svga_lock); 1286 spin_unlock(&dev_priv->svga_lock);
1288 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1287 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1289 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1288 DRM_ERROR("Failed evicting VRAM buffers.\n");
1289 vmw_write(dev_priv, SVGA_REG_ENABLE,
1290 SVGA_REG_ENABLE_HIDE |
1291 SVGA_REG_ENABLE_ENABLE);
1290 } else 1292 } else
1291 spin_unlock(&dev_priv->svga_lock); 1293 spin_unlock(&dev_priv->svga_lock);
1292 ttm_write_unlock(&dev_priv->reservation_sem); 1294 ttm_write_unlock(&dev_priv->reservation_sem);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index c9ea9b1277b0..f513e444125d 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -328,7 +328,7 @@ struct vmw_ctx_binding_state {
328 struct list_head list; 328 struct list_head list;
329 struct vmw_ctx_binding render_targets[SVGA3D_RT_MAX]; 329 struct vmw_ctx_binding render_targets[SVGA3D_RT_MAX];
330 struct vmw_ctx_binding texture_units[SVGA3D_NUM_TEXTURE_UNITS]; 330 struct vmw_ctx_binding texture_units[SVGA3D_NUM_TEXTURE_UNITS];
331 struct vmw_ctx_binding shaders[SVGA3D_SHADERTYPE_MAX]; 331 struct vmw_ctx_binding shaders[SVGA3D_SHADERTYPE_PREDX_MAX];
332}; 332};
333 333
334 334
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 40fdd0258664..847264f8a33a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -1981,8 +1981,6 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
1981 false, false, true), 1981 false, false, true),
1982 VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_MOB, &vmw_cmd_invalid, 1982 VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_MOB, &vmw_cmd_invalid,
1983 false, false, true), 1983 false, false, true),
1984 VMW_CMD_DEF(SVGA_3D_CMD_REDEFINE_GB_MOB, &vmw_cmd_invalid,
1985 false, false, true),
1986 VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING, &vmw_cmd_invalid, 1984 VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING, &vmw_cmd_invalid,
1987 false, false, true), 1985 false, false, true),
1988 VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SURFACE, &vmw_cmd_invalid, 1986 VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SURFACE, &vmw_cmd_invalid,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
index 7a6cf1700745..cb24936a18c1 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
@@ -119,7 +119,8 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
119 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 119 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
120 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 120 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
121 121
122 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE_HIDE); 122 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
123 SVGA_REG_ENABLE_HIDE);
123 vmw_write(dev_priv, SVGA_REG_TRACES, 0); 124 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
124 125
125 min = 4; 126 min = 4;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index 6db98289b8a4..91efe9cdd822 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -28,6 +28,7 @@
28#include "vmwgfx_drv.h" 28#include "vmwgfx_drv.h"
29#include <drm/vmwgfx_drm.h> 29#include <drm/vmwgfx_drm.h>
30#include "vmwgfx_kms.h" 30#include "vmwgfx_kms.h"
31#include "device_include/svga3d_caps.h"
31 32
32struct svga_3d_compat_cap { 33struct svga_3d_compat_cap {
33 SVGA3dCapsRecordHeader header; 34 SVGA3dCapsRecordHeader header;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c b/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
index c5897cb4e4d5..5b0287eba30d 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
@@ -253,7 +253,7 @@ int vmw_otables_setup(struct vmw_private *dev_priv)
253 VMWGFX_NUM_GB_CONTEXT * SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE; 253 VMWGFX_NUM_GB_CONTEXT * SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE;
254 otables[SVGA_OTABLE_SHADER].size = 254 otables[SVGA_OTABLE_SHADER].size =
255 VMWGFX_NUM_GB_SHADER * SVGA3D_OTABLE_SHADER_ENTRY_SIZE; 255 VMWGFX_NUM_GB_SHADER * SVGA3D_OTABLE_SHADER_ENTRY_SIZE;
256 otables[SVGA_OTABLE_SCREEN_TARGET].size = 256 otables[SVGA_OTABLE_SCREENTARGET].size =
257 VMWGFX_NUM_GB_SCREEN_TARGET * 257 VMWGFX_NUM_GB_SCREEN_TARGET *
258 SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE; 258 SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE;
259 259
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c b/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
index d839051cc1cb..755e94132a3b 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
@@ -31,8 +31,8 @@
31 31
32#include <drm/ttm/ttm_placement.h> 32#include <drm/ttm/ttm_placement.h>
33 33
34#include "svga_overlay.h" 34#include "device_include/svga_overlay.h"
35#include "svga_escape.h" 35#include "device_include/svga_escape.h"
36 36
37#define VMW_MAX_NUM_STREAMS 1 37#define VMW_MAX_NUM_STREAMS 1
38#define VMW_OVERLAY_CAP_MASK (SVGA_FIFO_CAP_VIDEO | SVGA_FIFO_CAP_ESCAPE) 38#define VMW_OVERLAY_CAP_MASK (SVGA_FIFO_CAP_VIDEO | SVGA_FIFO_CAP_ESCAPE)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_reg.h b/drivers/gpu/drm/vmwgfx/vmwgfx_reg.h
index 29d06a4cf024..529295da1fe9 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_reg.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_reg.h
@@ -50,8 +50,6 @@ struct svga_fifo_cmd_fence {
50#define SVGA_SYNC_GENERIC 1 50#define SVGA_SYNC_GENERIC 1
51#define SVGA_SYNC_FIFOFULL 2 51#define SVGA_SYNC_FIFOFULL 2
52 52
53#include "svga_types.h" 53#include "device_include/svga3d_reg.h"
54
55#include "svga3d_reg.h"
56 54
57#endif 55#endif
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
index 493fcd1eb803..d4a453703eed 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
@@ -26,7 +26,7 @@
26 ******************************************************************************/ 26 ******************************************************************************/
27 27
28#include "vmwgfx_kms.h" 28#include "vmwgfx_kms.h"
29#include "svga3d_surfacedefs.h" 29#include "device_include/svga3d_surfacedefs.h"
30#include <drm/drm_plane_helper.h> 30#include <drm/drm_plane_helper.h>
31 31
32#define vmw_crtc_to_stdu(x) \ 32#define vmw_crtc_to_stdu(x) \
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
index 843d7e04b376..eea1790eed6a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
@@ -28,7 +28,7 @@
28#include "vmwgfx_drv.h" 28#include "vmwgfx_drv.h"
29#include "vmwgfx_resource_priv.h" 29#include "vmwgfx_resource_priv.h"
30#include <ttm/ttm_placement.h> 30#include <ttm/ttm_placement.h>
31#include "svga3d_surfacedefs.h" 31#include "device_include/svga3d_surfacedefs.h"
32 32
33/** 33/**
34 * struct vmw_user_surface - User-space visible surface resource 34 * struct vmw_user_surface - User-space visible surface resource
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 08:06:29 -0400