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authorJun Nie <jun.nie@linaro.org>2015-07-31 03:49:19 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2015-08-05 01:07:26 -0400
commit8cd90e50d1408c65c355084b1c7f8f9085f49c6b (patch)
tree38c39695a7d4521ef61c048e440ace2afeb8efdc
parent09dcc7dfc05b31bf0bbcd1511cd1a2644908d5c8 (diff)
uart: pl011: Add support to ZTE ZX296702 uart
Support ZTE uart with some registers differing offset. Probe as platform device for not AMBA IP ID is available on ZTE uart. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/tty/serial/Kconfig4
-rw-r--r--drivers/tty/serial/amba-pl011.c195
-rw-r--r--include/linux/amba/serial.h14
3 files changed, 197 insertions, 16 deletions
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 687b1ea294b7..ed299b9e6375 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -47,12 +47,12 @@ config SERIAL_AMBA_PL010_CONSOLE
47 47
48config SERIAL_AMBA_PL011 48config SERIAL_AMBA_PL011
49 tristate "ARM AMBA PL011 serial port support" 49 tristate "ARM AMBA PL011 serial port support"
50 depends on ARM_AMBA 50 depends on ARM_AMBA || SOC_ZX296702
51 select SERIAL_CORE 51 select SERIAL_CORE
52 help 52 help
53 This selects the ARM(R) AMBA(R) PrimeCell PL011 UART. If you have 53 This selects the ARM(R) AMBA(R) PrimeCell PL011 UART. If you have
54 an Integrator/PP2, Integrator/CP or Versatile platform, say Y or M 54 an Integrator/PP2, Integrator/CP or Versatile platform, say Y or M
55 here. 55 here. Say Y or M if you have SOC_ZX296702.
56 56
57 If unsure, say N. 57 If unsure, say N.
58 58
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 017443d092c1..2af09ab153b6 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -74,6 +74,10 @@
74/* There is by now at least one vendor with differing details, so handle it */ 74/* There is by now at least one vendor with differing details, so handle it */
75struct vendor_data { 75struct vendor_data {
76 unsigned int ifls; 76 unsigned int ifls;
77 unsigned int fr_busy;
78 unsigned int fr_dsr;
79 unsigned int fr_cts;
80 unsigned int fr_ri;
77 unsigned int lcrh_tx; 81 unsigned int lcrh_tx;
78 unsigned int lcrh_rx; 82 unsigned int lcrh_rx;
79 u16 *reg_lut; 83 u16 *reg_lut;
@@ -127,6 +131,7 @@ static u16 arm_reg[] = {
127 [REG_DMACR] = UART011_DMACR, 131 [REG_DMACR] = UART011_DMACR,
128}; 132};
129 133
134#ifdef CONFIG_ARM_AMBA
130static unsigned int get_fifosize_arm(struct amba_device *dev) 135static unsigned int get_fifosize_arm(struct amba_device *dev)
131{ 136{
132 return amba_rev(dev) < 3 ? 16 : 32; 137 return amba_rev(dev) < 3 ? 16 : 32;
@@ -134,6 +139,10 @@ static unsigned int get_fifosize_arm(struct amba_device *dev)
134 139
135static struct vendor_data vendor_arm = { 140static struct vendor_data vendor_arm = {
136 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 141 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
142 .fr_busy = UART01x_FR_BUSY,
143 .fr_dsr = UART01x_FR_DSR,
144 .fr_cts = UART01x_FR_CTS,
145 .fr_ri = UART011_FR_RI,
137 .lcrh_tx = REG_LCRH, 146 .lcrh_tx = REG_LCRH,
138 .lcrh_rx = REG_LCRH, 147 .lcrh_rx = REG_LCRH,
139 .reg_lut = arm_reg, 148 .reg_lut = arm_reg,
@@ -144,8 +153,13 @@ static struct vendor_data vendor_arm = {
144 .fixed_options = false, 153 .fixed_options = false,
145 .get_fifosize = get_fifosize_arm, 154 .get_fifosize = get_fifosize_arm,
146}; 155};
156#endif
147 157
148static struct vendor_data vendor_sbsa = { 158static struct vendor_data vendor_sbsa = {
159 .fr_busy = UART01x_FR_BUSY,
160 .fr_dsr = UART01x_FR_DSR,
161 .fr_cts = UART01x_FR_CTS,
162 .fr_ri = UART011_FR_RI,
149 .reg_lut = arm_reg, 163 .reg_lut = arm_reg,
150 .oversampling = false, 164 .oversampling = false,
151 .dma_threshold = false, 165 .dma_threshold = false,
@@ -154,6 +168,7 @@ static struct vendor_data vendor_sbsa = {
154 .fixed_options = true, 168 .fixed_options = true,
155}; 169};
156 170
171#ifdef CONFIG_ARM_AMBA
157static u16 st_reg[] = { 172static u16 st_reg[] = {
158 [REG_DR] = UART01x_DR, 173 [REG_DR] = UART01x_DR,
159 [REG_RSR] = UART01x_RSR, 174 [REG_RSR] = UART01x_RSR,
@@ -180,6 +195,10 @@ static unsigned int get_fifosize_st(struct amba_device *dev)
180 195
181static struct vendor_data vendor_st = { 196static struct vendor_data vendor_st = {
182 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 197 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
198 .fr_busy = UART01x_FR_BUSY,
199 .fr_dsr = UART01x_FR_DSR,
200 .fr_cts = UART01x_FR_CTS,
201 .fr_ri = UART011_FR_RI,
183 .lcrh_tx = REG_LCRH, 202 .lcrh_tx = REG_LCRH,
184 .lcrh_rx = REG_ST_LCRH_RX, 203 .lcrh_rx = REG_ST_LCRH_RX,
185 .reg_lut = st_reg, 204 .reg_lut = st_reg,
@@ -190,6 +209,43 @@ static struct vendor_data vendor_st = {
190 .fixed_options = false, 209 .fixed_options = false,
191 .get_fifosize = get_fifosize_st, 210 .get_fifosize = get_fifosize_st,
192}; 211};
212#endif
213
214#ifdef CONFIG_SOC_ZX296702
215static u16 zte_reg[] = {
216 [REG_DR] = ZX_UART01x_DR,
217 [REG_RSR] = UART01x_RSR,
218 [REG_ST_DMAWM] = ST_UART011_DMAWM,
219 [REG_FR] = ZX_UART01x_FR,
220 [REG_ST_LCRH_RX] = ST_UART011_LCRH_RX,
221 [REG_ILPR] = UART01x_ILPR,
222 [REG_IBRD] = UART011_IBRD,
223 [REG_FBRD] = UART011_FBRD,
224 [REG_LCRH] = ZX_UART011_LCRH_TX,
225 [REG_CR] = ZX_UART011_CR,
226 [REG_IFLS] = ZX_UART011_IFLS,
227 [REG_IMSC] = ZX_UART011_IMSC,
228 [REG_RIS] = ZX_UART011_RIS,
229 [REG_MIS] = ZX_UART011_MIS,
230 [REG_ICR] = ZX_UART011_ICR,
231 [REG_DMACR] = ZX_UART011_DMACR,
232};
233
234static struct vendor_data vendor_zte = {
235 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
236 .fr_busy = ZX_UART01x_FR_BUSY,
237 .fr_dsr = ZX_UART01x_FR_DSR,
238 .fr_cts = ZX_UART01x_FR_CTS,
239 .fr_ri = ZX_UART011_FR_RI,
240 .lcrh_tx = REG_LCRH,
241 .lcrh_rx = REG_ST_LCRH_RX,
242 .reg_lut = zte_reg,
243 .oversampling = false,
244 .dma_threshold = false,
245 .cts_event_workaround = false,
246 .fixed_options = false,
247};
248#endif
193 249
194/* Deals with DMA transactions */ 250/* Deals with DMA transactions */
195 251
@@ -233,6 +289,10 @@ struct uart_amba_port {
233 unsigned int im; /* interrupt mask */ 289 unsigned int im; /* interrupt mask */
234 unsigned int old_status; 290 unsigned int old_status;
235 unsigned int fifosize; /* vendor-specific */ 291 unsigned int fifosize; /* vendor-specific */
292 unsigned int fr_busy; /* vendor-specific */
293 unsigned int fr_dsr; /* vendor-specific */
294 unsigned int fr_cts; /* vendor-specific */
295 unsigned int fr_ri; /* vendor-specific */
236 unsigned int lcrh_tx; /* vendor-specific */ 296 unsigned int lcrh_tx; /* vendor-specific */
237 unsigned int lcrh_rx; /* vendor-specific */ 297 unsigned int lcrh_rx; /* vendor-specific */
238 unsigned int old_cr; /* state during shutdown */ 298 unsigned int old_cr; /* state during shutdown */
@@ -1163,7 +1223,7 @@ static void pl011_dma_shutdown(struct uart_amba_port *uap)
1163 return; 1223 return;
1164 1224
1165 /* Disable RX and TX DMA */ 1225 /* Disable RX and TX DMA */
1166 while (pl011_readw(uap, REG_FR) & UART01x_FR_BUSY) 1226 while (pl011_readw(uap, REG_FR) & uap->fr_busy)
1167 barrier(); 1227 barrier();
1168 1228
1169 spin_lock_irq(&uap->port.lock); 1229 spin_lock_irq(&uap->port.lock);
@@ -1412,11 +1472,11 @@ static void pl011_modem_status(struct uart_amba_port *uap)
1412 if (delta & UART01x_FR_DCD) 1472 if (delta & UART01x_FR_DCD)
1413 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1473 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1414 1474
1415 if (delta & UART01x_FR_DSR) 1475 if (delta & uap->fr_dsr)
1416 uap->port.icount.dsr++; 1476 uap->port.icount.dsr++;
1417 1477
1418 if (delta & UART01x_FR_CTS) 1478 if (delta & uap->fr_cts)
1419 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); 1479 uart_handle_cts_change(&uap->port, status & uap->fr_cts);
1420 1480
1421 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1481 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1422} 1482}
@@ -1487,7 +1547,7 @@ static unsigned int pl011_tx_empty(struct uart_port *port)
1487 struct uart_amba_port *uap = 1547 struct uart_amba_port *uap =
1488 container_of(port, struct uart_amba_port, port); 1548 container_of(port, struct uart_amba_port, port);
1489 unsigned int status = pl011_readw(uap, REG_FR); 1549 unsigned int status = pl011_readw(uap, REG_FR);
1490 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; 1550 return status & (uap->fr_busy|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1491} 1551}
1492 1552
1493static unsigned int pl011_get_mctrl(struct uart_port *port) 1553static unsigned int pl011_get_mctrl(struct uart_port *port)
@@ -1502,9 +1562,9 @@ static unsigned int pl011_get_mctrl(struct uart_port *port)
1502 result |= tiocmbit 1562 result |= tiocmbit
1503 1563
1504 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1564 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1505 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); 1565 TIOCMBIT(uap->fr_dsr, TIOCM_DSR);
1506 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); 1566 TIOCMBIT(uap->fr_cts, TIOCM_CTS);
1507 TIOCMBIT(UART011_FR_RI, TIOCM_RNG); 1567 TIOCMBIT(uap->fr_ri, TIOCM_RNG);
1508#undef TIOCMBIT 1568#undef TIOCMBIT
1509 return result; 1569 return result;
1510} 1570}
@@ -1720,8 +1780,7 @@ static int pl011_startup(struct uart_port *port)
1720 /* 1780 /*
1721 * initialise the old status of the modem signals 1781 * initialise the old status of the modem signals
1722 */ 1782 */
1723 uap->old_status = pl011_readw(uap, REG_FR) & 1783 uap->old_status = pl011_readw(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1724 UART01x_FR_MODEM_ANY;
1725 1784
1726 /* Startup DMA */ 1785 /* Startup DMA */
1727 pl011_dma_startup(uap); 1786 pl011_dma_startup(uap);
@@ -1800,7 +1859,7 @@ static void pl011_disable_interrupts(struct uart_amba_port *uap)
1800 /* mask all interrupts and clear all pending ones */ 1859 /* mask all interrupts and clear all pending ones */
1801 uap->im = 0; 1860 uap->im = 0;
1802 pl011_writew(uap, uap->im, REG_IMSC); 1861 pl011_writew(uap, uap->im, REG_IMSC);
1803 pl011_writew(0xffff, REG_ICR); 1862 pl011_writew(uap, 0xffff, REG_ICR);
1804 1863
1805 spin_unlock_irq(&uap->port.lock); 1864 spin_unlock_irq(&uap->port.lock);
1806} 1865}
@@ -2178,7 +2237,7 @@ pl011_console_write(struct console *co, const char *s, unsigned int count)
2178 */ 2237 */
2179 do { 2238 do {
2180 status = pl011_readw(uap, REG_FR); 2239 status = pl011_readw(uap, REG_FR);
2181 } while (status & UART01x_FR_BUSY); 2240 } while (status & uap->fr_busy);
2182 if (!uap->vendor->always_enabled) 2241 if (!uap->vendor->always_enabled)
2183 pl011_writew(uap, old_cr, REG_CR); 2242 pl011_writew(uap, old_cr, REG_CR);
2184 2243
@@ -2295,7 +2354,7 @@ static void pl011_putc(struct uart_port *port, int c)
2295 while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) 2354 while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF)
2296 ; 2355 ;
2297 pl011_writeb(uap, c, REG_DR); 2356 pl011_writeb(uap, c, REG_DR);
2298 while (pl011_readw(uap, REG_FR) & UART01x_FR_BUSY) 2357 while (pl011_readw(uap, REG_FR) & uap->fr_busy)
2299 ; 2358 ;
2300} 2359}
2301 2360
@@ -2441,6 +2500,7 @@ static int pl011_register_port(struct uart_amba_port *uap)
2441 return ret; 2500 return ret;
2442} 2501}
2443 2502
2503#ifdef CONFIG_ARM_AMBA
2444static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2504static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2445{ 2505{
2446 struct uart_amba_port *uap; 2506 struct uart_amba_port *uap;
@@ -2464,6 +2524,10 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2464 uap->reg_lut = vendor->reg_lut; 2524 uap->reg_lut = vendor->reg_lut;
2465 uap->lcrh_rx = vendor->lcrh_rx; 2525 uap->lcrh_rx = vendor->lcrh_rx;
2466 uap->lcrh_tx = vendor->lcrh_tx; 2526 uap->lcrh_tx = vendor->lcrh_tx;
2527 uap->fr_busy = vendor->fr_busy;
2528 uap->fr_dsr = vendor->fr_dsr;
2529 uap->fr_cts = vendor->fr_cts;
2530 uap->fr_ri = vendor->fr_ri;
2467 uap->fifosize = vendor->get_fifosize(dev); 2531 uap->fifosize = vendor->get_fifosize(dev);
2468 uap->port.irq = dev->irq[0]; 2532 uap->port.irq = dev->irq[0];
2469 uap->port.ops = &amba_pl011_pops; 2533 uap->port.ops = &amba_pl011_pops;
@@ -2487,6 +2551,67 @@ static int pl011_remove(struct amba_device *dev)
2487 pl011_unregister_port(uap); 2551 pl011_unregister_port(uap);
2488 return 0; 2552 return 0;
2489} 2553}
2554#endif
2555
2556#ifdef CONFIG_SOC_ZX296702
2557static int zx_uart_probe(struct platform_device *pdev)
2558{
2559 struct uart_amba_port *uap;
2560 struct vendor_data *vendor = &vendor_zte;
2561 struct resource *res;
2562 int portnr, ret;
2563
2564 portnr = pl011_find_free_port();
2565 if (portnr < 0)
2566 return portnr;
2567
2568 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2569 GFP_KERNEL);
2570 if (!uap) {
2571 ret = -ENOMEM;
2572 goto out;
2573 }
2574
2575 uap->clk = devm_clk_get(&pdev->dev, NULL);
2576 if (IS_ERR(uap->clk)) {
2577 ret = PTR_ERR(uap->clk);
2578 goto out;
2579 }
2580
2581 uap->vendor = vendor;
2582 uap->reg_lut = vendor->reg_lut;
2583 uap->lcrh_rx = vendor->lcrh_rx;
2584 uap->lcrh_tx = vendor->lcrh_tx;
2585 uap->fr_busy = vendor->fr_busy;
2586 uap->fr_dsr = vendor->fr_dsr;
2587 uap->fr_cts = vendor->fr_cts;
2588 uap->fr_ri = vendor->fr_ri;
2589 uap->fifosize = 16;
2590 uap->port.irq = platform_get_irq(pdev, 0);
2591 uap->port.ops = &amba_pl011_pops;
2592
2593 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2594
2595 ret = pl011_setup_port(&pdev->dev, uap, res, portnr);
2596 if (ret)
2597 return ret;
2598
2599 platform_set_drvdata(pdev, uap);
2600
2601 return pl011_register_port(uap);
2602out:
2603 return ret;
2604}
2605
2606static int zx_uart_remove(struct platform_device *pdev)
2607{
2608 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2609
2610 uart_remove_one_port(&amba_reg, &uap->port);
2611 pl011_unregister_port(uap);
2612 return 0;
2613}
2614#endif
2490 2615
2491#ifdef CONFIG_PM_SLEEP 2616#ifdef CONFIG_PM_SLEEP
2492static int pl011_suspend(struct device *dev) 2617static int pl011_suspend(struct device *dev)
@@ -2544,6 +2669,10 @@ static int sbsa_uart_probe(struct platform_device *pdev)
2544 2669
2545 uap->vendor = &vendor_sbsa; 2670 uap->vendor = &vendor_sbsa;
2546 uap->reg_lut = vendor_sbsa.reg_lut; 2671 uap->reg_lut = vendor_sbsa.reg_lut;
2672 uap->fr_busy = vendor_sbsa.fr_busy;
2673 uap->fr_dsr = vendor_sbsa.fr_dsr;
2674 uap->fr_cts = vendor_sbsa.fr_cts;
2675 uap->fr_ri = vendor_sbsa.fr_ri;
2547 uap->fifosize = 32; 2676 uap->fifosize = 32;
2548 uap->port.irq = platform_get_irq(pdev, 0); 2677 uap->port.irq = platform_get_irq(pdev, 0);
2549 uap->port.ops = &sbsa_uart_pops; 2678 uap->port.ops = &sbsa_uart_pops;
@@ -2593,6 +2722,7 @@ static struct platform_driver arm_sbsa_uart_platform_driver = {
2593 }, 2722 },
2594}; 2723};
2595 2724
2725#ifdef CONFIG_ARM_AMBA
2596static struct amba_id pl011_ids[] = { 2726static struct amba_id pl011_ids[] = {
2597 { 2727 {
2598 .id = 0x00041011, 2728 .id = 0x00041011,
@@ -2618,20 +2748,57 @@ static struct amba_driver pl011_driver = {
2618 .probe = pl011_probe, 2748 .probe = pl011_probe,
2619 .remove = pl011_remove, 2749 .remove = pl011_remove,
2620}; 2750};
2751#endif
2752
2753#ifdef CONFIG_SOC_ZX296702
2754static const struct of_device_id zx_uart_dt_ids[] = {
2755 { .compatible = "zte,zx296702-uart", },
2756 { /* sentinel */ }
2757};
2758MODULE_DEVICE_TABLE(of, zx_uart_dt_ids);
2759
2760static struct platform_driver zx_uart_driver = {
2761 .driver = {
2762 .name = "zx-uart",
2763 .owner = THIS_MODULE,
2764 .pm = &pl011_dev_pm_ops,
2765 .of_match_table = zx_uart_dt_ids,
2766 },
2767 .probe = zx_uart_probe,
2768 .remove = zx_uart_remove,
2769};
2770#endif
2771
2621 2772
2622static int __init pl011_init(void) 2773static int __init pl011_init(void)
2623{ 2774{
2775 int ret;
2624 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 2776 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2625 2777
2626 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 2778 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2627 pr_warn("could not register SBSA UART platform driver\n"); 2779 pr_warn("could not register SBSA UART platform driver\n");
2628 return amba_driver_register(&pl011_driver); 2780
2781#ifdef CONFIG_SOC_ZX296702
2782 ret = platform_driver_register(&zx_uart_driver);
2783 if (ret)
2784 pr_warn("could not register ZX UART platform driver\n");
2785#endif
2786
2787#ifdef CONFIG_ARM_AMBA
2788 ret = amba_driver_register(&pl011_driver);
2789#endif
2790 return ret;
2629} 2791}
2630 2792
2631static void __exit pl011_exit(void) 2793static void __exit pl011_exit(void)
2632{ 2794{
2633 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 2795 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2796#ifdef CONFIG_SOC_ZX296702
2797 platform_driver_unregister(&zx_uart_driver);
2798#endif
2799#ifdef CONFIG_ARM_AMBA
2634 amba_driver_unregister(&pl011_driver); 2800 amba_driver_unregister(&pl011_driver);
2801#endif
2635} 2802}
2636 2803
2637/* 2804/*
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index 0ddb5c02ad8b..6a0a89ed7f81 100644
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -33,12 +33,14 @@
33#define UART01x_DR 0x00 /* Data read or written from the interface. */ 33#define UART01x_DR 0x00 /* Data read or written from the interface. */
34#define UART01x_RSR 0x04 /* Receive status register (Read). */ 34#define UART01x_RSR 0x04 /* Receive status register (Read). */
35#define UART01x_ECR 0x04 /* Error clear register (Write). */ 35#define UART01x_ECR 0x04 /* Error clear register (Write). */
36#define ZX_UART01x_DR 0x04 /* Data read or written from the interface. */
36#define UART010_LCRH 0x08 /* Line control register, high byte. */ 37#define UART010_LCRH 0x08 /* Line control register, high byte. */
37#define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */ 38#define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */
38#define UART010_LCRM 0x0C /* Line control register, middle byte. */ 39#define UART010_LCRM 0x0C /* Line control register, middle byte. */
39#define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */ 40#define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */
40#define UART010_LCRL 0x10 /* Line control register, low byte. */ 41#define UART010_LCRL 0x10 /* Line control register, low byte. */
41#define UART010_CR 0x14 /* Control register. */ 42#define UART010_CR 0x14 /* Control register. */
43#define ZX_UART01x_FR 0x14 /* Flag register (Read only). */
42#define UART01x_FR 0x18 /* Flag register (Read only). */ 44#define UART01x_FR 0x18 /* Flag register (Read only). */
43#define UART010_IIR 0x1C /* Interrupt identification register (Read). */ 45#define UART010_IIR 0x1C /* Interrupt identification register (Read). */
44#define UART010_ICR 0x1C /* Interrupt clear register (Write). */ 46#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
@@ -49,13 +51,21 @@
49#define UART011_LCRH 0x2c /* Line control register. */ 51#define UART011_LCRH 0x2c /* Line control register. */
50#define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */ 52#define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
51#define UART011_CR 0x30 /* Control register. */ 53#define UART011_CR 0x30 /* Control register. */
54#define ZX_UART011_LCRH_TX 0x30 /* Tx Line control register. */
52#define UART011_IFLS 0x34 /* Interrupt fifo level select. */ 55#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
56#define ZX_UART011_CR 0x34 /* Control register. */
57#define ZX_UART011_IFLS 0x38 /* Interrupt fifo level select. */
53#define UART011_IMSC 0x38 /* Interrupt mask. */ 58#define UART011_IMSC 0x38 /* Interrupt mask. */
54#define UART011_RIS 0x3c /* Raw interrupt status. */ 59#define UART011_RIS 0x3c /* Raw interrupt status. */
55#define UART011_MIS 0x40 /* Masked interrupt status. */ 60#define UART011_MIS 0x40 /* Masked interrupt status. */
61#define ZX_UART011_IMSC 0x40 /* Interrupt mask. */
56#define UART011_ICR 0x44 /* Interrupt clear register. */ 62#define UART011_ICR 0x44 /* Interrupt clear register. */
63#define ZX_UART011_RIS 0x44 /* Raw interrupt status. */
57#define UART011_DMACR 0x48 /* DMA control register. */ 64#define UART011_DMACR 0x48 /* DMA control register. */
65#define ZX_UART011_MIS 0x48 /* Masked interrupt status. */
66#define ZX_UART011_ICR 0x4c /* Interrupt clear register. */
58#define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */ 67#define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */
68#define ZX_UART011_DMACR 0x50 /* DMA control register. */
59#define ST_UART011_XON1 0x54 /* XON1 register. */ 69#define ST_UART011_XON1 0x54 /* XON1 register. */
60#define ST_UART011_XON2 0x58 /* XON2 register. */ 70#define ST_UART011_XON2 0x58 /* XON2 register. */
61#define ST_UART011_XOFF1 0x5C /* XON1 register. */ 71#define ST_UART011_XOFF1 0x5C /* XON1 register. */
@@ -75,15 +85,19 @@
75#define UART01x_RSR_PE 0x02 85#define UART01x_RSR_PE 0x02
76#define UART01x_RSR_FE 0x01 86#define UART01x_RSR_FE 0x01
77 87
88#define ZX_UART01x_FR_BUSY 0x300
78#define UART011_FR_RI 0x100 89#define UART011_FR_RI 0x100
79#define UART011_FR_TXFE 0x080 90#define UART011_FR_TXFE 0x080
80#define UART011_FR_RXFF 0x040 91#define UART011_FR_RXFF 0x040
81#define UART01x_FR_TXFF 0x020 92#define UART01x_FR_TXFF 0x020
82#define UART01x_FR_RXFE 0x010 93#define UART01x_FR_RXFE 0x010
83#define UART01x_FR_BUSY 0x008 94#define UART01x_FR_BUSY 0x008
95#define ZX_UART01x_FR_DSR 0x008
84#define UART01x_FR_DCD 0x004 96#define UART01x_FR_DCD 0x004
85#define UART01x_FR_DSR 0x002 97#define UART01x_FR_DSR 0x002
98#define ZX_UART01x_FR_CTS 0x002
86#define UART01x_FR_CTS 0x001 99#define UART01x_FR_CTS 0x001
100#define ZX_UART011_FR_RI 0x001
87#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY) 101#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
88 102
89#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */ 103#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */