diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-05-18 13:09:20 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-05-18 13:09:20 -0400 |
commit | 8ccaecd014bcb52cd6651fb8be15dca6e6b9e04f (patch) | |
tree | 53cea8c0d4c42ba056388940bae6a9c61bb84449 | |
parent | 163ced613c37a504f8ed94676fd21c85183d8e8c (diff) | |
parent | bc519d9574618e47a0c788000fb78da95e18d953 (diff) |
Merge tag 'spi-fix-v4.17-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"A small collection of fixes accumilated since the merge window, all
fairly small and driver specific"
* tag 'spi-fix-v4.17-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: bcm2835aux: ensure interrupts are enabled for shared handler
spi: bcm-qspi: Always read and set BSPI_MAST_N_BOOT_CTRL
spi: bcm-qspi: Avoid setting MSPI_CDRAM_PCS for spi-nor master
spi: pxa2xx: Allow 64-bit DMA
spi: cadence: Add usleep_range() for cdns_spi_fill_tx_fifo()
spi: sh-msiof: Fix bit field overflow writes to TSCR/RSCR
spi: imx: Update MODULE_DESCRIPTION to "SPI Controller driver"
-rw-r--r-- | drivers/spi/spi-bcm-qspi.c | 28 | ||||
-rw-r--r-- | drivers/spi/spi-bcm2835aux.c | 5 | ||||
-rw-r--r-- | drivers/spi/spi-cadence.c | 8 | ||||
-rw-r--r-- | drivers/spi/spi-imx.c | 2 | ||||
-rw-r--r-- | drivers/spi/spi-pxa2xx.h | 2 | ||||
-rw-r--r-- | drivers/spi/spi-sh-msiof.c | 1 |
6 files changed, 34 insertions, 12 deletions
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 1596d35498c5..6573152ce893 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c | |||
@@ -490,7 +490,7 @@ static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi, | |||
490 | 490 | ||
491 | static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi) | 491 | static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi) |
492 | { | 492 | { |
493 | if (!has_bspi(qspi) || (qspi->bspi_enabled)) | 493 | if (!has_bspi(qspi)) |
494 | return; | 494 | return; |
495 | 495 | ||
496 | qspi->bspi_enabled = 1; | 496 | qspi->bspi_enabled = 1; |
@@ -505,7 +505,7 @@ static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi) | |||
505 | 505 | ||
506 | static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi) | 506 | static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi) |
507 | { | 507 | { |
508 | if (!has_bspi(qspi) || (!qspi->bspi_enabled)) | 508 | if (!has_bspi(qspi)) |
509 | return; | 509 | return; |
510 | 510 | ||
511 | qspi->bspi_enabled = 0; | 511 | qspi->bspi_enabled = 0; |
@@ -519,16 +519,19 @@ static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi) | |||
519 | 519 | ||
520 | static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs) | 520 | static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs) |
521 | { | 521 | { |
522 | u32 data = 0; | 522 | u32 rd = 0; |
523 | u32 wr = 0; | ||
523 | 524 | ||
524 | if (qspi->curr_cs == cs) | ||
525 | return; | ||
526 | if (qspi->base[CHIP_SELECT]) { | 525 | if (qspi->base[CHIP_SELECT]) { |
527 | data = bcm_qspi_read(qspi, CHIP_SELECT, 0); | 526 | rd = bcm_qspi_read(qspi, CHIP_SELECT, 0); |
528 | data = (data & ~0xff) | (1 << cs); | 527 | wr = (rd & ~0xff) | (1 << cs); |
529 | bcm_qspi_write(qspi, CHIP_SELECT, 0, data); | 528 | if (rd == wr) |
529 | return; | ||
530 | bcm_qspi_write(qspi, CHIP_SELECT, 0, wr); | ||
530 | usleep_range(10, 20); | 531 | usleep_range(10, 20); |
531 | } | 532 | } |
533 | |||
534 | dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs); | ||
532 | qspi->curr_cs = cs; | 535 | qspi->curr_cs = cs; |
533 | } | 536 | } |
534 | 537 | ||
@@ -755,8 +758,13 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) | |||
755 | dev_dbg(&qspi->pdev->dev, "WR %04x\n", val); | 758 | dev_dbg(&qspi->pdev->dev, "WR %04x\n", val); |
756 | } | 759 | } |
757 | mspi_cdram = MSPI_CDRAM_CONT_BIT; | 760 | mspi_cdram = MSPI_CDRAM_CONT_BIT; |
758 | mspi_cdram |= (~(1 << spi->chip_select) & | 761 | |
759 | MSPI_CDRAM_PCS); | 762 | if (has_bspi(qspi)) |
763 | mspi_cdram &= ~1; | ||
764 | else | ||
765 | mspi_cdram |= (~(1 << spi->chip_select) & | ||
766 | MSPI_CDRAM_PCS); | ||
767 | |||
760 | mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 : | 768 | mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 : |
761 | MSPI_CDRAM_BITSE_BIT); | 769 | MSPI_CDRAM_BITSE_BIT); |
762 | 770 | ||
diff --git a/drivers/spi/spi-bcm2835aux.c b/drivers/spi/spi-bcm2835aux.c index 1431cb98fe40..3094d818cf06 100644 --- a/drivers/spi/spi-bcm2835aux.c +++ b/drivers/spi/spi-bcm2835aux.c | |||
@@ -184,6 +184,11 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id) | |||
184 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); | 184 | struct bcm2835aux_spi *bs = spi_master_get_devdata(master); |
185 | irqreturn_t ret = IRQ_NONE; | 185 | irqreturn_t ret = IRQ_NONE; |
186 | 186 | ||
187 | /* IRQ may be shared, so return if our interrupts are disabled */ | ||
188 | if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) & | ||
189 | (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE))) | ||
190 | return ret; | ||
191 | |||
187 | /* check if we have data to read */ | 192 | /* check if we have data to read */ |
188 | while (bs->rx_len && | 193 | while (bs->rx_len && |
189 | (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & | 194 | (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) & |
diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index 5c9516ae4942..4a001634023e 100644 --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c | |||
@@ -313,6 +313,14 @@ static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi) | |||
313 | 313 | ||
314 | while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) && | 314 | while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) && |
315 | (xspi->tx_bytes > 0)) { | 315 | (xspi->tx_bytes > 0)) { |
316 | |||
317 | /* When xspi in busy condition, bytes may send failed, | ||
318 | * then spi control did't work thoroughly, add one byte delay | ||
319 | */ | ||
320 | if (cdns_spi_read(xspi, CDNS_SPI_ISR) & | ||
321 | CDNS_SPI_IXR_TXFULL) | ||
322 | usleep_range(10, 20); | ||
323 | |||
316 | if (xspi->txbuf) | 324 | if (xspi->txbuf) |
317 | cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++); | 325 | cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++); |
318 | else | 326 | else |
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 6f57592a7f95..a056ee88a960 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c | |||
@@ -1701,7 +1701,7 @@ static struct platform_driver spi_imx_driver = { | |||
1701 | }; | 1701 | }; |
1702 | module_platform_driver(spi_imx_driver); | 1702 | module_platform_driver(spi_imx_driver); |
1703 | 1703 | ||
1704 | MODULE_DESCRIPTION("SPI Master Controller driver"); | 1704 | MODULE_DESCRIPTION("SPI Controller driver"); |
1705 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | 1705 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
1706 | MODULE_LICENSE("GPL"); | 1706 | MODULE_LICENSE("GPL"); |
1707 | MODULE_ALIAS("platform:" DRIVER_NAME); | 1707 | MODULE_ALIAS("platform:" DRIVER_NAME); |
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h index 513ec6c6e25b..0ae7defd3492 100644 --- a/drivers/spi/spi-pxa2xx.h +++ b/drivers/spi/spi-pxa2xx.h | |||
@@ -38,7 +38,7 @@ struct driver_data { | |||
38 | 38 | ||
39 | /* SSP register addresses */ | 39 | /* SSP register addresses */ |
40 | void __iomem *ioaddr; | 40 | void __iomem *ioaddr; |
41 | u32 ssdr_physical; | 41 | phys_addr_t ssdr_physical; |
42 | 42 | ||
43 | /* SSP masks*/ | 43 | /* SSP masks*/ |
44 | u32 dma_cr1; | 44 | u32 dma_cr1; |
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index ae086aab57d5..8171eedbfc90 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c | |||
@@ -283,6 +283,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |||
283 | } | 283 | } |
284 | 284 | ||
285 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1); | 285 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1); |
286 | brps = min_t(int, brps, 32); | ||
286 | 287 | ||
287 | scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps); | 288 | scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps); |
288 | sh_msiof_write(p, TSCR, scr); | 289 | sh_msiof_write(p, TSCR, scr); |