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authorJerome Brunet <jbrunet@baylibre.com>2018-08-29 11:45:51 -0400
committerKevin Hilman <khilman@baylibre.com>2018-09-13 00:14:33 -0400
commit8c0cf40f06af01eb3e14b19ec29f384b5030a85e (patch)
tree9cbcce7ddc896250e6d5340c1f7db9f50dcfc645
parent6f59dc1afbb2e12b218206c03c974dc93dc7db19 (diff)
arm64: dts: meson-axg: sort nodes consistently
Sort DT nodes by address when possible, by node node name otherwise. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-axg-s400.dts212
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-axg.dtsi1630
2 files changed, 921 insertions, 921 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index d399078d1f0c..ff64c429d432 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -60,6 +60,37 @@
60 serial1 = &uart_A; 60 serial1 = &uart_A;
61 }; 61 };
62 62
63 linein: audio-codec@0 {
64 #sound-dai-cells = <0>;
65 compatible = "everest,es7241";
66 VDDA-supply = <&vcc_3v3>;
67 VDDP-supply = <&vcc_3v3>;
68 VDDD-supply = <&vcc_3v3>;
69 status = "okay";
70 sound-name-prefix = "Linein";
71 };
72
73 lineout: audio-codec@1 {
74 #sound-dai-cells = <0>;
75 compatible = "everest,es7154";
76 VDD-supply = <&vcc_3v3>;
77 PVDD-supply = <&vcc_5v>;
78 status = "okay";
79 sound-name-prefix = "Lineout";
80 };
81
82 spdif_dit: audio-codec@2 {
83 #sound-dai-cells = <0>;
84 compatible = "linux,spdif-dit";
85 status = "okay";
86 sound-name-prefix = "DIT";
87 };
88
89 emmc_pwrseq: emmc-pwrseq {
90 compatible = "mmc-pwrseq-emmc";
91 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
92 };
93
63 main_12v: regulator-main_12v { 94 main_12v: regulator-main_12v {
64 compatible = "regulator-fixed"; 95 compatible = "regulator-fixed";
65 regulator-name = "12V"; 96 regulator-name = "12V";
@@ -68,15 +99,26 @@
68 regulator-always-on; 99 regulator-always-on;
69 }; 100 };
70 101
71 vddio_boot: regulator-vddio_boot { 102 vcc_3v3: regulator-vcc_3v3 {
72 compatible = "regulator-fixed"; 103 compatible = "regulator-fixed";
73 regulator-name = "VDDIO_BOOT"; 104 regulator-name = "VCC_3V3";
74 regulator-min-microvolt = <1800000>; 105 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <1800000>; 106 regulator-max-microvolt = <3300000>;
76 vin-supply = <&vddao_3v3>; 107 vin-supply = <&vddao_3v3>;
77 regulator-always-on; 108 regulator-always-on;
78 }; 109 };
79 110
111 vcc_5v: regulator-vcc_5v {
112 compatible = "regulator-fixed";
113 regulator-name = "VCC5V";
114 regulator-min-microvolt = <5000000>;
115 regulator-max-microvolt = <5000000>;
116 vin-supply = <&main_12v>;
117
118 gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
119 enable-active-high;
120 };
121
80 vddao_3v3: regulator-vddao_3v3 { 122 vddao_3v3: regulator-vddao_3v3 {
81 compatible = "regulator-fixed"; 123 compatible = "regulator-fixed";
82 regulator-name = "VDDAO_3V3"; 124 regulator-name = "VDDAO_3V3";
@@ -95,26 +137,15 @@
95 regulator-always-on; 137 regulator-always-on;
96 }; 138 };
97 139
98 vcc_3v3: regulator-vcc_3v3 { 140 vddio_boot: regulator-vddio_boot {
99 compatible = "regulator-fixed"; 141 compatible = "regulator-fixed";
100 regulator-name = "VCC_3V3"; 142 regulator-name = "VDDIO_BOOT";
101 regulator-min-microvolt = <3300000>; 143 regulator-min-microvolt = <1800000>;
102 regulator-max-microvolt = <3300000>; 144 regulator-max-microvolt = <1800000>;
103 vin-supply = <&vddao_3v3>; 145 vin-supply = <&vddao_3v3>;
104 regulator-always-on; 146 regulator-always-on;
105 }; 147 };
106 148
107 vcc_5v: regulator-vcc_5v {
108 compatible = "regulator-fixed";
109 regulator-name = "VCC5V";
110 regulator-min-microvolt = <5000000>;
111 regulator-max-microvolt = <5000000>;
112 vin-supply = <&main_12v>;
113
114 gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
115 enable-active-high;
116 };
117
118 usb_pwr: regulator-usb_pwr { 149 usb_pwr: regulator-usb_pwr {
119 compatible = "regulator-fixed"; 150 compatible = "regulator-fixed";
120 regulator-name = "USB_PWR"; 151 regulator-name = "USB_PWR";
@@ -126,11 +157,6 @@
126 enable-active-high; 157 enable-active-high;
127 }; 158 };
128 159
129 emmc_pwrseq: emmc-pwrseq {
130 compatible = "mmc-pwrseq-emmc";
131 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
132 };
133
134 sdio_pwrseq: sdio-pwrseq { 160 sdio_pwrseq: sdio-pwrseq {
135 compatible = "mmc-pwrseq-simple"; 161 compatible = "mmc-pwrseq-simple";
136 reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; 162 reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
@@ -138,13 +164,6 @@
138 clock-names = "ext_clock"; 164 clock-names = "ext_clock";
139 }; 165 };
140 166
141 wifi32k: wifi32k {
142 compatible = "pwm-clock";
143 #clock-cells = <0>;
144 clock-frequency = <32768>;
145 pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
146 };
147
148 speaker-leds { 167 speaker-leds {
149 compatible = "gpio-leds"; 168 compatible = "gpio-leds";
150 169
@@ -179,32 +198,6 @@
179 }; 198 };
180 }; 199 };
181 200
182 linein: audio-codec@0 {
183 #sound-dai-cells = <0>;
184 compatible = "everest,es7241";
185 VDDA-supply = <&vcc_3v3>;
186 VDDP-supply = <&vcc_3v3>;
187 VDDD-supply = <&vcc_3v3>;
188 status = "okay";
189 sound-name-prefix = "Linein";
190 };
191
192 lineout: audio-codec@1 {
193 #sound-dai-cells = <0>;
194 compatible = "everest,es7154";
195 VDD-supply = <&vcc_3v3>;
196 PVDD-supply = <&vcc_5v>;
197 status = "okay";
198 sound-name-prefix = "Lineout";
199 };
200
201 spdif_dit: audio-codec@2 {
202 #sound-dai-cells = <0>;
203 compatible = "linux,spdif-dit";
204 status = "okay";
205 sound-name-prefix = "DIT";
206 };
207
208 sound { 201 sound {
209 compatible = "amlogic,axg-sound-card"; 202 compatible = "amlogic,axg-sound-card";
210 model = "AXG-S400"; 203 model = "AXG-S400";
@@ -311,6 +304,13 @@
311 }; 304 };
312 }; 305 };
313 }; 306 };
307
308 wifi32k: wifi32k {
309 compatible = "pwm-clock";
310 #clock-cells = <0>;
311 clock-frequency = <32768>;
312 pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
313 };
314}; 314};
315 315
316&ethmac { 316&ethmac {
@@ -345,18 +345,6 @@
345 status = "okay"; 345 status = "okay";
346}; 346};
347 347
348&uart_A {
349 status = "okay";
350 pinctrl-0 = <&uart_a_pins>;
351 pinctrl-names = "default";
352};
353
354&uart_AO {
355 status = "okay";
356 pinctrl-0 = <&uart_ao_a_pins>;
357 pinctrl-names = "default";
358};
359
360&ir { 348&ir {
361 status = "okay"; 349 status = "okay";
362 pinctrl-0 = <&remote_input_ao_pins>; 350 pinctrl-0 = <&remote_input_ao_pins>;
@@ -403,24 +391,9 @@
403 pinctrl-names = "default"; 391 pinctrl-names = "default";
404}; 392};
405 393
406/* emmc storage */ 394&saradc {
407&sd_emmc_c {
408 status = "okay"; 395 status = "okay";
409 pinctrl-0 = <&emmc_pins>; 396 vref-supply = <&vddio_ao18>;
410 pinctrl-1 = <&emmc_clk_gate_pins>;
411 pinctrl-names = "default", "clk-gate";
412
413 bus-width = <8>;
414 cap-sd-highspeed;
415 cap-mmc-highspeed;
416 max-frequency = <180000000>;
417 non-removable;
418 disable-wp;
419 mmc-ddr-1_8v;
420 mmc-hs200-1_8v;
421
422 vmmc-supply = <&vcc_3v3>;
423 vqmmc-supply = <&vddio_boot>;
424}; 397};
425 398
426/* wifi module */ 399/* wifi module */
@@ -450,9 +423,24 @@
450 }; 423 };
451}; 424};
452 425
453&saradc { 426/* emmc storage */
427&sd_emmc_c {
454 status = "okay"; 428 status = "okay";
455 vref-supply = <&vddio_ao18>; 429 pinctrl-0 = <&emmc_pins>;
430 pinctrl-1 = <&emmc_clk_gate_pins>;
431 pinctrl-names = "default", "clk-gate";
432
433 bus-width = <8>;
434 cap-sd-highspeed;
435 cap-mmc-highspeed;
436 max-frequency = <180000000>;
437 non-removable;
438 disable-wp;
439 mmc-ddr-1_8v;
440 mmc-hs200-1_8v;
441
442 vmmc-supply = <&vcc_3v3>;
443 vqmmc-supply = <&vddio_boot>;
456}; 444};
457 445
458&spdifout { 446&spdifout {
@@ -461,45 +449,45 @@
461 status = "okay"; 449 status = "okay";
462}; 450};
463 451
464&tdmin_a { 452&tdmif_a {
453 pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
454 <&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
455 pinctrl-names = "default";
465 status = "okay"; 456 status = "okay";
466}; 457};
467 458
468&tdmin_b { 459&tdmif_b {
460 pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
461 <&tdmb_din3_pins>, <&mclk_b_pins>;
462 pinctrl-names = "default";
469 status = "okay"; 463 status = "okay";
470}; 464};
471 465
472&tdmin_c { 466&tdmif_c {
467 pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
468 <&tdmc_din1_pins>, <&tdmc_dout2_pins>,
469 <&mclk_c_pins>;
470 pinctrl-names = "default";
473 status = "okay"; 471 status = "okay";
474}; 472};
475 473
476&tdmin_lb { 474&tdmin_a {
477 status = "okay"; 475 status = "okay";
478}; 476};
479 477
480&tdmout_c { 478&tdmin_b {
481 status = "okay"; 479 status = "okay";
482}; 480};
483 481
484&tdmif_a { 482&tdmin_c {
485 pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
486 <&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
487 pinctrl-names = "default";
488 status = "okay"; 483 status = "okay";
489}; 484};
490 485
491&tdmif_b { 486&tdmin_lb {
492 pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
493 <&tdmb_din3_pins>, <&mclk_b_pins>;
494 pinctrl-names = "default";
495 status = "okay"; 487 status = "okay";
496}; 488};
497 489
498&tdmif_c { 490&tdmout_c {
499 pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
500 <&tdmc_din1_pins>, <&tdmc_dout2_pins>,
501 <&mclk_c_pins>;
502 pinctrl-names = "default";
503 status = "okay"; 491 status = "okay";
504}; 492};
505 493
@@ -514,3 +502,15 @@
514&toddr_c { 502&toddr_c {
515 status = "okay"; 503 status = "okay";
516}; 504};
505
506&uart_A {
507 status = "okay";
508 pinctrl-0 = <&uart_a_pins>;
509 pinctrl-names = "default";
510};
511
512&uart_AO {
513 status = "okay";
514 pinctrl-0 = <&uart_ao_a_pins>;
515 pinctrl-names = "default";
516};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 32f6dcacc2bc..36be63d69e7f 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -3,15 +3,15 @@
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */ 4 */
5 5
6#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/clock/axg-aoclkc.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/axg-audio-clkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h>
10#include <dt-bindings/clock/axg-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h>
11#include <dt-bindings/clock/axg-aoclkc.h> 9#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/gpio/meson-axg-gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h>
13#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15 15
16/ { 16/ {
17 compatible = "amlogic,meson-axg"; 17 compatible = "amlogic,meson-axg";
@@ -20,22 +20,53 @@
20 #address-cells = <2>; 20 #address-cells = <2>;
21 #size-cells = <2>; 21 #size-cells = <2>;
22 22
23 reserved-memory { 23 tdmif_a: audio-controller@0 {
24 #address-cells = <2>; 24 compatible = "amlogic,axg-tdm-iface";
25 #size-cells = <2>; 25 #sound-dai-cells = <0>;
26 ranges; 26 sound-name-prefix = "TDM_A";
27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
28 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
30 clock-names = "mclk", "sclk", "lrclk";
31 status = "disabled";
32 };
27 33
28 /* 16 MiB reserved for Hardware ROM Firmware */ 34 tdmif_b: audio-controller@1 {
29 hwrom_reserved: hwrom@0 { 35 compatible = "amlogic,axg-tdm-iface";
30 reg = <0x0 0x0 0x0 0x1000000>; 36 #sound-dai-cells = <0>;
31 no-map; 37 sound-name-prefix = "TDM_B";
32 }; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
39 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
41 clock-names = "mclk", "sclk", "lrclk";
42 status = "disabled";
43 };
33 44
34 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 45 tdmif_c: audio-controller@2 {
35 secmon_reserved: secmon@5000000 { 46 compatible = "amlogic,axg-tdm-iface";
36 reg = <0x0 0x05000000 0x0 0x300000>; 47 #sound-dai-cells = <0>;
37 no-map; 48 sound-name-prefix = "TDM_C";
38 }; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
50 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
52 clock-names = "mclk", "sclk", "lrclk";
53 status = "disabled";
54 };
55
56 ao_alt_xtal: ao_alt_xtal-clk {
57 compatible = "fixed-clock";
58 clock-frequency = <32000000>;
59 clock-output-names = "ao_alt_xtal";
60 #clock-cells = <0>;
61 };
62
63 arm-pmu {
64 compatible = "arm,cortex-a53-pmu";
65 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
39 }; 70 };
40 71
41 cpus { 72 cpus {
@@ -79,77 +110,27 @@
79 }; 110 };
80 }; 111 };
81 112
82 arm-pmu {
83 compatible = "arm,cortex-a53-pmu";
84 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
88 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
89 };
90
91 psci { 113 psci {
92 compatible = "arm,psci-1.0"; 114 compatible = "arm,psci-1.0";
93 method = "smc"; 115 method = "smc";
94 }; 116 };
95 117
96 tdmif_a: audio-controller@0 { 118 reserved-memory {
97 compatible = "amlogic,axg-tdm-iface"; 119 #address-cells = <2>;
98 #sound-dai-cells = <0>; 120 #size-cells = <2>;
99 sound-name-prefix = "TDM_A"; 121 ranges;
100 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
101 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
102 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
103 clock-names = "mclk", "sclk", "lrclk";
104 status = "disabled";
105 };
106
107 tdmif_b: audio-controller@1 {
108 compatible = "amlogic,axg-tdm-iface";
109 #sound-dai-cells = <0>;
110 sound-name-prefix = "TDM_B";
111 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
112 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
113 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
114 clock-names = "mclk", "sclk", "lrclk";
115 status = "disabled";
116 };
117
118 tdmif_c: audio-controller@2 {
119 compatible = "amlogic,axg-tdm-iface";
120 #sound-dai-cells = <0>;
121 sound-name-prefix = "TDM_C";
122 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
123 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
124 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
125 clock-names = "mclk", "sclk", "lrclk";
126 status = "disabled";
127 };
128
129 timer {
130 compatible = "arm,armv8-timer";
131 interrupts = <GIC_PPI 13
132 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
133 <GIC_PPI 14
134 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
135 <GIC_PPI 11
136 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
137 <GIC_PPI 10
138 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
139 };
140 122
141 xtal: xtal-clk { 123 /* 16 MiB reserved for Hardware ROM Firmware */
142 compatible = "fixed-clock"; 124 hwrom_reserved: hwrom@0 {
143 clock-frequency = <24000000>; 125 reg = <0x0 0x0 0x0 0x1000000>;
144 clock-output-names = "xtal"; 126 no-map;
145 #clock-cells = <0>; 127 };
146 };
147 128
148 ao_alt_xtal: ao_alt_xtal-clk { 129 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
149 compatible = "fixed-clock"; 130 secmon_reserved: secmon@5000000 {
150 clock-frequency = <32000000>; 131 reg = <0x0 0x05000000 0x0 0x300000>;
151 clock-output-names = "ao_alt_xtal"; 132 no-map;
152 #clock-cells = <0>; 133 };
153 }; 134 };
154 135
155 soc { 136 soc {
@@ -158,376 +139,10 @@
158 #size-cells = <2>; 139 #size-cells = <2>;
159 ranges; 140 ranges;
160 141
161 apb: apb@ffe00000 {
162 compatible = "simple-bus";
163 reg = <0x0 0xffe00000 0x0 0x200000>;
164 #address-cells = <2>;
165 #size-cells = <2>;
166 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
167
168 sd_emmc_b: sd@5000 {
169 compatible = "amlogic,meson-axg-mmc";
170 reg = <0x0 0x5000 0x0 0x800>;
171 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
172 status = "disabled";
173 clocks = <&clkc CLKID_SD_EMMC_B>,
174 <&clkc CLKID_SD_EMMC_B_CLK0>,
175 <&clkc CLKID_FCLK_DIV2>;
176 clock-names = "core", "clkin0", "clkin1";
177 resets = <&reset RESET_SD_EMMC_B>;
178 };
179
180 sd_emmc_c: mmc@7000 {
181 compatible = "amlogic,meson-axg-mmc";
182 reg = <0x0 0x7000 0x0 0x800>;
183 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
184 status = "disabled";
185 clocks = <&clkc CLKID_SD_EMMC_C>,
186 <&clkc CLKID_SD_EMMC_C_CLK0>,
187 <&clkc CLKID_FCLK_DIV2>;
188 clock-names = "core", "clkin0", "clkin1";
189 resets = <&reset RESET_SD_EMMC_C>;
190 };
191 };
192
193 audio: bus@ff642000 {
194 compatible = "simple-bus";
195 reg = <0x0 0xff642000 0x0 0x2000>;
196 #address-cells = <2>;
197 #size-cells = <2>;
198 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
199
200 clkc_audio: clock-controller@0 {
201 compatible = "amlogic,axg-audio-clkc";
202 reg = <0x0 0x0 0x0 0xb4>;
203 #clock-cells = <1>;
204
205 clocks = <&clkc CLKID_AUDIO>,
206 <&clkc CLKID_MPLL0>,
207 <&clkc CLKID_MPLL1>,
208 <&clkc CLKID_MPLL2>,
209 <&clkc CLKID_MPLL3>,
210 <&clkc CLKID_HIFI_PLL>,
211 <&clkc CLKID_FCLK_DIV3>,
212 <&clkc CLKID_FCLK_DIV4>,
213 <&clkc CLKID_GP0_PLL>;
214 clock-names = "pclk",
215 "mst_in0",
216 "mst_in1",
217 "mst_in2",
218 "mst_in3",
219 "mst_in4",
220 "mst_in5",
221 "mst_in6",
222 "mst_in7";
223
224 resets = <&reset RESET_AUDIO>;
225 };
226
227 toddr_a: audio-controller@100 {
228 compatible = "amlogic,axg-toddr";
229 reg = <0x0 0x100 0x0 0x1c>;
230 #sound-dai-cells = <0>;
231 sound-name-prefix = "TODDR_A";
232 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
233 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
234 resets = <&arb AXG_ARB_TODDR_A>;
235 status = "disabled";
236 };
237
238 toddr_b: audio-controller@140 {
239 compatible = "amlogic,axg-toddr";
240 reg = <0x0 0x140 0x0 0x1c>;
241 #sound-dai-cells = <0>;
242 sound-name-prefix = "TODDR_B";
243 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
244 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
245 resets = <&arb AXG_ARB_TODDR_B>;
246 status = "disabled";
247 };
248
249 toddr_c: audio-controller@180 {
250 compatible = "amlogic,axg-toddr";
251 reg = <0x0 0x180 0x0 0x1c>;
252 #sound-dai-cells = <0>;
253 sound-name-prefix = "TODDR_C";
254 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
255 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
256 resets = <&arb AXG_ARB_TODDR_C>;
257 status = "disabled";
258 };
259
260 frddr_a: audio-controller@1c0 {
261 compatible = "amlogic,axg-frddr";
262 reg = <0x0 0x1c0 0x0 0x1c>;
263 #sound-dai-cells = <0>;
264 sound-name-prefix = "FRDDR_A";
265 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
266 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
267 resets = <&arb AXG_ARB_FRDDR_A>;
268 status = "disabled";
269 };
270
271 frddr_b: audio-controller@200 {
272 compatible = "amlogic,axg-frddr";
273 reg = <0x0 0x200 0x0 0x1c>;
274 #sound-dai-cells = <0>;
275 sound-name-prefix = "FRDDR_B";
276 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
277 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
278 resets = <&arb AXG_ARB_FRDDR_B>;
279 status = "disabled";
280 };
281
282 frddr_c: audio-controller@240 {
283 compatible = "amlogic,axg-frddr";
284 reg = <0x0 0x240 0x0 0x1c>;
285 #sound-dai-cells = <0>;
286 sound-name-prefix = "FRDDR_C";
287 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
288 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
289 resets = <&arb AXG_ARB_FRDDR_C>;
290 status = "disabled";
291 };
292
293 arb: reset-controller@280 {
294 compatible = "amlogic,meson-axg-audio-arb";
295 reg = <0x0 0x280 0x0 0x4>;
296 #reset-cells = <1>;
297 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
298 };
299
300 tdmin_a: audio-controller@300 {
301 compatible = "amlogic,axg-tdmin";
302 reg = <0x0 0x300 0x0 0x40>;
303 sound-name-prefix = "TDMIN_A";
304 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
305 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
306 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
307 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
308 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
309 clock-names = "pclk", "sclk", "sclk_sel",
310 "lrclk", "lrclk_sel";
311 status = "disabled";
312 };
313
314 tdmin_b: audio-controller@340 {
315 compatible = "amlogic,axg-tdmin";
316 reg = <0x0 0x340 0x0 0x40>;
317 sound-name-prefix = "TDMIN_B";
318 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
319 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
320 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
321 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
322 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
323 clock-names = "pclk", "sclk", "sclk_sel",
324 "lrclk", "lrclk_sel";
325 status = "disabled";
326 };
327
328 tdmin_c: audio-controller@380 {
329 compatible = "amlogic,axg-tdmin";
330 reg = <0x0 0x380 0x0 0x40>;
331 sound-name-prefix = "TDMIN_C";
332 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
333 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
334 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
335 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
336 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
337 clock-names = "pclk", "sclk", "sclk_sel",
338 "lrclk", "lrclk_sel";
339 status = "disabled";
340 };
341
342 tdmin_lb: audio-controller@3c0 {
343 compatible = "amlogic,axg-tdmin";
344 reg = <0x0 0x3c0 0x0 0x40>;
345 sound-name-prefix = "TDMIN_LB";
346 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
347 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
348 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
349 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
350 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
351 clock-names = "pclk", "sclk", "sclk_sel",
352 "lrclk", "lrclk_sel";
353 status = "disabled";
354 };
355
356 spdifout: audio-controller@480 {
357 compatible = "amlogic,axg-spdifout";
358 reg = <0x0 0x480 0x0 0x50>;
359 #sound-dai-cells = <0>;
360 sound-name-prefix = "SPDIFOUT";
361 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
362 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
363 clock-names = "pclk", "mclk";
364 status = "disabled";
365 };
366
367 tdmout_a: audio-controller@500 {
368 compatible = "amlogic,axg-tdmout";
369 reg = <0x0 0x500 0x0 0x40>;
370 sound-name-prefix = "TDMOUT_A";
371 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
372 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
373 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
374 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
375 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
376 clock-names = "pclk", "sclk", "sclk_sel",
377 "lrclk", "lrclk_sel";
378 status = "disabled";
379 };
380
381 tdmout_b: audio-controller@540 {
382 compatible = "amlogic,axg-tdmout";
383 reg = <0x0 0x540 0x0 0x40>;
384 sound-name-prefix = "TDMOUT_B";
385 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
386 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
387 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
388 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
389 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
390 clock-names = "pclk", "sclk", "sclk_sel",
391 "lrclk", "lrclk_sel";
392 status = "disabled";
393 };
394
395 tdmout_c: audio-controller@580 {
396 compatible = "amlogic,axg-tdmout";
397 reg = <0x0 0x580 0x0 0x40>;
398 sound-name-prefix = "TDMOUT_C";
399 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
400 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
401 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
402 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
403 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
404 clock-names = "pclk", "sclk", "sclk_sel",
405 "lrclk", "lrclk_sel";
406 status = "disabled";
407 };
408 };
409
410 cbus: bus@ffd00000 {
411 compatible = "simple-bus";
412 reg = <0x0 0xffd00000 0x0 0x25000>;
413 #address-cells = <2>;
414 #size-cells = <2>;
415 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
416
417 gpio_intc: interrupt-controller@f080 {
418 compatible = "amlogic,meson-gpio-intc";
419 reg = <0x0 0xf080 0x0 0x10>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
423 status = "disabled";
424 };
425
426 pwm_ab: pwm@1b000 {
427 compatible = "amlogic,meson-axg-ee-pwm";
428 reg = <0x0 0x1b000 0x0 0x20>;
429 #pwm-cells = <3>;
430 status = "disabled";
431 };
432
433 pwm_cd: pwm@1a000 {
434 compatible = "amlogic,meson-axg-ee-pwm";
435 reg = <0x0 0x1a000 0x0 0x20>;
436 #pwm-cells = <3>;
437 status = "disabled";
438 };
439
440 reset: reset-controller@1004 {
441 compatible = "amlogic,meson-axg-reset";
442 reg = <0x0 0x01004 0x0 0x9c>;
443 #reset-cells = <1>;
444 };
445
446 spicc0: spi@13000 {
447 compatible = "amlogic,meson-axg-spicc";
448 reg = <0x0 0x13000 0x0 0x3c>;
449 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clkc CLKID_SPICC0>;
451 clock-names = "core";
452 #address-cells = <1>;
453 #size-cells = <0>;
454 status = "disabled";
455 };
456
457 spicc1: spi@15000 {
458 compatible = "amlogic,meson-axg-spicc";
459 reg = <0x0 0x15000 0x0 0x3c>;
460 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clkc CLKID_SPICC1>;
462 clock-names = "core";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 status = "disabled";
466 };
467
468 i2c0: i2c@1f000 {
469 compatible = "amlogic,meson-axg-i2c";
470 reg = <0x0 0x1f000 0x0 0x20>;
471 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
472 clocks = <&clkc CLKID_I2C>;
473 #address-cells = <1>;
474 #size-cells = <0>;
475 status = "disabled";
476 };
477
478 i2c1: i2c@1e000 {
479 compatible = "amlogic,meson-axg-i2c";
480 reg = <0x0 0x1e000 0x0 0x20>;
481 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
482 clocks = <&clkc CLKID_I2C>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 status = "disabled";
486 };
487
488 i2c2: i2c@1d000 {
489 compatible = "amlogic,meson-axg-i2c";
490 reg = <0x0 0x1d000 0x0 0x20>;
491 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
492 clocks = <&clkc CLKID_I2C>;
493 #address-cells = <1>;
494 #size-cells = <0>;
495 status = "disabled";
496 };
497
498 i2c3: i2c@1c000 {
499 compatible = "amlogic,meson-axg-i2c";
500 reg = <0x0 0x1c000 0x0 0x20>;
501 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
502 clocks = <&clkc CLKID_I2C>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 status = "disabled";
506 };
507
508 uart_A: serial@24000 {
509 compatible = "amlogic,meson-gx-uart";
510 reg = <0x0 0x24000 0x0 0x18>;
511 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
512 status = "disabled";
513 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
514 clock-names = "xtal", "pclk", "baud";
515 };
516
517 uart_B: serial@23000 {
518 compatible = "amlogic,meson-gx-uart";
519 reg = <0x0 0x23000 0x0 0x18>;
520 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
521 status = "disabled";
522 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
523 clock-names = "xtal", "pclk", "baud";
524 };
525 };
526
527 ethmac: ethernet@ff3f0000 { 142 ethmac: ethernet@ff3f0000 {
528 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 143 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
529 reg = <0x0 0xff3f0000 0x0 0x10000 144 reg = <0x0 0xff3f0000 0x0 0x10000
530 0x0 0xff634540 0x0 0x8>; 145 0x0 0xff634540 0x0 0x8>;
531 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 146 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
532 interrupt-names = "macirq"; 147 interrupt-names = "macirq";
533 clocks = <&clkc CLKID_ETH>, 148 clocks = <&clkc CLKID_ETH>,
@@ -537,54 +152,14 @@
537 status = "disabled"; 152 status = "disabled";
538 }; 153 };
539 154
540 gic: interrupt-controller@ffc01000 { 155 periphs: bus@ff634000 {
541 compatible = "arm,gic-400";
542 reg = <0x0 0xffc01000 0 0x1000>,
543 <0x0 0xffc02000 0 0x2000>,
544 <0x0 0xffc04000 0 0x2000>,
545 <0x0 0xffc06000 0 0x2000>;
546 interrupt-controller;
547 interrupts = <GIC_PPI 9
548 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
549 #interrupt-cells = <3>;
550 #address-cells = <0>;
551 };
552
553 hiubus: bus@ff63c000 {
554 compatible = "simple-bus";
555 reg = <0x0 0xff63c000 0x0 0x1c00>;
556 #address-cells = <2>;
557 #size-cells = <2>;
558 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
559
560 sysctrl: system-controller@0 {
561 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
562 reg = <0 0 0 0x400>;
563
564 clkc: clock-controller {
565 compatible = "amlogic,axg-clkc";
566 #clock-cells = <1>;
567 };
568 };
569 };
570
571 mailbox: mailbox@ff63dc00 {
572 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
573 reg = <0 0xff63dc00 0 0x400>;
574 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
575 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
576 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
577 #mbox-cells = <1>;
578 };
579
580 periphs: periphs@ff634000 {
581 compatible = "simple-bus"; 156 compatible = "simple-bus";
582 reg = <0x0 0xff634000 0x0 0x2000>; 157 reg = <0x0 0xff634000 0x0 0x2000>;
583 #address-cells = <2>; 158 #address-cells = <2>;
584 #size-cells = <2>; 159 #size-cells = <2>;
585 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 160 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
586 161
587 hwrng: rng { 162 hwrng: rng@18 {
588 compatible = "amlogic,meson-rng"; 163 compatible = "amlogic,meson-rng";
589 reg = <0x0 0x18 0x0 0x4>; 164 reg = <0x0 0x18 0x0 0x4>;
590 clocks = <&clkc CLKID_RNG0>; 165 clocks = <&clkc CLKID_RNG0>;
@@ -599,28 +174,92 @@
599 174
600 gpio: bank@480 { 175 gpio: bank@480 {
601 reg = <0x0 0x00480 0x0 0x40>, 176 reg = <0x0 0x00480 0x0 0x40>,
602 <0x0 0x004e8 0x0 0x14>, 177 <0x0 0x004e8 0x0 0x14>,
603 <0x0 0x00520 0x0 0x14>, 178 <0x0 0x00520 0x0 0x14>,
604 <0x0 0x00430 0x0 0x3c>; 179 <0x0 0x00430 0x0 0x3c>;
605 reg-names = "mux", "pull", "pull-enable", "gpio"; 180 reg-names = "mux", "pull", "pull-enable", "gpio";
606 gpio-controller; 181 gpio-controller;
607 #gpio-cells = <2>; 182 #gpio-cells = <2>;
608 gpio-ranges = <&pinctrl_periphs 0 0 86>; 183 gpio-ranges = <&pinctrl_periphs 0 0 86>;
609 }; 184 };
610 185
186 i2c0_pins: i2c0 {
187 mux {
188 groups = "i2c0_sck",
189 "i2c0_sda";
190 function = "i2c0";
191 };
192 };
193
194 i2c1_x_pins: i2c1_x {
195 mux {
196 groups = "i2c1_sck_x",
197 "i2c1_sda_x";
198 function = "i2c1";
199 };
200 };
201
202 i2c1_z_pins: i2c1_z {
203 mux {
204 groups = "i2c1_sck_z",
205 "i2c1_sda_z";
206 function = "i2c1";
207 };
208 };
209
210 i2c2_a_pins: i2c2_a {
211 mux {
212 groups = "i2c2_sck_a",
213 "i2c2_sda_a";
214 function = "i2c2";
215 };
216 };
217
218 i2c2_x_pins: i2c2_x {
219 mux {
220 groups = "i2c2_sck_x",
221 "i2c2_sda_x";
222 function = "i2c2";
223 };
224 };
225
226 i2c3_a6_pins: i2c3_a6 {
227 mux {
228 groups = "i2c3_sda_a6",
229 "i2c3_sck_a7";
230 function = "i2c3";
231 };
232 };
233
234 i2c3_a12_pins: i2c3_a12 {
235 mux {
236 groups = "i2c3_sda_a12",
237 "i2c3_sck_a13";
238 function = "i2c3";
239 };
240 };
241
242 i2c3_a19_pins: i2c3_a19 {
243 mux {
244 groups = "i2c3_sda_a19",
245 "i2c3_sck_a20";
246 function = "i2c3";
247 };
248 };
249
611 emmc_pins: emmc { 250 emmc_pins: emmc {
612 mux { 251 mux {
613 groups = "emmc_nand_d0", 252 groups = "emmc_nand_d0",
614 "emmc_nand_d1", 253 "emmc_nand_d1",
615 "emmc_nand_d2", 254 "emmc_nand_d2",
616 "emmc_nand_d3", 255 "emmc_nand_d3",
617 "emmc_nand_d4", 256 "emmc_nand_d4",
618 "emmc_nand_d5", 257 "emmc_nand_d5",
619 "emmc_nand_d6", 258 "emmc_nand_d6",
620 "emmc_nand_d7", 259 "emmc_nand_d7",
621 "emmc_clk", 260 "emmc_clk",
622 "emmc_cmd", 261 "emmc_cmd",
623 "emmc_ds"; 262 "emmc_ds";
624 function = "emmc"; 263 function = "emmc";
625 }; 264 };
626 }; 265 };
@@ -636,40 +275,57 @@
636 }; 275 };
637 }; 276 };
638 277
639 sdio_pins: sdio { 278 eth_rgmii_x_pins: eth-x-rgmii {
640 mux { 279 mux {
641 groups = "sdio_d0", 280 groups = "eth_mdio_x",
642 "sdio_d1", 281 "eth_mdc_x",
643 "sdio_d2", 282 "eth_rgmii_rx_clk_x",
644 "sdio_d3", 283 "eth_rx_dv_x",
645 "sdio_cmd", 284 "eth_rxd0_x",
646 "sdio_clk"; 285 "eth_rxd1_x",
647 function = "sdio"; 286 "eth_rxd2_rgmii",
287 "eth_rxd3_rgmii",
288 "eth_rgmii_tx_clk",
289 "eth_txen_x",
290 "eth_txd0_x",
291 "eth_txd1_x",
292 "eth_txd2_rgmii",
293 "eth_txd3_rgmii";
294 function = "eth";
648 }; 295 };
649 }; 296 };
650 297
651 sdio_clk_gate_pins: sdio_clk_gate { 298 eth_rgmii_y_pins: eth-y-rgmii {
652 mux { 299 mux {
653 groups = "GPIOX_4"; 300 groups = "eth_mdio_y",
654 function = "gpio_periphs"; 301 "eth_mdc_y",
655 }; 302 "eth_rgmii_rx_clk_y",
656 cfg-pull-down { 303 "eth_rx_dv_y",
657 pins = "GPIOX_4"; 304 "eth_rxd0_y",
658 bias-pull-down; 305 "eth_rxd1_y",
306 "eth_rxd2_rgmii",
307 "eth_rxd3_rgmii",
308 "eth_rgmii_tx_clk",
309 "eth_txen_y",
310 "eth_txd0_y",
311 "eth_txd1_y",
312 "eth_txd2_rgmii",
313 "eth_txd3_rgmii";
314 function = "eth";
659 }; 315 };
660 }; 316 };
661 317
662 eth_rmii_x_pins: eth-x-rmii { 318 eth_rmii_x_pins: eth-x-rmii {
663 mux { 319 mux {
664 groups = "eth_mdio_x", 320 groups = "eth_mdio_x",
665 "eth_mdc_x", 321 "eth_mdc_x",
666 "eth_rgmii_rx_clk_x", 322 "eth_rgmii_rx_clk_x",
667 "eth_rx_dv_x", 323 "eth_rx_dv_x",
668 "eth_rxd0_x", 324 "eth_rxd0_x",
669 "eth_rxd1_x", 325 "eth_rxd1_x",
670 "eth_txen_x", 326 "eth_txen_x",
671 "eth_txd0_x", 327 "eth_txd0_x",
672 "eth_txd1_x"; 328 "eth_txd1_x";
673 function = "eth"; 329 function = "eth";
674 }; 330 };
675 }; 331 };
@@ -677,55 +333,29 @@
677 eth_rmii_y_pins: eth-y-rmii { 333 eth_rmii_y_pins: eth-y-rmii {
678 mux { 334 mux {
679 groups = "eth_mdio_y", 335 groups = "eth_mdio_y",
680 "eth_mdc_y", 336 "eth_mdc_y",
681 "eth_rgmii_rx_clk_y", 337 "eth_rgmii_rx_clk_y",
682 "eth_rx_dv_y", 338 "eth_rx_dv_y",
683 "eth_rxd0_y", 339 "eth_rxd0_y",
684 "eth_rxd1_y", 340 "eth_rxd1_y",
685 "eth_txen_y", 341 "eth_txen_y",
686 "eth_txd0_y", 342 "eth_txd0_y",
687 "eth_txd1_y"; 343 "eth_txd1_y";
688 function = "eth"; 344 function = "eth";
689 }; 345 };
690 }; 346 };
691 347
692 eth_rgmii_x_pins: eth-x-rgmii { 348 mclk_b_pins: mclk_b {
693 mux { 349 mux {
694 groups = "eth_mdio_x", 350 groups = "mclk_b";
695 "eth_mdc_x", 351 function = "mclk_b";
696 "eth_rgmii_rx_clk_x",
697 "eth_rx_dv_x",
698 "eth_rxd0_x",
699 "eth_rxd1_x",
700 "eth_rxd2_rgmii",
701 "eth_rxd3_rgmii",
702 "eth_rgmii_tx_clk",
703 "eth_txen_x",
704 "eth_txd0_x",
705 "eth_txd1_x",
706 "eth_txd2_rgmii",
707 "eth_txd3_rgmii";
708 function = "eth";
709 }; 352 };
710 }; 353 };
711 354
712 eth_rgmii_y_pins: eth-y-rgmii { 355 mclk_c_pins: mclk_c {
713 mux { 356 mux {
714 groups = "eth_mdio_y", 357 groups = "mclk_c";
715 "eth_mdc_y", 358 function = "mclk_c";
716 "eth_rgmii_rx_clk_y",
717 "eth_rx_dv_y",
718 "eth_rxd0_y",
719 "eth_rxd1_y",
720 "eth_rxd2_rgmii",
721 "eth_rxd3_rgmii",
722 "eth_rgmii_tx_clk",
723 "eth_txen_y",
724 "eth_txd0_y",
725 "eth_txd1_y",
726 "eth_txd2_rgmii",
727 "eth_txd3_rgmii";
728 function = "eth";
729 }; 359 };
730 }; 360 };
731 361
@@ -855,6 +485,29 @@
855 }; 485 };
856 }; 486 };
857 487
488 sdio_pins: sdio {
489 mux {
490 groups = "sdio_d0",
491 "sdio_d1",
492 "sdio_d2",
493 "sdio_d3",
494 "sdio_cmd",
495 "sdio_clk";
496 function = "sdio";
497 };
498 };
499
500 sdio_clk_gate_pins: sdio_clk_gate {
501 mux {
502 groups = "GPIOX_4";
503 function = "gpio_periphs";
504 };
505 cfg-pull-down {
506 pins = "GPIOX_4";
507 bias-pull-down;
508 };
509 };
510
858 spdif_in_z_pins: spdif_in_z { 511 spdif_in_z_pins: spdif_in_z {
859 mux { 512 mux {
860 groups = "spdif_in_z"; 513 groups = "spdif_in_z";
@@ -890,13 +543,6 @@
890 }; 543 };
891 }; 544 };
892 545
893 spdif_out_z_pins: spdif_out_z {
894 mux {
895 groups = "spdif_out_z";
896 function = "spdif_out";
897 };
898 };
899
900 spdif_out_a1_pins: spdif_out_a1 { 546 spdif_out_a1_pins: spdif_out_a1 {
901 mux { 547 mux {
902 groups = "spdif_out_a1"; 548 groups = "spdif_out_a1";
@@ -925,11 +571,18 @@
925 }; 571 };
926 }; 572 };
927 573
574 spdif_out_z_pins: spdif_out_z {
575 mux {
576 groups = "spdif_out_z";
577 function = "spdif_out";
578 };
579 };
580
928 spi0_pins: spi0 { 581 spi0_pins: spi0 {
929 mux { 582 mux {
930 groups = "spi0_miso", 583 groups = "spi0_miso",
931 "spi0_mosi", 584 "spi0_mosi",
932 "spi0_clk"; 585 "spi0_clk";
933 function = "spi0"; 586 function = "spi0";
934 }; 587 };
935 }; 588 };
@@ -955,12 +608,11 @@
955 }; 608 };
956 }; 609 };
957 610
958
959 spi1_a_pins: spi1_a { 611 spi1_a_pins: spi1_a {
960 mux { 612 mux {
961 groups = "spi1_miso_a", 613 groups = "spi1_miso_a",
962 "spi1_mosi_a", 614 "spi1_mosi_a",
963 "spi1_clk_a"; 615 "spi1_clk_a";
964 function = "spi1"; 616 function = "spi1";
965 }; 617 };
966 }; 618 };
@@ -982,8 +634,8 @@
982 spi1_x_pins: spi1_x { 634 spi1_x_pins: spi1_x {
983 mux { 635 mux {
984 groups = "spi1_miso_x", 636 groups = "spi1_miso_x",
985 "spi1_mosi_x", 637 "spi1_mosi_x",
986 "spi1_clk_x"; 638 "spi1_clk_x";
987 function = "spi1"; 639 function = "spi1";
988 }; 640 };
989 }; 641 };
@@ -995,145 +647,52 @@
995 }; 647 };
996 }; 648 };
997 649
998 i2c0_pins: i2c0 { 650 tdma_din0_pins: tdma_din0 {
999 mux {
1000 groups = "i2c0_sck",
1001 "i2c0_sda";
1002 function = "i2c0";
1003 };
1004 };
1005
1006 i2c1_z_pins: i2c1_z {
1007 mux {
1008 groups = "i2c1_sck_z",
1009 "i2c1_sda_z";
1010 function = "i2c1";
1011 };
1012 };
1013
1014 i2c1_x_pins: i2c1_x {
1015 mux {
1016 groups = "i2c1_sck_x",
1017 "i2c1_sda_x";
1018 function = "i2c1";
1019 };
1020 };
1021
1022 i2c2_x_pins: i2c2_x {
1023 mux {
1024 groups = "i2c2_sck_x",
1025 "i2c2_sda_x";
1026 function = "i2c2";
1027 };
1028 };
1029
1030 i2c2_a_pins: i2c2_a {
1031 mux {
1032 groups = "i2c2_sck_a",
1033 "i2c2_sda_a";
1034 function = "i2c2";
1035 };
1036 };
1037
1038 i2c3_a6_pins: i2c3_a6 {
1039 mux {
1040 groups = "i2c3_sda_a6",
1041 "i2c3_sck_a7";
1042 function = "i2c3";
1043 };
1044 };
1045
1046 i2c3_a12_pins: i2c3_a12 {
1047 mux {
1048 groups = "i2c3_sda_a12",
1049 "i2c3_sck_a13";
1050 function = "i2c3";
1051 };
1052 };
1053
1054 i2c3_a19_pins: i2c3_a19 {
1055 mux {
1056 groups = "i2c3_sda_a19",
1057 "i2c3_sck_a20";
1058 function = "i2c3";
1059 };
1060 };
1061
1062 uart_a_pins: uart_a {
1063 mux {
1064 groups = "uart_tx_a",
1065 "uart_rx_a";
1066 function = "uart_a";
1067 };
1068 };
1069
1070 uart_a_cts_rts_pins: uart_a_cts_rts {
1071 mux {
1072 groups = "uart_cts_a",
1073 "uart_rts_a";
1074 function = "uart_a";
1075 };
1076 };
1077
1078 uart_b_x_pins: uart_b_x {
1079 mux {
1080 groups = "uart_tx_b_x",
1081 "uart_rx_b_x";
1082 function = "uart_b";
1083 };
1084 };
1085
1086 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1087 mux { 651 mux {
1088 groups = "uart_cts_b_x", 652 groups = "tdma_din0";
1089 "uart_rts_b_x"; 653 function = "tdma";
1090 function = "uart_b";
1091 }; 654 };
1092 }; 655 };
1093 656
1094 uart_b_z_pins: uart_b_z { 657 tdma_dout0_x14_pins: tdma_dout0_x14 {
1095 mux { 658 mux {
1096 groups = "uart_tx_b_z", 659 groups = "tdma_dout0_x14";
1097 "uart_rx_b_z"; 660 function = "tdma";
1098 function = "uart_b";
1099 }; 661 };
1100 }; 662 };
1101 663
1102 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 664 tdma_dout0_x15_pins: tdma_dout0_x15 {
1103 mux { 665 mux {
1104 groups = "uart_cts_b_z", 666 groups = "tdma_dout0_x15";
1105 "uart_rts_b_z"; 667 function = "tdma";
1106 function = "uart_b";
1107 }; 668 };
1108 }; 669 };
1109 670
1110 uart_ao_b_z_pins: uart_ao_b_z { 671 tdma_dout1_pins: tdma_dout1 {
1111 mux { 672 mux {
1112 groups = "uart_ao_tx_b_z", 673 groups = "tdma_dout1";
1113 "uart_ao_rx_b_z"; 674 function = "tdma";
1114 function = "uart_ao_b_z";
1115 }; 675 };
1116 }; 676 };
1117 677
1118 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 678 tdma_din1_pins: tdma_din1 {
1119 mux { 679 mux {
1120 groups = "uart_ao_cts_b_z", 680 groups = "tdma_din1";
1121 "uart_ao_rts_b_z"; 681 function = "tdma";
1122 function = "uart_ao_b_z";
1123 }; 682 };
1124 }; 683 };
1125 684
1126 mclk_b_pins: mclk_b { 685 tdma_fs_pins: tdma_fs {
1127 mux { 686 mux {
1128 groups = "mclk_b"; 687 groups = "tdma_fs";
1129 function = "mclk_b"; 688 function = "tdma";
1130 }; 689 };
1131 }; 690 };
1132 691
1133 mclk_c_pins: mclk_c { 692 tdma_fs_slv_pins: tdma_fs_slv {
1134 mux { 693 mux {
1135 groups = "mclk_c"; 694 groups = "tdma_fs_slv";
1136 function = "mclk_c"; 695 function = "tdma";
1137 }; 696 };
1138 }; 697 };
1139 698
@@ -1151,65 +710,58 @@
1151 }; 710 };
1152 }; 711 };
1153 712
1154 tdma_fs_pins: tdma_fs { 713 tdmb_din0_pins: tdmb_din0 {
1155 mux {
1156 groups = "tdma_fs";
1157 function = "tdma";
1158 };
1159 };
1160
1161 tdma_fs_slv_pins: tdma_fs_slv {
1162 mux { 714 mux {
1163 groups = "tdma_fs_slv"; 715 groups = "tdmb_din0";
1164 function = "tdma"; 716 function = "tdmb";
1165 }; 717 };
1166 }; 718 };
1167 719
1168 tdma_din0_pins: tdma_din0 { 720 tdmb_din1_pins: tdmb_din1 {
1169 mux { 721 mux {
1170 groups = "tdma_din0"; 722 groups = "tdmb_din1";
1171 function = "tdma"; 723 function = "tdmb";
1172 }; 724 };
1173 }; 725 };
1174 726
1175 tdma_dout0_x14_pins: tdma_dout0_x14 { 727 tdmb_din2_pins: tdmb_din2 {
1176 mux { 728 mux {
1177 groups = "tdma_dout0_x14"; 729 groups = "tdmb_din2";
1178 function = "tdma"; 730 function = "tdmb";
1179 }; 731 };
1180 }; 732 };
1181 733
1182 tdma_dout0_x15_pins: tdma_dout0_x15 { 734 tdmb_din3_pins: tdmb_din3 {
1183 mux { 735 mux {
1184 groups = "tdma_dout0_x15"; 736 groups = "tdmb_din3";
1185 function = "tdma"; 737 function = "tdmb";
1186 }; 738 };
1187 }; 739 };
1188 740
1189 tdma_dout1_pins: tdma_dout1 { 741 tdmb_dout0_pins: tdmb_dout0 {
1190 mux { 742 mux {
1191 groups = "tdma_dout1"; 743 groups = "tdmb_dout0";
1192 function = "tdma"; 744 function = "tdmb";
1193 }; 745 };
1194 }; 746 };
1195 747
1196 tdma_din1_pins: tdma_din1 { 748 tdmb_dout1_pins: tdmb_dout1 {
1197 mux { 749 mux {
1198 groups = "tdma_din1"; 750 groups = "tdmb_dout1";
1199 function = "tdma"; 751 function = "tdmb";
1200 }; 752 };
1201 }; 753 };
1202 754
1203 tdmb_sclk_pins: tdmb_sclk { 755 tdmb_dout2_pins: tdmb_dout2 {
1204 mux { 756 mux {
1205 groups = "tdmb_sclk"; 757 groups = "tdmb_dout2";
1206 function = "tdmb"; 758 function = "tdmb";
1207 }; 759 };
1208 }; 760 };
1209 761
1210 tdmb_sclk_slv_pins: tdmb_sclk_slv { 762 tdmb_dout3_pins: tdmb_dout3 {
1211 mux { 763 mux {
1212 groups = "tdmb_sclk_slv"; 764 groups = "tdmb_dout3";
1213 function = "tdmb"; 765 function = "tdmb";
1214 }; 766 };
1215 }; 767 };
@@ -1228,163 +780,412 @@
1228 }; 780 };
1229 }; 781 };
1230 782
1231 tdmb_din0_pins: tdmb_din0 { 783 tdmb_sclk_pins: tdmb_sclk {
1232 mux { 784 mux {
1233 groups = "tdmb_din0"; 785 groups = "tdmb_sclk";
1234 function = "tdmb"; 786 function = "tdmb";
1235 }; 787 };
1236 }; 788 };
1237 789
1238 tdmb_dout0_pins: tdmb_dout0 { 790 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1239 mux { 791 mux {
1240 groups = "tdmb_dout0"; 792 groups = "tdmb_sclk_slv";
1241 function = "tdmb"; 793 function = "tdmb";
1242 }; 794 };
1243 }; 795 };
1244 796
1245 tdmb_din1_pins: tdmb_din1 { 797 tdmc_fs_pins: tdmc_fs {
1246 mux { 798 mux {
1247 groups = "tdmb_din1"; 799 groups = "tdmc_fs";
1248 function = "tdmb"; 800 function = "tdmc";
1249 }; 801 };
1250 }; 802 };
1251 803
1252 tdmb_dout1_pins: tdmb_dout1 { 804 tdmc_fs_slv_pins: tdmc_fs_slv {
1253 mux { 805 mux {
1254 groups = "tdmb_dout1"; 806 groups = "tdmc_fs_slv";
1255 function = "tdmb"; 807 function = "tdmc";
1256 }; 808 };
1257 }; 809 };
1258 810
1259 tdmb_din2_pins: tdmb_din2 { 811 tdmc_sclk_pins: tdmc_sclk {
1260 mux { 812 mux {
1261 groups = "tdmb_din2"; 813 groups = "tdmc_sclk";
1262 function = "tdmb"; 814 function = "tdmc";
1263 }; 815 };
1264 }; 816 };
1265 817
1266 tdmb_dout2_pins: tdmb_dout2 { 818 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1267 mux { 819 mux {
1268 groups = "tdmb_dout2"; 820 groups = "tdmc_sclk_slv";
1269 function = "tdmb"; 821 function = "tdmc";
1270 }; 822 };
1271 }; 823 };
1272 824
1273 tdmb_din3_pins: tdmb_din3 { 825 tdmc_din0_pins: tdmc_din0 {
1274 mux { 826 mux {
1275 groups = "tdmb_din3"; 827 groups = "tdmc_din0";
1276 function = "tdmb"; 828 function = "tdmc";
1277 }; 829 };
1278 }; 830 };
1279 831
1280 tdmb_dout3_pins: tdmb_dout3 { 832 tdmc_din1_pins: tdmc_din1 {
1281 mux { 833 mux {
1282 groups = "tdmb_dout3"; 834 groups = "tdmc_din1";
1283 function = "tdmb"; 835 function = "tdmc";
1284 }; 836 };
1285 }; 837 };
1286 838
1287 tdmc_sclk_pins: tdmc_sclk { 839 tdmc_din2_pins: tdmc_din2 {
1288 mux { 840 mux {
1289 groups = "tdmc_sclk"; 841 groups = "tdmc_din2";
1290 function = "tdmc"; 842 function = "tdmc";
1291 }; 843 };
1292 }; 844 };
1293 845
1294 tdmc_sclk_slv_pins: tdmc_sclk_slv { 846 tdmc_din3_pins: tdmc_din3 {
1295 mux { 847 mux {
1296 groups = "tdmc_sclk_slv"; 848 groups = "tdmc_din3";
1297 function = "tdmc"; 849 function = "tdmc";
1298 }; 850 };
1299 }; 851 };
1300 852
1301 tdmc_fs_pins: tdmc_fs { 853 tdmc_dout0_pins: tdmc_dout0 {
1302 mux { 854 mux {
1303 groups = "tdmc_fs"; 855 groups = "tdmc_dout0";
1304 function = "tdmc"; 856 function = "tdmc";
1305 }; 857 };
1306 }; 858 };
1307 859
1308 tdmc_fs_slv_pins: tdmc_fs_slv { 860 tdmc_dout1_pins: tdmc_dout1 {
1309 mux { 861 mux {
1310 groups = "tdmc_fs_slv"; 862 groups = "tdmc_dout1";
1311 function = "tdmc"; 863 function = "tdmc";
1312 }; 864 };
1313 }; 865 };
1314 866
1315 tdmc_din0_pins: tdmc_din0 { 867 tdmc_dout2_pins: tdmc_dout2 {
1316 mux { 868 mux {
1317 groups = "tdmc_din0"; 869 groups = "tdmc_dout2";
1318 function = "tdmc"; 870 function = "tdmc";
1319 }; 871 };
1320 }; 872 };
1321 873
1322 tdmc_dout0_pins: tdmc_dout0 { 874 tdmc_dout3_pins: tdmc_dout3 {
1323 mux { 875 mux {
1324 groups = "tdmc_dout0"; 876 groups = "tdmc_dout3";
1325 function = "tdmc"; 877 function = "tdmc";
1326 }; 878 };
1327 }; 879 };
1328 880
1329 tdmc_din1_pins: tdmc_din1 { 881 uart_a_pins: uart_a {
1330 mux { 882 mux {
1331 groups = "tdmc_din1"; 883 groups = "uart_tx_a",
1332 function = "tdmc"; 884 "uart_rx_a";
885 function = "uart_a";
1333 }; 886 };
1334 }; 887 };
1335 888
1336 tdmc_dout1_pins: tdmc_dout1 { 889 uart_a_cts_rts_pins: uart_a_cts_rts {
1337 mux { 890 mux {
1338 groups = "tdmc_dout1"; 891 groups = "uart_cts_a",
1339 function = "tdmc"; 892 "uart_rts_a";
893 function = "uart_a";
1340 }; 894 };
1341 }; 895 };
1342 896
1343 tdmc_din2_pins: tdmc_din2 { 897 uart_b_x_pins: uart_b_x {
1344 mux { 898 mux {
1345 groups = "tdmc_din2"; 899 groups = "uart_tx_b_x",
1346 function = "tdmc"; 900 "uart_rx_b_x";
901 function = "uart_b";
1347 }; 902 };
1348 }; 903 };
1349 904
1350 tdmc_dout2_pins: tdmc_dout2 { 905 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1351 mux { 906 mux {
1352 groups = "tdmc_dout2"; 907 groups = "uart_cts_b_x",
1353 function = "tdmc"; 908 "uart_rts_b_x";
909 function = "uart_b";
1354 }; 910 };
1355 }; 911 };
1356 912
1357 tdmc_din3_pins: tdmc_din3 { 913 uart_b_z_pins: uart_b_z {
1358 mux { 914 mux {
1359 groups = "tdmc_din3"; 915 groups = "uart_tx_b_z",
1360 function = "tdmc"; 916 "uart_rx_b_z";
917 function = "uart_b";
1361 }; 918 };
1362 }; 919 };
1363 920
1364 tdmc_dout3_pins: tdmc_dout3 { 921 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1365 mux { 922 mux {
1366 groups = "tdmc_dout3"; 923 groups = "uart_cts_b_z",
1367 function = "tdmc"; 924 "uart_rts_b_z";
925 function = "uart_b";
926 };
927 };
928
929 uart_ao_b_z_pins: uart_ao_b_z {
930 mux {
931 groups = "uart_ao_tx_b_z",
932 "uart_ao_rx_b_z";
933 function = "uart_ao_b_z";
934 };
935 };
936
937 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
938 mux {
939 groups = "uart_ao_cts_b_z",
940 "uart_ao_rts_b_z";
941 function = "uart_ao_b_z";
1368 }; 942 };
1369 }; 943 };
1370 }; 944 };
1371 }; 945 };
1372 946
1373 sram: sram@fffc0000 { 947 hiubus: bus@ff63c000 {
1374 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 948 compatible = "simple-bus";
1375 reg = <0x0 0xfffc0000 0x0 0x20000>; 949 reg = <0x0 0xff63c000 0x0 0x1c00>;
1376 #address-cells = <1>; 950 #address-cells = <2>;
1377 #size-cells = <1>; 951 #size-cells = <2>;
1378 ranges = <0 0x0 0xfffc0000 0x20000>; 952 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1379 953
1380 cpu_scp_lpri: scp-shmem@0 { 954 sysctrl: system-controller@0 {
1381 compatible = "amlogic,meson-axg-scp-shmem"; 955 compatible = "amlogic,meson-axg-hhi-sysctrl",
1382 reg = <0x13000 0x400>; 956 "syscon", "simple-mfd";
957 reg = <0 0 0 0x400>;
958
959 clkc: clock-controller {
960 compatible = "amlogic,axg-clkc";
961 #clock-cells = <1>;
962 };
1383 }; 963 };
964 };
1384 965
1385 cpu_scp_hpri: scp-shmem@200 { 966 mailbox: mailbox@ff63dc00 {
1386 compatible = "amlogic,meson-axg-scp-shmem"; 967 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
1387 reg = <0x13400 0x400>; 968 reg = <0 0xff63dc00 0 0x400>;
969 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
970 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
971 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
972 #mbox-cells = <1>;
973 };
974
975 audio: bus@ff642000 {
976 compatible = "simple-bus";
977 reg = <0x0 0xff642000 0x0 0x2000>;
978 #address-cells = <2>;
979 #size-cells = <2>;
980 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
981
982 clkc_audio: clock-controller@0 {
983 compatible = "amlogic,axg-audio-clkc";
984 reg = <0x0 0x0 0x0 0xb4>;
985 #clock-cells = <1>;
986
987 clocks = <&clkc CLKID_AUDIO>,
988 <&clkc CLKID_MPLL0>,
989 <&clkc CLKID_MPLL1>,
990 <&clkc CLKID_MPLL2>,
991 <&clkc CLKID_MPLL3>,
992 <&clkc CLKID_HIFI_PLL>,
993 <&clkc CLKID_FCLK_DIV3>,
994 <&clkc CLKID_FCLK_DIV4>,
995 <&clkc CLKID_GP0_PLL>;
996 clock-names = "pclk",
997 "mst_in0",
998 "mst_in1",
999 "mst_in2",
1000 "mst_in3",
1001 "mst_in4",
1002 "mst_in5",
1003 "mst_in6",
1004 "mst_in7";
1005
1006 resets = <&reset RESET_AUDIO>;
1007 };
1008
1009 toddr_a: audio-controller@100 {
1010 compatible = "amlogic,axg-toddr";
1011 reg = <0x0 0x100 0x0 0x1c>;
1012 #sound-dai-cells = <0>;
1013 sound-name-prefix = "TODDR_A";
1014 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1015 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1016 resets = <&arb AXG_ARB_TODDR_A>;
1017 status = "disabled";
1018 };
1019
1020 toddr_b: audio-controller@140 {
1021 compatible = "amlogic,axg-toddr";
1022 reg = <0x0 0x140 0x0 0x1c>;
1023 #sound-dai-cells = <0>;
1024 sound-name-prefix = "TODDR_B";
1025 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1026 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1027 resets = <&arb AXG_ARB_TODDR_B>;
1028 status = "disabled";
1029 };
1030
1031 toddr_c: audio-controller@180 {
1032 compatible = "amlogic,axg-toddr";
1033 reg = <0x0 0x180 0x0 0x1c>;
1034 #sound-dai-cells = <0>;
1035 sound-name-prefix = "TODDR_C";
1036 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1037 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1038 resets = <&arb AXG_ARB_TODDR_C>;
1039 status = "disabled";
1040 };
1041
1042 frddr_a: audio-controller@1c0 {
1043 compatible = "amlogic,axg-frddr";
1044 reg = <0x0 0x1c0 0x0 0x1c>;
1045 #sound-dai-cells = <0>;
1046 sound-name-prefix = "FRDDR_A";
1047 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1048 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1049 resets = <&arb AXG_ARB_FRDDR_A>;
1050 status = "disabled";
1051 };
1052
1053 frddr_b: audio-controller@200 {
1054 compatible = "amlogic,axg-frddr";
1055 reg = <0x0 0x200 0x0 0x1c>;
1056 #sound-dai-cells = <0>;
1057 sound-name-prefix = "FRDDR_B";
1058 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1059 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1060 resets = <&arb AXG_ARB_FRDDR_B>;
1061 status = "disabled";
1062 };
1063
1064 frddr_c: audio-controller@240 {
1065 compatible = "amlogic,axg-frddr";
1066 reg = <0x0 0x240 0x0 0x1c>;
1067 #sound-dai-cells = <0>;
1068 sound-name-prefix = "FRDDR_C";
1069 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1070 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1071 resets = <&arb AXG_ARB_FRDDR_C>;
1072 status = "disabled";
1073 };
1074
1075 arb: reset-controller@280 {
1076 compatible = "amlogic,meson-axg-audio-arb";
1077 reg = <0x0 0x280 0x0 0x4>;
1078 #reset-cells = <1>;
1079 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1080 };
1081
1082 tdmin_a: audio-controller@300 {
1083 compatible = "amlogic,axg-tdmin";
1084 reg = <0x0 0x300 0x0 0x40>;
1085 sound-name-prefix = "TDMIN_A";
1086 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1087 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1088 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1089 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1090 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1091 clock-names = "pclk", "sclk", "sclk_sel",
1092 "lrclk", "lrclk_sel";
1093 status = "disabled";
1094 };
1095
1096 tdmin_b: audio-controller@340 {
1097 compatible = "amlogic,axg-tdmin";
1098 reg = <0x0 0x340 0x0 0x40>;
1099 sound-name-prefix = "TDMIN_B";
1100 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1101 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1102 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1103 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1104 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1105 clock-names = "pclk", "sclk", "sclk_sel",
1106 "lrclk", "lrclk_sel";
1107 status = "disabled";
1108 };
1109
1110 tdmin_c: audio-controller@380 {
1111 compatible = "amlogic,axg-tdmin";
1112 reg = <0x0 0x380 0x0 0x40>;
1113 sound-name-prefix = "TDMIN_C";
1114 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1115 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1116 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1117 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1118 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1119 clock-names = "pclk", "sclk", "sclk_sel",
1120 "lrclk", "lrclk_sel";
1121 status = "disabled";
1122 };
1123
1124 tdmin_lb: audio-controller@3c0 {
1125 compatible = "amlogic,axg-tdmin";
1126 reg = <0x0 0x3c0 0x0 0x40>;
1127 sound-name-prefix = "TDMIN_LB";
1128 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1129 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1130 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1131 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1132 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1133 clock-names = "pclk", "sclk", "sclk_sel",
1134 "lrclk", "lrclk_sel";
1135 status = "disabled";
1136 };
1137
1138 spdifout: audio-controller@480 {
1139 compatible = "amlogic,axg-spdifout";
1140 reg = <0x0 0x480 0x0 0x50>;
1141 #sound-dai-cells = <0>;
1142 sound-name-prefix = "SPDIFOUT";
1143 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1144 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1145 clock-names = "pclk", "mclk";
1146 status = "disabled";
1147 };
1148
1149 tdmout_a: audio-controller@500 {
1150 compatible = "amlogic,axg-tdmout";
1151 reg = <0x0 0x500 0x0 0x40>;
1152 sound-name-prefix = "TDMOUT_A";
1153 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1154 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1155 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1156 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1157 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1158 clock-names = "pclk", "sclk", "sclk_sel",
1159 "lrclk", "lrclk_sel";
1160 status = "disabled";
1161 };
1162
1163 tdmout_b: audio-controller@540 {
1164 compatible = "amlogic,axg-tdmout";
1165 reg = <0x0 0x540 0x0 0x40>;
1166 sound-name-prefix = "TDMOUT_B";
1167 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1168 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1169 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1170 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1171 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1172 clock-names = "pclk", "sclk", "sclk_sel",
1173 "lrclk", "lrclk_sel";
1174 status = "disabled";
1175 };
1176
1177 tdmout_c: audio-controller@580 {
1178 compatible = "amlogic,axg-tdmout";
1179 reg = <0x0 0x580 0x0 0x40>;
1180 sound-name-prefix = "TDMOUT_C";
1181 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1182 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1183 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1184 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1185 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1186 clock-names = "pclk", "sclk", "sclk_sel",
1187 "lrclk", "lrclk_sel";
1188 status = "disabled";
1388 }; 1189 };
1389 }; 1190 };
1390 1191
@@ -1414,8 +1215,8 @@
1414 1215
1415 gpio_ao: bank@14 { 1216 gpio_ao: bank@14 {
1416 reg = <0x0 0x00014 0x0 0x8>, 1217 reg = <0x0 0x00014 0x0 0x8>,
1417 <0x0 0x0002c 0x0 0x4>, 1218 <0x0 0x0002c 0x0 0x4>,
1418 <0x0 0x00024 0x0 0x8>; 1219 <0x0 0x00024 0x0 0x8>;
1419 reg-names = "mux", "pull", "gpio"; 1220 reg-names = "mux", "pull", "gpio";
1420 gpio-controller; 1221 gpio-controller;
1421 #gpio-cells = <2>; 1222 #gpio-cells = <2>;
@@ -1474,7 +1275,7 @@
1474 uart_ao_a_pins: uart_ao_a { 1275 uart_ao_a_pins: uart_ao_a {
1475 mux { 1276 mux {
1476 groups = "uart_ao_tx_a", 1277 groups = "uart_ao_tx_a",
1477 "uart_ao_rx_a"; 1278 "uart_ao_rx_a";
1478 function = "uart_ao_a"; 1279 function = "uart_ao_a";
1479 }; 1280 };
1480 }; 1281 };
@@ -1482,7 +1283,7 @@
1482 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1283 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1483 mux { 1284 mux {
1484 groups = "uart_ao_cts_a", 1285 groups = "uart_ao_cts_a",
1485 "uart_ao_rts_a"; 1286 "uart_ao_rts_a";
1486 function = "uart_ao_a"; 1287 function = "uart_ao_a";
1487 }; 1288 };
1488 }; 1289 };
@@ -1490,7 +1291,7 @@
1490 uart_ao_b_pins: uart_ao_b { 1291 uart_ao_b_pins: uart_ao_b {
1491 mux { 1292 mux {
1492 groups = "uart_ao_tx_b", 1293 groups = "uart_ao_tx_b",
1493 "uart_ao_rx_b"; 1294 "uart_ao_rx_b";
1494 function = "uart_ao_b"; 1295 function = "uart_ao_b";
1495 }; 1296 };
1496 }; 1297 };
@@ -1498,7 +1299,7 @@
1498 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1299 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1499 mux { 1300 mux {
1500 groups = "uart_ao_cts_b", 1301 groups = "uart_ao_cts_b",
1501 "uart_ao_rts_b"; 1302 "uart_ao_rts_b";
1502 function = "uart_ao_b"; 1303 function = "uart_ao_b";
1503 }; 1304 };
1504 }; 1305 };
@@ -1510,13 +1311,6 @@
1510 amlogic,has-chip-id; 1311 amlogic,has-chip-id;
1511 }; 1312 };
1512 1313
1513 pwm_AO_ab: pwm@7000 {
1514 compatible = "amlogic,meson-axg-ao-pwm";
1515 reg = <0x0 0x07000 0x0 0x20>;
1516 #pwm-cells = <3>;
1517 status = "disabled";
1518 };
1519
1520 pwm_AO_cd: pwm@2000 { 1314 pwm_AO_cd: pwm@2000 {
1521 compatible = "amlogic,meson-axg-ao-pwm"; 1315 compatible = "amlogic,meson-axg-ao-pwm";
1522 reg = <0x0 0x02000 0x0 0x20>; 1316 reg = <0x0 0x02000 0x0 0x20>;
@@ -1524,16 +1318,6 @@
1524 status = "disabled"; 1318 status = "disabled";
1525 }; 1319 };
1526 1320
1527 i2c_AO: i2c@5000 {
1528 compatible = "amlogic,meson-axg-i2c";
1529 reg = <0x0 0x05000 0x0 0x20>;
1530 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1531 clocks = <&clkc CLKID_AO_I2C>;
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1534 status = "disabled";
1535 };
1536
1537 uart_AO: serial@3000 { 1321 uart_AO: serial@3000 {
1538 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1322 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1539 reg = <0x0 0x3000 0x0 0x18>; 1323 reg = <0x0 0x3000 0x0 0x18>;
@@ -1552,6 +1336,23 @@
1552 status = "disabled"; 1336 status = "disabled";
1553 }; 1337 };
1554 1338
1339 i2c_AO: i2c@5000 {
1340 compatible = "amlogic,meson-axg-i2c";
1341 reg = <0x0 0x05000 0x0 0x20>;
1342 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1343 clocks = <&clkc CLKID_AO_I2C>;
1344 #address-cells = <1>;
1345 #size-cells = <0>;
1346 status = "disabled";
1347 };
1348
1349 pwm_AO_ab: pwm@7000 {
1350 compatible = "amlogic,meson-axg-ao-pwm";
1351 reg = <0x0 0x07000 0x0 0x20>;
1352 #pwm-cells = <3>;
1353 status = "disabled";
1354 };
1355
1555 ir: ir@8000 { 1356 ir: ir@8000 {
1556 compatible = "amlogic,meson-gxbb-ir"; 1357 compatible = "amlogic,meson-gxbb-ir";
1557 reg = <0x0 0x8000 0x0 0x20>; 1358 reg = <0x0 0x8000 0x0 0x20>;
@@ -1566,12 +1367,211 @@
1566 #io-channel-cells = <1>; 1367 #io-channel-cells = <1>;
1567 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1368 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1568 clocks = <&xtal>, 1369 clocks = <&xtal>,
1569 <&clkc_AO CLKID_AO_SAR_ADC>, 1370 <&clkc_AO CLKID_AO_SAR_ADC>,
1570 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1371 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1571 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1372 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1572 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1373 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1573 status = "disabled"; 1374 status = "disabled";
1574 }; 1375 };
1575 }; 1376 };
1377
1378 gic: interrupt-controller@ffc01000 {
1379 compatible = "arm,gic-400";
1380 reg = <0x0 0xffc01000 0 0x1000>,
1381 <0x0 0xffc02000 0 0x2000>,
1382 <0x0 0xffc04000 0 0x2000>,
1383 <0x0 0xffc06000 0 0x2000>;
1384 interrupt-controller;
1385 interrupts = <GIC_PPI 9
1386 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1387 #interrupt-cells = <3>;
1388 #address-cells = <0>;
1389 };
1390
1391 cbus: bus@ffd00000 {
1392 compatible = "simple-bus";
1393 reg = <0x0 0xffd00000 0x0 0x25000>;
1394 #address-cells = <2>;
1395 #size-cells = <2>;
1396 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1397
1398 reset: reset-controller@1004 {
1399 compatible = "amlogic,meson-axg-reset";
1400 reg = <0x0 0x01004 0x0 0x9c>;
1401 #reset-cells = <1>;
1402 };
1403
1404 gpio_intc: interrupt-controller@f080 {
1405 compatible = "amlogic,meson-gpio-intc";
1406 reg = <0x0 0xf080 0x0 0x10>;
1407 interrupt-controller;
1408 #interrupt-cells = <2>;
1409 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1410 status = "disabled";
1411 };
1412
1413 pwm_ab: pwm@1b000 {
1414 compatible = "amlogic,meson-axg-ee-pwm";
1415 reg = <0x0 0x1b000 0x0 0x20>;
1416 #pwm-cells = <3>;
1417 status = "disabled";
1418 };
1419
1420 pwm_cd: pwm@1a000 {
1421 compatible = "amlogic,meson-axg-ee-pwm";
1422 reg = <0x0 0x1a000 0x0 0x20>;
1423 #pwm-cells = <3>;
1424 status = "disabled";
1425 };
1426
1427 spicc0: spi@13000 {
1428 compatible = "amlogic,meson-axg-spicc";
1429 reg = <0x0 0x13000 0x0 0x3c>;
1430 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1431 clocks = <&clkc CLKID_SPICC0>;
1432 clock-names = "core";
1433 #address-cells = <1>;
1434 #size-cells = <0>;
1435 status = "disabled";
1436 };
1437
1438 spicc1: spi@15000 {
1439 compatible = "amlogic,meson-axg-spicc";
1440 reg = <0x0 0x15000 0x0 0x3c>;
1441 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1442 clocks = <&clkc CLKID_SPICC1>;
1443 clock-names = "core";
1444 #address-cells = <1>;
1445 #size-cells = <0>;
1446 status = "disabled";
1447 };
1448
1449 i2c3: i2c@1c000 {
1450 compatible = "amlogic,meson-axg-i2c";
1451 reg = <0x0 0x1c000 0x0 0x20>;
1452 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1453 clocks = <&clkc CLKID_I2C>;
1454 #address-cells = <1>;
1455 #size-cells = <0>;
1456 status = "disabled";
1457 };
1458
1459 i2c2: i2c@1d000 {
1460 compatible = "amlogic,meson-axg-i2c";
1461 reg = <0x0 0x1d000 0x0 0x20>;
1462 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1463 clocks = <&clkc CLKID_I2C>;
1464 #address-cells = <1>;
1465 #size-cells = <0>;
1466 status = "disabled";
1467 };
1468
1469 i2c1: i2c@1e000 {
1470 compatible = "amlogic,meson-axg-i2c";
1471 reg = <0x0 0x1e000 0x0 0x20>;
1472 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1473 clocks = <&clkc CLKID_I2C>;
1474 #address-cells = <1>;
1475 #size-cells = <0>;
1476 status = "disabled";
1477 };
1478
1479 i2c0: i2c@1f000 {
1480 compatible = "amlogic,meson-axg-i2c";
1481 reg = <0x0 0x1f000 0x0 0x20>;
1482 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1483 clocks = <&clkc CLKID_I2C>;
1484 #address-cells = <1>;
1485 #size-cells = <0>;
1486 status = "disabled";
1487 };
1488
1489 uart_B: serial@23000 {
1490 compatible = "amlogic,meson-gx-uart";
1491 reg = <0x0 0x23000 0x0 0x18>;
1492 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1493 status = "disabled";
1494 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1495 clock-names = "xtal", "pclk", "baud";
1496 };
1497
1498 uart_A: serial@24000 {
1499 compatible = "amlogic,meson-gx-uart";
1500 reg = <0x0 0x24000 0x0 0x18>;
1501 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1502 status = "disabled";
1503 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1504 clock-names = "xtal", "pclk", "baud";
1505 };
1506 };
1507
1508 apb: bus@ffe00000 {
1509 compatible = "simple-bus";
1510 reg = <0x0 0xffe00000 0x0 0x200000>;
1511 #address-cells = <2>;
1512 #size-cells = <2>;
1513 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1514
1515 sd_emmc_b: sd@5000 {
1516 compatible = "amlogic,meson-axg-mmc";
1517 reg = <0x0 0x5000 0x0 0x800>;
1518 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1519 status = "disabled";
1520 clocks = <&clkc CLKID_SD_EMMC_B>,
1521 <&clkc CLKID_SD_EMMC_B_CLK0>,
1522 <&clkc CLKID_FCLK_DIV2>;
1523 clock-names = "core", "clkin0", "clkin1";
1524 resets = <&reset RESET_SD_EMMC_B>;
1525 };
1526
1527 sd_emmc_c: mmc@7000 {
1528 compatible = "amlogic,meson-axg-mmc";
1529 reg = <0x0 0x7000 0x0 0x800>;
1530 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1531 status = "disabled";
1532 clocks = <&clkc CLKID_SD_EMMC_C>,
1533 <&clkc CLKID_SD_EMMC_C_CLK0>,
1534 <&clkc CLKID_FCLK_DIV2>;
1535 clock-names = "core", "clkin0", "clkin1";
1536 resets = <&reset RESET_SD_EMMC_C>;
1537 };
1538 };
1539
1540 sram: sram@fffc0000 {
1541 compatible = "amlogic,meson-axg-sram", "mmio-sram";
1542 reg = <0x0 0xfffc0000 0x0 0x20000>;
1543 #address-cells = <1>;
1544 #size-cells = <1>;
1545 ranges = <0 0x0 0xfffc0000 0x20000>;
1546
1547 cpu_scp_lpri: scp-shmem@0 {
1548 compatible = "amlogic,meson-axg-scp-shmem";
1549 reg = <0x13000 0x400>;
1550 };
1551
1552 cpu_scp_hpri: scp-shmem@200 {
1553 compatible = "amlogic,meson-axg-scp-shmem";
1554 reg = <0x13400 0x400>;
1555 };
1556 };
1557 };
1558
1559 timer {
1560 compatible = "arm,armv8-timer";
1561 interrupts = <GIC_PPI 13
1562 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1563 <GIC_PPI 14
1564 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1565 <GIC_PPI 11
1566 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1567 <GIC_PPI 10
1568 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1569 };
1570
1571 xtal: xtal-clk {
1572 compatible = "fixed-clock";
1573 clock-frequency = <24000000>;
1574 clock-output-names = "xtal";
1575 #clock-cells = <0>;
1576 }; 1576 };
1577}; 1577};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 02:53:43 -0400