diff options
author | Petr Machata <petrm@mellanox.com> | 2018-10-31 05:56:42 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2018-10-31 15:56:58 -0400 |
commit | 8b931821aa04823e2e5df0ae93937baabbd23286 (patch) | |
tree | e3b58bf07eb01e217b95a0801d045cc15cc54a2e | |
parent | c4d63c714715bc44fee3f7a818052e59216a7d8e (diff) |
mlxsw: reg: QEEC: Add minimum shaper fields
Add QEEC.mise (minimum shaper enable) and QEEC.min_shaper_rate to enable
configuration of minimum shaper.
Increase the QEEC length to 0x20 as well: that's the length that the
register has had for a long time now, but with the configurations that
mlxsw typically exercises, the firmware tolerated 0x1C-sized packets.
With mise=true however, FW rejects packets unless they have the full
required length.
Fixes: b9b7cee40579 ("mlxsw: reg: Add QoS ETS Element Configuration register")
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/reg.h | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 32cb6718bb17..db3d2790aeec 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h | |||
@@ -3284,7 +3284,7 @@ static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, | |||
3284 | * Configures the ETS elements. | 3284 | * Configures the ETS elements. |
3285 | */ | 3285 | */ |
3286 | #define MLXSW_REG_QEEC_ID 0x400D | 3286 | #define MLXSW_REG_QEEC_ID 0x400D |
3287 | #define MLXSW_REG_QEEC_LEN 0x1C | 3287 | #define MLXSW_REG_QEEC_LEN 0x20 |
3288 | 3288 | ||
3289 | MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); | 3289 | MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); |
3290 | 3290 | ||
@@ -3326,6 +3326,15 @@ MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); | |||
3326 | */ | 3326 | */ |
3327 | MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); | 3327 | MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); |
3328 | 3328 | ||
3329 | /* reg_qeec_mise | ||
3330 | * Min shaper configuration enable. Enables configuration of the min | ||
3331 | * shaper on this ETS element | ||
3332 | * 0 - Disable | ||
3333 | * 1 - Enable | ||
3334 | * Access: RW | ||
3335 | */ | ||
3336 | MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); | ||
3337 | |||
3329 | enum { | 3338 | enum { |
3330 | MLXSW_REG_QEEC_BYTES_MODE, | 3339 | MLXSW_REG_QEEC_BYTES_MODE, |
3331 | MLXSW_REG_QEEC_PACKETS_MODE, | 3340 | MLXSW_REG_QEEC_PACKETS_MODE, |
@@ -3342,6 +3351,17 @@ enum { | |||
3342 | */ | 3351 | */ |
3343 | MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); | 3352 | MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); |
3344 | 3353 | ||
3354 | /* The smallest permitted min shaper rate. */ | ||
3355 | #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ | ||
3356 | |||
3357 | /* reg_qeec_min_shaper_rate | ||
3358 | * Min shaper information rate. | ||
3359 | * For CPU port, can only be configured for port hierarchy. | ||
3360 | * When in bytes mode, value is specified in units of 1000bps. | ||
3361 | * Access: RW | ||
3362 | */ | ||
3363 | MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); | ||
3364 | |||
3345 | /* reg_qeec_mase | 3365 | /* reg_qeec_mase |
3346 | * Max shaper configuration enable. Enables configuration of the max | 3366 | * Max shaper configuration enable. Enables configuration of the max |
3347 | * shaper on this ETS element. | 3367 | * shaper on this ETS element. |