clk: rockchip: fix rk3368 cpuclk divider offsets

Due to a copy-paste error the the rk3368 cpuclk settings were acessing
rk3288-specific register offsets. This never caused problems till now,
as cpu frequency scaling in't used currently at all.

Reported-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 4d2e7e56ee68..1faf1602a3fc 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -184,13 +184,13 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
 
 #define RK3368_CLKSEL0(_offs, _aclkm)                                   \
         {                                                               \
-                .reg = RK3288_CLKSEL_CON(0 + _offs),                    \
+                .reg = RK3368_CLKSEL_CON(0 + _offs),                    \
                 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK,     \
                                 RK3368_DIV_ACLKM_SHIFT),                \
         }
 #define RK3368_CLKSEL1(_offs, _atclk, _pdbg)                            \
         {                                                               \
-                .reg = RK3288_CLKSEL_CON(1 + _offs),                    \
+                .reg = RK3368_CLKSEL_CON(1 + _offs),                    \
                 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK,     \
                                 RK3368_DIV_ATCLK_SHIFT) |               \
                        HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK,   \