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authorJanakarajan Natarajan <Janakarajan.Natarajan@amd.com>2017-07-06 16:50:44 -0400
committerRadim Krčmář <rkrcmar@redhat.com>2017-07-12 16:38:28 -0400
commit8a77e90966e92759f94087f9845d413290be0d70 (patch)
tree17bb4aae92b4ebf1aa096e25c7df0d25d70cc252
parentb742c1e6e79ddf4192d76336da2407c65ca7242f (diff)
KVM: SVM: Prepare for new bit definition in lbr_ctl
The lbr_ctl variable in the vmcb control area is used to enable or disable Last Branch Record (LBR) virtualization. However, this is to be done using only bit 0 of the variable. To correct this and to prepare for a new feature, change the current usage to work only on a particular bit. Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
-rw-r--r--arch/x86/include/asm/svm.h2
-rw-r--r--arch/x86/kvm/svm.c4
2 files changed, 4 insertions, 2 deletions
diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
index 14824fc78f7e..d1163f64d732 100644
--- a/arch/x86/include/asm/svm.h
+++ b/arch/x86/include/asm/svm.h
@@ -119,6 +119,8 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
119#define AVIC_ENABLE_SHIFT 31 119#define AVIC_ENABLE_SHIFT 31
120#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT) 120#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
121 121
122#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
123
122#define SVM_INTERRUPT_SHADOW_MASK 1 124#define SVM_INTERRUPT_SHADOW_MASK 1
123 125
124#define SVM_IOIO_STR_SHIFT 2 126#define SVM_IOIO_STR_SHIFT 2
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 3da42d7c629e..6e72127c0d0e 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -947,7 +947,7 @@ static void svm_enable_lbrv(struct vcpu_svm *svm)
947{ 947{
948 u32 *msrpm = svm->msrpm; 948 u32 *msrpm = svm->msrpm;
949 949
950 svm->vmcb->control.lbr_ctl = 1; 950 svm->vmcb->control.lbr_ctl |= LBR_CTL_ENABLE_MASK;
951 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); 951 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
952 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); 952 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
953 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); 953 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
@@ -958,7 +958,7 @@ static void svm_disable_lbrv(struct vcpu_svm *svm)
958{ 958{
959 u32 *msrpm = svm->msrpm; 959 u32 *msrpm = svm->msrpm;
960 960
961 svm->vmcb->control.lbr_ctl = 0; 961 svm->vmcb->control.lbr_ctl &= ~LBR_CTL_ENABLE_MASK;
962 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); 962 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
963 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); 963 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
964 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); 964 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);