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authorJay Agarwal <jagarwal@nvidia.com>2013-08-09 10:49:27 -0400
committerStephen Warren <swarren@nvidia.com>2013-08-12 16:19:33 -0400
commit89e7ada41674197387fa67ea0a853f3651b4e375 (patch)
tree09b7de4ba3ff1070fb4f5ab10f8c2b14875eeeb1
parente07e3dbd9c8f84ff37c117eb1ff80f3f41a4df4b (diff)
ARM: tegra: Enable PCIe controller on Cardhu
Root port 2 is routed to the bottom connector on Cardhu and is used by the development dock to provide gigabit ethernet and USB functionality. Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index d78c90cfaf1a..1ecd470e0c77 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -31,6 +31,26 @@
31 reg = <0x80000000 0x40000000>; 31 reg = <0x80000000 0x40000000>;
32 }; 32 };
33 33
34 pcie-controller {
35 status = "okay";
36 pex-clk-supply = <&pex_hvdd_3v3_reg>;
37 vdd-supply = <&ldo1_reg>;
38 avdd-supply = <&ldo2_reg>;
39
40 pci@1,0 {
41 nvidia,num-lanes = <4>;
42 };
43
44 pci@2,0 {
45 nvidia,num-lanes = <1>;
46 };
47
48 pci@3,0 {
49 status = "okay";
50 nvidia,num-lanes = <1>;
51 };
52 };
53
34 pinmux { 54 pinmux {
35 pinctrl-names = "default"; 55 pinctrl-names = "default";
36 pinctrl-0 = <&state_default>; 56 pinctrl-0 = <&state_default>;