diff options
author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2018-01-25 09:00:10 -0500 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2018-03-08 09:26:11 -0500 |
commit | 89e423c3f14c4a87d124e4a5437dc337b90b6f29 (patch) | |
tree | c0b4c3f81069563a635d987af89c4c7e6bb2372d | |
parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) |
clk: tegra: Add la clock for Tegra210
This clock is needed by the memory built-in self test work around.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Hector Martin <marcan@marcan.st>
Tested-by: Andre Heider <a.heider@gmail.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 14 | ||||
-rw-r--r-- | include/dt-bindings/clock/tegra210-car.h | 2 |
2 files changed, 15 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 9e6260869eb9..f790c2dc5b5d 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c | |||
@@ -41,6 +41,7 @@ | |||
41 | #define CLK_SOURCE_CSITE 0x1d4 | 41 | #define CLK_SOURCE_CSITE 0x1d4 |
42 | #define CLK_SOURCE_EMC 0x19c | 42 | #define CLK_SOURCE_EMC 0x19c |
43 | #define CLK_SOURCE_SOR1 0x410 | 43 | #define CLK_SOURCE_SOR1 0x410 |
44 | #define CLK_SOURCE_LA 0x1f8 | ||
44 | 45 | ||
45 | #define PLLC_BASE 0x80 | 46 | #define PLLC_BASE 0x80 |
46 | #define PLLC_OUT 0x84 | 47 | #define PLLC_OUT 0x84 |
@@ -2654,6 +2655,13 @@ static struct tegra_periph_init_data tegra210_periph[] = { | |||
2654 | sor1_parents_idx, 0, &sor1_lock), | 2655 | sor1_parents_idx, 0, &sor1_lock), |
2655 | }; | 2656 | }; |
2656 | 2657 | ||
2658 | static const char * const la_parents[] = { | ||
2659 | "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0" | ||
2660 | }; | ||
2661 | |||
2662 | static struct tegra_clk_periph tegra210_la = | ||
2663 | TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, 0); | ||
2664 | |||
2657 | static __init void tegra210_periph_clk_init(void __iomem *clk_base, | 2665 | static __init void tegra210_periph_clk_init(void __iomem *clk_base, |
2658 | void __iomem *pmc_base) | 2666 | void __iomem *pmc_base) |
2659 | { | 2667 | { |
@@ -2700,6 +2708,12 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, | |||
2700 | periph_clk_enb_refcnt); | 2708 | periph_clk_enb_refcnt); |
2701 | clks[TEGRA210_CLK_DSIB] = clk; | 2709 | clks[TEGRA210_CLK_DSIB] = clk; |
2702 | 2710 | ||
2711 | /* la */ | ||
2712 | clk = tegra_clk_register_periph("la", la_parents, | ||
2713 | ARRAY_SIZE(la_parents), &tegra210_la, clk_base, | ||
2714 | CLK_SOURCE_LA, 0); | ||
2715 | clks[TEGRA210_CLK_LA] = clk; | ||
2716 | |||
2703 | /* emc mux */ | 2717 | /* emc mux */ |
2704 | clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, | 2718 | clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, |
2705 | ARRAY_SIZE(mux_pllmcp_clkm), 0, | 2719 | ARRAY_SIZE(mux_pllmcp_clkm), 0, |
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 6422314e46eb..6b77e721f6b1 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h | |||
@@ -95,7 +95,7 @@ | |||
95 | #define TEGRA210_CLK_CSITE 73 | 95 | #define TEGRA210_CLK_CSITE 73 |
96 | /* 74 */ | 96 | /* 74 */ |
97 | /* 75 */ | 97 | /* 75 */ |
98 | /* 76 */ | 98 | #define TEGRA210_CLK_LA 76 |
99 | /* 77 */ | 99 | /* 77 */ |
100 | #define TEGRA210_CLK_SOC_THERM 78 | 100 | #define TEGRA210_CLK_SOC_THERM 78 |
101 | #define TEGRA210_CLK_DTV 79 | 101 | #define TEGRA210_CLK_DTV 79 |