drm/i915/execlists: Split the atomic test_and_clear_bit for irq handler

Rather than impose the cost of a locked test before queuing a new
request, reduce it to a simple test_bit() with a following clear_bit()
prior to doing the CSB check. This ensure that if an interrupt does
occur whilst reading from the CSB, we still detect it (the interrupt
would trigger a rescheduling of the tasklet anyway).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/20170321113320.2603-1-chris@chris-wilson.co.uk
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

1 files changed, 6 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dab73e7d9a6b..a88380876ce9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -530,13 +530,18 @@ static void intel_lrc_irq_handler(unsigned long data)
 
         intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
 
-        while (test_and_clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
+        /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
+         * imposing the cost of a locked atomic transaction when submitting a
+         * new request (outside of the context-switch interrupt).
+         */
+        while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
                 u32 __iomem *csb_mmio =
                         dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
                 u32 __iomem *buf =
                         dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
                 unsigned int csb, head, tail;
 
+                clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
                 csb = readl(csb_mmio);
                 head = GEN8_CSB_READ_PTR(csb);
                 tail = GEN8_CSB_WRITE_PTR(csb);