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authorMichael Chan <michael.chan@broadcom.com>2018-01-17 03:21:03 -0500
committerDavid S. Miller <davem@davemloft.net>2018-01-17 14:48:25 -0500
commit894aa69a90932907f3de9d849ab9970884151d0e (patch)
treeb08990996d49e1f651319476063b0fe2c42004c1
parentee81098efe0de33d1dbddcb293c6a3a6a126f9e0 (diff)
bnxt_en: Update firmware interface to 1.9.0.
The version has new firmware APIs to allocate PF/VF resources more flexibly. New toolchains were used to generate this file, resulting in a one-time large diffstat. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt.c19
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt.h6
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h11936
3 files changed, 5854 insertions, 6107 deletions
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
index 6b2a7fe0dbde..3015d863bc8c 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -1,7 +1,7 @@
1/* Broadcom NetXtreme-C/E network driver. 1/* Broadcom NetXtreme-C/E network driver.
2 * 2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation 3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited 4 * Copyright (c) 2016-2018 Broadcom Limited
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -4938,23 +4938,24 @@ static int bnxt_hwrm_ver_get(struct bnxt *bp)
4938 4938
4939 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); 4939 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4940 4940
4941 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 | 4941 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
4942 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd; 4942 resp->hwrm_intf_min_8b << 8 |
4943 if (resp->hwrm_intf_maj < 1) { 4943 resp->hwrm_intf_upd_8b;
4944 if (resp->hwrm_intf_maj_8b < 1) {
4944 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", 4945 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4945 resp->hwrm_intf_maj, resp->hwrm_intf_min, 4946 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
4946 resp->hwrm_intf_upd); 4947 resp->hwrm_intf_upd_8b);
4947 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); 4948 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4948 } 4949 }
4949 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d", 4950 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
4950 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld, 4951 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
4951 resp->hwrm_fw_rsvd); 4952 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
4952 4953
4953 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout); 4954 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4954 if (!bp->hwrm_cmd_timeout) 4955 if (!bp->hwrm_cmd_timeout)
4955 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT; 4956 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4956 4957
4957 if (resp->hwrm_intf_maj >= 1) 4958 if (resp->hwrm_intf_maj_8b >= 1)
4958 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len); 4959 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4959 4960
4960 bp->chip_num = le16_to_cpu(resp->chip_num); 4961 bp->chip_num = le16_to_cpu(resp->chip_num);
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
index 89887a88b1bd..6ef222b7fa71 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
@@ -1,7 +1,7 @@
1/* Broadcom NetXtreme-C/E network driver. 1/* Broadcom NetXtreme-C/E network driver.
2 * 2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation 3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited 4 * Copyright (c) 2016-2018 Broadcom Limited
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -12,10 +12,10 @@
12#define BNXT_H 12#define BNXT_H
13 13
14#define DRV_MODULE_NAME "bnxt_en" 14#define DRV_MODULE_NAME "bnxt_en"
15#define DRV_MODULE_VERSION "1.8.0" 15#define DRV_MODULE_VERSION "1.9.0"
16 16
17#define DRV_VER_MAJ 1 17#define DRV_VER_MAJ 1
18#define DRV_VER_MIN 8 18#define DRV_VER_MIN 9
19#define DRV_VER_UPD 0 19#define DRV_VER_UPD 0
20 20
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
index c99f4d0880e4..82d17f8cc0db 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
@@ -1,2437 +1,2700 @@
1/* Broadcom NetXtreme-C/E network driver. 1/* Broadcom NetXtreme-C/E network driver.
2 * 2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation 3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited 4 * Copyright (c) 2016-2018 Broadcom Limited
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation. 8 * the Free Software Foundation.
9 *
10 * DO NOT MODIFY!!! This file is automatically generated.
9 */ 11 */
10 12
11#ifndef BNXT_HSI_H 13#ifndef _BNXT_HSI_H_
12#define BNXT_HSI_H 14#define _BNXT_HSI_H_
15
16/* hwrm_cmd_hdr (size:128b/16B) */
17struct hwrm_cmd_hdr {
18 __le16 req_type;
19 __le16 cmpl_ring;
20 __le16 seq_id;
21 __le16 target_id;
22 __le64 resp_addr;
23};
24
25/* hwrm_resp_hdr (size:64b/8B) */
26struct hwrm_resp_hdr {
27 __le16 error_code;
28 __le16 req_type;
29 __le16 seq_id;
30 __le16 resp_len;
31};
32
33#define CMD_DISCR_TLV_ENCAP 0x8000UL
34#define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
35
36
37#define TLV_TYPE_HWRM_REQUEST 0x1UL
38#define TLV_TYPE_HWRM_RESPONSE 0x2UL
39#define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
40#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL
41#define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL
42#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
43#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
44#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
45#define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL
46#define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL
47#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
48#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
49
50
51/* tlv (size:64b/8B) */
52struct tlv {
53 __le16 cmd_discr;
54 u8 reserved_8b;
55 u8 flags;
56 #define TLV_FLAGS_MORE 0x1UL
57 #define TLV_FLAGS_MORE_LAST 0x0UL
58 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL
59 #define TLV_FLAGS_REQUIRED 0x2UL
60 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
61 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
62 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
63 __le16 tlv_type;
64 __le16 length;
65};
66
67/* input (size:128b/16B) */
68struct input {
69 __le16 req_type;
70 __le16 cmpl_ring;
71 __le16 seq_id;
72 __le16 target_id;
73 __le64 resp_addr;
74};
13 75
14/* HSI and HWRM Specification 1.8.3 */ 76/* output (size:64b/8B) */
15#define HWRM_VERSION_MAJOR 1 77struct output {
16#define HWRM_VERSION_MINOR 8 78 __le16 error_code;
17#define HWRM_VERSION_UPDATE 3 79 __le16 req_type;
80 __le16 seq_id;
81 __le16 resp_len;
82};
18 83
19#define HWRM_VERSION_RSVD 1 /* non-zero means beta version */ 84/* hwrm_short_input (size:128b/16B) */
85struct hwrm_short_input {
86 __le16 req_type;
87 __le16 signature;
88 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
89 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
90 __le16 unused_0;
91 __le16 size;
92 __le64 req_addr;
93};
20 94
21#define HWRM_VERSION_STR "1.8.3.1" 95/* cmd_nums (size:64b/8B) */
22/* 96struct cmd_nums {
23 * Following is the signature for HWRM message field that indicates not 97 __le16 req_type;
24 * applicable (All F's). Need to cast it the size of the field if needed. 98 #define HWRM_VER_GET 0x0UL
25 */ 99 #define HWRM_FUNC_BUF_UNRGTR 0xeUL
26#define HWRM_NA_SIGNATURE ((__le32)(-1)) 100 #define HWRM_FUNC_VF_CFG 0xfUL
27#define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 101 #define HWRM_RESERVED1 0x10UL
28#define HWRM_MAX_RESP_LEN (280) /* hwrm_selftest_qlist */ 102 #define HWRM_FUNC_RESET 0x11UL
29#define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 103 #define HWRM_FUNC_GETFID 0x12UL
30#define HW_HASH_KEY_SIZE 40 104 #define HWRM_FUNC_VF_ALLOC 0x13UL
31#define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 105 #define HWRM_FUNC_VF_FREE 0x14UL
32 106 #define HWRM_FUNC_QCAPS 0x15UL
33/* Statistics Ejection Buffer Completion Record (16 bytes) */ 107 #define HWRM_FUNC_QCFG 0x16UL
108 #define HWRM_FUNC_CFG 0x17UL
109 #define HWRM_FUNC_QSTATS 0x18UL
110 #define HWRM_FUNC_CLR_STATS 0x19UL
111 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL
112 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL
113 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL
114 #define HWRM_FUNC_DRV_RGTR 0x1dUL
115 #define HWRM_FUNC_DRV_QVER 0x1eUL
116 #define HWRM_FUNC_BUF_RGTR 0x1fUL
117 #define HWRM_PORT_PHY_CFG 0x20UL
118 #define HWRM_PORT_MAC_CFG 0x21UL
119 #define HWRM_PORT_TS_QUERY 0x22UL
120 #define HWRM_PORT_QSTATS 0x23UL
121 #define HWRM_PORT_LPBK_QSTATS 0x24UL
122 #define HWRM_PORT_CLR_STATS 0x25UL
123 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL
124 #define HWRM_PORT_PHY_QCFG 0x27UL
125 #define HWRM_PORT_MAC_QCFG 0x28UL
126 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL
127 #define HWRM_PORT_PHY_QCAPS 0x2aUL
128 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL
129 #define HWRM_PORT_PHY_I2C_READ 0x2cUL
130 #define HWRM_PORT_LED_CFG 0x2dUL
131 #define HWRM_PORT_LED_QCFG 0x2eUL
132 #define HWRM_PORT_LED_QCAPS 0x2fUL
133 #define HWRM_QUEUE_QPORTCFG 0x30UL
134 #define HWRM_QUEUE_QCFG 0x31UL
135 #define HWRM_QUEUE_CFG 0x32UL
136 #define HWRM_FUNC_VLAN_CFG 0x33UL
137 #define HWRM_FUNC_VLAN_QCFG 0x34UL
138 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL
139 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL
140 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL
141 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL
142 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL
143 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL
144 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL
145 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL
146 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL
147 #define HWRM_VNIC_ALLOC 0x40UL
148 #define HWRM_VNIC_FREE 0x41UL
149 #define HWRM_VNIC_CFG 0x42UL
150 #define HWRM_VNIC_QCFG 0x43UL
151 #define HWRM_VNIC_TPA_CFG 0x44UL
152 #define HWRM_VNIC_TPA_QCFG 0x45UL
153 #define HWRM_VNIC_RSS_CFG 0x46UL
154 #define HWRM_VNIC_RSS_QCFG 0x47UL
155 #define HWRM_VNIC_PLCMODES_CFG 0x48UL
156 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL
157 #define HWRM_VNIC_QCAPS 0x4aUL
158 #define HWRM_RING_ALLOC 0x50UL
159 #define HWRM_RING_FREE 0x51UL
160 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
161 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
162 #define HWRM_RING_RESET 0x5eUL
163 #define HWRM_RING_GRP_ALLOC 0x60UL
164 #define HWRM_RING_GRP_FREE 0x61UL
165 #define HWRM_RESERVED5 0x64UL
166 #define HWRM_RESERVED6 0x65UL
167 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL
168 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL
169 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
170 #define HWRM_CFA_L2_FILTER_FREE 0x91UL
171 #define HWRM_CFA_L2_FILTER_CFG 0x92UL
172 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL
173 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL
174 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL
175 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL
176 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL
177 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL
178 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL
179 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL
180 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL
181 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL
182 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL
183 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL
184 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
185 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
186 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
187 #define HWRM_STAT_CTX_ALLOC 0xb0UL
188 #define HWRM_STAT_CTX_FREE 0xb1UL
189 #define HWRM_STAT_CTX_QUERY 0xb2UL
190 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL
191 #define HWRM_FW_RESET 0xc0UL
192 #define HWRM_FW_QSTATUS 0xc1UL
193 #define HWRM_FW_SET_TIME 0xc8UL
194 #define HWRM_FW_GET_TIME 0xc9UL
195 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
196 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL
197 #define HWRM_FW_IPC_MAILBOX 0xccUL
198 #define HWRM_EXEC_FWD_RESP 0xd0UL
199 #define HWRM_REJECT_FWD_RESP 0xd1UL
200 #define HWRM_FWD_RESP 0xd2UL
201 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
202 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL
203 #define HWRM_WOL_FILTER_ALLOC 0xf0UL
204 #define HWRM_WOL_FILTER_FREE 0xf1UL
205 #define HWRM_WOL_FILTER_QCFG 0xf2UL
206 #define HWRM_WOL_REASON_QCFG 0xf3UL
207 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
208 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
209 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
210 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
211 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
212 #define HWRM_CFA_VFR_ALLOC 0xfdUL
213 #define HWRM_CFA_VFR_FREE 0xfeUL
214 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
215 #define HWRM_CFA_VF_PAIR_FREE 0x101UL
216 #define HWRM_CFA_VF_PAIR_INFO 0x102UL
217 #define HWRM_CFA_FLOW_ALLOC 0x103UL
218 #define HWRM_CFA_FLOW_FREE 0x104UL
219 #define HWRM_CFA_FLOW_FLUSH 0x105UL
220 #define HWRM_CFA_FLOW_STATS 0x106UL
221 #define HWRM_CFA_FLOW_INFO 0x107UL
222 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL
223 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL
224 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL
225 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL
226 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL
227 #define HWRM_CFA_PAIR_ALLOC 0x10dUL
228 #define HWRM_CFA_PAIR_FREE 0x10eUL
229 #define HWRM_CFA_PAIR_INFO 0x10fUL
230 #define HWRM_FW_IPC_MSG 0x110UL
231 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
232 #define HWRM_ENGINE_CKV_HELLO 0x12dUL
233 #define HWRM_ENGINE_CKV_STATUS 0x12eUL
234 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
235 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
236 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL
237 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL
238 #define HWRM_ENGINE_CKV_FLUSH 0x133UL
239 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL
240 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
241 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
242 #define HWRM_ENGINE_QG_QUERY 0x13dUL
243 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
244 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL
245 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL
246 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL
247 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL
248 #define HWRM_ENGINE_QG_METER_BIND 0x143UL
249 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL
250 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL
251 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL
252 #define HWRM_ENGINE_SG_QUERY 0x147UL
253 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL
254 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL
255 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL
256 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL
257 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL
258 #define HWRM_ENGINE_STATS_CONFIG 0x155UL
259 #define HWRM_ENGINE_STATS_CLEAR 0x156UL
260 #define HWRM_ENGINE_STATS_QUERY 0x157UL
261 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL
262 #define HWRM_ENGINE_RQ_FREE 0x15fUL
263 #define HWRM_ENGINE_CQ_ALLOC 0x160UL
264 #define HWRM_ENGINE_CQ_FREE 0x161UL
265 #define HWRM_ENGINE_NQ_ALLOC 0x162UL
266 #define HWRM_ENGINE_NQ_FREE 0x163UL
267 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
268 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
269 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
270 #define HWRM_SELFTEST_QLIST 0x200UL
271 #define HWRM_SELFTEST_EXEC 0x201UL
272 #define HWRM_SELFTEST_IRQ 0x202UL
273 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL
274 #define HWRM_DBG_READ_DIRECT 0xff10UL
275 #define HWRM_DBG_READ_INDIRECT 0xff11UL
276 #define HWRM_DBG_WRITE_DIRECT 0xff12UL
277 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL
278 #define HWRM_DBG_DUMP 0xff14UL
279 #define HWRM_DBG_ERASE_NVM 0xff15UL
280 #define HWRM_DBG_CFG 0xff16UL
281 #define HWRM_DBG_COREDUMP_LIST 0xff17UL
282 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL
283 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
284 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
285 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL
286 #define HWRM_NVM_FLUSH 0xfff0UL
287 #define HWRM_NVM_GET_VARIABLE 0xfff1UL
288 #define HWRM_NVM_SET_VARIABLE 0xfff2UL
289 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL
290 #define HWRM_NVM_MODIFY 0xfff4UL
291 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL
292 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL
293 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL
294 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL
295 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL
296 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL
297 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL
298 #define HWRM_NVM_RAW_DUMP 0xfffcUL
299 #define HWRM_NVM_READ 0xfffdUL
300 #define HWRM_NVM_WRITE 0xfffeUL
301 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL
302 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
303 __le16 unused_0[3];
304};
305
306/* ret_codes (size:64b/8B) */
307struct ret_codes {
308 __le16 error_code;
309 #define HWRM_ERR_CODE_SUCCESS 0x0UL
310 #define HWRM_ERR_CODE_FAIL 0x1UL
311 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
312 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
313 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
314 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
315 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
316 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
317 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
318 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
319 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
320 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
321 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
322 __le16 unused_0[3];
323};
324
325/* hwrm_err_output (size:128b/16B) */
326struct hwrm_err_output {
327 __le16 error_code;
328 __le16 req_type;
329 __le16 seq_id;
330 __le16 resp_len;
331 __le32 opaque_0;
332 __le16 opaque_1;
333 u8 cmd_err;
334 u8 valid;
335};
336#define HWRM_NA_SIGNATURE ((__le32)(-1))
337#define HWRM_MAX_REQ_LEN 128
338#define HWRM_MAX_RESP_LEN 280
339#define HW_HASH_INDEX_SIZE 0x80
340#define HW_HASH_KEY_SIZE 40
341#define HWRM_RESP_VALID_KEY 1
342#define HWRM_VERSION_MAJOR 1
343#define HWRM_VERSION_MINOR 9
344#define HWRM_VERSION_UPDATE 0
345#define HWRM_VERSION_RSVD 0
346#define HWRM_VERSION_STR "1.9.0.0"
347
348/* hwrm_ver_get_input (size:192b/24B) */
349struct hwrm_ver_get_input {
350 __le16 req_type;
351 __le16 cmpl_ring;
352 __le16 seq_id;
353 __le16 target_id;
354 __le64 resp_addr;
355 u8 hwrm_intf_maj;
356 u8 hwrm_intf_min;
357 u8 hwrm_intf_upd;
358 u8 unused_0[5];
359};
360
361/* hwrm_ver_get_output (size:1408b/176B) */
362struct hwrm_ver_get_output {
363 __le16 error_code;
364 __le16 req_type;
365 __le16 seq_id;
366 __le16 resp_len;
367 u8 hwrm_intf_maj_8b;
368 u8 hwrm_intf_min_8b;
369 u8 hwrm_intf_upd_8b;
370 u8 hwrm_intf_rsvd_8b;
371 u8 hwrm_fw_maj_8b;
372 u8 hwrm_fw_min_8b;
373 u8 hwrm_fw_bld_8b;
374 u8 hwrm_fw_rsvd_8b;
375 u8 mgmt_fw_maj_8b;
376 u8 mgmt_fw_min_8b;
377 u8 mgmt_fw_bld_8b;
378 u8 mgmt_fw_rsvd_8b;
379 u8 netctrl_fw_maj_8b;
380 u8 netctrl_fw_min_8b;
381 u8 netctrl_fw_bld_8b;
382 u8 netctrl_fw_rsvd_8b;
383 __le32 dev_caps_cfg;
384 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
385 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
386 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
387 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
388 u8 roce_fw_maj_8b;
389 u8 roce_fw_min_8b;
390 u8 roce_fw_bld_8b;
391 u8 roce_fw_rsvd_8b;
392 char hwrm_fw_name[16];
393 char mgmt_fw_name[16];
394 char netctrl_fw_name[16];
395 u8 reserved2[16];
396 char roce_fw_name[16];
397 __le16 chip_num;
398 u8 chip_rev;
399 u8 chip_metal;
400 u8 chip_bond_id;
401 u8 chip_platform_type;
402 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL
403 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL
404 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
405 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
406 __le16 max_req_win_len;
407 __le16 max_resp_len;
408 __le16 def_req_timeout;
409 u8 flags;
410 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL
411 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL
412 u8 unused_0[2];
413 u8 always_1;
414 __le16 hwrm_intf_major;
415 __le16 hwrm_intf_minor;
416 __le16 hwrm_intf_build;
417 __le16 hwrm_intf_patch;
418 __le16 hwrm_fw_major;
419 __le16 hwrm_fw_minor;
420 __le16 hwrm_fw_build;
421 __le16 hwrm_fw_patch;
422 __le16 mgmt_fw_major;
423 __le16 mgmt_fw_minor;
424 __le16 mgmt_fw_build;
425 __le16 mgmt_fw_patch;
426 __le16 netctrl_fw_major;
427 __le16 netctrl_fw_minor;
428 __le16 netctrl_fw_build;
429 __le16 netctrl_fw_patch;
430 __le16 roce_fw_major;
431 __le16 roce_fw_minor;
432 __le16 roce_fw_build;
433 __le16 roce_fw_patch;
434 __le16 max_ext_req_len;
435 u8 unused_1[5];
436 u8 valid;
437};
438
439/* eject_cmpl (size:128b/16B) */
34struct eject_cmpl { 440struct eject_cmpl {
35 __le16 type; 441 __le16 type;
36 #define EJECT_CMPL_TYPE_MASK 0x3fUL 442 #define EJECT_CMPL_TYPE_MASK 0x3fUL
37 #define EJECT_CMPL_TYPE_SFT 0 443 #define EJECT_CMPL_TYPE_SFT 0
38 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 444 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
39 __le16 len; 445 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
40 __le32 opaque; 446 __le16 len;
41 __le32 v; 447 __le32 opaque;
42 #define EJECT_CMPL_V 0x1UL 448 __le32 v;
43 __le32 unused_2; 449 #define EJECT_CMPL_V 0x1UL
44}; 450 __le32 unused_2;
45 451};
46/* HWRM Completion Record (16 bytes) */ 452
453/* hwrm_cmpl (size:128b/16B) */
47struct hwrm_cmpl { 454struct hwrm_cmpl {
48 __le16 type; 455 __le16 type;
49 #define CMPL_TYPE_MASK 0x3fUL 456 #define CMPL_TYPE_MASK 0x3fUL
50 #define CMPL_TYPE_SFT 0 457 #define CMPL_TYPE_SFT 0
51 #define CMPL_TYPE_HWRM_DONE 0x20UL 458 #define CMPL_TYPE_HWRM_DONE 0x20UL
52 __le16 sequence_id; 459 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE
53 __le32 unused_1; 460 __le16 sequence_id;
54 __le32 v; 461 __le32 unused_1;
55 #define CMPL_V 0x1UL 462 __le32 v;
56 __le32 unused_3; 463 #define CMPL_V 0x1UL
57}; 464 __le32 unused_3;
58 465};
59/* HWRM Forwarded Request (16 bytes) */ 466
467/* hwrm_fwd_req_cmpl (size:128b/16B) */
60struct hwrm_fwd_req_cmpl { 468struct hwrm_fwd_req_cmpl {
61 __le16 req_len_type; 469 __le16 req_len_type;
62 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 470 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL
63 #define FWD_REQ_CMPL_TYPE_SFT 0 471 #define FWD_REQ_CMPL_TYPE_SFT 0
64 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 472 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL
65 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 473 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
66 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 474 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
67 __le16 source_id; 475 #define FWD_REQ_CMPL_REQ_LEN_SFT 6
68 __le32 unused_0; 476 __le16 source_id;
69 __le32 req_buf_addr_v[2]; 477 __le32 unused0;
70 #define FWD_REQ_CMPL_V 0x1UL 478 __le32 req_buf_addr_v[2];
71 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 479 #define FWD_REQ_CMPL_V 0x1UL
72 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 480 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
73}; 481 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
74 482};
75/* HWRM Forwarded Response (16 bytes) */ 483
484/* hwrm_fwd_resp_cmpl (size:128b/16B) */
76struct hwrm_fwd_resp_cmpl { 485struct hwrm_fwd_resp_cmpl {
77 __le16 type; 486 __le16 type;
78 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 487 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL
79 #define FWD_RESP_CMPL_TYPE_SFT 0 488 #define FWD_RESP_CMPL_TYPE_SFT 0
80 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 489 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL
81 __le16 source_id; 490 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
82 __le16 resp_len; 491 __le16 source_id;
83 __le16 unused_1; 492 __le16 resp_len;
84 __le32 resp_buf_addr_v[2]; 493 __le16 unused_1;
85 #define FWD_RESP_CMPL_V 0x1UL 494 __le32 resp_buf_addr_v[2];
86 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 495 #define FWD_RESP_CMPL_V 0x1UL
87 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 496 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
88}; 497 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
89 498};
90/* HWRM Asynchronous Event Completion Record (16 bytes) */ 499
500/* hwrm_async_event_cmpl (size:128b/16B) */
91struct hwrm_async_event_cmpl { 501struct hwrm_async_event_cmpl {
92 __le16 type; 502 __le16 type;
93 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 503 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
94 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 504 #define ASYNC_EVENT_CMPL_TYPE_SFT 0
95 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 505 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
96 __le16 event_id; 506 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
97 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 507 __le16 event_id;
98 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 508 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
99 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 509 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL
100 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 510 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
101 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 511 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
512 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
102 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 513 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
103 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 514 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
104 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 515 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
105 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 516 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
106 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 517 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
107 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 518 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
108 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 519 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
109 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 520 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL
110 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 521 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL
111 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 522 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
112 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 523 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
113 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 524 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
114 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 525 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
115 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 526 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
116 __le32 event_data2; 527 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
117 u8 opaque_v; 528 __le32 event_data2;
118 #define ASYNC_EVENT_CMPL_V 0x1UL 529 u8 opaque_v;
119 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 530 #define ASYNC_EVENT_CMPL_V 0x1UL
120 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 531 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
121 u8 timestamp_lo; 532 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
122 __le16 timestamp_hi; 533 u8 timestamp_lo;
123 __le32 event_data1; 534 __le16 timestamp_hi;
124}; 535 __le32 event_data1;
125 536};
126/* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 537
538/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
127struct hwrm_async_event_cmpl_link_status_change { 539struct hwrm_async_event_cmpl_link_status_change {
128 __le16 type; 540 __le16 type;
129 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 541 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
130 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 542 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
131 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 543 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
132 __le16 event_id; 544 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
545 __le16 event_id;
133 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 546 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
134 __le32 event_data2; 547 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
135 u8 opaque_v; 548 __le32 event_data2;
136 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 549 u8 opaque_v;
137 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 550 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
138 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 551 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
139 u8 timestamp_lo; 552 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
140 __le16 timestamp_hi; 553 u8 timestamp_lo;
141 __le32 event_data1; 554 __le16 timestamp_hi;
142 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 555 __le32 event_data1;
143 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) 556 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
144 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) 557 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL
145 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 558 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL
146 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 559 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
147 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 560 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
148 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 561 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
149 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 562 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
150}; 563 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
151 564};
152/* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 565
153struct hwrm_async_event_cmpl_link_mtu_change { 566/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
154 __le16 type;
155 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL
156 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
157 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
158 __le16 event_id;
159 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL
160 __le32 event_data2;
161 u8 opaque_v;
162 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL
163 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL
164 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
165 u8 timestamp_lo;
166 __le16 timestamp_hi;
167 __le32 event_data1;
168 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL
169 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
170};
171
172/* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */
173struct hwrm_async_event_cmpl_link_speed_change {
174 __le16 type;
175 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL
176 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
177 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
178 __le16 event_id;
179 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
180 __le32 event_data2;
181 u8 opaque_v;
182 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL
183 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL
184 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
185 u8 timestamp_lo;
186 __le16 timestamp_hi;
187 __le32 event_data1;
188 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL
189 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL
190 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1
191 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1)
192 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1)
193 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1)
194 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1)
195 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1)
196 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1)
197 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1)
198 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1)
199 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1)
200 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1)
201 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
202 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL
203 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16
204};
205
206/* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */
207struct hwrm_async_event_cmpl_dcb_config_change {
208 __le16 type;
209 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL
210 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
211 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
212 __le16 event_id;
213 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
214 __le32 event_data2;
215 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS 0x1UL
216 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC 0x2UL
217 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP 0x4UL
218 u8 opaque_v;
219 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL
220 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL
221 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
222 u8 timestamp_lo;
223 __le16 timestamp_hi;
224 __le32 event_data1;
225 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
226 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
227 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL
228 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16
229 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (0xffUL << 16)
230 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
231 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK 0xff000000UL
232 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24
233 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (0xffUL << 24)
234 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
235};
236
237/* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */
238struct hwrm_async_event_cmpl_port_conn_not_allowed { 567struct hwrm_async_event_cmpl_port_conn_not_allowed {
239 __le16 type; 568 __le16 type;
240 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 569 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
241 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 570 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
242 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 571 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
243 __le16 event_id; 572 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
573 __le16 event_id;
244 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 574 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
245 __le32 event_data2; 575 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
246 u8 opaque_v; 576 __le32 event_data2;
247 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 577 u8 opaque_v;
578 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
248 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 579 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
249 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 580 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
250 u8 timestamp_lo; 581 u8 timestamp_lo;
251 __le16 timestamp_hi; 582 __le16 timestamp_hi;
252 __le32 event_data1; 583 __le32 event_data1;
253 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 584 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
254 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 585 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
255 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 586 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
256 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 587 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
257 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 588 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
258 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 589 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
259 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 590 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
260 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 591 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
261 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 592 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
262}; 593};
263 594
264/* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ 595/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
265struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
266 __le16 type;
267 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL
268 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0
269 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
270 __le16 event_id;
271 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
272 __le32 event_data2;
273 u8 opaque_v;
274 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL
275 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
276 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
277 u8 timestamp_lo;
278 __le16 timestamp_hi;
279 __le32 event_data1;
280 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
281 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
282};
283
284/* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */
285struct hwrm_async_event_cmpl_link_speed_cfg_change { 596struct hwrm_async_event_cmpl_link_speed_cfg_change {
286 __le16 type; 597 __le16 type;
287 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 598 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
288 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 599 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
289 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 600 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
290 __le16 event_id; 601 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
602 __le16 event_id;
291 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 603 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
292 __le32 event_data2; 604 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
293 u8 opaque_v; 605 __le32 event_data2;
294 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 606 u8 opaque_v;
607 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
295 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 608 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
296 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 609 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
297 u8 timestamp_lo; 610 u8 timestamp_lo;
298 __le16 timestamp_hi; 611 __le16 timestamp_hi;
299 __le32 event_data1; 612 __le32 event_data1;
300 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 613 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
301 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 614 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
302 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 615 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
303 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 616 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
304}; 617};
305 618
306/* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 619/* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
307struct hwrm_async_event_cmpl_func_drvr_unload {
308 __le16 type;
309 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL
310 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
311 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
312 __le16 event_id;
313 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
314 __le32 event_data2;
315 u8 opaque_v;
316 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL
317 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
318 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
319 u8 timestamp_lo;
320 __le16 timestamp_hi;
321 __le32 event_data1;
322 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
323 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
324};
325
326/* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */
327struct hwrm_async_event_cmpl_func_drvr_load {
328 __le16 type;
329 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL
330 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
331 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
332 __le16 event_id;
333 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
334 __le32 event_data2;
335 u8 opaque_v;
336 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL
337 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL
338 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
339 u8 timestamp_lo;
340 __le16 timestamp_hi;
341 __le32 event_data1;
342 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
343 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
344};
345
346/* HWRM Asynchronous Event Completion Record to indicate completion of FLR related processing (16 bytes) */
347struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
348 __le16 type;
349 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK 0x3fUL
350 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0
351 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT 0x2eUL
352 __le16 event_id;
353 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
354 __le32 event_data2;
355 u8 opaque_v;
356 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V 0x1UL
357 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK 0xfeUL
358 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
359 u8 timestamp_lo;
360 __le16 timestamp_hi;
361 __le32 event_data1;
362 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
363 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0
364};
365
366/* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */
367struct hwrm_async_event_cmpl_pf_drvr_unload { 620struct hwrm_async_event_cmpl_pf_drvr_unload {
368 __le16 type; 621 __le16 type;
369 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 622 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL
370 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 623 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
371 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 624 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
372 __le16 event_id; 625 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
626 __le16 event_id;
373 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 627 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
374 __le32 event_data2; 628 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
375 u8 opaque_v; 629 __le32 event_data2;
376 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 630 u8 opaque_v;
377 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 631 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL
378 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 632 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
379 u8 timestamp_lo; 633 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
380 __le16 timestamp_hi; 634 u8 timestamp_lo;
381 __le32 event_data1; 635 __le16 timestamp_hi;
636 __le32 event_data1;
382 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 637 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
383 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 638 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
384 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 639 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL
385 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 640 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
386}; 641};
387 642
388/* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 643/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
389struct hwrm_async_event_cmpl_pf_drvr_load {
390 __le16 type;
391 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL
392 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
393 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
394 __le16 event_id;
395 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL
396 __le32 event_data2;
397 u8 opaque_v;
398 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL
399 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL
400 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
401 u8 timestamp_lo;
402 __le16 timestamp_hi;
403 __le32 event_data1;
404 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
405 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
406 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL
407 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
408};
409
410/* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */
411struct hwrm_async_event_cmpl_vf_flr {
412 __le16 type;
413 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL
414 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
415 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
416 __le16 event_id;
417 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL
418 __le32 event_data2;
419 u8 opaque_v;
420 #define ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL
421 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL
422 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
423 u8 timestamp_lo;
424 __le16 timestamp_hi;
425 __le32 event_data1;
426 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL
427 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
428};
429
430/* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */
431struct hwrm_async_event_cmpl_vf_mac_addr_change {
432 __le16 type;
433 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL
434 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
435 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
436 __le16 event_id;
437 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
438 __le32 event_data2;
439 u8 opaque_v;
440 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL
441 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL
442 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
443 u8 timestamp_lo;
444 __le16 timestamp_hi;
445 __le32 event_data1;
446 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL
447 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
448};
449
450/* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */
451struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
452 __le16 type;
453 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL
454 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0
455 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
456 __le16 event_id;
457 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
458 __le32 event_data2;
459 u8 opaque_v;
460 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL
461 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
462 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
463 u8 timestamp_lo;
464 __le16 timestamp_hi;
465 __le32 event_data1;
466 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL
467};
468
469/* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */
470struct hwrm_async_event_cmpl_vf_cfg_change { 644struct hwrm_async_event_cmpl_vf_cfg_change {
471 __le16 type; 645 __le16 type;
472 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 646 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
473 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 647 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
474 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 648 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
475 __le16 event_id; 649 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
650 __le16 event_id;
476 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 651 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
477 __le32 event_data2; 652 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
478 u8 opaque_v; 653 __le32 event_data2;
479 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 654 u8 opaque_v;
480 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 655 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
481 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 656 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
482 u8 timestamp_lo; 657 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
483 __le16 timestamp_hi; 658 u8 timestamp_lo;
484 __le32 event_data1; 659 __le16 timestamp_hi;
485 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 660 __le32 event_data1;
486 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 661 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
487 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 662 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
488 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 663 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
489}; 664 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
490 665};
491/* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 666
492struct hwrm_async_event_cmpl_hwrm_error { 667/* hwrm_func_reset_input (size:192b/24B) */
493 __le16 type;
494 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL
495 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
496 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
497 __le16 event_id;
498 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL
499 __le32 event_data2;
500 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
501 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
502 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL
503 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL
504 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL
505 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
506 u8 opaque_v;
507 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL
508 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
509 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
510 u8 timestamp_lo;
511 __le16 timestamp_hi;
512 __le32 event_data1;
513 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
514};
515
516/* hwrm_ver_get */
517/* Input (24 bytes) */
518struct hwrm_ver_get_input {
519 __le16 req_type;
520 __le16 cmpl_ring;
521 __le16 seq_id;
522 __le16 target_id;
523 __le64 resp_addr;
524 u8 hwrm_intf_maj;
525 u8 hwrm_intf_min;
526 u8 hwrm_intf_upd;
527 u8 unused_0[5];
528};
529
530/* Output (128 bytes) */
531struct hwrm_ver_get_output {
532 __le16 error_code;
533 __le16 req_type;
534 __le16 seq_id;
535 __le16 resp_len;
536 u8 hwrm_intf_maj;
537 u8 hwrm_intf_min;
538 u8 hwrm_intf_upd;
539 u8 hwrm_intf_rsvd;
540 u8 hwrm_fw_maj;
541 u8 hwrm_fw_min;
542 u8 hwrm_fw_bld;
543 u8 hwrm_fw_rsvd;
544 u8 mgmt_fw_maj;
545 u8 mgmt_fw_min;
546 u8 mgmt_fw_bld;
547 u8 mgmt_fw_rsvd;
548 u8 netctrl_fw_maj;
549 u8 netctrl_fw_min;
550 u8 netctrl_fw_bld;
551 u8 netctrl_fw_rsvd;
552 __le32 dev_caps_cfg;
553 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
554 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
555 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
556 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
557 u8 roce_fw_maj;
558 u8 roce_fw_min;
559 u8 roce_fw_bld;
560 u8 roce_fw_rsvd;
561 char hwrm_fw_name[16];
562 char mgmt_fw_name[16];
563 char netctrl_fw_name[16];
564 __le32 reserved2[4];
565 char roce_fw_name[16];
566 __le16 chip_num;
567 u8 chip_rev;
568 u8 chip_metal;
569 u8 chip_bond_id;
570 u8 chip_platform_type;
571 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL
572 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL
573 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
574 __le16 max_req_win_len;
575 __le16 max_resp_len;
576 __le16 def_req_timeout;
577 u8 init_pending;
578 #define VER_GET_RESP_INIT_PENDING_DEV_NOT_RDY 0x1UL
579 u8 unused_0;
580 u8 unused_1;
581 u8 valid;
582};
583
584/* hwrm_func_reset */
585/* Input (24 bytes) */
586struct hwrm_func_reset_input { 668struct hwrm_func_reset_input {
587 __le16 req_type; 669 __le16 req_type;
588 __le16 cmpl_ring; 670 __le16 cmpl_ring;
589 __le16 seq_id; 671 __le16 seq_id;
590 __le16 target_id; 672 __le16 target_id;
591 __le64 resp_addr; 673 __le64 resp_addr;
592 __le32 enables; 674 __le32 enables;
593 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 675 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
594 __le16 vf_id; 676 __le16 vf_id;
595 u8 func_reset_level; 677 u8 func_reset_level;
596 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 678 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL
597 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 679 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
598 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 680 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
599 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 681 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL
600 u8 unused_0; 682 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
601}; 683 u8 unused_0;
602 684};
603/* Output (16 bytes) */ 685
686/* hwrm_func_reset_output (size:128b/16B) */
604struct hwrm_func_reset_output { 687struct hwrm_func_reset_output {
605 __le16 error_code; 688 __le16 error_code;
606 __le16 req_type; 689 __le16 req_type;
607 __le16 seq_id; 690 __le16 seq_id;
608 __le16 resp_len; 691 __le16 resp_len;
609 __le32 unused_0; 692 u8 unused_0[7];
610 u8 unused_1; 693 u8 valid;
611 u8 unused_2; 694};
612 u8 unused_3; 695
613 u8 valid; 696/* hwrm_func_getfid_input (size:192b/24B) */
614};
615
616/* hwrm_func_getfid */
617/* Input (24 bytes) */
618struct hwrm_func_getfid_input { 697struct hwrm_func_getfid_input {
619 __le16 req_type; 698 __le16 req_type;
620 __le16 cmpl_ring; 699 __le16 cmpl_ring;
621 __le16 seq_id; 700 __le16 seq_id;
622 __le16 target_id; 701 __le16 target_id;
623 __le64 resp_addr; 702 __le64 resp_addr;
624 __le32 enables; 703 __le32 enables;
625 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 704 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
626 __le16 pci_id; 705 __le16 pci_id;
627 __le16 unused_0; 706 u8 unused_0[2];
628}; 707};
629 708
630/* Output (16 bytes) */ 709/* hwrm_func_getfid_output (size:128b/16B) */
631struct hwrm_func_getfid_output { 710struct hwrm_func_getfid_output {
632 __le16 error_code; 711 __le16 error_code;
633 __le16 req_type; 712 __le16 req_type;
634 __le16 seq_id; 713 __le16 seq_id;
635 __le16 resp_len; 714 __le16 resp_len;
636 __le16 fid; 715 __le16 fid;
637 u8 unused_0; 716 u8 unused_0[5];
638 u8 unused_1; 717 u8 valid;
639 u8 unused_2; 718};
640 u8 unused_3; 719
641 u8 unused_4; 720/* hwrm_func_vf_alloc_input (size:192b/24B) */
642 u8 valid;
643};
644
645/* hwrm_func_vf_alloc */
646/* Input (24 bytes) */
647struct hwrm_func_vf_alloc_input { 721struct hwrm_func_vf_alloc_input {
648 __le16 req_type; 722 __le16 req_type;
649 __le16 cmpl_ring; 723 __le16 cmpl_ring;
650 __le16 seq_id; 724 __le16 seq_id;
651 __le16 target_id; 725 __le16 target_id;
652 __le64 resp_addr; 726 __le64 resp_addr;
653 __le32 enables; 727 __le32 enables;
654 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 728 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
655 __le16 first_vf_id; 729 __le16 first_vf_id;
656 __le16 num_vfs; 730 __le16 num_vfs;
657}; 731};
658 732
659/* Output (16 bytes) */ 733/* hwrm_func_vf_alloc_output (size:128b/16B) */
660struct hwrm_func_vf_alloc_output { 734struct hwrm_func_vf_alloc_output {
661 __le16 error_code; 735 __le16 error_code;
662 __le16 req_type; 736 __le16 req_type;
663 __le16 seq_id; 737 __le16 seq_id;
664 __le16 resp_len; 738 __le16 resp_len;
665 __le16 first_vf_id; 739 __le16 first_vf_id;
666 u8 unused_0; 740 u8 unused_0[5];
667 u8 unused_1; 741 u8 valid;
668 u8 unused_2; 742};
669 u8 unused_3; 743
670 u8 unused_4; 744/* hwrm_func_vf_free_input (size:192b/24B) */
671 u8 valid;
672};
673
674/* hwrm_func_vf_free */
675/* Input (24 bytes) */
676struct hwrm_func_vf_free_input { 745struct hwrm_func_vf_free_input {
677 __le16 req_type; 746 __le16 req_type;
678 __le16 cmpl_ring; 747 __le16 cmpl_ring;
679 __le16 seq_id; 748 __le16 seq_id;
680 __le16 target_id; 749 __le16 target_id;
681 __le64 resp_addr; 750 __le64 resp_addr;
682 __le32 enables; 751 __le32 enables;
683 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 752 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
684 __le16 first_vf_id; 753 __le16 first_vf_id;
685 __le16 num_vfs; 754 __le16 num_vfs;
686}; 755};
687 756
688/* Output (16 bytes) */ 757/* hwrm_func_vf_free_output (size:128b/16B) */
689struct hwrm_func_vf_free_output { 758struct hwrm_func_vf_free_output {
690 __le16 error_code; 759 __le16 error_code;
691 __le16 req_type; 760 __le16 req_type;
692 __le16 seq_id; 761 __le16 seq_id;
693 __le16 resp_len; 762 __le16 resp_len;
694 __le32 unused_0; 763 u8 unused_0[7];
695 u8 unused_1; 764 u8 valid;
696 u8 unused_2; 765};
697 u8 unused_3; 766
698 u8 valid; 767/* hwrm_func_vf_cfg_input (size:448b/56B) */
699};
700
701/* hwrm_func_vf_cfg */
702/* Input (32 bytes) */
703struct hwrm_func_vf_cfg_input { 768struct hwrm_func_vf_cfg_input {
704 __le16 req_type; 769 __le16 req_type;
705 __le16 cmpl_ring; 770 __le16 cmpl_ring;
706 __le16 seq_id; 771 __le16 seq_id;
707 __le16 target_id; 772 __le16 target_id;
708 __le64 resp_addr; 773 __le64 resp_addr;
709 __le32 enables; 774 __le32 enables;
710 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 775 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
711 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 776 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
712 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 777 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
713 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 778 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
714 __le16 mtu; 779 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL
715 __le16 guest_vlan; 780 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL
716 __le16 async_event_cr; 781 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL
717 u8 dflt_mac_addr[6]; 782 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL
718}; 783 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL
719 784 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL
720/* Output (16 bytes) */ 785 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL
786 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL
787 __le16 mtu;
788 __le16 guest_vlan;
789 __le16 async_event_cr;
790 u8 dflt_mac_addr[6];
791 __le32 flags;
792 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL
793 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL
794 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL
795 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL
796 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL
797 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL
798 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL
799 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL
800 __le16 num_rsscos_ctxs;
801 __le16 num_cmpl_rings;
802 __le16 num_tx_rings;
803 __le16 num_rx_rings;
804 __le16 num_l2_ctxs;
805 __le16 num_vnics;
806 __le16 num_stat_ctxs;
807 __le16 num_hw_ring_grps;
808 u8 unused_0[4];
809};
810
811/* hwrm_func_vf_cfg_output (size:128b/16B) */
721struct hwrm_func_vf_cfg_output { 812struct hwrm_func_vf_cfg_output {
722 __le16 error_code; 813 __le16 error_code;
723 __le16 req_type; 814 __le16 req_type;
724 __le16 seq_id; 815 __le16 seq_id;
725 __le16 resp_len; 816 __le16 resp_len;
726 __le32 unused_0; 817 u8 unused_0[7];
727 u8 unused_1; 818 u8 valid;
728 u8 unused_2; 819};
729 u8 unused_3; 820
730 u8 valid; 821/* hwrm_func_qcaps_input (size:192b/24B) */
731};
732
733/* hwrm_func_qcaps */
734/* Input (24 bytes) */
735struct hwrm_func_qcaps_input { 822struct hwrm_func_qcaps_input {
736 __le16 req_type; 823 __le16 req_type;
737 __le16 cmpl_ring; 824 __le16 cmpl_ring;
738 __le16 seq_id; 825 __le16 seq_id;
739 __le16 target_id; 826 __le16 target_id;
740 __le64 resp_addr; 827 __le64 resp_addr;
741 __le16 fid; 828 __le16 fid;
742 __le16 unused_0[3]; 829 u8 unused_0[6];
743}; 830};
744 831
745/* Output (80 bytes) */ 832/* hwrm_func_qcaps_output (size:640b/80B) */
746struct hwrm_func_qcaps_output { 833struct hwrm_func_qcaps_output {
747 __le16 error_code; 834 __le16 error_code;
748 __le16 req_type; 835 __le16 req_type;
749 __le16 seq_id; 836 __le16 seq_id;
750 __le16 resp_len; 837 __le16 resp_len;
751 __le16 fid; 838 __le16 fid;
752 __le16 port_id; 839 __le16 port_id;
753 __le32 flags; 840 __le32 flags;
754 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 841 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
755 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 842 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
756 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 843 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
757 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 844 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
758 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 845 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
759 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 846 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
760 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 847 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
761 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 848 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
762 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 849 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
763 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 850 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
764 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 851 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
765 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 852 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
766 u8 mac_address[6]; 853 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
767 __le16 max_rsscos_ctx; 854 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
768 __le16 max_cmpl_rings; 855 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
769 __le16 max_tx_rings; 856 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
770 __le16 max_rx_rings; 857 u8 mac_address[6];
771 __le16 max_l2_ctxs; 858 __le16 max_rsscos_ctx;
772 __le16 max_vnics; 859 __le16 max_cmpl_rings;
773 __le16 first_vf_id; 860 __le16 max_tx_rings;
774 __le16 max_vfs; 861 __le16 max_rx_rings;
775 __le16 max_stat_ctx; 862 __le16 max_l2_ctxs;
776 __le32 max_encap_records; 863 __le16 max_vnics;
777 __le32 max_decap_records; 864 __le16 first_vf_id;
778 __le32 max_tx_em_flows; 865 __le16 max_vfs;
779 __le32 max_tx_wm_flows; 866 __le16 max_stat_ctx;
780 __le32 max_rx_em_flows; 867 __le32 max_encap_records;
781 __le32 max_rx_wm_flows; 868 __le32 max_decap_records;
782 __le32 max_mcast_filters; 869 __le32 max_tx_em_flows;
783 __le32 max_flow_id; 870 __le32 max_tx_wm_flows;
784 __le32 max_hw_ring_grps; 871 __le32 max_rx_em_flows;
785 __le16 max_sp_tx_rings; 872 __le32 max_rx_wm_flows;
786 u8 unused_0; 873 __le32 max_mcast_filters;
787 u8 valid; 874 __le32 max_flow_id;
788}; 875 __le32 max_hw_ring_grps;
789 876 __le16 max_sp_tx_rings;
790/* hwrm_func_qcfg */ 877 u8 unused_0;
791/* Input (24 bytes) */ 878 u8 valid;
879};
880
881/* hwrm_func_qcfg_input (size:192b/24B) */
792struct hwrm_func_qcfg_input { 882struct hwrm_func_qcfg_input {
793 __le16 req_type; 883 __le16 req_type;
794 __le16 cmpl_ring; 884 __le16 cmpl_ring;
795 __le16 seq_id; 885 __le16 seq_id;
796 __le16 target_id; 886 __le16 target_id;
797 __le64 resp_addr; 887 __le64 resp_addr;
798 __le16 fid; 888 __le16 fid;
799 __le16 unused_0[3]; 889 u8 unused_0[6];
800}; 890};
801 891
802/* Output (72 bytes) */ 892/* hwrm_func_qcfg_output (size:640b/80B) */
803struct hwrm_func_qcfg_output { 893struct hwrm_func_qcfg_output {
804 __le16 error_code; 894 __le16 error_code;
805 __le16 req_type; 895 __le16 req_type;
806 __le16 seq_id; 896 __le16 seq_id;
807 __le16 resp_len; 897 __le16 resp_len;
808 __le16 fid; 898 __le16 fid;
809 __le16 port_id; 899 __le16 port_id;
810 __le16 vlan; 900 __le16 vlan;
811 __le16 flags; 901 __le16 flags;
812 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 902 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL
813 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 903 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL
814 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 904 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL
815 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 905 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
816 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 906 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
817 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 907 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
818 u8 mac_address[6]; 908 u8 mac_address[6];
819 __le16 pci_id; 909 __le16 pci_id;
820 __le16 alloc_rsscos_ctx; 910 __le16 alloc_rsscos_ctx;
821 __le16 alloc_cmpl_rings; 911 __le16 alloc_cmpl_rings;
822 __le16 alloc_tx_rings; 912 __le16 alloc_tx_rings;
823 __le16 alloc_rx_rings; 913 __le16 alloc_rx_rings;
824 __le16 alloc_l2_ctx; 914 __le16 alloc_l2_ctx;
825 __le16 alloc_vnics; 915 __le16 alloc_vnics;
826 __le16 mtu; 916 __le16 mtu;
827 __le16 mru; 917 __le16 mru;
828 __le16 stat_ctx_id; 918 __le16 stat_ctx_id;
829 u8 port_partition_type; 919 u8 port_partition_type;
830 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 920 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL
831 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 921 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL
832 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 922 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
833 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 923 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
834 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 924 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
835 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 925 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
836 u8 port_pf_cnt; 926 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
837 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 927 u8 port_pf_cnt;
838 __le16 dflt_vnic_id; 928 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
839 __le16 max_mtu_configured; 929 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
840 __le32 min_bw; 930 __le16 dflt_vnic_id;
841 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 931 __le16 max_mtu_configured;
842 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 932 __le32 min_bw;
843 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 933 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL
844 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 934 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0
845 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 935 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL
846 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 936 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28)
847 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 937 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28)
848 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 938 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
849 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 939 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
850 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 940 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29
851 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 941 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
852 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 942 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
943 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
944 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
853 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 945 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
854 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 946 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
855 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 947 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
856 __le32 max_bw; 948 __le32 max_bw;
857 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 949 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL
858 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 950 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0
859 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 951 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL
860 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 952 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28)
861 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 953 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28)
862 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 954 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
863 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 955 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
864 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 956 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29
865 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 957 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
866 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 958 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
867 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 959 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
868 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 960 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
869 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 961 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
870 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 962 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
871 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 963 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
872 u8 evb_mode; 964 u8 evb_mode;
873 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 965 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
874 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 966 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL
875 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 967 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL
876 u8 unused_0; 968 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA
877 __le16 alloc_vfs; 969 u8 cache_linesize;
878 __le32 alloc_mcast_filters; 970 #define FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_64 0x0UL
879 __le32 alloc_hw_ring_grps; 971 #define FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_128 0x1UL
880 __le16 alloc_sp_tx_rings; 972 #define FUNC_QCFG_RESP_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_128
881 u8 unused_1; 973 __le16 alloc_vfs;
882 u8 valid; 974 __le32 alloc_mcast_filters;
883}; 975 __le32 alloc_hw_ring_grps;
884 976 __le16 alloc_sp_tx_rings;
885/* hwrm_func_vlan_cfg */ 977 __le16 alloc_stat_ctx;
886/* Input (48 bytes) */ 978 u8 unused_2[7];
979 u8 valid;
980};
981
982/* hwrm_func_vlan_cfg_input (size:384b/48B) */
887struct hwrm_func_vlan_cfg_input { 983struct hwrm_func_vlan_cfg_input {
888 __le16 req_type; 984 __le16 req_type;
889 __le16 cmpl_ring; 985 __le16 cmpl_ring;
890 __le16 seq_id; 986 __le16 seq_id;
891 __le16 target_id; 987 __le16 target_id;
892 __le64 resp_addr; 988 __le64 resp_addr;
893 __le16 fid; 989 __le16 fid;
894 u8 unused_0; 990 u8 unused_0[2];
895 u8 unused_1; 991 __le32 enables;
896 __le32 enables; 992 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID 0x1UL
897 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID 0x1UL 993 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID 0x2UL
898 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID 0x2UL 994 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP 0x4UL
899 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP 0x4UL 995 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP 0x8UL
900 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP 0x8UL 996 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID 0x10UL
901 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID 0x10UL 997 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID 0x20UL
902 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID 0x20UL 998 __le16 stag_vid;
903 __le16 stag_vid; 999 u8 stag_pcp;
904 u8 stag_pcp; 1000 u8 unused_1;
905 u8 unused_2; 1001 __be16 stag_tpid;
906 __be16 stag_tpid; 1002 __le16 ctag_vid;
907 __le16 ctag_vid; 1003 u8 ctag_pcp;
908 u8 ctag_pcp; 1004 u8 unused_2;
909 u8 unused_3; 1005 __be16 ctag_tpid;
910 __be16 ctag_tpid; 1006 __le32 rsvd1;
911 __le32 rsvd1; 1007 __le32 rsvd2;
912 __le32 rsvd2; 1008 u8 unused_3[4];
913 __le32 unused_4; 1009};
914}; 1010
915 1011/* hwrm_func_vlan_cfg_output (size:128b/16B) */
916/* Output (16 bytes) */
917struct hwrm_func_vlan_cfg_output { 1012struct hwrm_func_vlan_cfg_output {
918 __le16 error_code; 1013 __le16 error_code;
919 __le16 req_type; 1014 __le16 req_type;
920 __le16 seq_id; 1015 __le16 seq_id;
921 __le16 resp_len; 1016 __le16 resp_len;
922 __le32 unused_0; 1017 u8 unused_0[7];
923 u8 unused_1; 1018 u8 valid;
924 u8 unused_2; 1019};
925 u8 unused_3; 1020
926 u8 valid; 1021/* hwrm_func_cfg_input (size:704b/88B) */
927};
928
929/* hwrm_func_cfg */
930/* Input (88 bytes) */
931struct hwrm_func_cfg_input { 1022struct hwrm_func_cfg_input {
932 __le16 req_type; 1023 __le16 req_type;
933 __le16 cmpl_ring; 1024 __le16 cmpl_ring;
934 __le16 seq_id; 1025 __le16 seq_id;
935 __le16 target_id; 1026 __le16 target_id;
936 __le64 resp_addr; 1027 __le64 resp_addr;
937 __le16 fid; 1028 __le16 fid;
938 u8 unused_0; 1029 u8 unused_0[2];
939 u8 unused_1; 1030 __le32 flags;
940 __le32 flags; 1031 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL
941 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1032 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL
942 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1033 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL
943 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1034 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2
944 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1035 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL
945 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1036 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL
946 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1037 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL
947 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1038 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL
948 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1039 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL
949 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1040 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL
950 __le32 enables; 1041 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL
951 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1042 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL
952 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1043 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL
953 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1044 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
954 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1045 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
955 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1046 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
956 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1047 __le32 enables;
957 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1048 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
958 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1049 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
959 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1050 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
960 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1051 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
961 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1052 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
962 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1053 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
963 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1054 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
964 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1055 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
965 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1056 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
966 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1057 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
967 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1058 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
968 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1059 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
969 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1060 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
970 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1061 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
971 __le16 mtu; 1062 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
972 __le16 mru; 1063 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
973 __le16 num_rsscos_ctxs; 1064 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
974 __le16 num_cmpl_rings; 1065 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
975 __le16 num_tx_rings; 1066 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
976 __le16 num_rx_rings; 1067 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
977 __le16 num_l2_ctxs; 1068 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
978 __le16 num_vnics; 1069 __le16 mtu;
979 __le16 num_stat_ctxs; 1070 __le16 mru;
980 __le16 num_hw_ring_grps; 1071 __le16 num_rsscos_ctxs;
981 u8 dflt_mac_addr[6]; 1072 __le16 num_cmpl_rings;
982 __le16 dflt_vlan; 1073 __le16 num_tx_rings;
983 __be32 dflt_ip_addr[4]; 1074 __le16 num_rx_rings;
984 __le32 min_bw; 1075 __le16 num_l2_ctxs;
985 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1076 __le16 num_vnics;
986 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1077 __le16 num_stat_ctxs;
987 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1078 __le16 num_hw_ring_grps;
988 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1079 u8 dflt_mac_addr[6];
989 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1080 __le16 dflt_vlan;
990 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1081 __be32 dflt_ip_addr[4];
991 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1082 __le32 min_bw;
992 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1083 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL
993 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1084 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0
994 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1085 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL
995 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1086 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28)
996 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1087 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28)
997 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1088 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
998 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1089 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
999 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1090 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29
1000 __le32 max_bw; 1091 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1001 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1092 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1002 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1093 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1003 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1094 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1004 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1095 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1005 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1096 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1006 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1097 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
1007 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1098 __le32 max_bw;
1008 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1099 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1009 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1100 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0
1010 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1101 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL
1011 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1102 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
1012 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1103 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
1013 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1104 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
1014 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1105 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1015 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1106 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
1016 __le16 async_event_cr; 1107 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1017 u8 vlan_antispoof_mode; 1108 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1018 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1109 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1019 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1110 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1020 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1111 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1112 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1113 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
1114 __le16 async_event_cr;
1115 u8 vlan_antispoof_mode;
1116 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL
1117 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL
1118 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL
1021 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1119 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
1022 u8 allowed_vlan_pris; 1120 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
1023 u8 evb_mode; 1121 u8 allowed_vlan_pris;
1024 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1122 u8 evb_mode;
1025 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1123 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
1026 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1124 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL
1027 u8 unused_2; 1125 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL
1028 __le16 num_mcast_filters; 1126 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA
1127 u8 cache_linesize;
1128 #define FUNC_CFG_REQ_CACHE_LINESIZE_CACHE_LINESIZE_64 0x0UL
1129 #define FUNC_CFG_REQ_CACHE_LINESIZE_CACHE_LINESIZE_128 0x1UL
1130 #define FUNC_CFG_REQ_CACHE_LINESIZE_LAST FUNC_CFG_REQ_CACHE_LINESIZE_CACHE_LINESIZE_128
1131 __le16 num_mcast_filters;
1132};
1133
1134/* hwrm_func_cfg_output (size:128b/16B) */
1135struct hwrm_func_cfg_output {
1136 __le16 error_code;
1137 __le16 req_type;
1138 __le16 seq_id;
1139 __le16 resp_len;
1140 u8 unused_0[7];
1141 u8 valid;
1029}; 1142};
1030 1143
1031/* Output (16 bytes) */ 1144/* hwrm_func_qstats_input (size:192b/24B) */
1032struct hwrm_func_cfg_output {
1033 __le16 error_code;
1034 __le16 req_type;
1035 __le16 seq_id;
1036 __le16 resp_len;
1037 __le32 unused_0;
1038 u8 unused_1;
1039 u8 unused_2;
1040 u8 unused_3;
1041 u8 valid;
1042};
1043
1044/* hwrm_func_qstats */
1045/* Input (24 bytes) */
1046struct hwrm_func_qstats_input { 1145struct hwrm_func_qstats_input {
1047 __le16 req_type; 1146 __le16 req_type;
1048 __le16 cmpl_ring; 1147 __le16 cmpl_ring;
1049 __le16 seq_id; 1148 __le16 seq_id;
1050 __le16 target_id; 1149 __le16 target_id;
1051 __le64 resp_addr; 1150 __le64 resp_addr;
1052 __le16 fid; 1151 __le16 fid;
1053 __le16 unused_0[3]; 1152 u8 unused_0[6];
1054}; 1153};
1055 1154
1056/* Output (176 bytes) */ 1155/* hwrm_func_qstats_output (size:1408b/176B) */
1057struct hwrm_func_qstats_output { 1156struct hwrm_func_qstats_output {
1058 __le16 error_code; 1157 __le16 error_code;
1059 __le16 req_type; 1158 __le16 req_type;
1060 __le16 seq_id; 1159 __le16 seq_id;
1061 __le16 resp_len; 1160 __le16 resp_len;
1062 __le64 tx_ucast_pkts; 1161 __le64 tx_ucast_pkts;
1063 __le64 tx_mcast_pkts; 1162 __le64 tx_mcast_pkts;
1064 __le64 tx_bcast_pkts; 1163 __le64 tx_bcast_pkts;
1065 __le64 tx_discard_pkts; 1164 __le64 tx_discard_pkts;
1066 __le64 tx_drop_pkts; 1165 __le64 tx_drop_pkts;
1067 __le64 tx_ucast_bytes; 1166 __le64 tx_ucast_bytes;
1068 __le64 tx_mcast_bytes; 1167 __le64 tx_mcast_bytes;
1069 __le64 tx_bcast_bytes; 1168 __le64 tx_bcast_bytes;
1070 __le64 rx_ucast_pkts; 1169 __le64 rx_ucast_pkts;
1071 __le64 rx_mcast_pkts; 1170 __le64 rx_mcast_pkts;
1072 __le64 rx_bcast_pkts; 1171 __le64 rx_bcast_pkts;
1073 __le64 rx_discard_pkts; 1172 __le64 rx_discard_pkts;
1074 __le64 rx_drop_pkts; 1173 __le64 rx_drop_pkts;
1075 __le64 rx_ucast_bytes; 1174 __le64 rx_ucast_bytes;
1076 __le64 rx_mcast_bytes; 1175 __le64 rx_mcast_bytes;
1077 __le64 rx_bcast_bytes; 1176 __le64 rx_bcast_bytes;
1078 __le64 rx_agg_pkts; 1177 __le64 rx_agg_pkts;
1079 __le64 rx_agg_bytes; 1178 __le64 rx_agg_bytes;
1080 __le64 rx_agg_events; 1179 __le64 rx_agg_events;
1081 __le64 rx_agg_aborts; 1180 __le64 rx_agg_aborts;
1082 __le32 unused_0; 1181 u8 unused_0[7];
1083 u8 unused_1; 1182 u8 valid;
1084 u8 unused_2; 1183};
1085 u8 unused_3; 1184
1086 u8 valid; 1185/* hwrm_func_clr_stats_input (size:192b/24B) */
1087};
1088
1089/* hwrm_func_clr_stats */
1090/* Input (24 bytes) */
1091struct hwrm_func_clr_stats_input { 1186struct hwrm_func_clr_stats_input {
1092 __le16 req_type; 1187 __le16 req_type;
1093 __le16 cmpl_ring; 1188 __le16 cmpl_ring;
1094 __le16 seq_id; 1189 __le16 seq_id;
1095 __le16 target_id; 1190 __le16 target_id;
1096 __le64 resp_addr; 1191 __le64 resp_addr;
1097 __le16 fid; 1192 __le16 fid;
1098 __le16 unused_0[3]; 1193 u8 unused_0[6];
1099}; 1194};
1100 1195
1101/* Output (16 bytes) */ 1196/* hwrm_func_clr_stats_output (size:128b/16B) */
1102struct hwrm_func_clr_stats_output { 1197struct hwrm_func_clr_stats_output {
1103 __le16 error_code; 1198 __le16 error_code;
1104 __le16 req_type; 1199 __le16 req_type;
1105 __le16 seq_id; 1200 __le16 seq_id;
1106 __le16 resp_len; 1201 __le16 resp_len;
1107 __le32 unused_0; 1202 u8 unused_0[7];
1108 u8 unused_1; 1203 u8 valid;
1109 u8 unused_2; 1204};
1110 u8 unused_3; 1205
1111 u8 valid; 1206/* hwrm_func_vf_resc_free_input (size:192b/24B) */
1112};
1113
1114/* hwrm_func_vf_resc_free */
1115/* Input (24 bytes) */
1116struct hwrm_func_vf_resc_free_input { 1207struct hwrm_func_vf_resc_free_input {
1117 __le16 req_type; 1208 __le16 req_type;
1118 __le16 cmpl_ring; 1209 __le16 cmpl_ring;
1119 __le16 seq_id; 1210 __le16 seq_id;
1120 __le16 target_id; 1211 __le16 target_id;
1121 __le64 resp_addr; 1212 __le64 resp_addr;
1122 __le16 vf_id; 1213 __le16 vf_id;
1123 __le16 unused_0[3]; 1214 u8 unused_0[6];
1124}; 1215};
1125 1216
1126/* Output (16 bytes) */ 1217/* hwrm_func_vf_resc_free_output (size:128b/16B) */
1127struct hwrm_func_vf_resc_free_output { 1218struct hwrm_func_vf_resc_free_output {
1128 __le16 error_code; 1219 __le16 error_code;
1129 __le16 req_type; 1220 __le16 req_type;
1130 __le16 seq_id; 1221 __le16 seq_id;
1131 __le16 resp_len; 1222 __le16 resp_len;
1132 __le32 unused_0; 1223 u8 unused_0[7];
1133 u8 unused_1; 1224 u8 valid;
1134 u8 unused_2; 1225};
1135 u8 unused_3; 1226
1136 u8 valid; 1227/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
1137};
1138
1139/* hwrm_func_vf_vnic_ids_query */
1140/* Input (32 bytes) */
1141struct hwrm_func_vf_vnic_ids_query_input { 1228struct hwrm_func_vf_vnic_ids_query_input {
1142 __le16 req_type; 1229 __le16 req_type;
1143 __le16 cmpl_ring; 1230 __le16 cmpl_ring;
1144 __le16 seq_id; 1231 __le16 seq_id;
1145 __le16 target_id; 1232 __le16 target_id;
1146 __le64 resp_addr; 1233 __le64 resp_addr;
1147 __le16 vf_id; 1234 __le16 vf_id;
1148 u8 unused_0; 1235 u8 unused_0[2];
1149 u8 unused_1; 1236 __le32 max_vnic_id_cnt;
1150 __le32 max_vnic_id_cnt; 1237 __le64 vnic_id_tbl_addr;
1151 __le64 vnic_id_tbl_addr; 1238};
1152}; 1239
1153 1240/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
1154/* Output (16 bytes) */
1155struct hwrm_func_vf_vnic_ids_query_output { 1241struct hwrm_func_vf_vnic_ids_query_output {
1156 __le16 error_code; 1242 __le16 error_code;
1157 __le16 req_type; 1243 __le16 req_type;
1158 __le16 seq_id; 1244 __le16 seq_id;
1159 __le16 resp_len; 1245 __le16 resp_len;
1160 __le32 vnic_id_cnt; 1246 __le32 vnic_id_cnt;
1161 u8 unused_0; 1247 u8 unused_0[3];
1162 u8 unused_1; 1248 u8 valid;
1163 u8 unused_2; 1249};
1164 u8 valid; 1250
1165}; 1251/* hwrm_func_drv_rgtr_input (size:832b/104B) */
1166
1167/* hwrm_func_drv_rgtr */
1168/* Input (80 bytes) */
1169struct hwrm_func_drv_rgtr_input { 1252struct hwrm_func_drv_rgtr_input {
1170 __le16 req_type; 1253 __le16 req_type;
1171 __le16 cmpl_ring; 1254 __le16 cmpl_ring;
1172 __le16 seq_id; 1255 __le16 seq_id;
1173 __le16 target_id; 1256 __le16 target_id;
1174 __le64 resp_addr; 1257 __le64 resp_addr;
1175 __le32 flags; 1258 __le32 flags;
1176 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1259 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1177 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1260 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1178 __le32 enables; 1261 __le32 enables;
1179 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1262 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1180 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1263 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
1181 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1264 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
1182 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1265 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
1183 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1266 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
1184 __le16 os_type; 1267 __le16 os_type;
1185 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1268 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL
1186 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1269 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
1187 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1270 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL
1188 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1271 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL
1189 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1272 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL
1190 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1273 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL
1191 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1274 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL
1192 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1275 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL
1193 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1276 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL
1194 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1277 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
1195 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1278 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL
1196 u8 ver_maj; 1279 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
1197 u8 ver_min; 1280 u8 ver_maj;
1198 u8 ver_upd; 1281 u8 ver_min;
1199 u8 unused_0; 1282 u8 ver_upd;
1200 __le16 unused_1; 1283 u8 unused_0[3];
1201 __le32 timestamp; 1284 __le32 timestamp;
1202 __le32 unused_2; 1285 u8 unused_1[4];
1203 __le32 vf_req_fwd[8]; 1286 __le32 vf_req_fwd[8];
1204 __le32 async_event_fwd[8]; 1287 __le32 async_event_fwd[8];
1205}; 1288};
1206 1289
1207/* Output (16 bytes) */ 1290/* hwrm_func_drv_rgtr_output (size:128b/16B) */
1208struct hwrm_func_drv_rgtr_output { 1291struct hwrm_func_drv_rgtr_output {
1209 __le16 error_code; 1292 __le16 error_code;
1210 __le16 req_type; 1293 __le16 req_type;
1211 __le16 seq_id; 1294 __le16 seq_id;
1212 __le16 resp_len; 1295 __le16 resp_len;
1213 __le32 unused_0; 1296 u8 unused_0[7];
1214 u8 unused_1; 1297 u8 valid;
1215 u8 unused_2; 1298};
1216 u8 unused_3; 1299
1217 u8 valid; 1300/* hwrm_func_drv_unrgtr_input (size:192b/24B) */
1218};
1219
1220/* hwrm_func_drv_unrgtr */
1221/* Input (24 bytes) */
1222struct hwrm_func_drv_unrgtr_input { 1301struct hwrm_func_drv_unrgtr_input {
1223 __le16 req_type; 1302 __le16 req_type;
1224 __le16 cmpl_ring; 1303 __le16 cmpl_ring;
1225 __le16 seq_id; 1304 __le16 seq_id;
1226 __le16 target_id; 1305 __le16 target_id;
1227 __le64 resp_addr; 1306 __le64 resp_addr;
1228 __le32 flags; 1307 __le32 flags;
1229 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1308 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
1230 __le32 unused_0; 1309 u8 unused_0[4];
1231}; 1310};
1232 1311
1233/* Output (16 bytes) */ 1312/* hwrm_func_drv_unrgtr_output (size:128b/16B) */
1234struct hwrm_func_drv_unrgtr_output { 1313struct hwrm_func_drv_unrgtr_output {
1235 __le16 error_code; 1314 __le16 error_code;
1236 __le16 req_type; 1315 __le16 req_type;
1237 __le16 seq_id; 1316 __le16 seq_id;
1238 __le16 resp_len; 1317 __le16 resp_len;
1239 __le32 unused_0; 1318 u8 unused_0[7];
1240 u8 unused_1; 1319 u8 valid;
1241 u8 unused_2; 1320};
1242 u8 unused_3; 1321
1243 u8 valid; 1322/* hwrm_func_buf_rgtr_input (size:1024b/128B) */
1244};
1245
1246/* hwrm_func_buf_rgtr */
1247/* Input (128 bytes) */
1248struct hwrm_func_buf_rgtr_input { 1323struct hwrm_func_buf_rgtr_input {
1249 __le16 req_type; 1324 __le16 req_type;
1250 __le16 cmpl_ring; 1325 __le16 cmpl_ring;
1251 __le16 seq_id; 1326 __le16 seq_id;
1252 __le16 target_id; 1327 __le16 target_id;
1253 __le64 resp_addr; 1328 __le64 resp_addr;
1254 __le32 enables; 1329 __le32 enables;
1255 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1330 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
1256 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1331 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
1257 __le16 vf_id; 1332 __le16 vf_id;
1258 __le16 req_buf_num_pages; 1333 __le16 req_buf_num_pages;
1259 __le16 req_buf_page_size; 1334 __le16 req_buf_page_size;
1260 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1335 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
1261 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1336 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL
1262 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1337 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL
1263 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1338 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
1264 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1339 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL
1265 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1340 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL
1266 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1341 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL
1267 __le16 req_buf_len; 1342 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
1268 __le16 resp_buf_len; 1343 __le16 req_buf_len;
1269 u8 unused_0; 1344 __le16 resp_buf_len;
1270 u8 unused_1; 1345 u8 unused_0[2];
1271 __le64 req_buf_page_addr0; 1346 __le64 req_buf_page_addr0;
1272 __le64 req_buf_page_addr1; 1347 __le64 req_buf_page_addr1;
1273 __le64 req_buf_page_addr2; 1348 __le64 req_buf_page_addr2;
1274 __le64 req_buf_page_addr3; 1349 __le64 req_buf_page_addr3;
1275 __le64 req_buf_page_addr4; 1350 __le64 req_buf_page_addr4;
1276 __le64 req_buf_page_addr5; 1351 __le64 req_buf_page_addr5;
1277 __le64 req_buf_page_addr6; 1352 __le64 req_buf_page_addr6;
1278 __le64 req_buf_page_addr7; 1353 __le64 req_buf_page_addr7;
1279 __le64 req_buf_page_addr8; 1354 __le64 req_buf_page_addr8;
1280 __le64 req_buf_page_addr9; 1355 __le64 req_buf_page_addr9;
1281 __le64 error_buf_addr; 1356 __le64 error_buf_addr;
1282 __le64 resp_buf_addr; 1357 __le64 resp_buf_addr;
1283}; 1358};
1284 1359
1285/* Output (16 bytes) */ 1360/* hwrm_func_buf_rgtr_output (size:128b/16B) */
1286struct hwrm_func_buf_rgtr_output { 1361struct hwrm_func_buf_rgtr_output {
1287 __le16 error_code; 1362 __le16 error_code;
1288 __le16 req_type; 1363 __le16 req_type;
1289 __le16 seq_id; 1364 __le16 seq_id;
1290 __le16 resp_len; 1365 __le16 resp_len;
1291 __le32 unused_0; 1366 u8 unused_0[7];
1292 u8 unused_1; 1367 u8 valid;
1293 u8 unused_2; 1368};
1294 u8 unused_3; 1369
1295 u8 valid; 1370/* hwrm_func_drv_qver_input (size:192b/24B) */
1296};
1297
1298/* hwrm_func_drv_qver */
1299/* Input (24 bytes) */
1300struct hwrm_func_drv_qver_input { 1371struct hwrm_func_drv_qver_input {
1301 __le16 req_type; 1372 __le16 req_type;
1302 __le16 cmpl_ring; 1373 __le16 cmpl_ring;
1303 __le16 seq_id; 1374 __le16 seq_id;
1304 __le16 target_id; 1375 __le16 target_id;
1305 __le64 resp_addr; 1376 __le64 resp_addr;
1306 __le32 reserved; 1377 __le32 reserved;
1307 __le16 fid; 1378 __le16 fid;
1308 __le16 unused_0; 1379 u8 unused_0[2];
1309}; 1380};
1310 1381
1311/* Output (16 bytes) */ 1382/* hwrm_func_drv_qver_output (size:128b/16B) */
1312struct hwrm_func_drv_qver_output { 1383struct hwrm_func_drv_qver_output {
1313 __le16 error_code; 1384 __le16 error_code;
1314 __le16 req_type; 1385 __le16 req_type;
1315 __le16 seq_id; 1386 __le16 seq_id;
1316 __le16 resp_len; 1387 __le16 resp_len;
1317 __le16 os_type; 1388 __le16 os_type;
1318 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1389 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL
1319 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1390 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL
1320 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1391 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL
1321 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1392 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL
1322 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1393 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL
1323 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1394 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL
1324 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1395 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL
1325 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1396 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL
1326 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1397 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL
1327 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1398 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
1328 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1399 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL
1329 u8 ver_maj; 1400 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
1330 u8 ver_min; 1401 u8 ver_maj;
1331 u8 ver_upd; 1402 u8 ver_min;
1332 u8 unused_0; 1403 u8 ver_upd;
1333 u8 unused_1; 1404 u8 unused_0[2];
1334 u8 valid; 1405 u8 valid;
1335}; 1406};
1336 1407
1337/* hwrm_port_phy_cfg */ 1408/* hwrm_func_resource_qcaps_input (size:192b/24B) */
1338/* Input (56 bytes) */ 1409struct hwrm_func_resource_qcaps_input {
1410 __le16 req_type;
1411 __le16 cmpl_ring;
1412 __le16 seq_id;
1413 __le16 target_id;
1414 __le64 resp_addr;
1415 __le16 fid;
1416 u8 unused_0[6];
1417};
1418
1419/* hwrm_func_resource_qcaps_output (size:384b/48B) */
1420struct hwrm_func_resource_qcaps_output {
1421 __le16 error_code;
1422 __le16 req_type;
1423 __le16 seq_id;
1424 __le16 resp_len;
1425 __le16 max_vfs;
1426 __le16 max_msix;
1427 __le16 vf_reservation_strategy;
1428 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL
1429 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL
1430 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL
1431 __le16 min_rsscos_ctx;
1432 __le16 max_rsscos_ctx;
1433 __le16 min_cmpl_rings;
1434 __le16 max_cmpl_rings;
1435 __le16 min_tx_rings;
1436 __le16 max_tx_rings;
1437 __le16 min_rx_rings;
1438 __le16 max_rx_rings;
1439 __le16 min_l2_ctxs;
1440 __le16 max_l2_ctxs;
1441 __le16 min_vnics;
1442 __le16 max_vnics;
1443 __le16 min_stat_ctx;
1444 __le16 max_stat_ctx;
1445 __le16 min_hw_ring_grps;
1446 __le16 max_hw_ring_grps;
1447 u8 unused_0;
1448 u8 valid;
1449};
1450
1451/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
1452struct hwrm_func_vf_resource_cfg_input {
1453 __le16 req_type;
1454 __le16 cmpl_ring;
1455 __le16 seq_id;
1456 __le16 target_id;
1457 __le64 resp_addr;
1458 __le16 vf_id;
1459 __le16 max_msix;
1460 __le16 min_rsscos_ctx;
1461 __le16 max_rsscos_ctx;
1462 __le16 min_cmpl_rings;
1463 __le16 max_cmpl_rings;
1464 __le16 min_tx_rings;
1465 __le16 max_tx_rings;
1466 __le16 min_rx_rings;
1467 __le16 max_rx_rings;
1468 __le16 min_l2_ctxs;
1469 __le16 max_l2_ctxs;
1470 __le16 min_vnics;
1471 __le16 max_vnics;
1472 __le16 min_stat_ctx;
1473 __le16 max_stat_ctx;
1474 __le16 min_hw_ring_grps;
1475 __le16 max_hw_ring_grps;
1476 u8 unused_0[4];
1477};
1478
1479/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
1480struct hwrm_func_vf_resource_cfg_output {
1481 __le16 error_code;
1482 __le16 req_type;
1483 __le16 seq_id;
1484 __le16 resp_len;
1485 __le16 reserved_rsscos_ctx;
1486 __le16 reserved_cmpl_rings;
1487 __le16 reserved_tx_rings;
1488 __le16 reserved_rx_rings;
1489 __le16 reserved_l2_ctxs;
1490 __le16 reserved_vnics;
1491 __le16 reserved_stat_ctx;
1492 __le16 reserved_hw_ring_grps;
1493 u8 unused_0[7];
1494 u8 valid;
1495};
1496
1497/* hwrm_port_phy_cfg_input (size:448b/56B) */
1339struct hwrm_port_phy_cfg_input { 1498struct hwrm_port_phy_cfg_input {
1340 __le16 req_type; 1499 __le16 req_type;
1341 __le16 cmpl_ring; 1500 __le16 cmpl_ring;
1342 __le16 seq_id; 1501 __le16 seq_id;
1343 __le16 target_id; 1502 __le16 target_id;
1344 __le64 resp_addr; 1503 __le64 resp_addr;
1345 __le32 flags; 1504 __le32 flags;
1346 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1505 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
1347 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 1506 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
1348 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1507 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
1349 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1508 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
1350 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1509 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
1351 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1510 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
1352 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1511 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
1353 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1512 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
1354 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1513 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
1355 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1514 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
1356 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1515 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
1357 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1516 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
1358 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1517 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
1359 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 1518 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
1360 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 1519 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
1361 __le32 enables; 1520 __le32 enables;
1362 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1521 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
1363 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1522 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
1364 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1523 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
1365 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1524 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
1366 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1525 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
1367 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1526 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
1368 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1527 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
1369 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1528 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
1370 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1529 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
1371 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1530 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
1372 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1531 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
1373 __le16 port_id; 1532 __le16 port_id;
1374 __le16 force_link_speed; 1533 __le16 force_link_speed;
1375 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1534 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
1376 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1535 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
1377 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1536 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL
1378 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1537 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
1379 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1538 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
1380 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1539 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL
1381 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1540 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
1382 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1541 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
1383 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1542 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
1384 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1543 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
1385 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1544 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL
1386 u8 auto_mode; 1545 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
1387 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1546 u8 auto_mode;
1388 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1547 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL
1389 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1548 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL
1390 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1549 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL
1391 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1550 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
1392 u8 auto_duplex; 1551 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
1393 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1552 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
1394 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1553 u8 auto_duplex;
1395 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1554 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
1396 u8 auto_pause; 1555 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
1397 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1556 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
1398 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1557 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
1399 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1558 u8 auto_pause;
1400 u8 unused_0; 1559 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
1401 __le16 auto_link_speed; 1560 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
1402 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1561 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
1403 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1562 u8 unused_0;
1404 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1563 __le16 auto_link_speed;
1405 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1564 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
1406 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1565 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL
1407 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1566 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL
1408 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1567 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
1409 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1568 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL
1410 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1569 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL
1411 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1570 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL
1412 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1571 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL
1413 __le16 auto_link_speed_mask; 1572 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL
1414 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1573 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
1415 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1574 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL
1416 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1575 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
1417 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1576 __le16 auto_link_speed_mask;
1418 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1577 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
1419 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1578 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
1420 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1579 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
1421 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1580 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
1422 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1581 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
1423 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1582 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
1424 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1583 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
1425 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1584 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
1426 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1585 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
1427 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1586 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
1428 u8 wirespeed; 1587 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
1429 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1588 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
1430 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1589 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
1431 u8 lpbk; 1590 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
1432 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1591 u8 wirespeed;
1433 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1592 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
1434 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1593 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
1435 u8 force_pause; 1594 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
1436 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1595 u8 lpbk;
1437 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1596 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL
1438 u8 unused_1; 1597 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL
1439 __le32 preemphasis; 1598 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL
1440 __le16 eee_link_speed_mask; 1599 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_REMOTE
1441 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1600 u8 force_pause;
1442 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 1601 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
1443 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1602 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
1444 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 1603 u8 unused_1;
1445 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1604 __le32 preemphasis;
1446 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1605 __le16 eee_link_speed_mask;
1447 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 1606 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
1448 u8 unused_2; 1607 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
1449 u8 unused_3; 1608 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
1450 __le32 tx_lpi_timer; 1609 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
1451 __le32 unused_4; 1610 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
1452 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 1611 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
1453 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1612 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
1454}; 1613 u8 unused_2[2];
1455 1614 __le32 tx_lpi_timer;
1456/* Output (16 bytes) */ 1615 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
1616 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
1617 __le32 unused_3;
1618};
1619
1620/* hwrm_port_phy_cfg_output (size:128b/16B) */
1457struct hwrm_port_phy_cfg_output { 1621struct hwrm_port_phy_cfg_output {
1458 __le16 error_code; 1622 __le16 error_code;
1459 __le16 req_type; 1623 __le16 req_type;
1460 __le16 seq_id; 1624 __le16 seq_id;
1461 __le16 resp_len; 1625 __le16 resp_len;
1462 __le32 unused_0; 1626 u8 unused_0[7];
1463 u8 unused_1; 1627 u8 valid;
1464 u8 unused_2; 1628};
1465 u8 unused_3; 1629
1466 u8 valid; 1630/* hwrm_port_phy_qcfg_input (size:192b/24B) */
1467};
1468
1469/* hwrm_port_phy_qcfg */
1470/* Input (24 bytes) */
1471struct hwrm_port_phy_qcfg_input { 1631struct hwrm_port_phy_qcfg_input {
1472 __le16 req_type; 1632 __le16 req_type;
1473 __le16 cmpl_ring; 1633 __le16 cmpl_ring;
1474 __le16 seq_id; 1634 __le16 seq_id;
1475 __le16 target_id; 1635 __le16 target_id;
1476 __le64 resp_addr; 1636 __le64 resp_addr;
1477 __le16 port_id; 1637 __le16 port_id;
1478 __le16 unused_0[3]; 1638 u8 unused_0[6];
1479}; 1639};
1480 1640
1481/* Output (96 bytes) */ 1641/* hwrm_port_phy_qcfg_output (size:768b/96B) */
1482struct hwrm_port_phy_qcfg_output { 1642struct hwrm_port_phy_qcfg_output {
1483 __le16 error_code; 1643 __le16 error_code;
1484 __le16 req_type; 1644 __le16 req_type;
1485 __le16 seq_id; 1645 __le16 seq_id;
1486 __le16 resp_len; 1646 __le16 resp_len;
1487 u8 link; 1647 u8 link;
1488 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 1648 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
1489 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 1649 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
1490 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 1650 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
1491 u8 unused_0; 1651 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
1492 __le16 link_speed; 1652 u8 unused_0;
1493 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 1653 __le16 link_speed;
1494 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 1654 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
1495 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 1655 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
1496 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 1656 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
1497 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 1657 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
1498 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 1658 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
1499 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 1659 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
1500 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 1660 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
1501 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 1661 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
1502 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 1662 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
1503 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 1663 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
1504 u8 duplex_cfg; 1664 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
1505 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 1665 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
1506 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 1666 u8 duplex_cfg;
1507 u8 pause; 1667 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
1508 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1668 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
1509 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1669 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
1510 __le16 support_speeds; 1670 u8 pause;
1511 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1671 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
1512 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1672 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
1513 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1673 __le16 support_speeds;
1514 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1674 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
1515 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1675 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
1516 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1676 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
1517 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1677 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
1518 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1678 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
1519 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1679 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
1520 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1680 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
1521 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1681 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
1522 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 1682 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
1523 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 1683 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
1524 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1684 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
1525 __le16 force_link_speed; 1685 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
1526 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 1686 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
1527 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 1687 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
1528 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 1688 __le16 force_link_speed;
1529 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 1689 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
1530 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 1690 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL
1531 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 1691 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL
1532 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 1692 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
1533 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 1693 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL
1534 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 1694 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL
1535 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 1695 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL
1536 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 1696 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL
1537 u8 auto_mode; 1697 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL
1538 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 1698 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
1539 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 1699 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL
1540 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 1700 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
1541 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 1701 u8 auto_mode;
1542 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 1702 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL
1543 u8 auto_pause; 1703 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL
1544 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1704 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL
1545 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1705 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
1546 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1706 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL
1547 __le16 auto_link_speed; 1707 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1548 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 1708 u8 auto_pause;
1549 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 1709 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
1550 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 1710 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
1551 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 1711 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
1552 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 1712 __le16 auto_link_speed;
1553 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 1713 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
1554 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 1714 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL
1555 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 1715 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL
1556 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 1716 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
1557 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 1717 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL
1558 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 1718 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL
1559 __le16 auto_link_speed_mask; 1719 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL
1560 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1720 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL
1561 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1721 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL
1562 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1722 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
1563 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1723 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL
1564 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1724 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
1565 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1725 __le16 auto_link_speed_mask;
1566 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1726 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
1567 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1727 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
1568 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1728 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
1569 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1729 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
1570 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1730 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
1571 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1731 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
1572 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1732 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
1573 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1733 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
1574 u8 wirespeed; 1734 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
1575 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 1735 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
1576 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 1736 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
1577 u8 lpbk; 1737 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
1578 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 1738 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
1579 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 1739 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
1580 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 1740 u8 wirespeed;
1581 u8 force_pause; 1741 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
1582 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1742 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
1583 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1743 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
1584 u8 module_status; 1744 u8 lpbk;
1585 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 1745 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL
1586 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 1746 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL
1587 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 1747 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL
1588 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 1748 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_REMOTE
1589 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 1749 u8 force_pause;
1590 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 1750 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
1591 __le32 preemphasis; 1751 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
1592 u8 phy_maj; 1752 u8 module_status;
1593 u8 phy_min; 1753 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL
1594 u8 phy_bld; 1754 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL
1595 u8 phy_type; 1755 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL
1596 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 1756 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL
1597 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 1757 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL
1598 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 1758 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
1599 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 1759 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
1600 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 1760 __le32 preemphasis;
1601 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 1761 u8 phy_maj;
1602 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 1762 u8 phy_min;
1603 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 1763 u8 phy_bld;
1604 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 1764 u8 phy_type;
1605 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 1765 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL
1606 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 1766 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL
1607 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 1767 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL
1608 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 1768 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL
1609 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 1769 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL
1610 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 1770 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL
1611 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 1771 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL
1612 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 1772 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL
1613 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 1773 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL
1614 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 1774 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL
1615 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 1775 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL
1616 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 1776 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL
1617 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 1777 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL
1618 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 1778 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL
1619 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 1779 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL
1620 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 1780 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL
1621 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 1781 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL
1622 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 1782 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL
1623 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 1783 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL
1624 u8 media_type; 1784 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL
1625 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 1785 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL
1626 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 1786 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL
1627 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 1787 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL
1628 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 1788 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL
1629 u8 xcvr_pkg_type; 1789 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
1630 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 1790 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
1631 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 1791 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
1632 u8 eee_config_phy_addr; 1792 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
1633 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1793 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX
1634 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1794 u8 media_type;
1635 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 1795 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
1636 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 1796 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
1637 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 1797 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
1638 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 1798 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
1639 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 1799 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
1640 u8 parallel_detect; 1800 u8 xcvr_pkg_type;
1641 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 1801 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
1642 #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL 1802 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
1643 #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1 1803 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
1644 __le16 link_partner_adv_speeds; 1804 u8 eee_config_phy_addr;
1645 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1805 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
1646 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1806 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
1647 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1807 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
1648 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1808 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
1649 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1809 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
1650 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1810 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
1651 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1811 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
1652 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1812 u8 parallel_detect;
1653 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1813 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
1654 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1814 __le16 link_partner_adv_speeds;
1655 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1815 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
1656 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 1816 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
1657 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 1817 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
1658 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1818 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
1659 u8 link_partner_adv_auto_mode; 1819 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
1660 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 1820 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
1661 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 1821 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
1662 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 1822 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
1823 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
1824 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
1825 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
1826 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
1827 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
1828 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
1829 u8 link_partner_adv_auto_mode;
1830 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL
1831 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL
1832 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL
1663 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 1833 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
1664 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 1834 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL
1665 u8 link_partner_adv_pause; 1835 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
1666 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1836 u8 link_partner_adv_pause;
1667 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1837 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
1668 __le16 adv_eee_link_speed_mask; 1838 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
1669 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1839 __le16 adv_eee_link_speed_mask;
1670 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1840 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
1671 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1841 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
1672 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1842 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
1673 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1843 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
1674 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1844 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
1675 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1845 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
1676 __le16 link_partner_adv_eee_link_speed_mask; 1846 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
1677 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1847 __le16 link_partner_adv_eee_link_speed_mask;
1678 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1848 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
1679 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1849 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
1680 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1850 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
1681 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1851 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
1682 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1852 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
1683 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1853 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
1684 __le32 xcvr_identifier_type_tx_lpi_timer; 1854 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
1685 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 1855 __le32 xcvr_identifier_type_tx_lpi_timer;
1686 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 1856 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
1687 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 1857 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
1688 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 1858 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
1859 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
1689 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 1860 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
1690 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 1861 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
1691 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 1862 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
1692 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 1863 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
1693 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1864 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
1694 __le16 fec_cfg; 1865 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
1695 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 1866 __le16 fec_cfg;
1696 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 1867 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
1697 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 1868 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
1698 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 1869 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
1699 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 1870 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
1700 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 1871 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
1701 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 1872 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
1702 u8 duplex_state; 1873 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
1703 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 1874 u8 duplex_state;
1704 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 1875 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
1705 u8 unused_1; 1876 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
1706 char phy_vendor_name[16]; 1877 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1707 char phy_vendor_partnumber[16]; 1878 u8 option_flags;
1708 __le32 unused_2; 1879 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
1709 u8 unused_3; 1880 char phy_vendor_name[16];
1710 u8 unused_4; 1881 char phy_vendor_partnumber[16];
1711 u8 unused_5; 1882 u8 unused_2[7];
1712 u8 valid; 1883 u8 valid;
1713}; 1884};
1714 1885
1715/* hwrm_port_mac_cfg */ 1886/* hwrm_port_mac_cfg_input (size:320b/40B) */
1716/* Input (40 bytes) */
1717struct hwrm_port_mac_cfg_input { 1887struct hwrm_port_mac_cfg_input {
1718 __le16 req_type; 1888 __le16 req_type;
1719 __le16 cmpl_ring; 1889 __le16 cmpl_ring;
1720 __le16 seq_id; 1890 __le16 seq_id;
1721 __le16 target_id; 1891 __le16 target_id;
1722 __le64 resp_addr; 1892 __le64 resp_addr;
1723 __le32 flags; 1893 __le32 flags;
1724 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1894 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
1725 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 1895 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL
1726 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1896 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
1727 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1897 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
1728 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 1898 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
1729 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 1899 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
1730 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 1900 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
1731 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1901 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
1732 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 1902 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL
1733 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 1903 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL
1734 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 1904 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL
1735 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 1905 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL
1736 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 1906 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL
1737 __le32 enables; 1907 __le32 enables;
1738 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1908 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
1739 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1909 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
1740 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 1910 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL
1741 #define PORT_MAC_CFG_REQ_ENABLES_RESERVED1 0x8UL 1911 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
1742 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1912 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
1743 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1913 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
1744 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 1914 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
1745 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1915 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
1746 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 1916 __le16 port_id;
1747 __le16 port_id; 1917 u8 ipg;
1748 u8 ipg; 1918 u8 lpbk;
1749 u8 lpbk; 1919 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
1750 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 1920 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL
1751 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 1921 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
1752 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 1922 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE
1753 u8 vlan_pri2cos_map_pri; 1923 u8 vlan_pri2cos_map_pri;
1754 u8 reserved1; 1924 u8 reserved1;
1755 u8 tunnel_pri2cos_map_pri; 1925 u8 tunnel_pri2cos_map_pri;
1756 u8 dscp2pri_map_pri; 1926 u8 dscp2pri_map_pri;
1757 __le16 rx_ts_capture_ptp_msg_type; 1927 __le16 rx_ts_capture_ptp_msg_type;
1758 __le16 tx_ts_capture_ptp_msg_type; 1928 __le16 tx_ts_capture_ptp_msg_type;
1759 u8 cos_field_cfg; 1929 u8 cos_field_cfg;
1760 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 1930 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL
1761 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 1931 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
1762 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 1932 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
1763 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 1933 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
1764 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 1934 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
1765 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 1935 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
1766 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 1936 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
1767 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 1937 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
1768 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 1938 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
1769 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 1939 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
1770 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 1940 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
1771 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 1941 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
1772 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 1942 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
1773 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 1943 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
1774 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 1944 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
1775 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 1945 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
1776 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 1946 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
1777 u8 unused_0[3]; 1947 u8 unused_0[3];
1778}; 1948};
1779 1949
1780/* Output (16 bytes) */ 1950/* hwrm_port_mac_cfg_output (size:128b/16B) */
1781struct hwrm_port_mac_cfg_output { 1951struct hwrm_port_mac_cfg_output {
1782 __le16 error_code; 1952 __le16 error_code;
1783 __le16 req_type; 1953 __le16 req_type;
1784 __le16 seq_id; 1954 __le16 seq_id;
1785 __le16 resp_len; 1955 __le16 resp_len;
1786 __le16 mru; 1956 __le16 mru;
1787 __le16 mtu; 1957 __le16 mtu;
1788 u8 ipg; 1958 u8 ipg;
1789 u8 lpbk; 1959 u8 lpbk;
1790 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 1960 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL
1791 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 1961 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL
1792 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 1962 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
1793 u8 unused_0; 1963 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE
1794 u8 valid; 1964 u8 unused_0;
1795}; 1965 u8 valid;
1796 1966};
1797/* hwrm_port_mac_ptp_qcfg */ 1967
1798/* Input (24 bytes) */ 1968/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
1799struct hwrm_port_mac_ptp_qcfg_input { 1969struct hwrm_port_mac_ptp_qcfg_input {
1800 __le16 req_type; 1970 __le16 req_type;
1801 __le16 cmpl_ring; 1971 __le16 cmpl_ring;
1802 __le16 seq_id; 1972 __le16 seq_id;
1803 __le16 target_id; 1973 __le16 target_id;
1804 __le64 resp_addr; 1974 __le64 resp_addr;
1805 __le16 port_id; 1975 __le16 port_id;
1806 __le16 unused_0[3]; 1976 u8 unused_0[6];
1807}; 1977};
1808 1978
1809/* Output (80 bytes) */ 1979/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
1810struct hwrm_port_mac_ptp_qcfg_output { 1980struct hwrm_port_mac_ptp_qcfg_output {
1811 __le16 error_code; 1981 __le16 error_code;
1812 __le16 req_type; 1982 __le16 req_type;
1813 __le16 seq_id; 1983 __le16 seq_id;
1814 __le16 resp_len; 1984 __le16 resp_len;
1815 u8 flags; 1985 u8 flags;
1816 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 1986 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
1817 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL 1987 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL
1818 u8 unused_0; 1988 u8 unused_0[3];
1819 __le16 unused_1; 1989 __le32 rx_ts_reg_off_lower;
1820 __le32 rx_ts_reg_off_lower; 1990 __le32 rx_ts_reg_off_upper;
1821 __le32 rx_ts_reg_off_upper; 1991 __le32 rx_ts_reg_off_seq_id;
1822 __le32 rx_ts_reg_off_seq_id; 1992 __le32 rx_ts_reg_off_src_id_0;
1823 __le32 rx_ts_reg_off_src_id_0; 1993 __le32 rx_ts_reg_off_src_id_1;
1824 __le32 rx_ts_reg_off_src_id_1; 1994 __le32 rx_ts_reg_off_src_id_2;
1825 __le32 rx_ts_reg_off_src_id_2; 1995 __le32 rx_ts_reg_off_domain_id;
1826 __le32 rx_ts_reg_off_domain_id; 1996 __le32 rx_ts_reg_off_fifo;
1827 __le32 rx_ts_reg_off_fifo; 1997 __le32 rx_ts_reg_off_fifo_adv;
1828 __le32 rx_ts_reg_off_fifo_adv; 1998 __le32 rx_ts_reg_off_granularity;
1829 __le32 rx_ts_reg_off_granularity; 1999 __le32 tx_ts_reg_off_lower;
1830 __le32 tx_ts_reg_off_lower; 2000 __le32 tx_ts_reg_off_upper;
1831 __le32 tx_ts_reg_off_upper; 2001 __le32 tx_ts_reg_off_seq_id;
1832 __le32 tx_ts_reg_off_seq_id; 2002 __le32 tx_ts_reg_off_fifo;
1833 __le32 tx_ts_reg_off_fifo; 2003 __le32 tx_ts_reg_off_granularity;
1834 __le32 tx_ts_reg_off_granularity; 2004 u8 unused_1[7];
1835 __le32 unused_2; 2005 u8 valid;
1836 u8 unused_3; 2006};
1837 u8 unused_4; 2007
1838 u8 unused_5; 2008/* hwrm_port_qstats_input (size:320b/40B) */
1839 u8 valid;
1840};
1841
1842/* hwrm_port_qstats */
1843/* Input (40 bytes) */
1844struct hwrm_port_qstats_input { 2009struct hwrm_port_qstats_input {
1845 __le16 req_type; 2010 __le16 req_type;
1846 __le16 cmpl_ring; 2011 __le16 cmpl_ring;
1847 __le16 seq_id; 2012 __le16 seq_id;
1848 __le16 target_id; 2013 __le16 target_id;
1849 __le64 resp_addr; 2014 __le64 resp_addr;
1850 __le16 port_id; 2015 __le16 port_id;
1851 u8 unused_0; 2016 u8 unused_0[6];
1852 u8 unused_1; 2017 __le64 tx_stat_host_addr;
1853 u8 unused_2[3]; 2018 __le64 rx_stat_host_addr;
1854 u8 unused_3; 2019};
1855 __le64 tx_stat_host_addr; 2020
1856 __le64 rx_stat_host_addr; 2021/* hwrm_port_qstats_output (size:128b/16B) */
1857};
1858
1859/* Output (16 bytes) */
1860struct hwrm_port_qstats_output { 2022struct hwrm_port_qstats_output {
1861 __le16 error_code; 2023 __le16 error_code;
1862 __le16 req_type; 2024 __le16 req_type;
1863 __le16 seq_id; 2025 __le16 seq_id;
1864 __le16 resp_len; 2026 __le16 resp_len;
1865 __le16 tx_stat_size; 2027 __le16 tx_stat_size;
1866 __le16 rx_stat_size; 2028 __le16 rx_stat_size;
1867 u8 unused_0; 2029 u8 unused_0[3];
1868 u8 unused_1; 2030 u8 valid;
1869 u8 unused_2; 2031};
1870 u8 valid; 2032
1871}; 2033/* hwrm_port_lpbk_qstats_input (size:128b/16B) */
1872
1873/* hwrm_port_lpbk_qstats */
1874/* Input (16 bytes) */
1875struct hwrm_port_lpbk_qstats_input { 2034struct hwrm_port_lpbk_qstats_input {
1876 __le16 req_type; 2035 __le16 req_type;
1877 __le16 cmpl_ring; 2036 __le16 cmpl_ring;
1878 __le16 seq_id; 2037 __le16 seq_id;
1879 __le16 target_id; 2038 __le16 target_id;
1880 __le64 resp_addr; 2039 __le64 resp_addr;
1881}; 2040};
1882 2041
1883/* Output (96 bytes) */ 2042/* hwrm_port_lpbk_qstats_output (size:768b/96B) */
1884struct hwrm_port_lpbk_qstats_output { 2043struct hwrm_port_lpbk_qstats_output {
1885 __le16 error_code; 2044 __le16 error_code;
1886 __le16 req_type; 2045 __le16 req_type;
1887 __le16 seq_id; 2046 __le16 seq_id;
1888 __le16 resp_len; 2047 __le16 resp_len;
1889 __le64 lpbk_ucast_frames; 2048 __le64 lpbk_ucast_frames;
1890 __le64 lpbk_mcast_frames; 2049 __le64 lpbk_mcast_frames;
1891 __le64 lpbk_bcast_frames; 2050 __le64 lpbk_bcast_frames;
1892 __le64 lpbk_ucast_bytes; 2051 __le64 lpbk_ucast_bytes;
1893 __le64 lpbk_mcast_bytes; 2052 __le64 lpbk_mcast_bytes;
1894 __le64 lpbk_bcast_bytes; 2053 __le64 lpbk_bcast_bytes;
1895 __le64 tx_stat_discard; 2054 __le64 tx_stat_discard;
1896 __le64 tx_stat_error; 2055 __le64 tx_stat_error;
1897 __le64 rx_stat_discard; 2056 __le64 rx_stat_discard;
1898 __le64 rx_stat_error; 2057 __le64 rx_stat_error;
1899 __le32 unused_0; 2058 u8 unused_0[7];
1900 u8 unused_1; 2059 u8 valid;
1901 u8 unused_2; 2060};
1902 u8 unused_3; 2061
1903 u8 valid; 2062/* hwrm_port_clr_stats_input (size:192b/24B) */
1904};
1905
1906/* hwrm_port_clr_stats */
1907/* Input (24 bytes) */
1908struct hwrm_port_clr_stats_input { 2063struct hwrm_port_clr_stats_input {
1909 __le16 req_type; 2064 __le16 req_type;
1910 __le16 cmpl_ring; 2065 __le16 cmpl_ring;
1911 __le16 seq_id; 2066 __le16 seq_id;
1912 __le16 target_id; 2067 __le16 target_id;
1913 __le64 resp_addr; 2068 __le64 resp_addr;
1914 __le16 port_id; 2069 __le16 port_id;
1915 __le16 unused_0[3]; 2070 u8 unused_0[6];
1916}; 2071};
1917 2072
1918/* Output (16 bytes) */ 2073/* hwrm_port_clr_stats_output (size:128b/16B) */
1919struct hwrm_port_clr_stats_output { 2074struct hwrm_port_clr_stats_output {
1920 __le16 error_code; 2075 __le16 error_code;
1921 __le16 req_type; 2076 __le16 req_type;
1922 __le16 seq_id; 2077 __le16 seq_id;
1923 __le16 resp_len; 2078 __le16 resp_len;
1924 __le32 unused_0; 2079 u8 unused_0[7];
1925 u8 unused_1; 2080 u8 valid;
1926 u8 unused_2; 2081};
1927 u8 unused_3; 2082
1928 u8 valid; 2083/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
1929};
1930
1931/* hwrm_port_lpbk_clr_stats */
1932/* Input (16 bytes) */
1933struct hwrm_port_lpbk_clr_stats_input { 2084struct hwrm_port_lpbk_clr_stats_input {
1934 __le16 req_type; 2085 __le16 req_type;
1935 __le16 cmpl_ring; 2086 __le16 cmpl_ring;
1936 __le16 seq_id; 2087 __le16 seq_id;
1937 __le16 target_id; 2088 __le16 target_id;
1938 __le64 resp_addr; 2089 __le64 resp_addr;
1939}; 2090};
1940 2091
1941/* Output (16 bytes) */ 2092/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
1942struct hwrm_port_lpbk_clr_stats_output { 2093struct hwrm_port_lpbk_clr_stats_output {
1943 __le16 error_code; 2094 __le16 error_code;
1944 __le16 req_type; 2095 __le16 req_type;
1945 __le16 seq_id; 2096 __le16 seq_id;
1946 __le16 resp_len; 2097 __le16 resp_len;
1947 __le32 unused_0; 2098 u8 unused_0[7];
1948 u8 unused_1; 2099 u8 valid;
1949 u8 unused_2; 2100};
1950 u8 unused_3; 2101
1951 u8 valid; 2102/* hwrm_port_phy_qcaps_input (size:192b/24B) */
1952};
1953
1954/* hwrm_port_phy_qcaps */
1955/* Input (24 bytes) */
1956struct hwrm_port_phy_qcaps_input { 2103struct hwrm_port_phy_qcaps_input {
1957 __le16 req_type; 2104 __le16 req_type;
1958 __le16 cmpl_ring; 2105 __le16 cmpl_ring;
1959 __le16 seq_id; 2106 __le16 seq_id;
1960 __le16 target_id; 2107 __le16 target_id;
1961 __le64 resp_addr; 2108 __le64 resp_addr;
1962 __le16 port_id; 2109 __le16 port_id;
1963 __le16 unused_0[3]; 2110 u8 unused_0[6];
1964}; 2111};
1965 2112
1966/* Output (24 bytes) */ 2113/* hwrm_port_phy_qcaps_output (size:192b/24B) */
1967struct hwrm_port_phy_qcaps_output { 2114struct hwrm_port_phy_qcaps_output {
1968 __le16 error_code; 2115 __le16 error_code;
1969 __le16 req_type; 2116 __le16 req_type;
1970 __le16 seq_id; 2117 __le16 seq_id;
1971 __le16 resp_len; 2118 __le16 resp_len;
1972 u8 flags; 2119 u8 flags;
1973 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 2120 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
1974 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfeUL 2121 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfeUL
1975 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 1 2122 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 1
1976 u8 port_cnt; 2123 u8 port_cnt;
1977 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 2124 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
1978 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 2125 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
1979 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 2126 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL
1980 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 2127 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL
1981 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 2128 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL
1982 __le16 supported_speeds_force_mode; 2129 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4
1983 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 2130 __le16 supported_speeds_force_mode;
1984 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 2131 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
1985 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 2132 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
1986 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 2133 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
1987 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 2134 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
1988 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 2135 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
1989 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 2136 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
1990 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 2137 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
1991 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 2138 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
1992 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 2139 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
1993 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 2140 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
1994 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 2141 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
1995 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 2142 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
1996 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 2143 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
1997 __le16 supported_speeds_auto_mode; 2144 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
1998 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 2145 __le16 supported_speeds_auto_mode;
1999 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 2146 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
2000 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 2147 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
2001 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 2148 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
2002 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 2149 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
2003 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 2150 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
2004 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 2151 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
2005 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 2152 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
2006 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 2153 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
2007 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 2154 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
2008 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 2155 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
2009 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 2156 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
2010 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 2157 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
2011 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 2158 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
2012 __le16 supported_speeds_eee_mode; 2159 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
2013 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 2160 __le16 supported_speeds_eee_mode;
2014 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 2161 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
2015 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 2162 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
2016 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 2163 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
2017 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 2164 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL
2018 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 2165 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
2019 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 2166 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
2020 __le32 tx_lpi_timer_low; 2167 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
2021 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 2168 __le32 tx_lpi_timer_low;
2022 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 2169 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
2023 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 2170 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
2024 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 2171 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL
2025 __le32 valid_tx_lpi_timer_high; 2172 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24
2026 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 2173 __le32 valid_tx_lpi_timer_high;
2027 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 2174 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
2028 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 2175 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
2029 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 2176 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL
2030}; 2177 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24
2031 2178};
2032/* hwrm_port_phy_i2c_read */ 2179
2033/* Input (40 bytes) */ 2180/* hwrm_port_phy_i2c_read_input (size:320b/40B) */
2034struct hwrm_port_phy_i2c_read_input { 2181struct hwrm_port_phy_i2c_read_input {
2035 __le16 req_type; 2182 __le16 req_type;
2036 __le16 cmpl_ring; 2183 __le16 cmpl_ring;
2037 __le16 seq_id; 2184 __le16 seq_id;
2038 __le16 target_id; 2185 __le16 target_id;
2039 __le64 resp_addr; 2186 __le64 resp_addr;
2040 __le32 flags; 2187 __le32 flags;
2041 __le32 enables; 2188 __le32 enables;
2042 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 2189 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL
2043 __le16 port_id; 2190 __le16 port_id;
2044 u8 i2c_slave_addr; 2191 u8 i2c_slave_addr;
2045 u8 unused_0; 2192 u8 unused_0;
2046 __le16 page_number; 2193 __le16 page_number;
2047 __le16 page_offset; 2194 __le16 page_offset;
2048 u8 data_length; 2195 u8 data_length;
2049 u8 unused_1[7]; 2196 u8 unused_1[7];
2050}; 2197};
2051 2198
2052/* Output (80 bytes) */ 2199/* hwrm_port_phy_i2c_read_output (size:640b/80B) */
2053struct hwrm_port_phy_i2c_read_output { 2200struct hwrm_port_phy_i2c_read_output {
2054 __le16 error_code; 2201 __le16 error_code;
2055 __le16 req_type; 2202 __le16 req_type;
2056 __le16 seq_id; 2203 __le16 seq_id;
2057 __le16 resp_len; 2204 __le16 resp_len;
2058 __le32 data[16]; 2205 __le32 data[16];
2059 __le32 unused_0; 2206 u8 unused_0[7];
2060 u8 unused_1; 2207 u8 valid;
2061 u8 unused_2; 2208};
2062 u8 unused_3; 2209
2063 u8 valid; 2210/* hwrm_port_led_cfg_input (size:512b/64B) */
2064};
2065
2066/* hwrm_port_led_cfg */
2067/* Input (64 bytes) */
2068struct hwrm_port_led_cfg_input { 2211struct hwrm_port_led_cfg_input {
2069 __le16 req_type; 2212 __le16 req_type;
2070 __le16 cmpl_ring; 2213 __le16 cmpl_ring;
2071 __le16 seq_id; 2214 __le16 seq_id;
2072 __le16 target_id; 2215 __le16 target_id;
2073 __le64 resp_addr; 2216 __le64 resp_addr;
2074 __le32 enables; 2217 __le32 enables;
2075 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 2218 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL
2076 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 2219 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL
2077 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 2220 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL
2078 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 2221 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL
2079 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 2222 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL
2080 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 2223 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL
2081 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 2224 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL
2082 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 2225 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL
2083 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 2226 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL
2084 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 2227 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL
2085 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 2228 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL
2086 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 2229 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL
2087 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 2230 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL
2088 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 2231 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL
2089 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 2232 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL
2090 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 2233 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL
2091 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 2234 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL
2092 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 2235 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL
2093 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 2236 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL
2094 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 2237 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL
2095 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 2238 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL
2096 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 2239 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL
2097 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 2240 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL
2098 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 2241 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL
2099 __le16 port_id; 2242 __le16 port_id;
2100 u8 num_leds; 2243 u8 num_leds;
2101 u8 rsvd; 2244 u8 rsvd;
2102 u8 led0_id; 2245 u8 led0_id;
2103 u8 led0_state; 2246 u8 led0_state;
2104 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 2247 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL
2105 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 2248 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL
2106 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 2249 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL
2107 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 2250 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL
2108 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 2251 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
2109 u8 led0_color; 2252 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
2110 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 2253 u8 led0_color;
2111 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 2254 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL
2112 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 2255 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL
2113 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 2256 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL
2114 u8 unused_0; 2257 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
2115 __le16 led0_blink_on; 2258 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
2116 __le16 led0_blink_off; 2259 u8 unused_0;
2117 u8 led0_group_id; 2260 __le16 led0_blink_on;
2118 u8 rsvd0; 2261 __le16 led0_blink_off;
2119 u8 led1_id; 2262 u8 led0_group_id;
2120 u8 led1_state; 2263 u8 rsvd0;
2121 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 2264 u8 led1_id;
2122 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 2265 u8 led1_state;
2123 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 2266 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL
2124 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 2267 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL
2125 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 2268 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL
2126 u8 led1_color; 2269 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL
2127 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 2270 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
2128 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 2271 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
2129 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 2272 u8 led1_color;
2130 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 2273 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL
2131 u8 unused_1; 2274 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL
2132 __le16 led1_blink_on; 2275 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL
2133 __le16 led1_blink_off; 2276 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
2134 u8 led1_group_id; 2277 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
2135 u8 rsvd1; 2278 u8 unused_1;
2136 u8 led2_id; 2279 __le16 led1_blink_on;
2137 u8 led2_state; 2280 __le16 led1_blink_off;
2138 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 2281 u8 led1_group_id;
2139 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 2282 u8 rsvd1;
2140 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 2283 u8 led2_id;
2141 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 2284 u8 led2_state;
2142 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 2285 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL
2143 u8 led2_color; 2286 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL
2144 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 2287 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL
2145 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 2288 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL
2146 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 2289 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
2147 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 2290 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
2148 u8 unused_2; 2291 u8 led2_color;
2149 __le16 led2_blink_on; 2292 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL
2150 __le16 led2_blink_off; 2293 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL
2151 u8 led2_group_id; 2294 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL
2152 u8 rsvd2; 2295 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
2153 u8 led3_id; 2296 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
2154 u8 led3_state; 2297 u8 unused_2;
2155 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 2298 __le16 led2_blink_on;
2156 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 2299 __le16 led2_blink_off;
2157 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 2300 u8 led2_group_id;
2158 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 2301 u8 rsvd2;
2159 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 2302 u8 led3_id;
2160 u8 led3_color; 2303 u8 led3_state;
2161 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 2304 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL
2162 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 2305 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL
2163 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 2306 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL
2164 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 2307 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL
2165 u8 unused_3; 2308 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
2166 __le16 led3_blink_on; 2309 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
2167 __le16 led3_blink_off; 2310 u8 led3_color;
2168 u8 led3_group_id; 2311 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL
2169 u8 rsvd3; 2312 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL
2170}; 2313 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL
2171 2314 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
2172/* Output (16 bytes) */ 2315 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
2316 u8 unused_3;
2317 __le16 led3_blink_on;
2318 __le16 led3_blink_off;
2319 u8 led3_group_id;
2320 u8 rsvd3;
2321};
2322
2323/* hwrm_port_led_cfg_output (size:128b/16B) */
2173struct hwrm_port_led_cfg_output { 2324struct hwrm_port_led_cfg_output {
2174 __le16 error_code; 2325 __le16 error_code;
2175 __le16 req_type; 2326 __le16 req_type;
2176 __le16 seq_id; 2327 __le16 seq_id;
2177 __le16 resp_len; 2328 __le16 resp_len;
2178 __le32 unused_0; 2329 u8 unused_0[7];
2179 u8 unused_1; 2330 u8 valid;
2180 u8 unused_2; 2331};
2181 u8 unused_3; 2332
2182 u8 valid; 2333/* hwrm_port_led_qcfg_input (size:192b/24B) */
2183}; 2334struct hwrm_port_led_qcfg_input {
2184 2335 __le16 req_type;
2185/* hwrm_port_led_qcaps */ 2336 __le16 cmpl_ring;
2186/* Input (24 bytes) */ 2337 __le16 seq_id;
2338 __le16 target_id;
2339 __le64 resp_addr;
2340 __le16 port_id;
2341 u8 unused_0[6];
2342};
2343
2344/* hwrm_port_led_qcfg_output (size:448b/56B) */
2345struct hwrm_port_led_qcfg_output {
2346 __le16 error_code;
2347 __le16 req_type;
2348 __le16 seq_id;
2349 __le16 resp_len;
2350 u8 num_leds;
2351 u8 led0_id;
2352 u8 led0_type;
2353 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL
2354 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
2355 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL
2356 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
2357 u8 led0_state;
2358 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL
2359 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL
2360 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL
2361 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL
2362 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
2363 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
2364 u8 led0_color;
2365 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL
2366 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL
2367 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL
2368 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
2369 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
2370 u8 unused_0;
2371 __le16 led0_blink_on;
2372 __le16 led0_blink_off;
2373 u8 led0_group_id;
2374 u8 led1_id;
2375 u8 led1_type;
2376 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL
2377 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
2378 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL
2379 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
2380 u8 led1_state;
2381 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL
2382 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL
2383 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL
2384 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL
2385 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
2386 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
2387 u8 led1_color;
2388 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL
2389 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL
2390 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL
2391 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
2392 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
2393 u8 unused_1;
2394 __le16 led1_blink_on;
2395 __le16 led1_blink_off;
2396 u8 led1_group_id;
2397 u8 led2_id;
2398 u8 led2_type;
2399 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL
2400 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
2401 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL
2402 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
2403 u8 led2_state;
2404 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL
2405 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL
2406 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL
2407 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL
2408 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
2409 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
2410 u8 led2_color;
2411 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL
2412 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL
2413 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL
2414 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
2415 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
2416 u8 unused_2;
2417 __le16 led2_blink_on;
2418 __le16 led2_blink_off;
2419 u8 led2_group_id;
2420 u8 led3_id;
2421 u8 led3_type;
2422 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL
2423 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
2424 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL
2425 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
2426 u8 led3_state;
2427 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL
2428 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL
2429 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL
2430 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL
2431 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
2432 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
2433 u8 led3_color;
2434 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL
2435 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL
2436 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL
2437 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
2438 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
2439 u8 unused_3;
2440 __le16 led3_blink_on;
2441 __le16 led3_blink_off;
2442 u8 led3_group_id;
2443 u8 unused_4[6];
2444 u8 valid;
2445};
2446
2447/* hwrm_port_led_qcaps_input (size:192b/24B) */
2187struct hwrm_port_led_qcaps_input { 2448struct hwrm_port_led_qcaps_input {
2188 __le16 req_type; 2449 __le16 req_type;
2189 __le16 cmpl_ring; 2450 __le16 cmpl_ring;
2190 __le16 seq_id; 2451 __le16 seq_id;
2191 __le16 target_id; 2452 __le16 target_id;
2192 __le64 resp_addr; 2453 __le64 resp_addr;
2193 __le16 port_id; 2454 __le16 port_id;
2194 __le16 unused_0[3]; 2455 u8 unused_0[6];
2195}; 2456};
2196 2457
2197/* Output (48 bytes) */ 2458/* hwrm_port_led_qcaps_output (size:384b/48B) */
2198struct hwrm_port_led_qcaps_output { 2459struct hwrm_port_led_qcaps_output {
2199 __le16 error_code; 2460 __le16 error_code;
2200 __le16 req_type; 2461 __le16 req_type;
2201 __le16 seq_id; 2462 __le16 seq_id;
2202 __le16 resp_len; 2463 __le16 resp_len;
2203 u8 num_leds; 2464 u8 num_leds;
2204 u8 unused_0[3]; 2465 u8 unused[3];
2205 u8 led0_id; 2466 u8 led0_id;
2206 u8 led0_type; 2467 u8 led0_type;
2207 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 2468 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL
2208 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 2469 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
2209 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 2470 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL
2210 u8 led0_group_id; 2471 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
2211 u8 unused_1; 2472 u8 led0_group_id;
2212 __le16 led0_state_caps; 2473 u8 unused_0;
2213 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 2474 __le16 led0_state_caps;
2214 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 2475 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL
2215 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 2476 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL
2216 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2477 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL
2217 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2478 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL
2218 __le16 led0_color_caps; 2479 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
2219 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 2480 __le16 led0_color_caps;
2220 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2481 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL
2221 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2482 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
2222 u8 led1_id; 2483 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
2223 u8 led1_type; 2484 u8 led1_id;
2224 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 2485 u8 led1_type;
2225 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 2486 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL
2226 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 2487 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
2227 u8 led1_group_id; 2488 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL
2228 u8 unused_2; 2489 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
2229 __le16 led1_state_caps; 2490 u8 led1_group_id;
2230 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 2491 u8 unused_1;
2231 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 2492 __le16 led1_state_caps;
2232 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 2493 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL
2233 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2494 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL
2234 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2495 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL
2235 __le16 led1_color_caps; 2496 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL
2236 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 2497 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
2237 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2498 __le16 led1_color_caps;
2238 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2499 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL
2239 u8 led2_id; 2500 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
2240 u8 led2_type; 2501 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
2241 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 2502 u8 led2_id;
2242 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 2503 u8 led2_type;
2243 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 2504 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL
2244 u8 led2_group_id; 2505 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
2245 u8 unused_3; 2506 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL
2246 __le16 led2_state_caps; 2507 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
2247 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 2508 u8 led2_group_id;
2248 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 2509 u8 unused_2;
2249 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 2510 __le16 led2_state_caps;
2250 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2511 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL
2251 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2512 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL
2252 __le16 led2_color_caps; 2513 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL
2253 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 2514 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL
2254 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2515 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
2255 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2516 __le16 led2_color_caps;
2256 u8 led3_id; 2517 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL
2257 u8 led3_type; 2518 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
2258 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 2519 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
2259 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 2520 u8 led3_id;
2260 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 2521 u8 led3_type;
2261 u8 led3_group_id; 2522 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL
2262 u8 unused_4; 2523 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
2263 __le16 led3_state_caps; 2524 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL
2264 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 2525 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
2265 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 2526 u8 led3_group_id;
2266 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 2527 u8 unused_3;
2267 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2528 __le16 led3_state_caps;
2268 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2529 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL
2269 __le16 led3_color_caps; 2530 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL
2270 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 2531 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL
2271 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2532 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL
2272 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2533 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
2273 u8 unused_5; 2534 __le16 led3_color_caps;
2274 u8 unused_6; 2535 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL
2275 u8 unused_7; 2536 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
2276 u8 valid; 2537 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
2277}; 2538 u8 unused_4[3];
2278 2539 u8 valid;
2279/* hwrm_queue_qportcfg */ 2540};
2280/* Input (24 bytes) */ 2541
2542/* hwrm_queue_qportcfg_input (size:192b/24B) */
2281struct hwrm_queue_qportcfg_input { 2543struct hwrm_queue_qportcfg_input {
2282 __le16 req_type; 2544 __le16 req_type;
2283 __le16 cmpl_ring; 2545 __le16 cmpl_ring;
2284 __le16 seq_id; 2546 __le16 seq_id;
2285 __le16 target_id; 2547 __le16 target_id;
2286 __le64 resp_addr; 2548 __le64 resp_addr;
2287 __le32 flags; 2549 __le32 flags;
2288 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2550 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
2289 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 2551 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL
2290 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 2552 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL
2291 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2553 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
2292 __le16 port_id; 2554 __le16 port_id;
2293 __le16 unused_0; 2555 u8 unused_0[2];
2294}; 2556};
2295 2557
2296/* Output (32 bytes) */ 2558/* hwrm_queue_qportcfg_output (size:256b/32B) */
2297struct hwrm_queue_qportcfg_output { 2559struct hwrm_queue_qportcfg_output {
2298 __le16 error_code; 2560 __le16 error_code;
2299 __le16 req_type; 2561 __le16 req_type;
2300 __le16 seq_id; 2562 __le16 seq_id;
2301 __le16 resp_len; 2563 __le16 resp_len;
2302 u8 max_configurable_queues; 2564 u8 max_configurable_queues;
2303 u8 max_configurable_lossless_queues; 2565 u8 max_configurable_lossless_queues;
2304 u8 queue_cfg_allowed; 2566 u8 queue_cfg_allowed;
2305 u8 queue_cfg_info; 2567 u8 queue_cfg_info;
2306 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2568 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
2307 u8 queue_pfcenable_cfg_allowed; 2569 u8 queue_pfcenable_cfg_allowed;
2308 u8 queue_pri2cos_cfg_allowed; 2570 u8 queue_pri2cos_cfg_allowed;
2309 u8 queue_cos2bw_cfg_allowed; 2571 u8 queue_cos2bw_cfg_allowed;
2310 u8 queue_id0; 2572 u8 queue_id0;
2311 u8 queue_id0_service_profile; 2573 u8 queue_id0_service_profile;
2312 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 2574 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL
2313 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 2575 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL
2314 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 2576 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL
2315 u8 queue_id1; 2577 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
2316 u8 queue_id1_service_profile; 2578 u8 queue_id1;
2317 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 2579 u8 queue_id1_service_profile;
2580 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL
2318 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 2581 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL
2319 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 2582 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL
2320 u8 queue_id2; 2583 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
2321 u8 queue_id2_service_profile; 2584 u8 queue_id2;
2322 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 2585 u8 queue_id2_service_profile;
2586 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL
2323 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 2587 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL
2324 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 2588 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL
2325 u8 queue_id3; 2589 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
2326 u8 queue_id3_service_profile; 2590 u8 queue_id3;
2327 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 2591 u8 queue_id3_service_profile;
2592 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL
2328 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 2593 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL
2329 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 2594 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL
2330 u8 queue_id4; 2595 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
2331 u8 queue_id4_service_profile; 2596 u8 queue_id4;
2332 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 2597 u8 queue_id4_service_profile;
2598 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL
2333 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 2599 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL
2334 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 2600 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL
2335 u8 queue_id5; 2601 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
2336 u8 queue_id5_service_profile; 2602 u8 queue_id5;
2337 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 2603 u8 queue_id5_service_profile;
2604 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL
2338 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 2605 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL
2339 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 2606 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL
2340 u8 queue_id6; 2607 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
2341 u8 queue_id6_service_profile; 2608 u8 queue_id6;
2342 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 2609 u8 queue_id6_service_profile;
2610 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL
2343 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 2611 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL
2344 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 2612 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL
2345 u8 queue_id7; 2613 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
2346 u8 queue_id7_service_profile; 2614 u8 queue_id7;
2347 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 2615 u8 queue_id7_service_profile;
2616 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL
2348 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 2617 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL
2349 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 2618 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL
2350 u8 valid; 2619 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
2620 u8 valid;
2351}; 2621};
2352 2622
2353/* hwrm_queue_cfg */ 2623/* hwrm_queue_cfg_input (size:320b/40B) */
2354/* Input (40 bytes) */
2355struct hwrm_queue_cfg_input { 2624struct hwrm_queue_cfg_input {
2356 __le16 req_type; 2625 __le16 req_type;
2357 __le16 cmpl_ring; 2626 __le16 cmpl_ring;
2358 __le16 seq_id; 2627 __le16 seq_id;
2359 __le16 target_id; 2628 __le16 target_id;
2360 __le64 resp_addr; 2629 __le64 resp_addr;
2361 __le32 flags; 2630 __le32 flags;
2362 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2631 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
2363 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 2632 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0
2364 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 2633 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL
2365 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 2634 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL
2366 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2635 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
2367 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 2636 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
2368 __le32 enables; 2637 __le32 enables;
2369 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2638 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
2370 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2639 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
2371 __le32 queue_id; 2640 __le32 queue_id;
2372 __le32 dflt_len; 2641 __le32 dflt_len;
2373 u8 service_profile; 2642 u8 service_profile;
2374 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 2643 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL
2375 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 2644 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
2376 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 2645 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL
2377 u8 unused_0[7]; 2646 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
2378}; 2647 u8 unused_0[7];
2379 2648};
2380/* Output (16 bytes) */ 2649
2650/* hwrm_queue_cfg_output (size:128b/16B) */
2381struct hwrm_queue_cfg_output { 2651struct hwrm_queue_cfg_output {
2382 __le16 error_code; 2652 __le16 error_code;
2383 __le16 req_type; 2653 __le16 req_type;
2384 __le16 seq_id; 2654 __le16 seq_id;
2385 __le16 resp_len; 2655 __le16 resp_len;
2386 __le32 unused_0; 2656 u8 unused_0[7];
2387 u8 unused_1; 2657 u8 valid;
2388 u8 unused_2; 2658};
2389 u8 unused_3; 2659
2390 u8 valid; 2660/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
2391};
2392
2393/* hwrm_queue_pfcenable_qcfg */
2394/* Input (24 bytes) */
2395struct hwrm_queue_pfcenable_qcfg_input { 2661struct hwrm_queue_pfcenable_qcfg_input {
2396 __le16 req_type; 2662 __le16 req_type;
2397 __le16 cmpl_ring; 2663 __le16 cmpl_ring;
2398 __le16 seq_id; 2664 __le16 seq_id;
2399 __le16 target_id; 2665 __le16 target_id;
2400 __le64 resp_addr; 2666 __le64 resp_addr;
2401 __le16 port_id; 2667 __le16 port_id;
2402 __le16 unused_0[3]; 2668 u8 unused_0[6];
2403}; 2669};
2404 2670
2405/* Output (16 bytes) */ 2671/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
2406struct hwrm_queue_pfcenable_qcfg_output { 2672struct hwrm_queue_pfcenable_qcfg_output {
2407 __le16 error_code; 2673 __le16 error_code;
2408 __le16 req_type; 2674 __le16 req_type;
2409 __le16 seq_id; 2675 __le16 seq_id;
2410 __le16 resp_len; 2676 __le16 resp_len;
2411 __le32 flags; 2677 __le32 flags;
2412 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 2678 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL
2413 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 2679 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL
2414 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 2680 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL
2415 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 2681 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL
2416 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 2682 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL
2417 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 2683 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL
2418 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 2684 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL
2419 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 2685 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL
2420 u8 unused_0; 2686 u8 unused_0[3];
2421 u8 unused_1; 2687 u8 valid;
2422 u8 unused_2; 2688};
2423 u8 valid; 2689
2424}; 2690/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
2425
2426/* hwrm_queue_pfcenable_cfg */
2427/* Input (24 bytes) */
2428struct hwrm_queue_pfcenable_cfg_input { 2691struct hwrm_queue_pfcenable_cfg_input {
2429 __le16 req_type; 2692 __le16 req_type;
2430 __le16 cmpl_ring; 2693 __le16 cmpl_ring;
2431 __le16 seq_id; 2694 __le16 seq_id;
2432 __le16 target_id; 2695 __le16 target_id;
2433 __le64 resp_addr; 2696 __le64 resp_addr;
2434 __le32 flags; 2697 __le32 flags;
2435 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2698 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
2436 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2699 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
2437 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2700 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
@@ -2440,1729 +2703,1664 @@ struct hwrm_queue_pfcenable_cfg_input {
2440 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2703 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
2441 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2704 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
2442 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2705 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
2443 __le16 port_id; 2706 __le16 port_id;
2444 __le16 unused_0; 2707 u8 unused_0[2];
2445}; 2708};
2446 2709
2447/* Output (16 bytes) */ 2710/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
2448struct hwrm_queue_pfcenable_cfg_output { 2711struct hwrm_queue_pfcenable_cfg_output {
2449 __le16 error_code; 2712 __le16 error_code;
2450 __le16 req_type; 2713 __le16 req_type;
2451 __le16 seq_id; 2714 __le16 seq_id;
2452 __le16 resp_len; 2715 __le16 resp_len;
2453 __le32 unused_0; 2716 u8 unused_0[7];
2454 u8 unused_1; 2717 u8 valid;
2455 u8 unused_2; 2718};
2456 u8 unused_3; 2719
2457 u8 valid; 2720/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
2458};
2459
2460/* hwrm_queue_pri2cos_qcfg */
2461/* Input (24 bytes) */
2462struct hwrm_queue_pri2cos_qcfg_input { 2721struct hwrm_queue_pri2cos_qcfg_input {
2463 __le16 req_type; 2722 __le16 req_type;
2464 __le16 cmpl_ring; 2723 __le16 cmpl_ring;
2465 __le16 seq_id; 2724 __le16 seq_id;
2466 __le16 target_id; 2725 __le16 target_id;
2467 __le64 resp_addr; 2726 __le64 resp_addr;
2468 __le32 flags; 2727 __le32 flags;
2469 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 2728 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL
2470 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2729 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL
2471 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2730 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL
2472 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 2731 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
2473 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 2732 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL
2474 u8 port_id; 2733 u8 port_id;
2475 u8 unused_0[3]; 2734 u8 unused_0[3];
2476}; 2735};
2477 2736
2478/* Output (24 bytes) */ 2737/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
2479struct hwrm_queue_pri2cos_qcfg_output { 2738struct hwrm_queue_pri2cos_qcfg_output {
2480 __le16 error_code; 2739 __le16 error_code;
2481 __le16 req_type; 2740 __le16 req_type;
2482 __le16 seq_id; 2741 __le16 seq_id;
2483 __le16 resp_len; 2742 __le16 resp_len;
2484 u8 pri0_cos_queue_id; 2743 u8 pri0_cos_queue_id;
2485 u8 pri1_cos_queue_id; 2744 u8 pri1_cos_queue_id;
2486 u8 pri2_cos_queue_id; 2745 u8 pri2_cos_queue_id;
2487 u8 pri3_cos_queue_id; 2746 u8 pri3_cos_queue_id;
2488 u8 pri4_cos_queue_id; 2747 u8 pri4_cos_queue_id;
2489 u8 pri5_cos_queue_id; 2748 u8 pri5_cos_queue_id;
2490 u8 pri6_cos_queue_id; 2749 u8 pri6_cos_queue_id;
2491 u8 pri7_cos_queue_id; 2750 u8 pri7_cos_queue_id;
2492 u8 queue_cfg_info; 2751 u8 queue_cfg_info;
2493 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2752 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
2494 u8 unused_0; 2753 u8 unused_0[6];
2495 __le16 unused_1; 2754 u8 valid;
2496 u8 unused_2; 2755};
2497 u8 unused_3; 2756
2498 u8 unused_4; 2757/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
2499 u8 valid;
2500};
2501
2502/* hwrm_queue_pri2cos_cfg */
2503/* Input (40 bytes) */
2504struct hwrm_queue_pri2cos_cfg_input { 2758struct hwrm_queue_pri2cos_cfg_input {
2505 __le16 req_type; 2759 __le16 req_type;
2506 __le16 cmpl_ring; 2760 __le16 cmpl_ring;
2507 __le16 seq_id; 2761 __le16 seq_id;
2508 __le16 target_id; 2762 __le16 target_id;
2509 __le64 resp_addr; 2763 __le64 resp_addr;
2510 __le32 flags; 2764 __le32 flags;
2511 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2765 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
2512 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 2766 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0
2513 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2767 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL
2514 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2768 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL
2515 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR (0x2UL << 0) 2769 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
2516 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 2770 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
2517 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 2771 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL
2518 __le32 enables; 2772 __le32 enables;
2519 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 2773 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL
2520 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 2774 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL
2521 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 2775 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL
2522 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 2776 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL
2523 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 2777 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL
2524 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 2778 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL
2525 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 2779 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL
2526 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 2780 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL
2527 u8 port_id; 2781 u8 port_id;
2528 u8 pri0_cos_queue_id; 2782 u8 pri0_cos_queue_id;
2529 u8 pri1_cos_queue_id; 2783 u8 pri1_cos_queue_id;
2530 u8 pri2_cos_queue_id; 2784 u8 pri2_cos_queue_id;
2531 u8 pri3_cos_queue_id; 2785 u8 pri3_cos_queue_id;
2532 u8 pri4_cos_queue_id; 2786 u8 pri4_cos_queue_id;
2533 u8 pri5_cos_queue_id; 2787 u8 pri5_cos_queue_id;
2534 u8 pri6_cos_queue_id; 2788 u8 pri6_cos_queue_id;
2535 u8 pri7_cos_queue_id; 2789 u8 pri7_cos_queue_id;
2536 u8 unused_0[7]; 2790 u8 unused_0[7];
2537}; 2791};
2538 2792
2539/* Output (16 bytes) */ 2793/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
2540struct hwrm_queue_pri2cos_cfg_output { 2794struct hwrm_queue_pri2cos_cfg_output {
2541 __le16 error_code; 2795 __le16 error_code;
2542 __le16 req_type; 2796 __le16 req_type;
2543 __le16 seq_id; 2797 __le16 seq_id;
2544 __le16 resp_len; 2798 __le16 resp_len;
2545 __le32 unused_0; 2799 u8 unused_0[7];
2546 u8 unused_1; 2800 u8 valid;
2547 u8 unused_2; 2801};
2548 u8 unused_3; 2802
2549 u8 valid; 2803/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
2550};
2551
2552/* hwrm_queue_cos2bw_qcfg */
2553/* Input (24 bytes) */
2554struct hwrm_queue_cos2bw_qcfg_input { 2804struct hwrm_queue_cos2bw_qcfg_input {
2555 __le16 req_type; 2805 __le16 req_type;
2556 __le16 cmpl_ring; 2806 __le16 cmpl_ring;
2557 __le16 seq_id; 2807 __le16 seq_id;
2558 __le16 target_id; 2808 __le16 target_id;
2559 __le64 resp_addr; 2809 __le64 resp_addr;
2560 __le16 port_id; 2810 __le16 port_id;
2561 __le16 unused_0[3]; 2811 u8 unused_0[6];
2562}; 2812};
2563 2813
2564/* Output (112 bytes) */ 2814/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
2565struct hwrm_queue_cos2bw_qcfg_output { 2815struct hwrm_queue_cos2bw_qcfg_output {
2566 __le16 error_code; 2816 __le16 error_code;
2567 __le16 req_type; 2817 __le16 req_type;
2568 __le16 seq_id; 2818 __le16 seq_id;
2569 __le16 resp_len; 2819 __le16 resp_len;
2570 u8 queue_id0; 2820 u8 queue_id0;
2571 u8 unused_0; 2821 u8 unused_0;
2572 __le16 unused_1; 2822 __le16 unused_1;
2573 __le32 queue_id0_min_bw; 2823 __le32 queue_id0_min_bw;
2574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2824 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2575 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2825 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
2576 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2826 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
2577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
2578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
2579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 2829 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
2580 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2830 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2581 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2831 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
2582 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2832 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2583 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2833 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2584 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2834 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2585 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2835 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2586 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2836 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2587 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2837 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2588 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2838 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
2589 __le32 queue_id0_max_bw; 2839 __le32 queue_id0_max_bw;
2590 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2840 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2591 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2841 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
2592 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2842 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
2593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2843 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
2594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2844 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
2595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 2845 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
2596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2846 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2847 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
2598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2848 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2849 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2850 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2851 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2852 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2853 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2854 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
2605 u8 queue_id0_tsa_assign; 2855 u8 queue_id0_tsa_assign;
2606 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2856 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
2607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2857 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
2608 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2858 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
2609 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2859 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
2610 u8 queue_id0_pri_lvl; 2860 u8 queue_id0_pri_lvl;
2611 u8 queue_id0_bw_weight; 2861 u8 queue_id0_bw_weight;
2612 u8 queue_id1; 2862 u8 queue_id1;
2613 __le32 queue_id1_min_bw; 2863 __le32 queue_id1_min_bw;
2614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2864 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2865 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
2616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2866 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
2617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2867 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
2618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2868 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
2619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 2869 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES
2620 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2870 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2621 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2871 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
2622 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2872 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2623 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2873 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2624 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2874 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2625 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2875 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2626 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2876 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2627 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2877 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2628 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2878 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
2629 __le32 queue_id1_max_bw; 2879 __le32 queue_id1_max_bw;
2630 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2631 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2881 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
2632 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2882 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
2633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
2634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
2635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 2885 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES
2636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2886 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2887 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
2638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2888 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2889 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2890 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2891 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2892 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2893 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2894 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
2645 u8 queue_id1_tsa_assign; 2895 u8 queue_id1_tsa_assign;
2646 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2896 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
2647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2897 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
2648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2898 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
2649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2899 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
2650 u8 queue_id1_pri_lvl; 2900 u8 queue_id1_pri_lvl;
2651 u8 queue_id1_bw_weight; 2901 u8 queue_id1_bw_weight;
2652 u8 queue_id2; 2902 u8 queue_id2;
2653 __le32 queue_id2_min_bw; 2903 __le32 queue_id2_min_bw;
2654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2904 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2905 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
2656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 2906 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
2657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 2907 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
2658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 2908 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
2659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 2909 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES
2660 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2910 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2661 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2911 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
2662 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2912 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2663 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2913 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2664 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2914 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2665 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2915 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2666 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2916 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2667 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2917 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2668 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2918 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
2669 __le32 queue_id2_max_bw; 2919 __le32 queue_id2_max_bw;
2670 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2920 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2671 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2921 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
2672 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 2922 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
2673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 2923 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
2674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 2924 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
2675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 2925 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES
2676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2926 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2927 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
2678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2928 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2929 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2930 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2931 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2932 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2933 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2934 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
2685 u8 queue_id2_tsa_assign; 2935 u8 queue_id2_tsa_assign;
2686 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2936 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
2687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2937 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
2688 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2938 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
2689 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2939 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
2690 u8 queue_id2_pri_lvl; 2940 u8 queue_id2_pri_lvl;
2691 u8 queue_id2_bw_weight; 2941 u8 queue_id2_bw_weight;
2692 u8 queue_id3; 2942 u8 queue_id3;
2693 __le32 queue_id3_min_bw; 2943 __le32 queue_id3_min_bw;
2694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2944 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2945 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
2696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 2946 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
2697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 2947 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
2698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 2948 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
2699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 2949 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES
2700 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2950 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2701 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2951 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
2702 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2952 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2703 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2953 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2704 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2954 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2705 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2955 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2706 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2956 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2707 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2957 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2708 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2958 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
2709 __le32 queue_id3_max_bw; 2959 __le32 queue_id3_max_bw;
2710 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2960 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2711 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2961 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
2712 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 2962 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
2713 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 2963 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
2714 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 2964 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
2715 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 2965 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES
2716 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2966 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2717 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2967 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
2718 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2968 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2969 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2970 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2971 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2972 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2973 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2974 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
2725 u8 queue_id3_tsa_assign; 2975 u8 queue_id3_tsa_assign;
2726 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2976 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
2727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2977 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
2728 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2978 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
2729 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2979 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
2730 u8 queue_id3_pri_lvl; 2980 u8 queue_id3_pri_lvl;
2731 u8 queue_id3_bw_weight; 2981 u8 queue_id3_bw_weight;
2732 u8 queue_id4; 2982 u8 queue_id4;
2733 __le32 queue_id4_min_bw; 2983 __le32 queue_id4_min_bw;
2734 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2984 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2985 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
2736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 2986 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
2737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 2987 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
2738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 2988 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
2739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 2989 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES
2740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2990 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2991 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
2742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2992 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2993 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2744 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2994 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2745 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2995 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2746 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2996 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2747 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2997 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2748 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2998 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
2749 __le32 queue_id4_max_bw; 2999 __le32 queue_id4_max_bw;
2750 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3000 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2751 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 3001 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
2752 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3002 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
2753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3003 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
2754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3004 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
2755 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 3005 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES
2756 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3006 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2757 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3007 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
2758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3008 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3009 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3010 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3011 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3012 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3013 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3014 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
2765 u8 queue_id4_tsa_assign; 3015 u8 queue_id4_tsa_assign;
2766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3016 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
2767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3017 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
2768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3018 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
2769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3019 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
2770 u8 queue_id4_pri_lvl; 3020 u8 queue_id4_pri_lvl;
2771 u8 queue_id4_bw_weight; 3021 u8 queue_id4_bw_weight;
2772 u8 queue_id5; 3022 u8 queue_id5;
2773 __le32 queue_id5_min_bw; 3023 __le32 queue_id5_min_bw;
2774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3024 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3025 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
2776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3026 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
2777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3027 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
2778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3028 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
2779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 3029 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES
2780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3030 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3031 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
2782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3032 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3033 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3034 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2785 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3035 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2786 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3036 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2787 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3037 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2788 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3038 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
2789 __le32 queue_id5_max_bw; 3039 __le32 queue_id5_max_bw;
2790 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3040 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2791 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3041 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
2792 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3042 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
2793 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3043 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
2794 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3044 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
2795 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 3045 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES
2796 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3046 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2797 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3047 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
2798 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3048 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2799 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3049 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2800 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3050 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2801 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3051 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2802 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3052 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2803 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3053 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2804 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3054 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
2805 u8 queue_id5_tsa_assign; 3055 u8 queue_id5_tsa_assign;
2806 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3056 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
2807 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3057 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
2808 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3058 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
2809 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3059 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
2810 u8 queue_id5_pri_lvl; 3060 u8 queue_id5_pri_lvl;
2811 u8 queue_id5_bw_weight; 3061 u8 queue_id5_bw_weight;
2812 u8 queue_id6; 3062 u8 queue_id6;
2813 __le32 queue_id6_min_bw; 3063 __le32 queue_id6_min_bw;
2814 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3064 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2815 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3065 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
2816 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3066 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
2817 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3067 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
2818 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3068 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
2819 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 3069 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES
2820 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3070 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2821 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3071 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
2822 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3072 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2823 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3073 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2824 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3074 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2825 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3075 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2826 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3076 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3077 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3078 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
2829 __le32 queue_id6_max_bw; 3079 __le32 queue_id6_max_bw;
2830 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3080 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2831 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3081 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
2832 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3082 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
2833 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3083 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
2834 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3084 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
2835 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 3085 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES
2836 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3086 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2837 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3087 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
2838 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3088 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2839 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3089 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2840 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3090 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2841 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3091 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2842 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3092 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2843 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3093 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2844 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3094 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
2845 u8 queue_id6_tsa_assign; 3095 u8 queue_id6_tsa_assign;
2846 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3096 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
2847 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3097 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
2848 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3098 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
2849 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3099 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
2850 u8 queue_id6_pri_lvl; 3100 u8 queue_id6_pri_lvl;
2851 u8 queue_id6_bw_weight; 3101 u8 queue_id6_bw_weight;
2852 u8 queue_id7; 3102 u8 queue_id7;
2853 __le32 queue_id7_min_bw; 3103 __le32 queue_id7_min_bw;
2854 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3104 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2855 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3105 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
2856 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3106 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
2857 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3107 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
2858 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3108 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
2859 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 3109 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES
2860 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3110 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2861 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3111 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
2862 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3112 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2863 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3113 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2864 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3114 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2865 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3115 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2866 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3116 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2867 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3117 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2868 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3118 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
2869 __le32 queue_id7_max_bw; 3119 __le32 queue_id7_max_bw;
2870 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3120 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2871 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3121 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
2872 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3122 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
2873 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3123 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
2874 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3124 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
2875 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 3125 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES
2876 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3126 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2877 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3127 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
2878 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3128 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2879 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3129 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3130 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2881 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3131 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2882 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3132 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3133 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3134 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
2885 u8 queue_id7_tsa_assign; 3135 u8 queue_id7_tsa_assign;
2886 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3136 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
2887 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3137 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
2888 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3138 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
2889 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3139 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
2890 u8 queue_id7_pri_lvl; 3140 u8 queue_id7_pri_lvl;
2891 u8 queue_id7_bw_weight; 3141 u8 queue_id7_bw_weight;
2892 u8 unused_2; 3142 u8 unused_2[4];
2893 u8 unused_3; 3143 u8 valid;
2894 u8 unused_4; 3144};
2895 u8 unused_5; 3145
2896 u8 valid; 3146/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
2897};
2898
2899/* hwrm_queue_cos2bw_cfg */
2900/* Input (128 bytes) */
2901struct hwrm_queue_cos2bw_cfg_input { 3147struct hwrm_queue_cos2bw_cfg_input {
2902 __le16 req_type; 3148 __le16 req_type;
2903 __le16 cmpl_ring; 3149 __le16 cmpl_ring;
2904 __le16 seq_id; 3150 __le16 seq_id;
2905 __le16 target_id; 3151 __le16 target_id;
2906 __le64 resp_addr; 3152 __le64 resp_addr;
2907 __le32 flags; 3153 __le32 flags;
2908 __le32 enables; 3154 __le32 enables;
2909 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 3155 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
2910 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 3156 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
2911 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 3157 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
2912 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 3158 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
2913 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 3159 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
2914 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 3160 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
2915 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 3161 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
2916 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 3162 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
2917 __le16 port_id; 3163 __le16 port_id;
2918 u8 queue_id0; 3164 u8 queue_id0;
2919 u8 unused_0; 3165 u8 unused_0;
2920 __le32 queue_id0_min_bw; 3166 __le32 queue_id0_min_bw;
2921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3167 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 3168 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
2923 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 3169 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
2924 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 3170 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
2925 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 3171 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
2926 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 3172 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
2927 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3173 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2928 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 3174 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
2929 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3175 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2930 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3176 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2931 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3177 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2932 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3178 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2933 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3179 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2934 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3180 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2935 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 3181 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
2936 __le32 queue_id0_max_bw; 3182 __le32 queue_id0_max_bw;
2937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3183 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 3184 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
2939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 3185 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
2940 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 3186 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
2941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 3187 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
2942 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 3188 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
2943 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3189 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2944 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 3190 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
2945 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3191 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3192 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2947 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3193 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3194 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2949 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3195 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2950 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3196 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2951 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 3197 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
2952 u8 queue_id0_tsa_assign; 3198 u8 queue_id0_tsa_assign;
2953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 3199 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
2954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 3200 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
2955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3201 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
2956 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 3202 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
2957 u8 queue_id0_pri_lvl; 3203 u8 queue_id0_pri_lvl;
2958 u8 queue_id0_bw_weight; 3204 u8 queue_id0_bw_weight;
2959 u8 queue_id1; 3205 u8 queue_id1;
2960 __le32 queue_id1_min_bw; 3206 __le32 queue_id1_min_bw;
2961 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3207 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 3208 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
2963 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 3209 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
2964 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 3210 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
2965 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 3211 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
2966 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 3212 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES
2967 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3213 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2968 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 3214 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
2969 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3215 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2970 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3216 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2971 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3217 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2972 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3218 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2973 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3219 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2974 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3220 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2975 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 3221 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
2976 __le32 queue_id1_max_bw; 3222 __le32 queue_id1_max_bw;
2977 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2978 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 3224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
2979 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 3225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
2980 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 3226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
2981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 3227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
2982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 3228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES
2983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 3230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
2985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
2986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3232 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
2987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
2988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
2989 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3236 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
2991 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 3237 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
2992 u8 queue_id1_tsa_assign; 3238 u8 queue_id1_tsa_assign;
2993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 3239 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
2994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 3240 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
2995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3241 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
2996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 3242 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
2997 u8 queue_id1_pri_lvl; 3243 u8 queue_id1_pri_lvl;
2998 u8 queue_id1_bw_weight; 3244 u8 queue_id1_bw_weight;
2999 u8 queue_id2; 3245 u8 queue_id2;
3000 __le32 queue_id2_min_bw; 3246 __le32 queue_id2_min_bw;
3001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3247 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 3248 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
3003 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 3249 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
3004 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 3250 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
3005 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 3251 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
3006 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 3252 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES
3007 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3253 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3008 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 3254 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
3009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3255 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3010 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3256 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3011 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3257 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3012 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3258 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3013 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3259 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3260 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 3261 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
3016 __le32 queue_id2_max_bw; 3262 __le32 queue_id2_max_bw;
3017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3263 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 3264 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
3019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 3265 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
3020 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 3266 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
3021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 3267 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
3022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 3268 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES
3023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3269 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 3270 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
3025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3271 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3272 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3273 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3274 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3275 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3276 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3031 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 3277 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
3032 u8 queue_id2_tsa_assign; 3278 u8 queue_id2_tsa_assign;
3033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 3279 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
3034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 3280 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
3035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3281 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 3282 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
3037 u8 queue_id2_pri_lvl; 3283 u8 queue_id2_pri_lvl;
3038 u8 queue_id2_bw_weight; 3284 u8 queue_id2_bw_weight;
3039 u8 queue_id3; 3285 u8 queue_id3;
3040 __le32 queue_id3_min_bw; 3286 __le32 queue_id3_min_bw;
3041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3287 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 3288 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
3043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 3289 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
3044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 3290 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
3045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 3291 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
3046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 3292 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES
3047 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3293 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3048 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 3294 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
3049 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3295 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3050 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3296 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3051 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3297 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3052 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3298 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3053 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3299 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3054 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3300 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3055 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 3301 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
3056 __le32 queue_id3_max_bw; 3302 __le32 queue_id3_max_bw;
3057 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3303 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3058 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 3304 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
3059 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 3305 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
3060 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 3306 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
3061 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 3307 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
3062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 3308 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES
3063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3309 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 3310 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
3065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3311 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3312 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3313 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3314 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3315 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3316 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3071 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 3317 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
3072 u8 queue_id3_tsa_assign; 3318 u8 queue_id3_tsa_assign;
3073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 3319 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
3074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 3320 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
3075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3321 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 3322 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
3077 u8 queue_id3_pri_lvl; 3323 u8 queue_id3_pri_lvl;
3078 u8 queue_id3_bw_weight; 3324 u8 queue_id3_bw_weight;
3079 u8 queue_id4; 3325 u8 queue_id4;
3080 __le32 queue_id4_min_bw; 3326 __le32 queue_id4_min_bw;
3081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3327 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 3328 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
3083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 3329 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
3084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 3330 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
3085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 3331 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
3086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 3332 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES
3087 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3333 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3088 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 3334 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
3089 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3335 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3090 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3336 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3091 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3337 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3092 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3338 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3093 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3339 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3094 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3340 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3095 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 3341 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
3096 __le32 queue_id4_max_bw; 3342 __le32 queue_id4_max_bw;
3097 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3343 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3098 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 3344 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
3099 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3345 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
3100 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3346 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
3101 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3347 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
3102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 3348 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES
3103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
3105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3352 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3353 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3354 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3109 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3355 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3356 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3111 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3357 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
3112 u8 queue_id4_tsa_assign; 3358 u8 queue_id4_tsa_assign;
3113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3359 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
3114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3360 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
3115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3361 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3116 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3362 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
3117 u8 queue_id4_pri_lvl; 3363 u8 queue_id4_pri_lvl;
3118 u8 queue_id4_bw_weight; 3364 u8 queue_id4_bw_weight;
3119 u8 queue_id5; 3365 u8 queue_id5;
3120 __le32 queue_id5_min_bw; 3366 __le32 queue_id5_min_bw;
3121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3367 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3368 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
3123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3369 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
3124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3370 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
3125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3371 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
3126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 3372 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES
3127 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3373 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3128 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3374 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
3129 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3375 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3130 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3376 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3131 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3377 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3132 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3378 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3133 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3379 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3134 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3380 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3135 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3381 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
3136 __le32 queue_id5_max_bw; 3382 __le32 queue_id5_max_bw;
3137 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3383 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3138 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3384 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
3139 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3385 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
3140 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3386 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
3141 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3387 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
3142 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 3388 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES
3143 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3389 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3144 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3390 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
3145 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3391 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3146 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3392 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3147 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3393 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3148 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3394 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3149 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3395 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3150 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3396 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3151 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3397 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
3152 u8 queue_id5_tsa_assign; 3398 u8 queue_id5_tsa_assign;
3153 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3399 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
3154 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3400 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
3155 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3401 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3156 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3402 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
3157 u8 queue_id5_pri_lvl; 3403 u8 queue_id5_pri_lvl;
3158 u8 queue_id5_bw_weight; 3404 u8 queue_id5_bw_weight;
3159 u8 queue_id6; 3405 u8 queue_id6;
3160 __le32 queue_id6_min_bw; 3406 __le32 queue_id6_min_bw;
3161 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3407 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3162 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3408 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
3163 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3409 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
3164 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3410 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
3165 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3411 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
3166 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 3412 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES
3167 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3413 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3168 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3414 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
3169 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3415 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3170 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3416 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3171 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3417 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3172 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3418 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3173 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3419 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3174 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3420 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3175 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3421 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
3176 __le32 queue_id6_max_bw; 3422 __le32 queue_id6_max_bw;
3177 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3423 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3178 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3424 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
3179 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3425 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
3180 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3426 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
3181 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3427 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
3182 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 3428 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES
3183 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3429 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3184 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3430 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
3185 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3431 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3186 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3432 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3187 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3433 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3188 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3434 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3189 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3435 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3190 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3436 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3191 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3437 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
3192 u8 queue_id6_tsa_assign; 3438 u8 queue_id6_tsa_assign;
3193 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3439 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
3194 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3440 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
3195 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3441 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3196 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3442 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
3197 u8 queue_id6_pri_lvl; 3443 u8 queue_id6_pri_lvl;
3198 u8 queue_id6_bw_weight; 3444 u8 queue_id6_bw_weight;
3199 u8 queue_id7; 3445 u8 queue_id7;
3200 __le32 queue_id7_min_bw; 3446 __le32 queue_id7_min_bw;
3201 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3447 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3202 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3448 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
3203 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3449 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
3204 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3450 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
3205 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3451 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
3206 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 3452 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES
3207 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3453 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3208 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3454 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
3209 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3455 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3210 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3456 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3211 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3457 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3212 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3458 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3213 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3459 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3214 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3460 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3215 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3461 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
3216 __le32 queue_id7_max_bw; 3462 __le32 queue_id7_max_bw;
3217 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3463 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3218 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3464 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
3219 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3465 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
3220 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3466 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
3221 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3467 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
3222 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 3468 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES
3223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3470 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
3225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3471 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3472 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3473 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3474 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3477 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
3232 u8 queue_id7_tsa_assign; 3478 u8 queue_id7_tsa_assign;
3233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3479 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
3234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
3235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
3236 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
3237 u8 queue_id7_pri_lvl; 3483 u8 queue_id7_pri_lvl;
3238 u8 queue_id7_bw_weight; 3484 u8 queue_id7_bw_weight;
3239 u8 unused_1[5]; 3485 u8 unused_1[5];
3240}; 3486};
3241 3487
3242/* Output (16 bytes) */ 3488/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
3243struct hwrm_queue_cos2bw_cfg_output { 3489struct hwrm_queue_cos2bw_cfg_output {
3244 __le16 error_code; 3490 __le16 error_code;
3245 __le16 req_type; 3491 __le16 req_type;
3246 __le16 seq_id; 3492 __le16 seq_id;
3247 __le16 resp_len; 3493 __le16 resp_len;
3248 __le32 unused_0; 3494 u8 unused_0[7];
3249 u8 unused_1; 3495 u8 valid;
3250 u8 unused_2; 3496};
3251 u8 unused_3; 3497
3252 u8 valid; 3498/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
3253};
3254
3255/* hwrm_queue_dscp_qcaps */
3256/* Input (24 bytes) */
3257struct hwrm_queue_dscp_qcaps_input { 3499struct hwrm_queue_dscp_qcaps_input {
3258 __le16 req_type; 3500 __le16 req_type;
3259 __le16 cmpl_ring; 3501 __le16 cmpl_ring;
3260 __le16 seq_id; 3502 __le16 seq_id;
3261 __le16 target_id; 3503 __le16 target_id;
3262 __le64 resp_addr; 3504 __le64 resp_addr;
3263 u8 port_id; 3505 u8 port_id;
3264 u8 unused_0[7]; 3506 u8 unused_0[7];
3265}; 3507};
3266 3508
3267/* Output (16 bytes) */ 3509/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
3268struct hwrm_queue_dscp_qcaps_output { 3510struct hwrm_queue_dscp_qcaps_output {
3269 __le16 error_code; 3511 __le16 error_code;
3270 __le16 req_type; 3512 __le16 req_type;
3271 __le16 seq_id; 3513 __le16 seq_id;
3272 __le16 resp_len; 3514 __le16 resp_len;
3273 u8 num_dscp_bits; 3515 u8 num_dscp_bits;
3274 u8 unused_0; 3516 u8 unused_0;
3275 __le16 max_entries; 3517 __le16 max_entries;
3276 u8 unused_1; 3518 u8 unused_1[3];
3277 u8 unused_2; 3519 u8 valid;
3278 u8 unused_3; 3520};
3279 u8 valid; 3521
3280}; 3522/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
3281
3282/* hwrm_queue_dscp2pri_qcfg */
3283/* Input (32 bytes) */
3284struct hwrm_queue_dscp2pri_qcfg_input { 3523struct hwrm_queue_dscp2pri_qcfg_input {
3285 __le16 req_type; 3524 __le16 req_type;
3286 __le16 cmpl_ring; 3525 __le16 cmpl_ring;
3287 __le16 seq_id; 3526 __le16 seq_id;
3288 __le16 target_id; 3527 __le16 target_id;
3289 __le64 resp_addr; 3528 __le64 resp_addr;
3290 __le64 dest_data_addr; 3529 __le64 dest_data_addr;
3291 u8 port_id; 3530 u8 port_id;
3292 u8 unused_0; 3531 u8 unused_0;
3293 __le16 dest_data_buffer_size; 3532 __le16 dest_data_buffer_size;
3294 __le32 unused_1; 3533 u8 unused_1[4];
3295}; 3534};
3296 3535
3297/* Output (16 bytes) */ 3536/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
3298struct hwrm_queue_dscp2pri_qcfg_output { 3537struct hwrm_queue_dscp2pri_qcfg_output {
3299 __le16 error_code; 3538 __le16 error_code;
3300 __le16 req_type; 3539 __le16 req_type;
3301 __le16 seq_id; 3540 __le16 seq_id;
3302 __le16 resp_len; 3541 __le16 resp_len;
3303 __le16 entry_cnt; 3542 __le16 entry_cnt;
3304 u8 default_pri; 3543 u8 default_pri;
3305 u8 unused_0; 3544 u8 unused_0[4];
3306 u8 unused_1; 3545 u8 valid;
3307 u8 unused_2; 3546};
3308 u8 unused_3; 3547
3309 u8 valid; 3548/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
3310};
3311
3312/* hwrm_queue_dscp2pri_cfg */
3313/* Input (40 bytes) */
3314struct hwrm_queue_dscp2pri_cfg_input { 3549struct hwrm_queue_dscp2pri_cfg_input {
3315 __le16 req_type; 3550 __le16 req_type;
3316 __le16 cmpl_ring; 3551 __le16 cmpl_ring;
3317 __le16 seq_id; 3552 __le16 seq_id;
3318 __le16 target_id; 3553 __le16 target_id;
3319 __le64 resp_addr; 3554 __le64 resp_addr;
3320 __le64 src_data_addr; 3555 __le64 src_data_addr;
3321 __le32 flags; 3556 __le32 flags;
3322 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 3557 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL
3323 __le32 enables; 3558 __le32 enables;
3324 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 3559 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL
3325 u8 port_id; 3560 u8 port_id;
3326 u8 default_pri; 3561 u8 default_pri;
3327 __le16 entry_cnt; 3562 __le16 entry_cnt;
3328 __le32 unused_0; 3563 u8 unused_0[4];
3329}; 3564};
3330 3565
3331/* Output (16 bytes) */ 3566/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
3332struct hwrm_queue_dscp2pri_cfg_output { 3567struct hwrm_queue_dscp2pri_cfg_output {
3333 __le16 error_code; 3568 __le16 error_code;
3334 __le16 req_type; 3569 __le16 req_type;
3335 __le16 seq_id; 3570 __le16 seq_id;
3336 __le16 resp_len; 3571 __le16 resp_len;
3337 __le32 unused_0; 3572 u8 unused_0[7];
3338 u8 unused_1; 3573 u8 valid;
3339 u8 unused_2; 3574};
3340 u8 unused_3; 3575
3341 u8 valid; 3576/* hwrm_vnic_alloc_input (size:192b/24B) */
3342};
3343
3344/* hwrm_vnic_alloc */
3345/* Input (24 bytes) */
3346struct hwrm_vnic_alloc_input { 3577struct hwrm_vnic_alloc_input {
3347 __le16 req_type; 3578 __le16 req_type;
3348 __le16 cmpl_ring; 3579 __le16 cmpl_ring;
3349 __le16 seq_id; 3580 __le16 seq_id;
3350 __le16 target_id; 3581 __le16 target_id;
3351 __le64 resp_addr; 3582 __le64 resp_addr;
3352 __le32 flags; 3583 __le32 flags;
3353 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 3584 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
3354 __le32 unused_0; 3585 u8 unused_0[4];
3355}; 3586};
3356 3587
3357/* Output (16 bytes) */ 3588/* hwrm_vnic_alloc_output (size:128b/16B) */
3358struct hwrm_vnic_alloc_output { 3589struct hwrm_vnic_alloc_output {
3359 __le16 error_code; 3590 __le16 error_code;
3360 __le16 req_type; 3591 __le16 req_type;
3361 __le16 seq_id; 3592 __le16 seq_id;
3362 __le16 resp_len; 3593 __le16 resp_len;
3363 __le32 vnic_id; 3594 __le32 vnic_id;
3364 u8 unused_0; 3595 u8 unused_0[3];
3365 u8 unused_1; 3596 u8 valid;
3366 u8 unused_2; 3597};
3367 u8 valid; 3598
3368}; 3599/* hwrm_vnic_free_input (size:192b/24B) */
3369
3370/* hwrm_vnic_free */
3371/* Input (24 bytes) */
3372struct hwrm_vnic_free_input { 3600struct hwrm_vnic_free_input {
3373 __le16 req_type; 3601 __le16 req_type;
3374 __le16 cmpl_ring; 3602 __le16 cmpl_ring;
3375 __le16 seq_id; 3603 __le16 seq_id;
3376 __le16 target_id; 3604 __le16 target_id;
3377 __le64 resp_addr; 3605 __le64 resp_addr;
3378 __le32 vnic_id; 3606 __le32 vnic_id;
3379 __le32 unused_0; 3607 u8 unused_0[4];
3380}; 3608};
3381 3609
3382/* Output (16 bytes) */ 3610/* hwrm_vnic_free_output (size:128b/16B) */
3383struct hwrm_vnic_free_output { 3611struct hwrm_vnic_free_output {
3384 __le16 error_code; 3612 __le16 error_code;
3385 __le16 req_type; 3613 __le16 req_type;
3386 __le16 seq_id; 3614 __le16 seq_id;
3387 __le16 resp_len; 3615 __le16 resp_len;
3388 __le32 unused_0; 3616 u8 unused_0[7];
3389 u8 unused_1; 3617 u8 valid;
3390 u8 unused_2; 3618};
3391 u8 unused_3; 3619
3392 u8 valid; 3620/* hwrm_vnic_cfg_input (size:320b/40B) */
3393};
3394
3395/* hwrm_vnic_cfg */
3396/* Input (40 bytes) */
3397struct hwrm_vnic_cfg_input { 3621struct hwrm_vnic_cfg_input {
3398 __le16 req_type; 3622 __le16 req_type;
3399 __le16 cmpl_ring; 3623 __le16 cmpl_ring;
3400 __le16 seq_id; 3624 __le16 seq_id;
3401 __le16 target_id; 3625 __le16 target_id;
3402 __le64 resp_addr; 3626 __le64 resp_addr;
3403 __le32 flags; 3627 __le32 flags;
3404 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 3628 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
3405 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 3629 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
3406 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 3630 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
3407 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 3631 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
3408 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 3632 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
3409 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 3633 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL
3410 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 3634 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL
3411 __le32 enables; 3635 __le32 enables;
3412 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 3636 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
3413 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 3637 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
3414 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 3638 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
3415 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 3639 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
3416 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 3640 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
3417 __le16 vnic_id; 3641 __le16 vnic_id;
3418 __le16 dflt_ring_grp; 3642 __le16 dflt_ring_grp;
3419 __le16 rss_rule; 3643 __le16 rss_rule;
3420 __le16 cos_rule; 3644 __le16 cos_rule;
3421 __le16 lb_rule; 3645 __le16 lb_rule;
3422 __le16 mru; 3646 __le16 mru;
3423 __le32 unused_0; 3647 u8 unused_0[4];
3424}; 3648};
3425 3649
3426/* Output (16 bytes) */ 3650/* hwrm_vnic_cfg_output (size:128b/16B) */
3427struct hwrm_vnic_cfg_output { 3651struct hwrm_vnic_cfg_output {
3428 __le16 error_code; 3652 __le16 error_code;
3429 __le16 req_type; 3653 __le16 req_type;
3430 __le16 seq_id; 3654 __le16 seq_id;
3431 __le16 resp_len; 3655 __le16 resp_len;
3432 __le32 unused_0; 3656 u8 unused_0[7];
3433 u8 unused_1; 3657 u8 valid;
3434 u8 unused_2; 3658};
3435 u8 unused_3; 3659
3436 u8 valid; 3660/* hwrm_vnic_qcaps_input (size:192b/24B) */
3437};
3438
3439/* hwrm_vnic_qcaps */
3440/* Input (24 bytes) */
3441struct hwrm_vnic_qcaps_input { 3661struct hwrm_vnic_qcaps_input {
3442 __le16 req_type; 3662 __le16 req_type;
3443 __le16 cmpl_ring; 3663 __le16 cmpl_ring;
3444 __le16 seq_id; 3664 __le16 seq_id;
3445 __le16 target_id; 3665 __le16 target_id;
3446 __le64 resp_addr; 3666 __le64 resp_addr;
3447 __le32 enables; 3667 __le32 enables;
3448 __le32 unused_0; 3668 u8 unused_0[4];
3449}; 3669};
3450 3670
3451/* Output (24 bytes) */ 3671/* hwrm_vnic_qcaps_output (size:192b/24B) */
3452struct hwrm_vnic_qcaps_output { 3672struct hwrm_vnic_qcaps_output {
3453 __le16 error_code; 3673 __le16 error_code;
3454 __le16 req_type; 3674 __le16 req_type;
3455 __le16 seq_id; 3675 __le16 seq_id;
3456 __le16 resp_len; 3676 __le16 resp_len;
3457 __le16 mru; 3677 __le16 mru;
3458 u8 unused_0; 3678 u8 unused_0[2];
3459 u8 unused_1; 3679 __le32 flags;
3460 __le32 flags; 3680 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL
3461 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 3681 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL
3462 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 3682 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL
3463 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 3683 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL
3464 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 3684 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL
3465 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 3685 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
3466 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 3686 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
3467 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRROING_CAPABLE_VNIC_CAP 0x40UL 3687 u8 unused_1[7];
3468 __le32 unused_2; 3688 u8 valid;
3469 u8 unused_3; 3689};
3470 u8 unused_4; 3690
3471 u8 unused_5; 3691/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
3472 u8 valid;
3473};
3474
3475/* hwrm_vnic_tpa_cfg */
3476/* Input (40 bytes) */
3477struct hwrm_vnic_tpa_cfg_input { 3692struct hwrm_vnic_tpa_cfg_input {
3478 __le16 req_type; 3693 __le16 req_type;
3479 __le16 cmpl_ring; 3694 __le16 cmpl_ring;
3480 __le16 seq_id; 3695 __le16 seq_id;
3481 __le16 target_id; 3696 __le16 target_id;
3482 __le64 resp_addr; 3697 __le64 resp_addr;
3483 __le32 flags; 3698 __le32 flags;
3484 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 3699 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
3485 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 3700 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
3486 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 3701 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
3487 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 3702 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
3488 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 3703 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
3489 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 3704 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
3490 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 3705 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
3491 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 3706 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
3492 __le32 enables; 3707 __le32 enables;
3493 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 3708 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
3494 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 3709 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
3495 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 3710 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
3496 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 3711 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
3497 __le16 vnic_id; 3712 __le16 vnic_id;
3498 __le16 max_agg_segs; 3713 __le16 max_agg_segs;
3499 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 3714 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL
3500 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 3715 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL
3501 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 3716 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL
3502 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 3717 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL
3503 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 3718 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
3504 __le16 max_aggs; 3719 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
3505 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 3720 __le16 max_aggs;
3506 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 3721 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL
3507 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 3722 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL
3508 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 3723 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL
3509 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 3724 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL
3510 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 3725 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL
3511 u8 unused_0; 3726 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
3512 u8 unused_1; 3727 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
3513 __le32 max_agg_timer; 3728 u8 unused_0[2];
3514 __le32 min_agg_len; 3729 __le32 max_agg_timer;
3515}; 3730 __le32 min_agg_len;
3516 3731};
3517/* Output (16 bytes) */ 3732
3733/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
3518struct hwrm_vnic_tpa_cfg_output { 3734struct hwrm_vnic_tpa_cfg_output {
3519 __le16 error_code; 3735 __le16 error_code;
3520 __le16 req_type; 3736 __le16 req_type;
3521 __le16 seq_id; 3737 __le16 seq_id;
3522 __le16 resp_len; 3738 __le16 resp_len;
3523 __le32 unused_0; 3739 u8 unused_0[7];
3524 u8 unused_1; 3740 u8 valid;
3525 u8 unused_2; 3741};
3526 u8 unused_3; 3742
3527 u8 valid; 3743/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
3528}; 3744struct hwrm_vnic_tpa_qcfg_input {
3529 3745 __le16 req_type;
3530/* hwrm_vnic_rss_cfg */ 3746 __le16 cmpl_ring;
3531/* Input (48 bytes) */ 3747 __le16 seq_id;
3748 __le16 target_id;
3749 __le64 resp_addr;
3750 __le16 vnic_id;
3751 u8 unused_0[6];
3752};
3753
3754/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
3755struct hwrm_vnic_tpa_qcfg_output {
3756 __le16 error_code;
3757 __le16 req_type;
3758 __le16 seq_id;
3759 __le16 resp_len;
3760 __le32 flags;
3761 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL
3762 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL
3763 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL
3764 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL
3765 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL
3766 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
3767 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL
3768 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL
3769 __le16 max_agg_segs;
3770 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL
3771 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL
3772 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL
3773 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL
3774 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
3775 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
3776 __le16 max_aggs;
3777 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL
3778 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL
3779 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL
3780 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL
3781 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL
3782 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
3783 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
3784 __le32 max_agg_timer;
3785 __le32 min_agg_len;
3786 u8 unused_0[7];
3787 u8 valid;
3788};
3789
3790/* hwrm_vnic_rss_cfg_input (size:384b/48B) */
3532struct hwrm_vnic_rss_cfg_input { 3791struct hwrm_vnic_rss_cfg_input {
3533 __le16 req_type; 3792 __le16 req_type;
3534 __le16 cmpl_ring; 3793 __le16 cmpl_ring;
3535 __le16 seq_id; 3794 __le16 seq_id;
3536 __le16 target_id; 3795 __le16 target_id;
3537 __le64 resp_addr; 3796 __le64 resp_addr;
3538 __le32 hash_type; 3797 __le32 hash_type;
3539 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 3798 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
3540 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 3799 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
3541 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 3800 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
3542 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 3801 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
3543 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 3802 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
3544 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 3803 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
3545 __le32 unused_0; 3804 u8 unused_0[4];
3546 __le64 ring_grp_tbl_addr; 3805 __le64 ring_grp_tbl_addr;
3547 __le64 hash_key_tbl_addr; 3806 __le64 hash_key_tbl_addr;
3548 __le16 rss_ctx_idx; 3807 __le16 rss_ctx_idx;
3549 __le16 unused_1[3]; 3808 u8 unused_1[6];
3550}; 3809};
3551 3810
3552/* Output (16 bytes) */ 3811/* hwrm_vnic_rss_cfg_output (size:128b/16B) */
3553struct hwrm_vnic_rss_cfg_output { 3812struct hwrm_vnic_rss_cfg_output {
3554 __le16 error_code; 3813 __le16 error_code;
3555 __le16 req_type; 3814 __le16 req_type;
3556 __le16 seq_id; 3815 __le16 seq_id;
3557 __le16 resp_len; 3816 __le16 resp_len;
3558 __le32 unused_0; 3817 u8 unused_0[7];
3559 u8 unused_1; 3818 u8 valid;
3560 u8 unused_2; 3819};
3561 u8 unused_3; 3820
3562 u8 valid; 3821/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
3563};
3564
3565/* hwrm_vnic_plcmodes_cfg */
3566/* Input (40 bytes) */
3567struct hwrm_vnic_plcmodes_cfg_input { 3822struct hwrm_vnic_plcmodes_cfg_input {
3568 __le16 req_type; 3823 __le16 req_type;
3569 __le16 cmpl_ring; 3824 __le16 cmpl_ring;
3570 __le16 seq_id; 3825 __le16 seq_id;
3571 __le16 target_id; 3826 __le16 target_id;
3572 __le64 resp_addr; 3827 __le64 resp_addr;
3573 __le32 flags; 3828 __le32 flags;
3574 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 3829 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
3575 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 3830 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
3576 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 3831 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
3577 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 3832 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
3578 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 3833 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
3579 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 3834 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
3580 __le32 enables; 3835 __le32 enables;
3581 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 3836 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
3582 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 3837 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
3583 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 3838 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
3584 __le32 vnic_id; 3839 __le32 vnic_id;
3585 __le16 jumbo_thresh; 3840 __le16 jumbo_thresh;
3586 __le16 hds_offset; 3841 __le16 hds_offset;
3587 __le16 hds_threshold; 3842 __le16 hds_threshold;
3588 __le16 unused_0[3]; 3843 u8 unused_0[6];
3589}; 3844};
3590 3845
3591/* Output (16 bytes) */ 3846/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
3592struct hwrm_vnic_plcmodes_cfg_output { 3847struct hwrm_vnic_plcmodes_cfg_output {
3593 __le16 error_code; 3848 __le16 error_code;
3594 __le16 req_type; 3849 __le16 req_type;
3595 __le16 seq_id; 3850 __le16 seq_id;
3596 __le16 resp_len; 3851 __le16 resp_len;
3597 __le32 unused_0; 3852 u8 unused_0[7];
3598 u8 unused_1; 3853 u8 valid;
3599 u8 unused_2; 3854};
3600 u8 unused_3; 3855
3601 u8 valid; 3856/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
3602};
3603
3604/* hwrm_vnic_rss_cos_lb_ctx_alloc */
3605/* Input (16 bytes) */
3606struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 3857struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
3607 __le16 req_type; 3858 __le16 req_type;
3608 __le16 cmpl_ring; 3859 __le16 cmpl_ring;
3609 __le16 seq_id; 3860 __le16 seq_id;
3610 __le16 target_id; 3861 __le16 target_id;
3611 __le64 resp_addr; 3862 __le64 resp_addr;
3612}; 3863};
3613 3864
3614/* Output (16 bytes) */ 3865/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
3615struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 3866struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
3616 __le16 error_code; 3867 __le16 error_code;
3617 __le16 req_type; 3868 __le16 req_type;
3618 __le16 seq_id; 3869 __le16 seq_id;
3619 __le16 resp_len; 3870 __le16 resp_len;
3620 __le16 rss_cos_lb_ctx_id; 3871 __le16 rss_cos_lb_ctx_id;
3621 u8 unused_0; 3872 u8 unused_0[5];
3622 u8 unused_1; 3873 u8 valid;
3623 u8 unused_2; 3874};
3624 u8 unused_3; 3875
3625 u8 unused_4; 3876/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
3626 u8 valid;
3627};
3628
3629/* hwrm_vnic_rss_cos_lb_ctx_free */
3630/* Input (24 bytes) */
3631struct hwrm_vnic_rss_cos_lb_ctx_free_input { 3877struct hwrm_vnic_rss_cos_lb_ctx_free_input {
3632 __le16 req_type; 3878 __le16 req_type;
3633 __le16 cmpl_ring; 3879 __le16 cmpl_ring;
3634 __le16 seq_id; 3880 __le16 seq_id;
3635 __le16 target_id; 3881 __le16 target_id;
3636 __le64 resp_addr; 3882 __le64 resp_addr;
3637 __le16 rss_cos_lb_ctx_id; 3883 __le16 rss_cos_lb_ctx_id;
3638 __le16 unused_0[3]; 3884 u8 unused_0[6];
3639}; 3885};
3640 3886
3641/* Output (16 bytes) */ 3887/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
3642struct hwrm_vnic_rss_cos_lb_ctx_free_output { 3888struct hwrm_vnic_rss_cos_lb_ctx_free_output {
3643 __le16 error_code; 3889 __le16 error_code;
3644 __le16 req_type; 3890 __le16 req_type;
3645 __le16 seq_id; 3891 __le16 seq_id;
3646 __le16 resp_len; 3892 __le16 resp_len;
3647 __le32 unused_0; 3893 u8 unused_0[7];
3648 u8 unused_1; 3894 u8 valid;
3649 u8 unused_2; 3895};
3650 u8 unused_3; 3896
3651 u8 valid; 3897/* hwrm_ring_alloc_input (size:640b/80B) */
3652};
3653
3654/* hwrm_ring_alloc */
3655/* Input (80 bytes) */
3656struct hwrm_ring_alloc_input { 3898struct hwrm_ring_alloc_input {
3657 __le16 req_type; 3899 __le16 req_type;
3658 __le16 cmpl_ring; 3900 __le16 cmpl_ring;
3659 __le16 seq_id; 3901 __le16 seq_id;
3660 __le16 target_id; 3902 __le16 target_id;
3661 __le64 resp_addr; 3903 __le64 resp_addr;
3662 __le32 enables; 3904 __le32 enables;
3663 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL 3905 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
3664 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 3906 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
3665 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL 3907 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
3666 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 3908 u8 ring_type;
3667 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL 3909 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
3668 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 3910 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
3669 u8 ring_type; 3911 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
3670 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 3912 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
3671 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 3913 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL
3672 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 3914 u8 unused_0[3];
3673 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3915 __le64 page_tbl_addr;
3674 u8 unused_0; 3916 __le32 fbo;
3675 __le16 unused_1; 3917 u8 page_size;
3676 __le64 page_tbl_addr; 3918 u8 page_tbl_depth;
3677 __le32 fbo; 3919 u8 unused_1[2];
3678 u8 page_size; 3920 __le32 length;
3679 u8 page_tbl_depth; 3921 __le16 logical_id;
3680 u8 unused_2; 3922 __le16 cmpl_ring_id;
3681 u8 unused_3; 3923 __le16 queue_id;
3682 __le32 length; 3924 u8 unused_2[2];
3683 __le16 logical_id; 3925 __le32 reserved1;
3684 __le16 cmpl_ring_id; 3926 __le16 ring_arb_cfg;
3685 __le16 queue_id; 3927 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL
3686 u8 unused_4; 3928 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0
3687 u8 unused_5; 3929 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL
3688 __le32 reserved1; 3930 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL
3689 __le16 ring_arb_cfg; 3931 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
3690 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 3932 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL
3691 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 3933 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4
3692 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP (0x1UL << 0) 3934 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
3693 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ (0x2UL << 0) 3935 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
3694 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 3936 __le16 unused_3;
3695 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 3937 __le32 reserved3;
3696 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 3938 __le32 stat_ctx_id;
3697 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 3939 __le32 reserved4;
3698 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 3940 __le32 max_bw;
3699 u8 unused_6; 3941 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
3700 u8 unused_7; 3942 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0
3701 __le32 reserved3; 3943 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL
3702 __le32 stat_ctx_id; 3944 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
3703 __le32 reserved4; 3945 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
3704 __le32 max_bw; 3946 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
3705 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3947 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3706 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 3948 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
3707 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 3949 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3708 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 3950 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3709 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 3951 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3710 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 3952 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3711 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3712 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
3713 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3714 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3715 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
3716 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
3717 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3953 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
3718 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3954 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
3719 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 3955 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
3720 u8 int_mode; 3956 u8 int_mode;
3721 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 3957 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
3722 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 3958 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL
3723 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 3959 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL
3724 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 3960 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
3725 u8 unused_8[3]; 3961 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL
3962 u8 unused_4[3];
3726}; 3963};
3727 3964
3728/* Output (16 bytes) */ 3965/* hwrm_ring_alloc_output (size:128b/16B) */
3729struct hwrm_ring_alloc_output { 3966struct hwrm_ring_alloc_output {
3730 __le16 error_code; 3967 __le16 error_code;
3731 __le16 req_type; 3968 __le16 req_type;
3732 __le16 seq_id; 3969 __le16 seq_id;
3733 __le16 resp_len; 3970 __le16 resp_len;
3734 __le16 ring_id; 3971 __le16 ring_id;
3735 __le16 logical_ring_id; 3972 __le16 logical_ring_id;
3736 u8 unused_0; 3973 u8 unused_0[3];
3737 u8 unused_1; 3974 u8 valid;
3738 u8 unused_2; 3975};
3739 u8 valid; 3976
3740}; 3977/* hwrm_ring_free_input (size:192b/24B) */
3741
3742/* hwrm_ring_free */
3743/* Input (24 bytes) */
3744struct hwrm_ring_free_input { 3978struct hwrm_ring_free_input {
3745 __le16 req_type; 3979 __le16 req_type;
3746 __le16 cmpl_ring; 3980 __le16 cmpl_ring;
3747 __le16 seq_id; 3981 __le16 seq_id;
3748 __le16 target_id; 3982 __le16 target_id;
3749 __le64 resp_addr; 3983 __le64 resp_addr;
3750 u8 ring_type; 3984 u8 ring_type;
3751 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 3985 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL
3752 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 3986 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL
3753 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 3987 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL
3754 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3988 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
3755 u8 unused_0; 3989 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_ROCE_CMPL
3756 __le16 ring_id; 3990 u8 unused_0;
3757 __le32 unused_1; 3991 __le16 ring_id;
3758}; 3992 u8 unused_1[4];
3759 3993};
3760/* Output (16 bytes) */ 3994
3995/* hwrm_ring_free_output (size:128b/16B) */
3761struct hwrm_ring_free_output { 3996struct hwrm_ring_free_output {
3762 __le16 error_code; 3997 __le16 error_code;
3763 __le16 req_type; 3998 __le16 req_type;
3764 __le16 seq_id; 3999 __le16 seq_id;
3765 __le16 resp_len; 4000 __le16 resp_len;
3766 __le32 unused_0; 4001 u8 unused_0[7];
3767 u8 unused_1; 4002 u8 valid;
3768 u8 unused_2; 4003};
3769 u8 unused_3; 4004
3770 u8 valid; 4005/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
3771};
3772
3773/* hwrm_ring_cmpl_ring_qaggint_params */
3774/* Input (24 bytes) */
3775struct hwrm_ring_cmpl_ring_qaggint_params_input { 4006struct hwrm_ring_cmpl_ring_qaggint_params_input {
3776 __le16 req_type; 4007 __le16 req_type;
3777 __le16 cmpl_ring; 4008 __le16 cmpl_ring;
3778 __le16 seq_id; 4009 __le16 seq_id;
3779 __le16 target_id; 4010 __le16 target_id;
3780 __le64 resp_addr; 4011 __le64 resp_addr;
3781 __le16 ring_id; 4012 __le16 ring_id;
3782 __le16 unused_0[3]; 4013 u8 unused_0[6];
3783}; 4014};
3784 4015
3785/* Output (32 bytes) */ 4016/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
3786struct hwrm_ring_cmpl_ring_qaggint_params_output { 4017struct hwrm_ring_cmpl_ring_qaggint_params_output {
3787 __le16 error_code; 4018 __le16 error_code;
3788 __le16 req_type; 4019 __le16 req_type;
3789 __le16 seq_id; 4020 __le16 seq_id;
3790 __le16 resp_len; 4021 __le16 resp_len;
3791 __le16 flags; 4022 __le16 flags;
3792 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 4023 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
3793 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 4024 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
3794 __le16 num_cmpl_dma_aggr; 4025 __le16 num_cmpl_dma_aggr;
3795 __le16 num_cmpl_dma_aggr_during_int; 4026 __le16 num_cmpl_dma_aggr_during_int;
3796 __le16 cmpl_aggr_dma_tmr; 4027 __le16 cmpl_aggr_dma_tmr;
3797 __le16 cmpl_aggr_dma_tmr_during_int; 4028 __le16 cmpl_aggr_dma_tmr_during_int;
3798 __le16 int_lat_tmr_min; 4029 __le16 int_lat_tmr_min;
3799 __le16 int_lat_tmr_max; 4030 __le16 int_lat_tmr_max;
3800 __le16 num_cmpl_aggr_int; 4031 __le16 num_cmpl_aggr_int;
3801 __le32 unused_0; 4032 u8 unused_0[7];
3802 u8 unused_1; 4033 u8 valid;
3803 u8 unused_2; 4034};
3804 u8 unused_3; 4035
3805 u8 valid; 4036/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
3806};
3807
3808/* hwrm_ring_cmpl_ring_cfg_aggint_params */
3809/* Input (40 bytes) */
3810struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 4037struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
3811 __le16 req_type; 4038 __le16 req_type;
3812 __le16 cmpl_ring; 4039 __le16 cmpl_ring;
3813 __le16 seq_id; 4040 __le16 seq_id;
3814 __le16 target_id; 4041 __le16 target_id;
3815 __le64 resp_addr; 4042 __le64 resp_addr;
3816 __le16 ring_id; 4043 __le16 ring_id;
3817 __le16 flags; 4044 __le16 flags;
3818 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 4045 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
3819 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 4046 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
3820 __le16 num_cmpl_dma_aggr; 4047 __le16 num_cmpl_dma_aggr;
3821 __le16 num_cmpl_dma_aggr_during_int; 4048 __le16 num_cmpl_dma_aggr_during_int;
3822 __le16 cmpl_aggr_dma_tmr; 4049 __le16 cmpl_aggr_dma_tmr;
3823 __le16 cmpl_aggr_dma_tmr_during_int; 4050 __le16 cmpl_aggr_dma_tmr_during_int;
3824 __le16 int_lat_tmr_min; 4051 __le16 int_lat_tmr_min;
3825 __le16 int_lat_tmr_max; 4052 __le16 int_lat_tmr_max;
3826 __le16 num_cmpl_aggr_int; 4053 __le16 num_cmpl_aggr_int;
3827 __le16 unused_0[3]; 4054 u8 unused_0[6];
3828}; 4055};
3829 4056
3830/* Output (16 bytes) */ 4057/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
3831struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 4058struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
3832 __le16 error_code; 4059 __le16 error_code;
3833 __le16 req_type; 4060 __le16 req_type;
3834 __le16 seq_id; 4061 __le16 seq_id;
3835 __le16 resp_len; 4062 __le16 resp_len;
3836 __le32 unused_0; 4063 u8 unused_0[7];
3837 u8 unused_1; 4064 u8 valid;
3838 u8 unused_2; 4065};
3839 u8 unused_3; 4066
3840 u8 valid; 4067/* hwrm_ring_reset_input (size:192b/24B) */
3841};
3842
3843/* hwrm_ring_reset */
3844/* Input (24 bytes) */
3845struct hwrm_ring_reset_input { 4068struct hwrm_ring_reset_input {
3846 __le16 req_type; 4069 __le16 req_type;
3847 __le16 cmpl_ring; 4070 __le16 cmpl_ring;
3848 __le16 seq_id; 4071 __le16 seq_id;
3849 __le16 target_id; 4072 __le16 target_id;
3850 __le64 resp_addr; 4073 __le64 resp_addr;
3851 u8 ring_type; 4074 u8 ring_type;
3852 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 4075 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL
3853 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 4076 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL
3854 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 4077 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL
3855 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 4078 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
3856 u8 unused_0; 4079 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_ROCE_CMPL
3857 __le16 ring_id; 4080 u8 unused_0;
3858 __le32 unused_1; 4081 __le16 ring_id;
3859}; 4082 u8 unused_1[4];
3860 4083};
3861/* Output (16 bytes) */ 4084
4085/* hwrm_ring_reset_output (size:128b/16B) */
3862struct hwrm_ring_reset_output { 4086struct hwrm_ring_reset_output {
3863 __le16 error_code; 4087 __le16 error_code;
3864 __le16 req_type; 4088 __le16 req_type;
3865 __le16 seq_id; 4089 __le16 seq_id;
3866 __le16 resp_len; 4090 __le16 resp_len;
3867 __le32 unused_0; 4091 u8 unused_0[7];
3868 u8 unused_1; 4092 u8 valid;
3869 u8 unused_2; 4093};
3870 u8 unused_3; 4094
3871 u8 valid; 4095/* hwrm_ring_grp_alloc_input (size:192b/24B) */
3872};
3873
3874/* hwrm_ring_grp_alloc */
3875/* Input (24 bytes) */
3876struct hwrm_ring_grp_alloc_input { 4096struct hwrm_ring_grp_alloc_input {
3877 __le16 req_type; 4097 __le16 req_type;
3878 __le16 cmpl_ring; 4098 __le16 cmpl_ring;
3879 __le16 seq_id; 4099 __le16 seq_id;
3880 __le16 target_id; 4100 __le16 target_id;
3881 __le64 resp_addr; 4101 __le64 resp_addr;
3882 __le16 cr; 4102 __le16 cr;
3883 __le16 rr; 4103 __le16 rr;
3884 __le16 ar; 4104 __le16 ar;
3885 __le16 sc; 4105 __le16 sc;
3886}; 4106};
3887 4107
3888/* Output (16 bytes) */ 4108/* hwrm_ring_grp_alloc_output (size:128b/16B) */
3889struct hwrm_ring_grp_alloc_output { 4109struct hwrm_ring_grp_alloc_output {
3890 __le16 error_code; 4110 __le16 error_code;
3891 __le16 req_type; 4111 __le16 req_type;
3892 __le16 seq_id; 4112 __le16 seq_id;
3893 __le16 resp_len; 4113 __le16 resp_len;
3894 __le32 ring_group_id; 4114 __le32 ring_group_id;
3895 u8 unused_0; 4115 u8 unused_0[3];
3896 u8 unused_1; 4116 u8 valid;
3897 u8 unused_2; 4117};
3898 u8 valid; 4118
3899}; 4119/* hwrm_ring_grp_free_input (size:192b/24B) */
3900
3901/* hwrm_ring_grp_free */
3902/* Input (24 bytes) */
3903struct hwrm_ring_grp_free_input { 4120struct hwrm_ring_grp_free_input {
3904 __le16 req_type; 4121 __le16 req_type;
3905 __le16 cmpl_ring; 4122 __le16 cmpl_ring;
3906 __le16 seq_id; 4123 __le16 seq_id;
3907 __le16 target_id; 4124 __le16 target_id;
3908 __le64 resp_addr; 4125 __le64 resp_addr;
3909 __le32 ring_group_id; 4126 __le32 ring_group_id;
3910 __le32 unused_0; 4127 u8 unused_0[4];
3911}; 4128};
3912 4129
3913/* Output (16 bytes) */ 4130/* hwrm_ring_grp_free_output (size:128b/16B) */
3914struct hwrm_ring_grp_free_output { 4131struct hwrm_ring_grp_free_output {
3915 __le16 error_code; 4132 __le16 error_code;
3916 __le16 req_type; 4133 __le16 req_type;
3917 __le16 seq_id; 4134 __le16 seq_id;
3918 __le16 resp_len; 4135 __le16 resp_len;
3919 __le32 unused_0; 4136 u8 unused_0[7];
3920 u8 unused_1; 4137 u8 valid;
3921 u8 unused_2; 4138};
3922 u8 unused_3; 4139
3923 u8 valid; 4140/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
3924};
3925
3926/* hwrm_cfa_l2_filter_alloc */
3927/* Input (96 bytes) */
3928struct hwrm_cfa_l2_filter_alloc_input { 4141struct hwrm_cfa_l2_filter_alloc_input {
3929 __le16 req_type; 4142 __le16 req_type;
3930 __le16 cmpl_ring; 4143 __le16 cmpl_ring;
3931 __le16 seq_id; 4144 __le16 seq_id;
3932 __le16 target_id; 4145 __le16 target_id;
3933 __le64 resp_addr; 4146 __le64 resp_addr;
3934 __le32 flags; 4147 __le32 flags;
3935 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 4148 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
3936 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 4149 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
3937 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 4150 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
3938 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 4151 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
3939 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 4152 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
3940 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 4153 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
3941 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 4154 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
3942 __le32 enables; 4155 __le32 enables;
3943 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 4156 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
3944 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 4157 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
3945 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 4158 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
3946 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 4159 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
3947 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 4160 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
3948 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 4161 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
3949 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 4162 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
3950 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 4163 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
3951 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 4164 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
3952 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 4165 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
3953 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 4166 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
3954 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 4167 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
3955 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 4168 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
3956 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 4169 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
3957 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 4170 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
3958 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 4171 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
3959 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 4172 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
3960 u8 l2_addr[6]; 4173 u8 l2_addr[6];
3961 u8 unused_0; 4174 u8 unused_0[2];
3962 u8 unused_1; 4175 u8 l2_addr_mask[6];
3963 u8 l2_addr_mask[6]; 4176 __le16 l2_ovlan;
3964 __le16 l2_ovlan; 4177 __le16 l2_ovlan_mask;
3965 __le16 l2_ovlan_mask; 4178 __le16 l2_ivlan;
3966 __le16 l2_ivlan; 4179 __le16 l2_ivlan_mask;
3967 __le16 l2_ivlan_mask; 4180 u8 unused_1[2];
3968 u8 unused_2; 4181 u8 t_l2_addr[6];
3969 u8 unused_3; 4182 u8 unused_2[2];
3970 u8 t_l2_addr[6]; 4183 u8 t_l2_addr_mask[6];
3971 u8 unused_4; 4184 __le16 t_l2_ovlan;
3972 u8 unused_5; 4185 __le16 t_l2_ovlan_mask;
3973 u8 t_l2_addr_mask[6]; 4186 __le16 t_l2_ivlan;
3974 __le16 t_l2_ovlan; 4187 __le16 t_l2_ivlan_mask;
3975 __le16 t_l2_ovlan_mask; 4188 u8 src_type;
3976 __le16 t_l2_ivlan; 4189 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
3977 __le16 t_l2_ivlan_mask; 4190 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL
3978 u8 src_type; 4191 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL
3979 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 4192 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL
3980 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 4193 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL
3981 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 4194 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL
3982 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 4195 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL
3983 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 4196 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL
3984 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 4197 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
3985 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 4198 u8 unused_3;
3986 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 4199 __le32 src_id;
3987 u8 unused_6; 4200 u8 tunnel_type;
3988 __le32 src_id; 4201 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
3989 u8 tunnel_type; 4202 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
3990 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4203 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
3991 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4204 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
3992 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4205 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
3993 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4206 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
3994 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4207 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
3995 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4208 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
3996 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4209 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
3997 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4210 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
3998 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4211 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
3999 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4212 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
4000 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4213 u8 unused_4;
4001 u8 unused_7; 4214 __le16 dst_id;
4002 __le16 dst_id; 4215 __le16 mirror_vnic_id;
4003 __le16 mirror_vnic_id; 4216 u8 pri_hint;
4004 u8 pri_hint; 4217 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
4005 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4218 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
4006 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 4219 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
4007 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 4220 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL
4008 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 4221 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL
4009 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 4222 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
4010 u8 unused_8; 4223 u8 unused_5;
4011 __le32 unused_9; 4224 __le32 unused_6;
4012 __le64 l2_filter_id_hint; 4225 __le64 l2_filter_id_hint;
4013}; 4226};
4014 4227
4015/* Output (24 bytes) */ 4228/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
4016struct hwrm_cfa_l2_filter_alloc_output { 4229struct hwrm_cfa_l2_filter_alloc_output {
4017 __le16 error_code; 4230 __le16 error_code;
4018 __le16 req_type; 4231 __le16 req_type;
4019 __le16 seq_id; 4232 __le16 seq_id;
4020 __le16 resp_len; 4233 __le16 resp_len;
4021 __le64 l2_filter_id; 4234 __le64 l2_filter_id;
4022 __le32 flow_id; 4235 __le32 flow_id;
4023 u8 unused_0; 4236 u8 unused_0[3];
4024 u8 unused_1; 4237 u8 valid;
4025 u8 unused_2; 4238};
4026 u8 valid; 4239
4027}; 4240/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
4028
4029/* hwrm_cfa_l2_filter_free */
4030/* Input (24 bytes) */
4031struct hwrm_cfa_l2_filter_free_input { 4241struct hwrm_cfa_l2_filter_free_input {
4032 __le16 req_type; 4242 __le16 req_type;
4033 __le16 cmpl_ring; 4243 __le16 cmpl_ring;
4034 __le16 seq_id; 4244 __le16 seq_id;
4035 __le16 target_id; 4245 __le16 target_id;
4036 __le64 resp_addr; 4246 __le64 resp_addr;
4037 __le64 l2_filter_id; 4247 __le64 l2_filter_id;
4038}; 4248};
4039 4249
4040/* Output (16 bytes) */ 4250/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
4041struct hwrm_cfa_l2_filter_free_output { 4251struct hwrm_cfa_l2_filter_free_output {
4042 __le16 error_code; 4252 __le16 error_code;
4043 __le16 req_type; 4253 __le16 req_type;
4044 __le16 seq_id; 4254 __le16 seq_id;
4045 __le16 resp_len; 4255 __le16 resp_len;
4046 __le32 unused_0; 4256 u8 unused_0[7];
4047 u8 unused_1; 4257 u8 valid;
4048 u8 unused_2; 4258};
4049 u8 unused_3; 4259
4050 u8 valid; 4260/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
4051};
4052
4053/* hwrm_cfa_l2_filter_cfg */
4054/* Input (40 bytes) */
4055struct hwrm_cfa_l2_filter_cfg_input { 4261struct hwrm_cfa_l2_filter_cfg_input {
4056 __le16 req_type; 4262 __le16 req_type;
4057 __le16 cmpl_ring; 4263 __le16 cmpl_ring;
4058 __le16 seq_id; 4264 __le16 seq_id;
4059 __le16 target_id; 4265 __le16 target_id;
4060 __le64 resp_addr; 4266 __le64 resp_addr;
4061 __le32 flags; 4267 __le32 flags;
4062 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 4268 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
4063 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 4269 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
4064 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 4270 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
4065 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 4271 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
4066 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 4272 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
4067 __le32 enables; 4273 __le32 enables;
4068 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 4274 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
4069 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4275 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
4070 __le64 l2_filter_id; 4276 __le64 l2_filter_id;
4071 __le32 dst_id; 4277 __le32 dst_id;
4072 __le32 new_mirror_vnic_id; 4278 __le32 new_mirror_vnic_id;
4073}; 4279};
4074 4280
4075/* Output (16 bytes) */ 4281/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
4076struct hwrm_cfa_l2_filter_cfg_output { 4282struct hwrm_cfa_l2_filter_cfg_output {
4077 __le16 error_code; 4283 __le16 error_code;
4078 __le16 req_type; 4284 __le16 req_type;
4079 __le16 seq_id; 4285 __le16 seq_id;
4080 __le16 resp_len; 4286 __le16 resp_len;
4081 __le32 unused_0; 4287 u8 unused_0[7];
4082 u8 unused_1; 4288 u8 valid;
4083 u8 unused_2; 4289};
4084 u8 unused_3; 4290
4085 u8 valid; 4291/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
4086};
4087
4088/* hwrm_cfa_l2_set_rx_mask */
4089/* Input (56 bytes) */
4090struct hwrm_cfa_l2_set_rx_mask_input { 4292struct hwrm_cfa_l2_set_rx_mask_input {
4091 __le16 req_type; 4293 __le16 req_type;
4092 __le16 cmpl_ring; 4294 __le16 cmpl_ring;
4093 __le16 seq_id; 4295 __le16 seq_id;
4094 __le16 target_id; 4296 __le16 target_id;
4095 __le64 resp_addr; 4297 __le64 resp_addr;
4096 __le32 vnic_id; 4298 __le32 vnic_id;
4097 __le32 mask; 4299 __le32 mask;
4098 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL 4300 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
4099 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 4301 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
4100 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 4302 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
4101 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 4303 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
4102 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 4304 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
4103 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 4305 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL
4104 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 4306 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL
4105 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 4307 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL
4106 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 4308 __le64 mc_tbl_addr;
4107 __le64 mc_tbl_addr; 4309 __le32 num_mc_entries;
4108 __le32 num_mc_entries; 4310 u8 unused_0[4];
4109 __le32 unused_0; 4311 __le64 vlan_tag_tbl_addr;
4110 __le64 vlan_tag_tbl_addr; 4312 __le32 num_vlan_tags;
4111 __le32 num_vlan_tags; 4313 u8 unused_1[4];
4112 __le32 unused_1; 4314};
4113}; 4315
4114 4316/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
4115/* Output (16 bytes) */
4116struct hwrm_cfa_l2_set_rx_mask_output { 4317struct hwrm_cfa_l2_set_rx_mask_output {
4117 __le16 error_code; 4318 __le16 error_code;
4118 __le16 req_type; 4319 __le16 req_type;
4119 __le16 seq_id; 4320 __le16 seq_id;
4120 __le16 resp_len; 4321 __le16 resp_len;
4121 __le32 unused_0; 4322 u8 unused_0[7];
4122 u8 unused_1; 4323 u8 valid;
4123 u8 unused_2; 4324};
4124 u8 unused_3; 4325
4125 u8 valid; 4326/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
4126};
4127
4128/* Command specific Error Codes (8 bytes) */
4129struct hwrm_cfa_l2_set_rx_mask_cmd_err { 4327struct hwrm_cfa_l2_set_rx_mask_cmd_err {
4130 u8 code; 4328 u8 code;
4131 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 4329 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL
4132 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 4330 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
4133 u8 unused_0[7]; 4331 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
4332 u8 unused_0[7];
4134}; 4333};
4135 4334
4136/* hwrm_cfa_tunnel_filter_alloc */ 4335/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
4137/* Input (88 bytes) */
4138struct hwrm_cfa_tunnel_filter_alloc_input { 4336struct hwrm_cfa_tunnel_filter_alloc_input {
4139 __le16 req_type; 4337 __le16 req_type;
4140 __le16 cmpl_ring; 4338 __le16 cmpl_ring;
4141 __le16 seq_id; 4339 __le16 seq_id;
4142 __le16 target_id; 4340 __le16 target_id;
4143 __le64 resp_addr; 4341 __le64 resp_addr;
4144 __le32 flags; 4342 __le32 flags;
4145 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4343 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
4146 __le32 enables; 4344 __le32 enables;
4147 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4345 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
4148 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 4346 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
4149 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 4347 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
4150 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 4348 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
4151 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 4349 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
4152 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 4350 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
4153 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 4351 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
4154 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 4352 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
4155 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 4353 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
4156 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 4354 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
4157 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 4355 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
4158 __le64 l2_filter_id; 4356 __le64 l2_filter_id;
4159 u8 l2_addr[6]; 4357 u8 l2_addr[6];
4160 __le16 l2_ivlan; 4358 __le16 l2_ivlan;
4161 __le32 l3_addr[4]; 4359 __le32 l3_addr[4];
4162 __le32 t_l3_addr[4]; 4360 __le32 t_l3_addr[4];
4163 u8 l3_addr_type; 4361 u8 l3_addr_type;
4164 u8 t_l3_addr_type; 4362 u8 t_l3_addr_type;
4165 u8 tunnel_type; 4363 u8 tunnel_type;
4166 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4364 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
4167 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4365 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
4168 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4366 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
@@ -4174,158 +4372,204 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
4174 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4372 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
4175 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4373 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
4176 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4374 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
4177 u8 unused_0; 4375 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
4178 __le32 vni; 4376 u8 tunnel_flags;
4179 __le32 dst_vnic_id; 4377 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL
4180 __le32 mirror_vnic_id; 4378 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL
4379 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL
4380 __le32 vni;
4381 __le32 dst_vnic_id;
4382 __le32 mirror_vnic_id;
4181}; 4383};
4182 4384
4183/* Output (24 bytes) */ 4385/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
4184struct hwrm_cfa_tunnel_filter_alloc_output { 4386struct hwrm_cfa_tunnel_filter_alloc_output {
4185 __le16 error_code; 4387 __le16 error_code;
4186 __le16 req_type; 4388 __le16 req_type;
4187 __le16 seq_id; 4389 __le16 seq_id;
4188 __le16 resp_len; 4390 __le16 resp_len;
4189 __le64 tunnel_filter_id; 4391 __le64 tunnel_filter_id;
4190 __le32 flow_id; 4392 __le32 flow_id;
4191 u8 unused_0; 4393 u8 unused_0[3];
4192 u8 unused_1; 4394 u8 valid;
4193 u8 unused_2; 4395};
4194 u8 valid; 4396
4195}; 4397/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
4196
4197/* hwrm_cfa_tunnel_filter_free */
4198/* Input (24 bytes) */
4199struct hwrm_cfa_tunnel_filter_free_input { 4398struct hwrm_cfa_tunnel_filter_free_input {
4200 __le16 req_type; 4399 __le16 req_type;
4201 __le16 cmpl_ring; 4400 __le16 cmpl_ring;
4202 __le16 seq_id; 4401 __le16 seq_id;
4203 __le16 target_id; 4402 __le16 target_id;
4204 __le64 resp_addr; 4403 __le64 resp_addr;
4205 __le64 tunnel_filter_id; 4404 __le64 tunnel_filter_id;
4206}; 4405};
4207 4406
4208/* Output (16 bytes) */ 4407/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
4209struct hwrm_cfa_tunnel_filter_free_output { 4408struct hwrm_cfa_tunnel_filter_free_output {
4210 __le16 error_code; 4409 __le16 error_code;
4211 __le16 req_type; 4410 __le16 req_type;
4212 __le16 seq_id; 4411 __le16 seq_id;
4213 __le16 resp_len; 4412 __le16 resp_len;
4214 __le32 unused_0; 4413 u8 unused_0[7];
4215 u8 unused_1; 4414 u8 valid;
4216 u8 unused_2; 4415};
4217 u8 unused_3; 4416
4218 u8 valid; 4417/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
4219}; 4418struct hwrm_vxlan_ipv4_hdr {
4220 4419 u8 ver_hlen;
4221/* hwrm_cfa_encap_record_alloc */ 4420 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
4222/* Input (32 bytes) */ 4421 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
4422 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL
4423 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
4424 u8 tos;
4425 __be16 ip_id;
4426 __be16 flags_frag_offset;
4427 u8 ttl;
4428 u8 protocol;
4429 __be32 src_ip_addr;
4430 __be32 dest_ip_addr;
4431};
4432
4433/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
4434struct hwrm_vxlan_ipv6_hdr {
4435 __be32 ver_tc_flow_label;
4436 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL
4437 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL
4438 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL
4439 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL
4440 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL
4441 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
4442 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
4443 __be16 payload_len;
4444 u8 next_hdr;
4445 u8 ttl;
4446 __be32 src_ip_addr[4];
4447 __be32 dest_ip_addr[4];
4448};
4449
4450/* hwrm_cfa_encap_data_vxlan (size:576b/72B) */
4451struct hwrm_cfa_encap_data_vxlan {
4452 u8 src_mac_addr[6];
4453 __le16 unused_0;
4454 u8 dst_mac_addr[6];
4455 u8 num_vlan_tags;
4456 u8 unused_1;
4457 __be16 ovlan_tpid;
4458 __be16 ovlan_tci;
4459 __be16 ivlan_tpid;
4460 __be16 ivlan_tci;
4461 __le32 l3[10];
4462 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
4463 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
4464 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
4465 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
4466 __be16 src_port;
4467 __be16 dst_port;
4468 __be32 vni;
4469};
4470
4471/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
4223struct hwrm_cfa_encap_record_alloc_input { 4472struct hwrm_cfa_encap_record_alloc_input {
4224 __le16 req_type; 4473 __le16 req_type;
4225 __le16 cmpl_ring; 4474 __le16 cmpl_ring;
4226 __le16 seq_id; 4475 __le16 seq_id;
4227 __le16 target_id; 4476 __le16 target_id;
4228 __le64 resp_addr; 4477 __le64 resp_addr;
4229 __le32 flags; 4478 __le32 flags;
4230 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4479 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
4231 u8 encap_type; 4480 u8 encap_type;
4232 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 4481 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
4233 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 4482 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
4234 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 4483 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
4235 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 4484 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
4236 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 4485 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
4237 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 4486 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
4238 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 4487 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
4239 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 4488 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
4240 u8 unused_0; 4489 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE
4241 __le16 unused_1; 4490 u8 unused_0[3];
4242 __le32 encap_data[20]; 4491 __le32 encap_data[20];
4243}; 4492};
4244 4493
4245/* Output (16 bytes) */ 4494/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
4246struct hwrm_cfa_encap_record_alloc_output { 4495struct hwrm_cfa_encap_record_alloc_output {
4247 __le16 error_code; 4496 __le16 error_code;
4248 __le16 req_type; 4497 __le16 req_type;
4249 __le16 seq_id; 4498 __le16 seq_id;
4250 __le16 resp_len; 4499 __le16 resp_len;
4251 __le32 encap_record_id; 4500 __le32 encap_record_id;
4252 u8 unused_0; 4501 u8 unused_0[3];
4253 u8 unused_1; 4502 u8 valid;
4254 u8 unused_2; 4503};
4255 u8 valid; 4504
4256}; 4505/* hwrm_cfa_encap_record_free_input (size:192b/24B) */
4257
4258/* hwrm_cfa_encap_record_free */
4259/* Input (24 bytes) */
4260struct hwrm_cfa_encap_record_free_input { 4506struct hwrm_cfa_encap_record_free_input {
4261 __le16 req_type; 4507 __le16 req_type;
4262 __le16 cmpl_ring; 4508 __le16 cmpl_ring;
4263 __le16 seq_id; 4509 __le16 seq_id;
4264 __le16 target_id; 4510 __le16 target_id;
4265 __le64 resp_addr; 4511 __le64 resp_addr;
4266 __le32 encap_record_id; 4512 __le32 encap_record_id;
4267 __le32 unused_0; 4513 u8 unused_0[4];
4268}; 4514};
4269 4515
4270/* Output (16 bytes) */ 4516/* hwrm_cfa_encap_record_free_output (size:128b/16B) */
4271struct hwrm_cfa_encap_record_free_output { 4517struct hwrm_cfa_encap_record_free_output {
4272 __le16 error_code; 4518 __le16 error_code;
4273 __le16 req_type; 4519 __le16 req_type;
4274 __le16 seq_id; 4520 __le16 seq_id;
4275 __le16 resp_len; 4521 __le16 resp_len;
4276 __le32 unused_0; 4522 u8 unused_0[7];
4277 u8 unused_1; 4523 u8 valid;
4278 u8 unused_2; 4524};
4279 u8 unused_3; 4525
4280 u8 valid; 4526/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
4281};
4282
4283/* hwrm_cfa_ntuple_filter_alloc */
4284/* Input (128 bytes) */
4285struct hwrm_cfa_ntuple_filter_alloc_input { 4527struct hwrm_cfa_ntuple_filter_alloc_input {
4286 __le16 req_type; 4528 __le16 req_type;
4287 __le16 cmpl_ring; 4529 __le16 cmpl_ring;
4288 __le16 seq_id; 4530 __le16 seq_id;
4289 __le16 target_id; 4531 __le16 target_id;
4290 __le64 resp_addr; 4532 __le64 resp_addr;
4291 __le32 flags; 4533 __le32 flags;
4292 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4534 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
4293 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 4535 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
4294 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 4536 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL
4295 __le32 enables; 4537 __le32 enables;
4296 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4538 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
4297 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 4539 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
4298 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 4540 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
4299 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 4541 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
4300 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 4542 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
4301 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 4543 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
4302 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 4544 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
4303 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 4545 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
4304 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 4546 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
4305 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 4547 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
4306 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 4548 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
4307 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 4549 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
4308 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 4550 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
4309 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 4551 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
4310 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 4552 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
4311 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 4553 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
4312 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 4554 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
4313 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 4555 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
4314 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 4556 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
4315 __le64 l2_filter_id; 4557 __le64 l2_filter_id;
4316 u8 src_macaddr[6]; 4558 u8 src_macaddr[6];
4317 __be16 ethertype; 4559 __be16 ethertype;
4318 u8 ip_addr_type; 4560 u8 ip_addr_type;
4319 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4561 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
4320 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4562 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
4321 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4563 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
4322 u8 ip_protocol; 4564 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
4323 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4565 u8 ip_protocol;
4324 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 4566 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
4325 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 4567 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
4326 __le16 dst_id; 4568 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
4327 __le16 mirror_vnic_id; 4569 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
4328 u8 tunnel_type; 4570 __le16 dst_id;
4571 __le16 mirror_vnic_id;
4572 u8 tunnel_type;
4329 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4573 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
4330 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4574 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
4331 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4575 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
@@ -4337,2221 +4581,1723 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
4337 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4581 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
4338 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4582 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
4339 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4583 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
4340 u8 pri_hint; 4584 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
4341 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4585 u8 pri_hint;
4342 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 4586 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
4343 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 4587 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL
4344 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 4588 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL
4345 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 4589 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL
4346 __be32 src_ipaddr[4]; 4590 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL
4347 __be32 src_ipaddr_mask[4]; 4591 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST
4348 __be32 dst_ipaddr[4]; 4592 __be32 src_ipaddr[4];
4349 __be32 dst_ipaddr_mask[4]; 4593 __be32 src_ipaddr_mask[4];
4350 __be16 src_port; 4594 __be32 dst_ipaddr[4];
4351 __be16 src_port_mask; 4595 __be32 dst_ipaddr_mask[4];
4352 __be16 dst_port; 4596 __be16 src_port;
4353 __be16 dst_port_mask; 4597 __be16 src_port_mask;
4354 __le64 ntuple_filter_id_hint; 4598 __be16 dst_port;
4355}; 4599 __be16 dst_port_mask;
4356 4600 __le64 ntuple_filter_id_hint;
4357/* Output (24 bytes) */ 4601};
4602
4603/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
4358struct hwrm_cfa_ntuple_filter_alloc_output { 4604struct hwrm_cfa_ntuple_filter_alloc_output {
4359 __le16 error_code; 4605 __le16 error_code;
4360 __le16 req_type; 4606 __le16 req_type;
4361 __le16 seq_id; 4607 __le16 seq_id;
4362 __le16 resp_len; 4608 __le16 resp_len;
4363 __le64 ntuple_filter_id; 4609 __le64 ntuple_filter_id;
4364 __le32 flow_id; 4610 __le32 flow_id;
4365 u8 unused_0; 4611 u8 unused_0[3];
4366 u8 unused_1; 4612 u8 valid;
4367 u8 unused_2; 4613};
4368 u8 valid; 4614
4369}; 4615/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
4370
4371/* Command specific Error Codes (8 bytes) */
4372struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 4616struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
4373 u8 code; 4617 u8 code;
4374 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 4618 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
4375 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 4619 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL
4376 u8 unused_0[7]; 4620 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
4621 u8 unused_0[7];
4377}; 4622};
4378 4623
4379/* hwrm_cfa_ntuple_filter_free */ 4624/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
4380/* Input (24 bytes) */
4381struct hwrm_cfa_ntuple_filter_free_input { 4625struct hwrm_cfa_ntuple_filter_free_input {
4382 __le16 req_type; 4626 __le16 req_type;
4383 __le16 cmpl_ring; 4627 __le16 cmpl_ring;
4384 __le16 seq_id; 4628 __le16 seq_id;
4385 __le16 target_id; 4629 __le16 target_id;
4386 __le64 resp_addr; 4630 __le64 resp_addr;
4387 __le64 ntuple_filter_id; 4631 __le64 ntuple_filter_id;
4388}; 4632};
4389 4633
4390/* Output (16 bytes) */ 4634/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
4391struct hwrm_cfa_ntuple_filter_free_output { 4635struct hwrm_cfa_ntuple_filter_free_output {
4392 __le16 error_code; 4636 __le16 error_code;
4393 __le16 req_type; 4637 __le16 req_type;
4394 __le16 seq_id; 4638 __le16 seq_id;
4395 __le16 resp_len; 4639 __le16 resp_len;
4396 __le32 unused_0; 4640 u8 unused_0[7];
4397 u8 unused_1; 4641 u8 valid;
4398 u8 unused_2; 4642};
4399 u8 unused_3; 4643
4400 u8 valid; 4644/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
4401};
4402
4403/* hwrm_cfa_ntuple_filter_cfg */
4404/* Input (48 bytes) */
4405struct hwrm_cfa_ntuple_filter_cfg_input { 4645struct hwrm_cfa_ntuple_filter_cfg_input {
4406 __le16 req_type; 4646 __le16 req_type;
4407 __le16 cmpl_ring; 4647 __le16 cmpl_ring;
4408 __le16 seq_id; 4648 __le16 seq_id;
4409 __le16 target_id; 4649 __le16 target_id;
4410 __le64 resp_addr; 4650 __le64 resp_addr;
4411 __le32 enables; 4651 __le32 enables;
4412 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 4652 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
4413 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4653 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
4414 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 4654 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
4415 __le32 unused_0; 4655 u8 unused_0[4];
4416 __le64 ntuple_filter_id; 4656 __le64 ntuple_filter_id;
4417 __le32 new_dst_id; 4657 __le32 new_dst_id;
4418 __le32 new_mirror_vnic_id; 4658 __le32 new_mirror_vnic_id;
4419 __le16 new_meter_instance_id; 4659 __le16 new_meter_instance_id;
4420 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 4660 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
4421 __le16 unused_1[3]; 4661 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
4662 u8 unused_1[6];
4422}; 4663};
4423 4664
4424/* Output (16 bytes) */ 4665/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
4425struct hwrm_cfa_ntuple_filter_cfg_output { 4666struct hwrm_cfa_ntuple_filter_cfg_output {
4426 __le16 error_code; 4667 __le16 error_code;
4427 __le16 req_type; 4668 __le16 req_type;
4428 __le16 seq_id; 4669 __le16 seq_id;
4429 __le16 resp_len; 4670 __le16 resp_len;
4430 __le32 unused_0; 4671 u8 unused_0[7];
4431 u8 unused_1; 4672 u8 valid;
4432 u8 unused_2; 4673};
4433 u8 unused_3; 4674
4434 u8 valid; 4675/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
4435};
4436
4437/* hwrm_cfa_decap_filter_alloc */
4438/* Input (104 bytes) */
4439struct hwrm_cfa_decap_filter_alloc_input { 4676struct hwrm_cfa_decap_filter_alloc_input {
4440 __le16 req_type; 4677 __le16 req_type;
4441 __le16 cmpl_ring; 4678 __le16 cmpl_ring;
4442 __le16 seq_id; 4679 __le16 seq_id;
4443 __le16 target_id; 4680 __le16 target_id;
4444 __le64 resp_addr; 4681 __le64 resp_addr;
4445 __le32 flags; 4682 __le32 flags;
4446 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 4683 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL
4447 __le32 enables; 4684 __le32 enables;
4448 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 4685 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL
4449 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 4686 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL
4450 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 4687 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL
4451 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 4688 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL
4452 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 4689 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL
4453 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 4690 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL
4454 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 4691 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL
4455 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 4692 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL
4456 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 4693 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL
4457 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 4694 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL
4458 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 4695 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL
4459 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 4696 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL
4460 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 4697 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL
4461 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 4698 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL
4462 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 4699 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL
4463 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 4700 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
4464 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 4701 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
4465 __be32 tunnel_id; 4702 __be32 tunnel_id;
4466 u8 tunnel_type; 4703 u8 tunnel_type;
4467 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4704 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
4468 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4705 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
4469 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4706 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
4470 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4707 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
4471 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4708 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
4472 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4709 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
4473 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4710 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
4474 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4711 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
4475 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4712 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
4476 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4713 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
4477 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4714 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
4478 u8 unused_0; 4715 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
4479 __le16 unused_1; 4716 u8 unused_0;
4480 u8 src_macaddr[6]; 4717 __le16 unused_1;
4481 u8 unused_2; 4718 u8 src_macaddr[6];
4482 u8 unused_3; 4719 u8 unused_2[2];
4483 u8 dst_macaddr[6]; 4720 u8 dst_macaddr[6];
4484 __be16 ovlan_vid; 4721 __be16 ovlan_vid;
4485 __be16 ivlan_vid; 4722 __be16 ivlan_vid;
4486 __be16 t_ovlan_vid; 4723 __be16 t_ovlan_vid;
4487 __be16 t_ivlan_vid; 4724 __be16 t_ivlan_vid;
4488 __be16 ethertype; 4725 __be16 ethertype;
4489 u8 ip_addr_type; 4726 u8 ip_addr_type;
4490 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4727 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
4491 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4728 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
4492 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4729 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
4493 u8 ip_protocol; 4730 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
4494 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4731 u8 ip_protocol;
4495 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 4732 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
4496 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 4733 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
4497 u8 unused_4; 4734 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
4498 u8 unused_5; 4735 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
4499 u8 unused_6[3]; 4736 __le16 unused_3;
4500 u8 unused_7; 4737 __le32 unused_4;
4501 __be32 src_ipaddr[4]; 4738 __be32 src_ipaddr[4];
4502 __be32 dst_ipaddr[4]; 4739 __be32 dst_ipaddr[4];
4503 __be16 src_port; 4740 __be16 src_port;
4504 __be16 dst_port; 4741 __be16 dst_port;
4505 __le16 dst_id; 4742 __le16 dst_id;
4506 __le16 l2_ctxt_ref_id; 4743 __le16 l2_ctxt_ref_id;
4507}; 4744};
4508 4745
4509/* Output (16 bytes) */ 4746/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
4510struct hwrm_cfa_decap_filter_alloc_output { 4747struct hwrm_cfa_decap_filter_alloc_output {
4511 __le16 error_code; 4748 __le16 error_code;
4512 __le16 req_type; 4749 __le16 req_type;
4513 __le16 seq_id; 4750 __le16 seq_id;
4514 __le16 resp_len; 4751 __le16 resp_len;
4515 __le32 decap_filter_id; 4752 __le32 decap_filter_id;
4516 u8 unused_0; 4753 u8 unused_0[3];
4517 u8 unused_1; 4754 u8 valid;
4518 u8 unused_2; 4755};
4519 u8 valid; 4756
4520}; 4757/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
4521
4522/* hwrm_cfa_decap_filter_free */
4523/* Input (24 bytes) */
4524struct hwrm_cfa_decap_filter_free_input { 4758struct hwrm_cfa_decap_filter_free_input {
4525 __le16 req_type; 4759 __le16 req_type;
4526 __le16 cmpl_ring; 4760 __le16 cmpl_ring;
4527 __le16 seq_id; 4761 __le16 seq_id;
4528 __le16 target_id; 4762 __le16 target_id;
4529 __le64 resp_addr; 4763 __le64 resp_addr;
4530 __le32 decap_filter_id; 4764 __le32 decap_filter_id;
4531 __le32 unused_0; 4765 u8 unused_0[4];
4532}; 4766};
4533 4767
4534/* Output (16 bytes) */ 4768/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
4535struct hwrm_cfa_decap_filter_free_output { 4769struct hwrm_cfa_decap_filter_free_output {
4536 __le16 error_code; 4770 __le16 error_code;
4537 __le16 req_type; 4771 __le16 req_type;
4538 __le16 seq_id; 4772 __le16 seq_id;
4539 __le16 resp_len; 4773 __le16 resp_len;
4540 __le32 unused_0; 4774 u8 unused_0[7];
4541 u8 unused_1; 4775 u8 valid;
4542 u8 unused_2; 4776};
4543 u8 unused_3; 4777
4544 u8 valid; 4778/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
4545};
4546
4547/* hwrm_cfa_flow_alloc */
4548/* Input (128 bytes) */
4549struct hwrm_cfa_flow_alloc_input { 4779struct hwrm_cfa_flow_alloc_input {
4550 __le16 req_type; 4780 __le16 req_type;
4551 __le16 cmpl_ring; 4781 __le16 cmpl_ring;
4552 __le16 seq_id; 4782 __le16 seq_id;
4553 __le16 target_id; 4783 __le16 target_id;
4554 __le64 resp_addr; 4784 __le64 resp_addr;
4555 __le16 flags; 4785 __le16 flags;
4556 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 4786 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
4557 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 4787 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
4558 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 4788 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
4559 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 4789 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
4560 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 4790 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
4561 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 4791 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
4562 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 4792 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
4563 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 4793 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
4564 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 4794 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
4565 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 4795 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
4566 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 4796 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
4567 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 4797 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
4568 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 4798 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
4569 __le16 src_fid; 4799 __le16 src_fid;
4570 __le32 tunnel_handle; 4800 __le32 tunnel_handle;
4571 __le16 action_flags; 4801 __le16 action_flags;
4572 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 4802 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
4573 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 4803 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
4574 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 4804 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
4575 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 4805 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
4576 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 4806 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
4577 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 4807 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
4578 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 4808 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
4579 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 4809 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
4580 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 4810 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
4581 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 4811 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
4582 __le16 dst_fid; 4812 __le16 dst_fid;
4583 __be16 l2_rewrite_vlan_tpid; 4813 __be16 l2_rewrite_vlan_tpid;
4584 __be16 l2_rewrite_vlan_tci; 4814 __be16 l2_rewrite_vlan_tci;
4585 __le16 act_meter_id; 4815 __le16 act_meter_id;
4586 __le16 ref_flow_handle; 4816 __le16 ref_flow_handle;
4587 __be16 ethertype; 4817 __be16 ethertype;
4588 __be16 outer_vlan_tci; 4818 __be16 outer_vlan_tci;
4589 __be16 dmac[3]; 4819 __be16 dmac[3];
4590 __be16 inner_vlan_tci; 4820 __be16 inner_vlan_tci;
4591 __be16 smac[3]; 4821 __be16 smac[3];
4592 u8 ip_dst_mask_len; 4822 u8 ip_dst_mask_len;
4593 u8 ip_src_mask_len; 4823 u8 ip_src_mask_len;
4594 __be32 ip_dst[4]; 4824 __be32 ip_dst[4];
4595 __be32 ip_src[4]; 4825 __be32 ip_src[4];
4596 __be16 l4_src_port; 4826 __be16 l4_src_port;
4597 __be16 l4_src_port_mask; 4827 __be16 l4_src_port_mask;
4598 __be16 l4_dst_port; 4828 __be16 l4_dst_port;
4599 __be16 l4_dst_port_mask; 4829 __be16 l4_dst_port_mask;
4600 __be32 nat_ip_address[4]; 4830 __be32 nat_ip_address[4];
4601 __be16 l2_rewrite_dmac[3]; 4831 __be16 l2_rewrite_dmac[3];
4602 __be16 nat_port; 4832 __be16 nat_port;
4603 __be16 l2_rewrite_smac[3]; 4833 __be16 l2_rewrite_smac[3];
4604 u8 ip_proto; 4834 u8 ip_proto;
4605 u8 unused_0; 4835 u8 unused_0;
4606}; 4836};
4607 4837
4608/* Output (16 bytes) */ 4838/* hwrm_cfa_flow_alloc_output (size:128b/16B) */
4609struct hwrm_cfa_flow_alloc_output { 4839struct hwrm_cfa_flow_alloc_output {
4610 __le16 error_code; 4840 __le16 error_code;
4611 __le16 req_type; 4841 __le16 req_type;
4612 __le16 seq_id; 4842 __le16 seq_id;
4613 __le16 resp_len; 4843 __le16 resp_len;
4614 __le16 flow_handle; 4844 __le16 flow_handle;
4615 u8 unused_0; 4845 u8 unused_0[5];
4616 u8 unused_1; 4846 u8 valid;
4617 u8 unused_2; 4847};
4618 u8 unused_3; 4848
4619 u8 unused_4; 4849/* hwrm_cfa_flow_free_input (size:192b/24B) */
4620 u8 valid;
4621};
4622
4623/* hwrm_cfa_flow_free */
4624/* Input (24 bytes) */
4625struct hwrm_cfa_flow_free_input { 4850struct hwrm_cfa_flow_free_input {
4626 __le16 req_type; 4851 __le16 req_type;
4627 __le16 cmpl_ring; 4852 __le16 cmpl_ring;
4628 __le16 seq_id; 4853 __le16 seq_id;
4629 __le16 target_id; 4854 __le16 target_id;
4630 __le64 resp_addr; 4855 __le64 resp_addr;
4631 __le16 flow_handle; 4856 __le16 flow_handle;
4632 __le16 unused_0[3]; 4857 u8 unused_0[6];
4633}; 4858};
4634 4859
4635/* Output (32 bytes) */ 4860/* hwrm_cfa_flow_free_output (size:256b/32B) */
4636struct hwrm_cfa_flow_free_output { 4861struct hwrm_cfa_flow_free_output {
4637 __le16 error_code; 4862 __le16 error_code;
4638 __le16 req_type; 4863 __le16 req_type;
4639 __le16 seq_id; 4864 __le16 seq_id;
4640 __le16 resp_len; 4865 __le16 resp_len;
4641 __le64 packet; 4866 __le64 packet;
4642 __le64 byte; 4867 __le64 byte;
4643 __le32 unused_0; 4868 u8 unused_0[7];
4644 u8 unused_1; 4869 u8 valid;
4645 u8 unused_2; 4870};
4646 u8 unused_3; 4871
4647 u8 valid; 4872/* hwrm_cfa_flow_stats_input (size:320b/40B) */
4648};
4649
4650/* hwrm_cfa_flow_stats */
4651/* Input (40 bytes) */
4652struct hwrm_cfa_flow_stats_input { 4873struct hwrm_cfa_flow_stats_input {
4653 __le16 req_type; 4874 __le16 req_type;
4654 __le16 cmpl_ring; 4875 __le16 cmpl_ring;
4655 __le16 seq_id; 4876 __le16 seq_id;
4656 __le16 target_id; 4877 __le16 target_id;
4657 __le64 resp_addr; 4878 __le64 resp_addr;
4658 __le16 num_flows; 4879 __le16 num_flows;
4659 __le16 flow_handle_0; 4880 __le16 flow_handle_0;
4660 __le16 flow_handle_1; 4881 __le16 flow_handle_1;
4661 __le16 flow_handle_2; 4882 __le16 flow_handle_2;
4662 __le16 flow_handle_3; 4883 __le16 flow_handle_3;
4663 __le16 flow_handle_4; 4884 __le16 flow_handle_4;
4664 __le16 flow_handle_5; 4885 __le16 flow_handle_5;
4665 __le16 flow_handle_6; 4886 __le16 flow_handle_6;
4666 __le16 flow_handle_7; 4887 __le16 flow_handle_7;
4667 __le16 flow_handle_8; 4888 __le16 flow_handle_8;
4668 __le16 flow_handle_9; 4889 __le16 flow_handle_9;
4669 __le16 unused_0; 4890 u8 unused_0[2];
4670}; 4891};
4671 4892
4672/* Output (176 bytes) */ 4893/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
4673struct hwrm_cfa_flow_stats_output { 4894struct hwrm_cfa_flow_stats_output {
4674 __le16 error_code; 4895 __le16 error_code;
4675 __le16 req_type; 4896 __le16 req_type;
4676 __le16 seq_id; 4897 __le16 seq_id;
4677 __le16 resp_len; 4898 __le16 resp_len;
4678 __le64 packet_0; 4899 __le64 packet_0;
4679 __le64 packet_1; 4900 __le64 packet_1;
4680 __le64 packet_2; 4901 __le64 packet_2;
4681 __le64 packet_3; 4902 __le64 packet_3;
4682 __le64 packet_4; 4903 __le64 packet_4;
4683 __le64 packet_5; 4904 __le64 packet_5;
4684 __le64 packet_6; 4905 __le64 packet_6;
4685 __le64 packet_7; 4906 __le64 packet_7;
4686 __le64 packet_8; 4907 __le64 packet_8;
4687 __le64 packet_9; 4908 __le64 packet_9;
4688 __le64 byte_0; 4909 __le64 byte_0;
4689 __le64 byte_1; 4910 __le64 byte_1;
4690 __le64 byte_2; 4911 __le64 byte_2;
4691 __le64 byte_3; 4912 __le64 byte_3;
4692 __le64 byte_4; 4913 __le64 byte_4;
4693 __le64 byte_5; 4914 __le64 byte_5;
4694 __le64 byte_6; 4915 __le64 byte_6;
4695 __le64 byte_7; 4916 __le64 byte_7;
4696 __le64 byte_8; 4917 __le64 byte_8;
4697 __le64 byte_9; 4918 __le64 byte_9;
4698 __le32 unused_0; 4919 u8 unused_0[7];
4699 u8 unused_1; 4920 u8 valid;
4700 u8 unused_2; 4921};
4701 u8 unused_3; 4922
4702 u8 valid; 4923/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
4703};
4704
4705/* hwrm_cfa_vfr_alloc */
4706/* Input (32 bytes) */
4707struct hwrm_cfa_vfr_alloc_input { 4924struct hwrm_cfa_vfr_alloc_input {
4708 __le16 req_type; 4925 __le16 req_type;
4709 __le16 cmpl_ring; 4926 __le16 cmpl_ring;
4710 __le16 seq_id; 4927 __le16 seq_id;
4711 __le16 target_id; 4928 __le16 target_id;
4712 __le64 resp_addr; 4929 __le64 resp_addr;
4713 __le16 vf_id; 4930 __le16 vf_id;
4714 __le16 reserved; 4931 __le16 reserved;
4715 __le32 unused_0; 4932 u8 unused_0[4];
4716 char vfr_name[32]; 4933 char vfr_name[32];
4717}; 4934};
4718 4935
4719/* Output (16 bytes) */ 4936/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
4720struct hwrm_cfa_vfr_alloc_output { 4937struct hwrm_cfa_vfr_alloc_output {
4721 __le16 error_code; 4938 __le16 error_code;
4722 __le16 req_type; 4939 __le16 req_type;
4723 __le16 seq_id; 4940 __le16 seq_id;
4724 __le16 resp_len; 4941 __le16 resp_len;
4725 __le16 rx_cfa_code; 4942 __le16 rx_cfa_code;
4726 __le16 tx_cfa_action; 4943 __le16 tx_cfa_action;
4727 u8 unused_0; 4944 u8 unused_0[3];
4728 u8 unused_1; 4945 u8 valid;
4729 u8 unused_2; 4946};
4730 u8 valid; 4947
4731}; 4948/* hwrm_cfa_vfr_free_input (size:384b/48B) */
4732
4733/* hwrm_cfa_vfr_free */
4734/* Input (24 bytes) */
4735struct hwrm_cfa_vfr_free_input { 4949struct hwrm_cfa_vfr_free_input {
4736 __le16 req_type; 4950 __le16 req_type;
4737 __le16 cmpl_ring; 4951 __le16 cmpl_ring;
4738 __le16 seq_id; 4952 __le16 seq_id;
4739 __le16 target_id; 4953 __le16 target_id;
4740 __le64 resp_addr; 4954 __le64 resp_addr;
4741 char vfr_name[32]; 4955 char vfr_name[32];
4742}; 4956};
4743 4957
4744/* Output (16 bytes) */ 4958/* hwrm_cfa_vfr_free_output (size:128b/16B) */
4745struct hwrm_cfa_vfr_free_output { 4959struct hwrm_cfa_vfr_free_output {
4746 __le16 error_code; 4960 __le16 error_code;
4747 __le16 req_type; 4961 __le16 req_type;
4748 __le16 seq_id; 4962 __le16 seq_id;
4749 __le16 resp_len; 4963 __le16 resp_len;
4750 __le32 unused_0; 4964 u8 unused_0[7];
4751 u8 unused_1; 4965 u8 valid;
4752 u8 unused_2; 4966};
4753 u8 unused_3; 4967
4754 u8 valid; 4968/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
4755};
4756
4757/* hwrm_tunnel_dst_port_query */
4758/* Input (24 bytes) */
4759struct hwrm_tunnel_dst_port_query_input { 4969struct hwrm_tunnel_dst_port_query_input {
4760 __le16 req_type; 4970 __le16 req_type;
4761 __le16 cmpl_ring; 4971 __le16 cmpl_ring;
4762 __le16 seq_id; 4972 __le16 seq_id;
4763 __le16 target_id; 4973 __le16 target_id;
4764 __le64 resp_addr; 4974 __le64 resp_addr;
4765 u8 tunnel_type; 4975 u8 tunnel_type;
4766 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4976 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
4767 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4977 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
4768 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4978 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
4769 u8 unused_0[7]; 4979 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4
4770}; 4980 u8 unused_0[7];
4771 4981};
4772/* Output (16 bytes) */ 4982
4983/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
4773struct hwrm_tunnel_dst_port_query_output { 4984struct hwrm_tunnel_dst_port_query_output {
4774 __le16 error_code; 4985 __le16 error_code;
4775 __le16 req_type; 4986 __le16 req_type;
4776 __le16 seq_id; 4987 __le16 seq_id;
4777 __le16 resp_len; 4988 __le16 resp_len;
4778 __le16 tunnel_dst_port_id; 4989 __le16 tunnel_dst_port_id;
4779 __be16 tunnel_dst_port_val; 4990 __be16 tunnel_dst_port_val;
4780 u8 unused_0; 4991 u8 unused_0[3];
4781 u8 unused_1; 4992 u8 valid;
4782 u8 unused_2; 4993};
4783 u8 valid; 4994
4784}; 4995/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
4785
4786/* hwrm_tunnel_dst_port_alloc */
4787/* Input (24 bytes) */
4788struct hwrm_tunnel_dst_port_alloc_input { 4996struct hwrm_tunnel_dst_port_alloc_input {
4789 __le16 req_type; 4997 __le16 req_type;
4790 __le16 cmpl_ring; 4998 __le16 cmpl_ring;
4791 __le16 seq_id; 4999 __le16 seq_id;
4792 __le16 target_id; 5000 __le16 target_id;
4793 __le64 resp_addr; 5001 __le64 resp_addr;
4794 u8 tunnel_type; 5002 u8 tunnel_type;
4795 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5003 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
4796 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5004 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
4797 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5005 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
4798 u8 unused_0; 5006 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4
4799 __be16 tunnel_dst_port_val; 5007 u8 unused_0;
4800 __be32 unused_1; 5008 __be16 tunnel_dst_port_val;
4801}; 5009 u8 unused_1[4];
4802 5010};
4803/* Output (16 bytes) */ 5011
5012/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
4804struct hwrm_tunnel_dst_port_alloc_output { 5013struct hwrm_tunnel_dst_port_alloc_output {
4805 __le16 error_code; 5014 __le16 error_code;
4806 __le16 req_type; 5015 __le16 req_type;
4807 __le16 seq_id; 5016 __le16 seq_id;
4808 __le16 resp_len; 5017 __le16 resp_len;
4809 __le16 tunnel_dst_port_id; 5018 __le16 tunnel_dst_port_id;
4810 u8 unused_0; 5019 u8 unused_0[5];
4811 u8 unused_1; 5020 u8 valid;
4812 u8 unused_2; 5021};
4813 u8 unused_3; 5022
4814 u8 unused_4; 5023/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
4815 u8 valid;
4816};
4817
4818/* hwrm_tunnel_dst_port_free */
4819/* Input (24 bytes) */
4820struct hwrm_tunnel_dst_port_free_input { 5024struct hwrm_tunnel_dst_port_free_input {
4821 __le16 req_type; 5025 __le16 req_type;
4822 __le16 cmpl_ring; 5026 __le16 cmpl_ring;
4823 __le16 seq_id; 5027 __le16 seq_id;
4824 __le16 target_id; 5028 __le16 target_id;
4825 __le64 resp_addr; 5029 __le64 resp_addr;
4826 u8 tunnel_type; 5030 u8 tunnel_type;
4827 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5031 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
4828 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5032 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
4829 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5033 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
4830 u8 unused_0; 5034 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4
4831 __le16 tunnel_dst_port_id; 5035 u8 unused_0;
4832 __le32 unused_1; 5036 __le16 tunnel_dst_port_id;
4833}; 5037 u8 unused_1[4];
4834 5038};
4835/* Output (16 bytes) */ 5039
5040/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
4836struct hwrm_tunnel_dst_port_free_output { 5041struct hwrm_tunnel_dst_port_free_output {
4837 __le16 error_code; 5042 __le16 error_code;
4838 __le16 req_type; 5043 __le16 req_type;
4839 __le16 seq_id; 5044 __le16 seq_id;
4840 __le16 resp_len; 5045 __le16 resp_len;
4841 __le32 unused_0; 5046 u8 unused_1[7];
4842 u8 unused_1; 5047 u8 valid;
4843 u8 unused_2; 5048};
4844 u8 unused_3; 5049
4845 u8 valid; 5050/* ctx_hw_stats (size:1280b/160B) */
4846}; 5051struct ctx_hw_stats {
4847 5052 __le64 rx_ucast_pkts;
4848/* hwrm_stat_ctx_alloc */ 5053 __le64 rx_mcast_pkts;
4849/* Input (32 bytes) */ 5054 __le64 rx_bcast_pkts;
5055 __le64 rx_discard_pkts;
5056 __le64 rx_drop_pkts;
5057 __le64 rx_ucast_bytes;
5058 __le64 rx_mcast_bytes;
5059 __le64 rx_bcast_bytes;
5060 __le64 tx_ucast_pkts;
5061 __le64 tx_mcast_pkts;
5062 __le64 tx_bcast_pkts;
5063 __le64 tx_discard_pkts;
5064 __le64 tx_drop_pkts;
5065 __le64 tx_ucast_bytes;
5066 __le64 tx_mcast_bytes;
5067 __le64 tx_bcast_bytes;
5068 __le64 tpa_pkts;
5069 __le64 tpa_bytes;
5070 __le64 tpa_events;
5071 __le64 tpa_aborts;
5072};
5073
5074/* hwrm_stat_ctx_alloc_input (size:256b/32B) */
4850struct hwrm_stat_ctx_alloc_input { 5075struct hwrm_stat_ctx_alloc_input {
4851 __le16 req_type; 5076 __le16 req_type;
4852 __le16 cmpl_ring; 5077 __le16 cmpl_ring;
4853 __le16 seq_id; 5078 __le16 seq_id;
4854 __le16 target_id; 5079 __le16 target_id;
4855 __le64 resp_addr; 5080 __le64 resp_addr;
4856 __le64 stats_dma_addr; 5081 __le64 stats_dma_addr;
4857 __le32 update_period_ms; 5082 __le32 update_period_ms;
4858 u8 stat_ctx_flags; 5083 u8 stat_ctx_flags;
4859 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 5084 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL
4860 u8 unused_0[3]; 5085 u8 unused_0[3];
4861}; 5086};
4862 5087
4863/* Output (16 bytes) */ 5088/* hwrm_stat_ctx_alloc_output (size:128b/16B) */
4864struct hwrm_stat_ctx_alloc_output { 5089struct hwrm_stat_ctx_alloc_output {
4865 __le16 error_code; 5090 __le16 error_code;
4866 __le16 req_type; 5091 __le16 req_type;
4867 __le16 seq_id; 5092 __le16 seq_id;
4868 __le16 resp_len; 5093 __le16 resp_len;
4869 __le32 stat_ctx_id; 5094 __le32 stat_ctx_id;
4870 u8 unused_0; 5095 u8 unused_0[3];
4871 u8 unused_1; 5096 u8 valid;
4872 u8 unused_2; 5097};
4873 u8 valid; 5098
4874}; 5099/* hwrm_stat_ctx_free_input (size:192b/24B) */
4875
4876/* hwrm_stat_ctx_free */
4877/* Input (24 bytes) */
4878struct hwrm_stat_ctx_free_input { 5100struct hwrm_stat_ctx_free_input {
4879 __le16 req_type; 5101 __le16 req_type;
4880 __le16 cmpl_ring; 5102 __le16 cmpl_ring;
4881 __le16 seq_id; 5103 __le16 seq_id;
4882 __le16 target_id; 5104 __le16 target_id;
4883 __le64 resp_addr; 5105 __le64 resp_addr;
4884 __le32 stat_ctx_id; 5106 __le32 stat_ctx_id;
4885 __le32 unused_0; 5107 u8 unused_0[4];
4886}; 5108};
4887 5109
4888/* Output (16 bytes) */ 5110/* hwrm_stat_ctx_free_output (size:128b/16B) */
4889struct hwrm_stat_ctx_free_output { 5111struct hwrm_stat_ctx_free_output {
4890 __le16 error_code; 5112 __le16 error_code;
4891 __le16 req_type; 5113 __le16 req_type;
4892 __le16 seq_id; 5114 __le16 seq_id;
4893 __le16 resp_len; 5115 __le16 resp_len;
4894 __le32 stat_ctx_id; 5116 __le32 stat_ctx_id;
4895 u8 unused_0; 5117 u8 unused_0[3];
4896 u8 unused_1; 5118 u8 valid;
4897 u8 unused_2; 5119};
4898 u8 valid; 5120
4899}; 5121/* hwrm_stat_ctx_query_input (size:192b/24B) */
4900
4901/* hwrm_stat_ctx_query */
4902/* Input (24 bytes) */
4903struct hwrm_stat_ctx_query_input { 5122struct hwrm_stat_ctx_query_input {
4904 __le16 req_type; 5123 __le16 req_type;
4905 __le16 cmpl_ring; 5124 __le16 cmpl_ring;
4906 __le16 seq_id; 5125 __le16 seq_id;
4907 __le16 target_id; 5126 __le16 target_id;
4908 __le64 resp_addr; 5127 __le64 resp_addr;
4909 __le32 stat_ctx_id; 5128 __le32 stat_ctx_id;
4910 __le32 unused_0; 5129 u8 unused_0[4];
4911}; 5130};
4912 5131
4913/* Output (176 bytes) */ 5132/* hwrm_stat_ctx_query_output (size:1408b/176B) */
4914struct hwrm_stat_ctx_query_output { 5133struct hwrm_stat_ctx_query_output {
4915 __le16 error_code; 5134 __le16 error_code;
4916 __le16 req_type; 5135 __le16 req_type;
4917 __le16 seq_id; 5136 __le16 seq_id;
4918 __le16 resp_len; 5137 __le16 resp_len;
4919 __le64 tx_ucast_pkts; 5138 __le64 tx_ucast_pkts;
4920 __le64 tx_mcast_pkts; 5139 __le64 tx_mcast_pkts;
4921 __le64 tx_bcast_pkts; 5140 __le64 tx_bcast_pkts;
4922 __le64 tx_err_pkts; 5141 __le64 tx_err_pkts;
4923 __le64 tx_drop_pkts; 5142 __le64 tx_drop_pkts;
4924 __le64 tx_ucast_bytes; 5143 __le64 tx_ucast_bytes;
4925 __le64 tx_mcast_bytes; 5144 __le64 tx_mcast_bytes;
4926 __le64 tx_bcast_bytes; 5145 __le64 tx_bcast_bytes;
4927 __le64 rx_ucast_pkts; 5146 __le64 rx_ucast_pkts;
4928 __le64 rx_mcast_pkts; 5147 __le64 rx_mcast_pkts;
4929 __le64 rx_bcast_pkts; 5148 __le64 rx_bcast_pkts;
4930 __le64 rx_err_pkts; 5149 __le64 rx_err_pkts;
4931 __le64 rx_drop_pkts; 5150 __le64 rx_drop_pkts;
4932 __le64 rx_ucast_bytes; 5151 __le64 rx_ucast_bytes;
4933 __le64 rx_mcast_bytes; 5152 __le64 rx_mcast_bytes;
4934 __le64 rx_bcast_bytes; 5153 __le64 rx_bcast_bytes;
4935 __le64 rx_agg_pkts; 5154 __le64 rx_agg_pkts;
4936 __le64 rx_agg_bytes; 5155 __le64 rx_agg_bytes;
4937 __le64 rx_agg_events; 5156 __le64 rx_agg_events;
4938 __le64 rx_agg_aborts; 5157 __le64 rx_agg_aborts;
4939 __le32 unused_0; 5158 u8 unused_0[7];
4940 u8 unused_1; 5159 u8 valid;
4941 u8 unused_2; 5160};
4942 u8 unused_3; 5161
4943 u8 valid; 5162/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
4944};
4945
4946/* hwrm_stat_ctx_clr_stats */
4947/* Input (24 bytes) */
4948struct hwrm_stat_ctx_clr_stats_input { 5163struct hwrm_stat_ctx_clr_stats_input {
4949 __le16 req_type; 5164 __le16 req_type;
4950 __le16 cmpl_ring; 5165 __le16 cmpl_ring;
4951 __le16 seq_id; 5166 __le16 seq_id;
4952 __le16 target_id; 5167 __le16 target_id;
4953 __le64 resp_addr; 5168 __le64 resp_addr;
4954 __le32 stat_ctx_id; 5169 __le32 stat_ctx_id;
4955 __le32 unused_0; 5170 u8 unused_0[4];
4956}; 5171};
4957 5172
4958/* Output (16 bytes) */ 5173/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
4959struct hwrm_stat_ctx_clr_stats_output { 5174struct hwrm_stat_ctx_clr_stats_output {
4960 __le16 error_code; 5175 __le16 error_code;
4961 __le16 req_type; 5176 __le16 req_type;
4962 __le16 seq_id; 5177 __le16 seq_id;
4963 __le16 resp_len; 5178 __le16 resp_len;
4964 __le32 unused_0; 5179 u8 unused_0[7];
4965 u8 unused_1; 5180 u8 valid;
4966 u8 unused_2; 5181};
4967 u8 unused_3; 5182
4968 u8 valid; 5183/* tx_port_stats (size:3264b/408B) */
4969}; 5184struct tx_port_stats {
4970 5185 __le64 tx_64b_frames;
4971/* hwrm_fw_reset */ 5186 __le64 tx_65b_127b_frames;
4972/* Input (24 bytes) */ 5187 __le64 tx_128b_255b_frames;
5188 __le64 tx_256b_511b_frames;
5189 __le64 tx_512b_1023b_frames;
5190 __le64 tx_1024b_1518_frames;
5191 __le64 tx_good_vlan_frames;
5192 __le64 tx_1519b_2047_frames;
5193 __le64 tx_2048b_4095b_frames;
5194 __le64 tx_4096b_9216b_frames;
5195 __le64 tx_9217b_16383b_frames;
5196 __le64 tx_good_frames;
5197 __le64 tx_total_frames;
5198 __le64 tx_ucast_frames;
5199 __le64 tx_mcast_frames;
5200 __le64 tx_bcast_frames;
5201 __le64 tx_pause_frames;
5202 __le64 tx_pfc_frames;
5203 __le64 tx_jabber_frames;
5204 __le64 tx_fcs_err_frames;
5205 __le64 tx_control_frames;
5206 __le64 tx_oversz_frames;
5207 __le64 tx_single_dfrl_frames;
5208 __le64 tx_multi_dfrl_frames;
5209 __le64 tx_single_coll_frames;
5210 __le64 tx_multi_coll_frames;
5211 __le64 tx_late_coll_frames;
5212 __le64 tx_excessive_coll_frames;
5213 __le64 tx_frag_frames;
5214 __le64 tx_err;
5215 __le64 tx_tagged_frames;
5216 __le64 tx_dbl_tagged_frames;
5217 __le64 tx_runt_frames;
5218 __le64 tx_fifo_underruns;
5219 __le64 tx_pfc_ena_frames_pri0;
5220 __le64 tx_pfc_ena_frames_pri1;
5221 __le64 tx_pfc_ena_frames_pri2;
5222 __le64 tx_pfc_ena_frames_pri3;
5223 __le64 tx_pfc_ena_frames_pri4;
5224 __le64 tx_pfc_ena_frames_pri5;
5225 __le64 tx_pfc_ena_frames_pri6;
5226 __le64 tx_pfc_ena_frames_pri7;
5227 __le64 tx_eee_lpi_events;
5228 __le64 tx_eee_lpi_duration;
5229 __le64 tx_llfc_logical_msgs;
5230 __le64 tx_hcfc_msgs;
5231 __le64 tx_total_collisions;
5232 __le64 tx_bytes;
5233 __le64 tx_xthol_frames;
5234 __le64 tx_stat_discard;
5235 __le64 tx_stat_error;
5236};
5237
5238/* rx_port_stats (size:4224b/528B) */
5239struct rx_port_stats {
5240 __le64 rx_64b_frames;
5241 __le64 rx_65b_127b_frames;
5242 __le64 rx_128b_255b_frames;
5243 __le64 rx_256b_511b_frames;
5244 __le64 rx_512b_1023b_frames;
5245 __le64 rx_1024b_1518_frames;
5246 __le64 rx_good_vlan_frames;
5247 __le64 rx_1519b_2047b_frames;
5248 __le64 rx_2048b_4095b_frames;
5249 __le64 rx_4096b_9216b_frames;
5250 __le64 rx_9217b_16383b_frames;
5251 __le64 rx_total_frames;
5252 __le64 rx_ucast_frames;
5253 __le64 rx_mcast_frames;
5254 __le64 rx_bcast_frames;
5255 __le64 rx_fcs_err_frames;
5256 __le64 rx_ctrl_frames;
5257 __le64 rx_pause_frames;
5258 __le64 rx_pfc_frames;
5259 __le64 rx_unsupported_opcode_frames;
5260 __le64 rx_unsupported_da_pausepfc_frames;
5261 __le64 rx_wrong_sa_frames;
5262 __le64 rx_align_err_frames;
5263 __le64 rx_oor_len_frames;
5264 __le64 rx_code_err_frames;
5265 __le64 rx_false_carrier_frames;
5266 __le64 rx_ovrsz_frames;
5267 __le64 rx_jbr_frames;
5268 __le64 rx_mtu_err_frames;
5269 __le64 rx_match_crc_frames;
5270 __le64 rx_promiscuous_frames;
5271 __le64 rx_tagged_frames;
5272 __le64 rx_double_tagged_frames;
5273 __le64 rx_trunc_frames;
5274 __le64 rx_good_frames;
5275 __le64 rx_pfc_xon2xoff_frames_pri0;
5276 __le64 rx_pfc_xon2xoff_frames_pri1;
5277 __le64 rx_pfc_xon2xoff_frames_pri2;
5278 __le64 rx_pfc_xon2xoff_frames_pri3;
5279 __le64 rx_pfc_xon2xoff_frames_pri4;
5280 __le64 rx_pfc_xon2xoff_frames_pri5;
5281 __le64 rx_pfc_xon2xoff_frames_pri6;
5282 __le64 rx_pfc_xon2xoff_frames_pri7;
5283 __le64 rx_pfc_ena_frames_pri0;
5284 __le64 rx_pfc_ena_frames_pri1;
5285 __le64 rx_pfc_ena_frames_pri2;
5286 __le64 rx_pfc_ena_frames_pri3;
5287 __le64 rx_pfc_ena_frames_pri4;
5288 __le64 rx_pfc_ena_frames_pri5;
5289 __le64 rx_pfc_ena_frames_pri6;
5290 __le64 rx_pfc_ena_frames_pri7;
5291 __le64 rx_sch_crc_err_frames;
5292 __le64 rx_undrsz_frames;
5293 __le64 rx_frag_frames;
5294 __le64 rx_eee_lpi_events;
5295 __le64 rx_eee_lpi_duration;
5296 __le64 rx_llfc_physical_msgs;
5297 __le64 rx_llfc_logical_msgs;
5298 __le64 rx_llfc_msgs_with_crc_err;
5299 __le64 rx_hcfc_msgs;
5300 __le64 rx_hcfc_msgs_with_crc_err;
5301 __le64 rx_bytes;
5302 __le64 rx_runt_bytes;
5303 __le64 rx_runt_frames;
5304 __le64 rx_stat_discard;
5305 __le64 rx_stat_err;
5306};
5307
5308/* hwrm_fw_reset_input (size:192b/24B) */
4973struct hwrm_fw_reset_input { 5309struct hwrm_fw_reset_input {
4974 __le16 req_type; 5310 __le16 req_type;
4975 __le16 cmpl_ring; 5311 __le16 cmpl_ring;
4976 __le16 seq_id; 5312 __le16 seq_id;
4977 __le16 target_id; 5313 __le16 target_id;
4978 __le64 resp_addr; 5314 __le64 resp_addr;
4979 u8 embedded_proc_type; 5315 u8 embedded_proc_type;
4980 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 5316 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
4981 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 5317 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
4982 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 5318 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
4983 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 5319 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
4984 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 5320 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
4985 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 5321 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
4986 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 5322 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
4987 u8 selfrst_status; 5323 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP
4988 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 5324 u8 selfrst_status;
4989 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 5325 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
4990 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 5326 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
4991 u8 host_idx; 5327 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
4992 u8 unused_0[5]; 5328 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST
4993}; 5329 u8 host_idx;
4994 5330 u8 unused_0[5];
4995/* Output (16 bytes) */ 5331};
5332
5333/* hwrm_fw_reset_output (size:128b/16B) */
4996struct hwrm_fw_reset_output { 5334struct hwrm_fw_reset_output {
4997 __le16 error_code; 5335 __le16 error_code;
4998 __le16 req_type; 5336 __le16 req_type;
4999 __le16 seq_id; 5337 __le16 seq_id;
5000 __le16 resp_len; 5338 __le16 resp_len;
5001 u8 selfrst_status; 5339 u8 selfrst_status;
5002 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 5340 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
5003 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 5341 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
5004 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 5342 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
5005 u8 unused_0; 5343 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST
5006 __le16 unused_1; 5344 u8 unused_0[6];
5007 u8 unused_2; 5345 u8 valid;
5008 u8 unused_3; 5346};
5009 u8 unused_4; 5347
5010 u8 valid; 5348/* hwrm_fw_qstatus_input (size:192b/24B) */
5011};
5012
5013/* hwrm_fw_qstatus */
5014/* Input (24 bytes) */
5015struct hwrm_fw_qstatus_input { 5349struct hwrm_fw_qstatus_input {
5016 __le16 req_type; 5350 __le16 req_type;
5017 __le16 cmpl_ring; 5351 __le16 cmpl_ring;
5018 __le16 seq_id; 5352 __le16 seq_id;
5019 __le16 target_id; 5353 __le16 target_id;
5020 __le64 resp_addr; 5354 __le64 resp_addr;
5021 u8 embedded_proc_type; 5355 u8 embedded_proc_type;
5022 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 5356 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
5023 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 5357 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
5024 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 5358 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
5025 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 5359 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
5026 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 5360 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
5027 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 5361 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
5028 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 5362 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
5029 u8 unused_0[7]; 5363 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
5030}; 5364 u8 unused_0[7];
5031 5365};
5032/* Output (16 bytes) */ 5366
5367/* hwrm_fw_qstatus_output (size:128b/16B) */
5033struct hwrm_fw_qstatus_output { 5368struct hwrm_fw_qstatus_output {
5034 __le16 error_code; 5369 __le16 error_code;
5035 __le16 req_type; 5370 __le16 req_type;
5036 __le16 seq_id; 5371 __le16 seq_id;
5037 __le16 resp_len; 5372 __le16 resp_len;
5038 u8 selfrst_status; 5373 u8 selfrst_status;
5039 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 5374 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
5040 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 5375 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
5041 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 5376 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
5042 u8 unused_0; 5377 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST
5043 __le16 unused_1; 5378 u8 unused_0[6];
5044 u8 unused_2; 5379 u8 valid;
5045 u8 unused_3; 5380};
5046 u8 unused_4; 5381
5047 u8 valid; 5382/* hwrm_fw_set_time_input (size:256b/32B) */
5048};
5049
5050/* hwrm_fw_set_time */
5051/* Input (32 bytes) */
5052struct hwrm_fw_set_time_input { 5383struct hwrm_fw_set_time_input {
5053 __le16 req_type; 5384 __le16 req_type;
5054 __le16 cmpl_ring; 5385 __le16 cmpl_ring;
5055 __le16 seq_id; 5386 __le16 seq_id;
5056 __le16 target_id; 5387 __le16 target_id;
5057 __le64 resp_addr; 5388 __le64 resp_addr;
5058 __le16 year; 5389 __le16 year;
5059 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 5390 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
5060 u8 month; 5391 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN
5061 u8 day; 5392 u8 month;
5062 u8 hour; 5393 u8 day;
5063 u8 minute; 5394 u8 hour;
5064 u8 second; 5395 u8 minute;
5065 u8 unused_0; 5396 u8 second;
5066 __le16 millisecond; 5397 u8 unused_0;
5067 __le16 zone; 5398 __le16 millisecond;
5068 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 5399 __le16 zone;
5069 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 5400 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL
5070 __le32 unused_1; 5401 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL
5071}; 5402 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN
5072 5403 u8 unused_1[4];
5073/* Output (16 bytes) */ 5404};
5405
5406/* hwrm_fw_set_time_output (size:128b/16B) */
5074struct hwrm_fw_set_time_output { 5407struct hwrm_fw_set_time_output {
5075 __le16 error_code; 5408 __le16 error_code;
5076 __le16 req_type; 5409 __le16 req_type;
5077 __le16 seq_id; 5410 __le16 seq_id;
5078 __le16 resp_len; 5411 __le16 resp_len;
5079 __le32 unused_0; 5412 u8 unused_0[7];
5080 u8 unused_1; 5413 u8 valid;
5081 u8 unused_2; 5414};
5082 u8 unused_3; 5415
5083 u8 valid; 5416/* hwrm_struct_hdr (size:128b/16B) */
5084}; 5417struct hwrm_struct_hdr {
5085 5418 __le16 struct_id;
5086/* hwrm_fw_set_structured_data */ 5419 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
5087/* Input (32 bytes) */ 5420 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
5421 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
5422 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
5423 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
5424 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
5425 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
5426 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
5427 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
5428 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
5429 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2
5430 __le16 len;
5431 u8 version;
5432 u8 count;
5433 __le16 subtype;
5434 __le16 next_offset;
5435 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
5436 u8 unused_0[6];
5437};
5438
5439/* hwrm_struct_data_dcbx_app (size:64b/8B) */
5440struct hwrm_struct_data_dcbx_app {
5441 __be16 protocol_id;
5442 u8 protocol_selector;
5443 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
5444 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
5445 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
5446 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
5447 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
5448 u8 priority;
5449 u8 valid;
5450 u8 unused_0[3];
5451};
5452
5453/* hwrm_fw_set_structured_data_input (size:256b/32B) */
5088struct hwrm_fw_set_structured_data_input { 5454struct hwrm_fw_set_structured_data_input {
5089 __le16 req_type; 5455 __le16 req_type;
5090 __le16 cmpl_ring; 5456 __le16 cmpl_ring;
5091 __le16 seq_id; 5457 __le16 seq_id;
5092 __le16 target_id; 5458 __le16 target_id;
5093 __le64 resp_addr; 5459 __le64 resp_addr;
5094 __le64 src_data_addr; 5460 __le64 src_data_addr;
5095 __le16 data_len; 5461 __le16 data_len;
5096 u8 hdr_cnt; 5462 u8 hdr_cnt;
5097 u8 unused_0[5]; 5463 u8 unused_0[5];
5098}; 5464};
5099 5465
5100/* Output (16 bytes) */ 5466/* hwrm_fw_set_structured_data_output (size:128b/16B) */
5101struct hwrm_fw_set_structured_data_output { 5467struct hwrm_fw_set_structured_data_output {
5102 __le16 error_code; 5468 __le16 error_code;
5103 __le16 req_type; 5469 __le16 req_type;
5104 __le16 seq_id; 5470 __le16 seq_id;
5105 __le16 resp_len; 5471 __le16 resp_len;
5106 __le32 unused_0; 5472 u8 unused_0[7];
5107 u8 unused_1; 5473 u8 valid;
5108 u8 unused_2; 5474};
5109 u8 unused_3; 5475
5110 u8 valid; 5476/* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
5111};
5112
5113/* Command specific Error Codes (8 bytes) */
5114struct hwrm_fw_set_structured_data_cmd_err { 5477struct hwrm_fw_set_structured_data_cmd_err {
5115 u8 code; 5478 u8 code;
5116 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 5479 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
5117 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 5480 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
5118 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 5481 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL
5119 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 5482 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
5120 u8 unused_0[7]; 5483 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
5484 u8 unused_0[7];
5121}; 5485};
5122 5486
5123/* hwrm_fw_get_structured_data */ 5487/* hwrm_fw_get_structured_data_input (size:256b/32B) */
5124/* Input (32 bytes) */
5125struct hwrm_fw_get_structured_data_input { 5488struct hwrm_fw_get_structured_data_input {
5126 __le16 req_type; 5489 __le16 req_type;
5127 __le16 cmpl_ring; 5490 __le16 cmpl_ring;
5128 __le16 seq_id; 5491 __le16 seq_id;
5129 __le16 target_id; 5492 __le16 target_id;
5130 __le64 resp_addr; 5493 __le64 resp_addr;
5131 __le64 dest_data_addr; 5494 __le64 dest_data_addr;
5132 __le16 data_len; 5495 __le16 data_len;
5133 __le16 structure_id; 5496 __le16 structure_id;
5134 __le16 subtype; 5497 __le16 subtype;
5135 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 5498 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL
5136 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 5499 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL
5137 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 5500 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL
5501 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL
5138 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 5502 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
5139 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 5503 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL
5140 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 5504 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL
5141 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 5505 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL
5142 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 5506 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL
5143 u8 count; 5507 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL
5144 u8 unused_0; 5508 u8 count;
5509 u8 unused_0;
5145}; 5510};
5146 5511
5147/* Output (16 bytes) */ 5512/* hwrm_fw_get_structured_data_output (size:128b/16B) */
5148struct hwrm_fw_get_structured_data_output { 5513struct hwrm_fw_get_structured_data_output {
5149 __le16 error_code; 5514 __le16 error_code;
5150 __le16 req_type; 5515 __le16 req_type;
5151 __le16 seq_id; 5516 __le16 seq_id;
5152 __le16 resp_len; 5517 __le16 resp_len;
5153 u8 hdr_cnt; 5518 u8 hdr_cnt;
5154 u8 unused_0; 5519 u8 unused_0[6];
5155 __le16 unused_1; 5520 u8 valid;
5156 u8 unused_2; 5521};
5157 u8 unused_3; 5522
5158 u8 unused_4; 5523/* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
5159 u8 valid;
5160};
5161
5162/* Command specific Error Codes (8 bytes) */
5163struct hwrm_fw_get_structured_data_cmd_err { 5524struct hwrm_fw_get_structured_data_cmd_err {
5164 u8 code; 5525 u8 code;
5165 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 5526 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
5166 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 5527 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
5167 u8 unused_0[7]; 5528 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
5529 u8 unused_0[7];
5168}; 5530};
5169 5531
5170/* hwrm_exec_fwd_resp */ 5532/* hwrm_exec_fwd_resp_input (size:1024b/128B) */
5171/* Input (128 bytes) */
5172struct hwrm_exec_fwd_resp_input { 5533struct hwrm_exec_fwd_resp_input {
5173 __le16 req_type; 5534 __le16 req_type;
5174 __le16 cmpl_ring; 5535 __le16 cmpl_ring;
5175 __le16 seq_id; 5536 __le16 seq_id;
5176 __le16 target_id; 5537 __le16 target_id;
5177 __le64 resp_addr; 5538 __le64 resp_addr;
5178 __le32 encap_request[26]; 5539 __le32 encap_request[26];
5179 __le16 encap_resp_target_id; 5540 __le16 encap_resp_target_id;
5180 __le16 unused_0[3]; 5541 u8 unused_0[6];
5181}; 5542};
5182 5543
5183/* Output (16 bytes) */ 5544/* hwrm_exec_fwd_resp_output (size:128b/16B) */
5184struct hwrm_exec_fwd_resp_output { 5545struct hwrm_exec_fwd_resp_output {
5185 __le16 error_code; 5546 __le16 error_code;
5186 __le16 req_type; 5547 __le16 req_type;
5187 __le16 seq_id; 5548 __le16 seq_id;
5188 __le16 resp_len; 5549 __le16 resp_len;
5189 __le32 unused_0; 5550 u8 unused_0[7];
5190 u8 unused_1; 5551 u8 valid;
5191 u8 unused_2; 5552};
5192 u8 unused_3; 5553
5193 u8 valid; 5554/* hwrm_reject_fwd_resp_input (size:1024b/128B) */
5194};
5195
5196/* hwrm_reject_fwd_resp */
5197/* Input (128 bytes) */
5198struct hwrm_reject_fwd_resp_input { 5555struct hwrm_reject_fwd_resp_input {
5199 __le16 req_type; 5556 __le16 req_type;
5200 __le16 cmpl_ring; 5557 __le16 cmpl_ring;
5201 __le16 seq_id; 5558 __le16 seq_id;
5202 __le16 target_id; 5559 __le16 target_id;
5203 __le64 resp_addr; 5560 __le64 resp_addr;
5204 __le32 encap_request[26]; 5561 __le32 encap_request[26];
5205 __le16 encap_resp_target_id; 5562 __le16 encap_resp_target_id;
5206 __le16 unused_0[3]; 5563 u8 unused_0[6];
5207}; 5564};
5208 5565
5209/* Output (16 bytes) */ 5566/* hwrm_reject_fwd_resp_output (size:128b/16B) */
5210struct hwrm_reject_fwd_resp_output { 5567struct hwrm_reject_fwd_resp_output {
5211 __le16 error_code; 5568 __le16 error_code;
5212 __le16 req_type; 5569 __le16 req_type;
5213 __le16 seq_id; 5570 __le16 seq_id;
5214 __le16 resp_len; 5571 __le16 resp_len;
5215 __le32 unused_0; 5572 u8 unused_0[7];
5216 u8 unused_1; 5573 u8 valid;
5217 u8 unused_2; 5574};
5218 u8 unused_3; 5575
5219 u8 valid; 5576/* hwrm_fwd_resp_input (size:1024b/128B) */
5220};
5221
5222/* hwrm_fwd_resp */
5223/* Input (40 bytes) */
5224struct hwrm_fwd_resp_input { 5577struct hwrm_fwd_resp_input {
5225 __le16 req_type; 5578 __le16 req_type;
5226 __le16 cmpl_ring; 5579 __le16 cmpl_ring;
5227 __le16 seq_id; 5580 __le16 seq_id;
5228 __le16 target_id; 5581 __le16 target_id;
5229 __le64 resp_addr; 5582 __le64 resp_addr;
5230 __le16 encap_resp_target_id; 5583 __le16 encap_resp_target_id;
5231 __le16 encap_resp_cmpl_ring; 5584 __le16 encap_resp_cmpl_ring;
5232 __le16 encap_resp_len; 5585 __le16 encap_resp_len;
5233 u8 unused_0; 5586 u8 unused_0;
5234 u8 unused_1; 5587 u8 unused_1;
5235 __le64 encap_resp_addr; 5588 __le64 encap_resp_addr;
5236 __le32 encap_resp[24]; 5589 __le32 encap_resp[24];
5237}; 5590};
5238 5591
5239/* Output (16 bytes) */ 5592/* hwrm_fwd_resp_output (size:128b/16B) */
5240struct hwrm_fwd_resp_output { 5593struct hwrm_fwd_resp_output {
5241 __le16 error_code; 5594 __le16 error_code;
5242 __le16 req_type; 5595 __le16 req_type;
5243 __le16 seq_id; 5596 __le16 seq_id;
5244 __le16 resp_len; 5597 __le16 resp_len;
5245 __le32 unused_0; 5598 u8 unused_0[7];
5246 u8 unused_1; 5599 u8 valid;
5247 u8 unused_2; 5600};
5248 u8 unused_3; 5601
5249 u8 valid; 5602/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
5250};
5251
5252/* hwrm_fwd_async_event_cmpl */
5253/* Input (32 bytes) */
5254struct hwrm_fwd_async_event_cmpl_input { 5603struct hwrm_fwd_async_event_cmpl_input {
5255 __le16 req_type; 5604 __le16 req_type;
5256 __le16 cmpl_ring; 5605 __le16 cmpl_ring;
5257 __le16 seq_id; 5606 __le16 seq_id;
5258 __le16 target_id; 5607 __le16 target_id;
5259 __le64 resp_addr; 5608 __le64 resp_addr;
5260 __le16 encap_async_event_target_id; 5609 __le16 encap_async_event_target_id;
5261 u8 unused_0; 5610 u8 unused_0[6];
5262 u8 unused_1; 5611 __le32 encap_async_event_cmpl[4];
5263 u8 unused_2[3]; 5612};
5264 u8 unused_3; 5613
5265 __le32 encap_async_event_cmpl[4]; 5614/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
5266};
5267
5268/* Output (16 bytes) */
5269struct hwrm_fwd_async_event_cmpl_output { 5615struct hwrm_fwd_async_event_cmpl_output {
5270 __le16 error_code; 5616 __le16 error_code;
5271 __le16 req_type; 5617 __le16 req_type;
5272 __le16 seq_id; 5618 __le16 seq_id;
5273 __le16 resp_len; 5619 __le16 resp_len;
5274 __le32 unused_0; 5620 u8 unused_0[7];
5275 u8 unused_1; 5621 u8 valid;
5276 u8 unused_2; 5622};
5277 u8 unused_3; 5623
5278 u8 valid; 5624/* hwrm_temp_monitor_query_input (size:128b/16B) */
5279};
5280
5281/* hwrm_temp_monitor_query */
5282/* Input (16 bytes) */
5283struct hwrm_temp_monitor_query_input { 5625struct hwrm_temp_monitor_query_input {
5284 __le16 req_type; 5626 __le16 req_type;
5285 __le16 cmpl_ring; 5627 __le16 cmpl_ring;
5286 __le16 seq_id; 5628 __le16 seq_id;
5287 __le16 target_id; 5629 __le16 target_id;
5288 __le64 resp_addr; 5630 __le64 resp_addr;
5289}; 5631};
5290 5632
5291/* Output (16 bytes) */ 5633/* hwrm_temp_monitor_query_output (size:128b/16B) */
5292struct hwrm_temp_monitor_query_output { 5634struct hwrm_temp_monitor_query_output {
5293 __le16 error_code; 5635 __le16 error_code;
5294 __le16 req_type; 5636 __le16 req_type;
5295 __le16 seq_id; 5637 __le16 seq_id;
5296 __le16 resp_len; 5638 __le16 resp_len;
5297 u8 temp; 5639 u8 temp;
5298 u8 unused_0; 5640 u8 unused_0[6];
5299 __le16 unused_1; 5641 u8 valid;
5300 u8 unused_2; 5642};
5301 u8 unused_3; 5643
5302 u8 unused_4; 5644/* hwrm_wol_filter_alloc_input (size:512b/64B) */
5303 u8 valid;
5304};
5305
5306/* hwrm_wol_filter_alloc */
5307/* Input (64 bytes) */
5308struct hwrm_wol_filter_alloc_input { 5645struct hwrm_wol_filter_alloc_input {
5309 __le16 req_type; 5646 __le16 req_type;
5310 __le16 cmpl_ring; 5647 __le16 cmpl_ring;
5311 __le16 seq_id; 5648 __le16 seq_id;
5312 __le16 target_id; 5649 __le16 target_id;
5313 __le64 resp_addr; 5650 __le64 resp_addr;
5314 __le32 flags; 5651 __le32 flags;
5315 __le32 enables; 5652 __le32 enables;
5316 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 5653 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL
5317 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 5654 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL
5318 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 5655 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL
5319 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 5656 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL
5320 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 5657 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL
5321 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 5658 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL
5322 __le16 port_id; 5659 __le16 port_id;
5323 u8 wol_type; 5660 u8 wol_type;
5324 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 5661 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
5325 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 5662 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL
5326 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 5663 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL
5327 u8 unused_0; 5664 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
5328 __le32 unused_1; 5665 u8 unused_0[5];
5329 u8 mac_address[6]; 5666 u8 mac_address[6];
5330 __le16 pattern_offset; 5667 __le16 pattern_offset;
5331 __le16 pattern_buf_size; 5668 __le16 pattern_buf_size;
5332 __le16 pattern_mask_size; 5669 __le16 pattern_mask_size;
5333 __le32 unused_2; 5670 u8 unused_1[4];
5334 __le64 pattern_buf_addr; 5671 __le64 pattern_buf_addr;
5335 __le64 pattern_mask_addr; 5672 __le64 pattern_mask_addr;
5336}; 5673};
5337 5674
5338/* Output (16 bytes) */ 5675/* hwrm_wol_filter_alloc_output (size:128b/16B) */
5339struct hwrm_wol_filter_alloc_output { 5676struct hwrm_wol_filter_alloc_output {
5340 __le16 error_code; 5677 __le16 error_code;
5341 __le16 req_type; 5678 __le16 req_type;
5342 __le16 seq_id; 5679 __le16 seq_id;
5343 __le16 resp_len; 5680 __le16 resp_len;
5344 u8 wol_filter_id; 5681 u8 wol_filter_id;
5345 u8 unused_0; 5682 u8 unused_0[6];
5346 __le16 unused_1; 5683 u8 valid;
5347 u8 unused_2; 5684};
5348 u8 unused_3; 5685
5349 u8 unused_4; 5686/* hwrm_wol_filter_free_input (size:256b/32B) */
5350 u8 valid;
5351};
5352
5353/* hwrm_wol_filter_free */
5354/* Input (32 bytes) */
5355struct hwrm_wol_filter_free_input { 5687struct hwrm_wol_filter_free_input {
5356 __le16 req_type; 5688 __le16 req_type;
5357 __le16 cmpl_ring; 5689 __le16 cmpl_ring;
5358 __le16 seq_id; 5690 __le16 seq_id;
5359 __le16 target_id; 5691 __le16 target_id;
5360 __le64 resp_addr; 5692 __le64 resp_addr;
5361 __le32 flags; 5693 __le32 flags;
5362 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 5694 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL
5363 __le32 enables; 5695 __le32 enables;
5364 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 5696 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL
5365 __le16 port_id; 5697 __le16 port_id;
5366 u8 wol_filter_id; 5698 u8 wol_filter_id;
5367 u8 unused_0[5]; 5699 u8 unused_0[5];
5368}; 5700};
5369 5701
5370/* Output (16 bytes) */ 5702/* hwrm_wol_filter_free_output (size:128b/16B) */
5371struct hwrm_wol_filter_free_output { 5703struct hwrm_wol_filter_free_output {
5372 __le16 error_code; 5704 __le16 error_code;
5373 __le16 req_type; 5705 __le16 req_type;
5374 __le16 seq_id; 5706 __le16 seq_id;
5375 __le16 resp_len; 5707 __le16 resp_len;
5376 __le32 unused_0; 5708 u8 unused_0[7];
5377 u8 unused_1; 5709 u8 valid;
5378 u8 unused_2; 5710};
5379 u8 unused_3; 5711
5380 u8 valid; 5712/* hwrm_wol_filter_qcfg_input (size:448b/56B) */
5381};
5382
5383/* hwrm_wol_filter_qcfg */
5384/* Input (56 bytes) */
5385struct hwrm_wol_filter_qcfg_input { 5713struct hwrm_wol_filter_qcfg_input {
5386 __le16 req_type; 5714 __le16 req_type;
5387 __le16 cmpl_ring; 5715 __le16 cmpl_ring;
5388 __le16 seq_id; 5716 __le16 seq_id;
5389 __le16 target_id; 5717 __le16 target_id;
5390 __le64 resp_addr; 5718 __le64 resp_addr;
5391 __le16 port_id; 5719 __le16 port_id;
5392 __le16 handle; 5720 __le16 handle;
5393 __le32 unused_0; 5721 u8 unused_0[4];
5394 __le64 pattern_buf_addr; 5722 __le64 pattern_buf_addr;
5395 __le16 pattern_buf_size; 5723 __le16 pattern_buf_size;
5396 u8 unused_1; 5724 u8 unused_1[6];
5397 u8 unused_2; 5725 __le64 pattern_mask_addr;
5398 u8 unused_3[3]; 5726 __le16 pattern_mask_size;
5399 u8 unused_4; 5727 u8 unused_2[6];
5400 __le64 pattern_mask_addr; 5728};
5401 __le16 pattern_mask_size; 5729
5402 __le16 unused_5[3]; 5730/* hwrm_wol_filter_qcfg_output (size:256b/32B) */
5403};
5404
5405/* Output (32 bytes) */
5406struct hwrm_wol_filter_qcfg_output { 5731struct hwrm_wol_filter_qcfg_output {
5407 __le16 error_code; 5732 __le16 error_code;
5408 __le16 req_type; 5733 __le16 req_type;
5409 __le16 seq_id; 5734 __le16 seq_id;
5410 __le16 resp_len; 5735 __le16 resp_len;
5411 __le16 next_handle; 5736 __le16 next_handle;
5412 u8 wol_filter_id; 5737 u8 wol_filter_id;
5413 u8 wol_type; 5738 u8 wol_type;
5414 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 5739 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
5415 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 5740 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL
5416 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 5741 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL
5417 __le32 unused_0; 5742 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
5418 u8 mac_address[6]; 5743 __le32 unused_0;
5419 __le16 pattern_offset; 5744 u8 mac_address[6];
5420 __le16 pattern_size; 5745 __le16 pattern_offset;
5421 __le16 pattern_mask_size; 5746 __le16 pattern_size;
5422 u8 unused_1; 5747 __le16 pattern_mask_size;
5423 u8 unused_2; 5748 u8 unused_1[3];
5424 u8 unused_3; 5749 u8 valid;
5425 u8 valid; 5750};
5426}; 5751
5427 5752/* hwrm_wol_reason_qcfg_input (size:320b/40B) */
5428/* hwrm_wol_reason_qcfg */
5429/* Input (40 bytes) */
5430struct hwrm_wol_reason_qcfg_input { 5753struct hwrm_wol_reason_qcfg_input {
5431 __le16 req_type; 5754 __le16 req_type;
5432 __le16 cmpl_ring; 5755 __le16 cmpl_ring;
5433 __le16 seq_id; 5756 __le16 seq_id;
5434 __le16 target_id; 5757 __le16 target_id;
5435 __le64 resp_addr; 5758 __le64 resp_addr;
5436 __le16 port_id; 5759 __le16 port_id;
5437 u8 unused_0; 5760 u8 unused_0[6];
5438 u8 unused_1; 5761 __le64 wol_pkt_buf_addr;
5439 u8 unused_2[3]; 5762 __le16 wol_pkt_buf_size;
5440 u8 unused_3; 5763 u8 unused_1[6];
5441 __le64 wol_pkt_buf_addr; 5764};
5442 __le16 wol_pkt_buf_size; 5765
5443 __le16 unused_4[3]; 5766/* hwrm_wol_reason_qcfg_output (size:128b/16B) */
5444};
5445
5446/* Output (16 bytes) */
5447struct hwrm_wol_reason_qcfg_output { 5767struct hwrm_wol_reason_qcfg_output {
5448 __le16 error_code; 5768 __le16 error_code;
5449 __le16 req_type; 5769 __le16 req_type;
5450 __le16 seq_id; 5770 __le16 seq_id;
5451 __le16 resp_len; 5771 __le16 resp_len;
5452 u8 wol_filter_id; 5772 u8 wol_filter_id;
5453 u8 wol_reason; 5773 u8 wol_reason;
5454 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 5774 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
5455 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 5775 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL
5456 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 5776 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL
5457 u8 wol_pkt_len; 5777 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
5458 u8 unused_0; 5778 u8 wol_pkt_len;
5459 u8 unused_1; 5779 u8 unused_0[4];
5460 u8 unused_2; 5780 u8 valid;
5461 u8 unused_3; 5781};
5462 u8 valid; 5782
5463}; 5783/* hwrm_nvm_read_input (size:320b/40B) */
5464
5465/* hwrm_dbg_read_direct */
5466/* Input (32 bytes) */
5467struct hwrm_dbg_read_direct_input {
5468 __le16 req_type;
5469 __le16 cmpl_ring;
5470 __le16 seq_id;
5471 __le16 target_id;
5472 __le64 resp_addr;
5473 __le64 host_dest_addr;
5474 __le32 read_addr;
5475 __le32 read_len32;
5476};
5477
5478/* Output (16 bytes) */
5479struct hwrm_dbg_read_direct_output {
5480 __le16 error_code;
5481 __le16 req_type;
5482 __le16 seq_id;
5483 __le16 resp_len;
5484 __le32 unused_0;
5485 u8 unused_1;
5486 u8 unused_2;
5487 u8 unused_3;
5488 u8 valid;
5489};
5490
5491/* hwrm_nvm_read */
5492/* Input (40 bytes) */
5493struct hwrm_nvm_read_input { 5784struct hwrm_nvm_read_input {
5494 __le16 req_type; 5785 __le16 req_type;
5495 __le16 cmpl_ring; 5786 __le16 cmpl_ring;
5496 __le16 seq_id; 5787 __le16 seq_id;
5497 __le16 target_id; 5788 __le16 target_id;
5498 __le64 resp_addr; 5789 __le64 resp_addr;
5499 __le64 host_dest_addr; 5790 __le64 host_dest_addr;
5500 __le16 dir_idx; 5791 __le16 dir_idx;
5501 u8 unused_0; 5792 u8 unused_0[2];
5502 u8 unused_1; 5793 __le32 offset;
5503 __le32 offset; 5794 __le32 len;
5504 __le32 len; 5795 u8 unused_1[4];
5505 __le32 unused_2; 5796};
5506}; 5797
5507 5798/* hwrm_nvm_read_output (size:128b/16B) */
5508/* Output (16 bytes) */
5509struct hwrm_nvm_read_output { 5799struct hwrm_nvm_read_output {
5510 __le16 error_code; 5800 __le16 error_code;
5511 __le16 req_type; 5801 __le16 req_type;
5512 __le16 seq_id; 5802 __le16 seq_id;
5513 __le16 resp_len; 5803 __le16 resp_len;
5514 __le32 unused_0; 5804 u8 unused_0[7];
5515 u8 unused_1; 5805 u8 valid;
5516 u8 unused_2; 5806};
5517 u8 unused_3; 5807
5518 u8 valid; 5808/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
5519};
5520
5521/* hwrm_nvm_get_dir_entries */
5522/* Input (24 bytes) */
5523struct hwrm_nvm_get_dir_entries_input { 5809struct hwrm_nvm_get_dir_entries_input {
5524 __le16 req_type; 5810 __le16 req_type;
5525 __le16 cmpl_ring; 5811 __le16 cmpl_ring;
5526 __le16 seq_id; 5812 __le16 seq_id;
5527 __le16 target_id; 5813 __le16 target_id;
5528 __le64 resp_addr; 5814 __le64 resp_addr;
5529 __le64 host_dest_addr; 5815 __le64 host_dest_addr;
5530}; 5816};
5531 5817
5532/* Output (16 bytes) */ 5818/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
5533struct hwrm_nvm_get_dir_entries_output { 5819struct hwrm_nvm_get_dir_entries_output {
5534 __le16 error_code; 5820 __le16 error_code;
5535 __le16 req_type; 5821 __le16 req_type;
5536 __le16 seq_id; 5822 __le16 seq_id;
5537 __le16 resp_len; 5823 __le16 resp_len;
5538 __le32 unused_0; 5824 u8 unused_0[7];
5539 u8 unused_1; 5825 u8 valid;
5540 u8 unused_2; 5826};
5541 u8 unused_3; 5827
5542 u8 valid; 5828/* hwrm_nvm_get_dir_info_input (size:128b/16B) */
5543};
5544
5545/* hwrm_nvm_get_dir_info */
5546/* Input (16 bytes) */
5547struct hwrm_nvm_get_dir_info_input { 5829struct hwrm_nvm_get_dir_info_input {
5548 __le16 req_type; 5830 __le16 req_type;
5549 __le16 cmpl_ring; 5831 __le16 cmpl_ring;
5550 __le16 seq_id; 5832 __le16 seq_id;
5551 __le16 target_id; 5833 __le16 target_id;
5552 __le64 resp_addr; 5834 __le64 resp_addr;
5553}; 5835};
5554 5836
5555/* Output (24 bytes) */ 5837/* hwrm_nvm_get_dir_info_output (size:192b/24B) */
5556struct hwrm_nvm_get_dir_info_output { 5838struct hwrm_nvm_get_dir_info_output {
5557 __le16 error_code; 5839 __le16 error_code;
5558 __le16 req_type; 5840 __le16 req_type;
5559 __le16 seq_id; 5841 __le16 seq_id;
5560 __le16 resp_len; 5842 __le16 resp_len;
5561 __le32 entries; 5843 __le32 entries;
5562 __le32 entry_length; 5844 __le32 entry_length;
5563 __le32 unused_0; 5845 u8 unused_0[7];
5564 u8 unused_1; 5846 u8 valid;
5565 u8 unused_2; 5847};
5566 u8 unused_3; 5848
5567 u8 valid; 5849/* hwrm_nvm_write_input (size:384b/48B) */
5568};
5569
5570/* hwrm_nvm_write */
5571/* Input (48 bytes) */
5572struct hwrm_nvm_write_input { 5850struct hwrm_nvm_write_input {
5573 __le16 req_type; 5851 __le16 req_type;
5574 __le16 cmpl_ring; 5852 __le16 cmpl_ring;
5575 __le16 seq_id; 5853 __le16 seq_id;
5576 __le16 target_id; 5854 __le16 target_id;
5577 __le64 resp_addr; 5855 __le64 resp_addr;
5578 __le64 host_src_addr; 5856 __le64 host_src_addr;
5579 __le16 dir_type; 5857 __le16 dir_type;
5580 __le16 dir_ordinal; 5858 __le16 dir_ordinal;
5581 __le16 dir_ext; 5859 __le16 dir_ext;
5582 __le16 dir_attr; 5860 __le16 dir_attr;
5583 __le32 dir_data_length; 5861 __le32 dir_data_length;
5584 __le16 option; 5862 __le16 option;
5585 __le16 flags; 5863 __le16 flags;
5586 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 5864 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
5587 __le32 dir_item_length; 5865 __le32 dir_item_length;
5588 __le32 unused_0; 5866 __le32 unused_0;
5589}; 5867};
5590 5868
5591/* Output (16 bytes) */ 5869/* hwrm_nvm_write_output (size:128b/16B) */
5592struct hwrm_nvm_write_output { 5870struct hwrm_nvm_write_output {
5593 __le16 error_code; 5871 __le16 error_code;
5594 __le16 req_type; 5872 __le16 req_type;
5595 __le16 seq_id; 5873 __le16 seq_id;
5596 __le16 resp_len; 5874 __le16 resp_len;
5597 __le32 dir_item_length; 5875 __le32 dir_item_length;
5598 __le16 dir_idx; 5876 __le16 dir_idx;
5599 u8 unused_0; 5877 u8 unused_0;
5600 u8 valid; 5878 u8 valid;
5601}; 5879};
5602 5880
5603/* Command specific Error Codes (8 bytes) */ 5881/* hwrm_nvm_write_cmd_err (size:64b/8B) */
5604struct hwrm_nvm_write_cmd_err { 5882struct hwrm_nvm_write_cmd_err {
5605 u8 code; 5883 u8 code;
5606 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 5884 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL
5607 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 5885 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
5608 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 5886 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
5609 u8 unused_0[7]; 5887 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE
5888 u8 unused_0[7];
5610}; 5889};
5611 5890
5612/* hwrm_nvm_modify */ 5891/* hwrm_nvm_modify_input (size:320b/40B) */
5613/* Input (40 bytes) */
5614struct hwrm_nvm_modify_input { 5892struct hwrm_nvm_modify_input {
5615 __le16 req_type; 5893 __le16 req_type;
5616 __le16 cmpl_ring; 5894 __le16 cmpl_ring;
5617 __le16 seq_id; 5895 __le16 seq_id;
5618 __le16 target_id; 5896 __le16 target_id;
5619 __le64 resp_addr; 5897 __le64 resp_addr;
5620 __le64 host_src_addr; 5898 __le64 host_src_addr;
5621 __le16 dir_idx; 5899 __le16 dir_idx;
5622 u8 unused_0; 5900 u8 unused_0[2];
5623 u8 unused_1; 5901 __le32 offset;
5624 __le32 offset; 5902 __le32 len;
5625 __le32 len; 5903 u8 unused_1[4];
5626 __le32 unused_2; 5904};
5627}; 5905
5628 5906/* hwrm_nvm_modify_output (size:128b/16B) */
5629/* Output (16 bytes) */
5630struct hwrm_nvm_modify_output { 5907struct hwrm_nvm_modify_output {
5631 __le16 error_code; 5908 __le16 error_code;
5632 __le16 req_type; 5909 __le16 req_type;
5633 __le16 seq_id; 5910 __le16 seq_id;
5634 __le16 resp_len; 5911 __le16 resp_len;
5635 __le32 unused_0; 5912 u8 unused_0[7];
5636 u8 unused_1; 5913 u8 valid;
5637 u8 unused_2; 5914};
5638 u8 unused_3; 5915
5639 u8 valid; 5916/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
5640};
5641
5642/* hwrm_nvm_find_dir_entry */
5643/* Input (32 bytes) */
5644struct hwrm_nvm_find_dir_entry_input { 5917struct hwrm_nvm_find_dir_entry_input {
5645 __le16 req_type; 5918 __le16 req_type;
5646 __le16 cmpl_ring; 5919 __le16 cmpl_ring;
5647 __le16 seq_id; 5920 __le16 seq_id;
5648 __le16 target_id; 5921 __le16 target_id;
5649 __le64 resp_addr; 5922 __le64 resp_addr;
5650 __le32 enables; 5923 __le32 enables;
5651 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 5924 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
5652 __le16 dir_idx; 5925 __le16 dir_idx;
5653 __le16 dir_type; 5926 __le16 dir_type;
5654 __le16 dir_ordinal; 5927 __le16 dir_ordinal;
5655 __le16 dir_ext; 5928 __le16 dir_ext;
5656 u8 opt_ordinal; 5929 u8 opt_ordinal;
5657 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 5930 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
5658 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 5931 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
5659 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 5932 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL
5660 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 5933 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL
5661 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 5934 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL
5662 u8 unused_1[3]; 5935 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
5663}; 5936 u8 unused_0[3];
5664 5937};
5665/* Output (32 bytes) */ 5938
5939/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
5666struct hwrm_nvm_find_dir_entry_output { 5940struct hwrm_nvm_find_dir_entry_output {
5667 __le16 error_code; 5941 __le16 error_code;
5668 __le16 req_type; 5942 __le16 req_type;
5669 __le16 seq_id; 5943 __le16 seq_id;
5670 __le16 resp_len; 5944 __le16 resp_len;
5671 __le32 dir_item_length; 5945 __le32 dir_item_length;
5672 __le32 dir_data_length; 5946 __le32 dir_data_length;
5673 __le32 fw_ver; 5947 __le32 fw_ver;
5674 __le16 dir_ordinal; 5948 __le16 dir_ordinal;
5675 __le16 dir_idx; 5949 __le16 dir_idx;
5676 __le32 unused_0; 5950 u8 unused_0[7];
5677 u8 unused_1; 5951 u8 valid;
5678 u8 unused_2; 5952};
5679 u8 unused_3; 5953
5680 u8 valid; 5954/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
5681};
5682
5683/* hwrm_nvm_erase_dir_entry */
5684/* Input (24 bytes) */
5685struct hwrm_nvm_erase_dir_entry_input { 5955struct hwrm_nvm_erase_dir_entry_input {
5686 __le16 req_type; 5956 __le16 req_type;
5687 __le16 cmpl_ring; 5957 __le16 cmpl_ring;
5688 __le16 seq_id; 5958 __le16 seq_id;
5689 __le16 target_id; 5959 __le16 target_id;
5690 __le64 resp_addr; 5960 __le64 resp_addr;
5691 __le16 dir_idx; 5961 __le16 dir_idx;
5692 __le16 unused_0[3]; 5962 u8 unused_0[6];
5693}; 5963};
5694 5964
5695/* Output (16 bytes) */ 5965/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
5696struct hwrm_nvm_erase_dir_entry_output { 5966struct hwrm_nvm_erase_dir_entry_output {
5697 __le16 error_code; 5967 __le16 error_code;
5698 __le16 req_type; 5968 __le16 req_type;
5699 __le16 seq_id; 5969 __le16 seq_id;
5700 __le16 resp_len; 5970 __le16 resp_len;
5701 __le32 unused_0; 5971 u8 unused_0[7];
5702 u8 unused_1; 5972 u8 valid;
5703 u8 unused_2; 5973};
5704 u8 unused_3; 5974
5705 u8 valid; 5975/* hwrm_nvm_get_dev_info_input (size:128b/16B) */
5706};
5707
5708/* hwrm_nvm_get_dev_info */
5709/* Input (16 bytes) */
5710struct hwrm_nvm_get_dev_info_input { 5976struct hwrm_nvm_get_dev_info_input {
5711 __le16 req_type; 5977 __le16 req_type;
5712 __le16 cmpl_ring; 5978 __le16 cmpl_ring;
5713 __le16 seq_id; 5979 __le16 seq_id;
5714 __le16 target_id; 5980 __le16 target_id;
5715 __le64 resp_addr; 5981 __le64 resp_addr;
5716}; 5982};
5717 5983
5718/* Output (32 bytes) */ 5984/* hwrm_nvm_get_dev_info_output (size:256b/32B) */
5719struct hwrm_nvm_get_dev_info_output { 5985struct hwrm_nvm_get_dev_info_output {
5720 __le16 error_code; 5986 __le16 error_code;
5721 __le16 req_type; 5987 __le16 req_type;
5722 __le16 seq_id; 5988 __le16 seq_id;
5723 __le16 resp_len; 5989 __le16 resp_len;
5724 __le16 manufacturer_id; 5990 __le16 manufacturer_id;
5725 __le16 device_id; 5991 __le16 device_id;
5726 __le32 sector_size; 5992 __le32 sector_size;
5727 __le32 nvram_size; 5993 __le32 nvram_size;
5728 __le32 reserved_size; 5994 __le32 reserved_size;
5729 __le32 available_size; 5995 __le32 available_size;
5730 u8 unused_0; 5996 u8 unused_0[3];
5731 u8 unused_1; 5997 u8 valid;
5732 u8 unused_2; 5998};
5733 u8 valid; 5999
5734}; 6000/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
5735
5736/* hwrm_nvm_mod_dir_entry */
5737/* Input (32 bytes) */
5738struct hwrm_nvm_mod_dir_entry_input { 6001struct hwrm_nvm_mod_dir_entry_input {
5739 __le16 req_type; 6002 __le16 req_type;
5740 __le16 cmpl_ring; 6003 __le16 cmpl_ring;
5741 __le16 seq_id; 6004 __le16 seq_id;
5742 __le16 target_id; 6005 __le16 target_id;
5743 __le64 resp_addr; 6006 __le64 resp_addr;
5744 __le32 enables; 6007 __le32 enables;
5745 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 6008 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
5746 __le16 dir_idx; 6009 __le16 dir_idx;
5747 __le16 dir_ordinal; 6010 __le16 dir_ordinal;
5748 __le16 dir_ext; 6011 __le16 dir_ext;
5749 __le16 dir_attr; 6012 __le16 dir_attr;
5750 __le32 checksum; 6013 __le32 checksum;
5751}; 6014};
5752 6015
5753/* Output (16 bytes) */ 6016/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
5754struct hwrm_nvm_mod_dir_entry_output { 6017struct hwrm_nvm_mod_dir_entry_output {
5755 __le16 error_code; 6018 __le16 error_code;
5756 __le16 req_type; 6019 __le16 req_type;
5757 __le16 seq_id; 6020 __le16 seq_id;
5758 __le16 resp_len; 6021 __le16 resp_len;
5759 __le32 unused_0; 6022 u8 unused_0[7];
5760 u8 unused_1; 6023 u8 valid;
5761 u8 unused_2; 6024};
5762 u8 unused_3; 6025
5763 u8 valid; 6026/* hwrm_nvm_verify_update_input (size:192b/24B) */
5764};
5765
5766/* hwrm_nvm_verify_update */
5767/* Input (24 bytes) */
5768struct hwrm_nvm_verify_update_input { 6027struct hwrm_nvm_verify_update_input {
5769 __le16 req_type; 6028 __le16 req_type;
5770 __le16 cmpl_ring; 6029 __le16 cmpl_ring;
5771 __le16 seq_id; 6030 __le16 seq_id;
5772 __le16 target_id; 6031 __le16 target_id;
5773 __le64 resp_addr; 6032 __le64 resp_addr;
5774 __le16 dir_type; 6033 __le16 dir_type;
5775 __le16 dir_ordinal; 6034 __le16 dir_ordinal;
5776 __le16 dir_ext; 6035 __le16 dir_ext;
5777 __le16 unused_0; 6036 u8 unused_0[2];
5778}; 6037};
5779 6038
5780/* Output (16 bytes) */ 6039/* hwrm_nvm_verify_update_output (size:128b/16B) */
5781struct hwrm_nvm_verify_update_output { 6040struct hwrm_nvm_verify_update_output {
5782 __le16 error_code; 6041 __le16 error_code;
5783 __le16 req_type; 6042 __le16 req_type;
5784 __le16 seq_id; 6043 __le16 seq_id;
5785 __le16 resp_len; 6044 __le16 resp_len;
5786 __le32 unused_0; 6045 u8 unused_0[7];
5787 u8 unused_1; 6046 u8 valid;
5788 u8 unused_2; 6047};
5789 u8 unused_3; 6048
5790 u8 valid; 6049/* hwrm_nvm_install_update_input (size:192b/24B) */
5791};
5792
5793/* hwrm_nvm_install_update */
5794/* Input (24 bytes) */
5795struct hwrm_nvm_install_update_input { 6050struct hwrm_nvm_install_update_input {
5796 __le16 req_type; 6051 __le16 req_type;
5797 __le16 cmpl_ring; 6052 __le16 cmpl_ring;
5798 __le16 seq_id; 6053 __le16 seq_id;
5799 __le16 target_id; 6054 __le16 target_id;
5800 __le64 resp_addr; 6055 __le64 resp_addr;
5801 __le32 install_type; 6056 __le32 install_type;
5802 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 6057 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
5803 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 6058 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL
5804 __le16 flags; 6059 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
5805 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 6060 __le16 flags;
5806 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 6061 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL
5807 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 6062 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL
5808 __le16 unused_0; 6063 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL
5809}; 6064 u8 unused_0[2];
5810 6065};
5811/* Output (24 bytes) */ 6066
6067/* hwrm_nvm_install_update_output (size:192b/24B) */
5812struct hwrm_nvm_install_update_output { 6068struct hwrm_nvm_install_update_output {
5813 __le16 error_code; 6069 __le16 error_code;
5814 __le16 req_type; 6070 __le16 req_type;
5815 __le16 seq_id; 6071 __le16 seq_id;
5816 __le16 resp_len; 6072 __le16 resp_len;
5817 __le64 installed_items; 6073 __le64 installed_items;
5818 u8 result; 6074 u8 result;
5819 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 6075 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
5820 u8 problem_item; 6076 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS
5821 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 6077 u8 problem_item;
5822 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 6078 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL
5823 u8 reset_required; 6079 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
5824 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 6080 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
5825 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 6081 u8 reset_required;
5826 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 6082 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL
5827 u8 unused_0; 6083 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL
5828 u8 unused_1; 6084 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
5829 u8 unused_2; 6085 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
5830 u8 unused_3; 6086 u8 unused_0[4];
5831 u8 valid; 6087 u8 valid;
5832}; 6088};
5833 6089
5834/* Command specific Error Codes (8 bytes) */ 6090/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
5835struct hwrm_nvm_install_update_cmd_err { 6091struct hwrm_nvm_install_update_cmd_err {
5836 u8 code; 6092 u8 code;
5837 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 6093 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL
5838 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 6094 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
5839 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 6095 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
5840 u8 unused_0[7]; 6096 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
6097 u8 unused_0[7];
5841}; 6098};
5842 6099
5843/* hwrm_nvm_get_variable */ 6100/* hwrm_nvm_get_variable_input (size:320b/40B) */
5844/* Input (40 bytes) */
5845struct hwrm_nvm_get_variable_input { 6101struct hwrm_nvm_get_variable_input {
5846 __le16 req_type; 6102 __le16 req_type;
5847 __le16 cmpl_ring; 6103 __le16 cmpl_ring;
5848 __le16 seq_id; 6104 __le16 seq_id;
5849 __le16 target_id; 6105 __le16 target_id;
5850 __le64 resp_addr; 6106 __le64 resp_addr;
5851 __le64 dest_data_addr; 6107 __le64 dest_data_addr;
5852 __le16 data_len; 6108 __le16 data_len;
5853 __le16 option_num; 6109 __le16 option_num;
5854 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 6110 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
5855 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 6111 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
5856 __le16 dimensions; 6112 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
5857 __le16 index_0; 6113 __le16 dimensions;
5858 __le16 index_1; 6114 __le16 index_0;
5859 __le16 index_2; 6115 __le16 index_1;
5860 __le16 index_3; 6116 __le16 index_2;
5861 u8 flags; 6117 __le16 index_3;
5862 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 6118 u8 flags;
5863 u8 unused_0; 6119 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL
5864}; 6120 u8 unused_0;
5865 6121};
5866/* Output (16 bytes) */ 6122
6123/* hwrm_nvm_get_variable_output (size:128b/16B) */
5867struct hwrm_nvm_get_variable_output { 6124struct hwrm_nvm_get_variable_output {
5868 __le16 error_code; 6125 __le16 error_code;
5869 __le16 req_type; 6126 __le16 req_type;
5870 __le16 seq_id; 6127 __le16 seq_id;
5871 __le16 resp_len; 6128 __le16 resp_len;
5872 __le16 data_len; 6129 __le16 data_len;
5873 __le16 option_num; 6130 __le16 option_num;
5874 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 6131 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL
5875 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 6132 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
5876 u8 unused_0; 6133 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
5877 u8 unused_1; 6134 u8 unused_0[3];
5878 u8 unused_2; 6135 u8 valid;
5879 u8 valid; 6136};
5880}; 6137
5881 6138/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
5882/* Command specific Error Codes (8 bytes) */
5883struct hwrm_nvm_get_variable_cmd_err { 6139struct hwrm_nvm_get_variable_cmd_err {
5884 u8 code; 6140 u8 code;
5885 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 6141 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
5886 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 6142 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
5887 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 6143 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
5888 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 6144 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
5889 u8 unused_0[7]; 6145 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
6146 u8 unused_0[7];
5890}; 6147};
5891 6148
5892/* hwrm_nvm_set_variable */ 6149/* hwrm_nvm_set_variable_input (size:320b/40B) */
5893/* Input (40 bytes) */
5894struct hwrm_nvm_set_variable_input { 6150struct hwrm_nvm_set_variable_input {
5895 __le16 req_type; 6151 __le16 req_type;
5896 __le16 cmpl_ring; 6152 __le16 cmpl_ring;
5897 __le16 seq_id; 6153 __le16 seq_id;
5898 __le16 target_id; 6154 __le16 target_id;
5899 __le64 resp_addr; 6155 __le64 resp_addr;
5900 __le64 src_data_addr; 6156 __le64 src_data_addr;
5901 __le16 data_len; 6157 __le16 data_len;
5902 __le16 option_num; 6158 __le16 option_num;
5903 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 6159 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
5904 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 6160 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
5905 __le16 dimensions; 6161 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
5906 __le16 index_0; 6162 __le16 dimensions;
5907 __le16 index_1; 6163 __le16 index_0;
5908 __le16 index_2; 6164 __le16 index_1;
5909 __le16 index_3; 6165 __le16 index_2;
5910 u8 flags; 6166 __le16 index_3;
5911 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 6167 u8 flags;
5912 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 6168 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL
5913 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 6169 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL
5914 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 6170 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1
5915 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 6171 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1)
5916 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 6172 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1)
5917 u8 unused_0; 6173 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1
5918}; 6174 u8 unused_0;
5919 6175};
5920/* Output (16 bytes) */ 6176
6177/* hwrm_nvm_set_variable_output (size:128b/16B) */
5921struct hwrm_nvm_set_variable_output { 6178struct hwrm_nvm_set_variable_output {
5922 __le16 error_code; 6179 __le16 error_code;
5923 __le16 req_type; 6180 __le16 req_type;
5924 __le16 seq_id; 6181 __le16 seq_id;
5925 __le16 resp_len; 6182 __le16 resp_len;
5926 __le32 unused_0; 6183 u8 unused_0[7];
5927 u8 unused_1; 6184 u8 valid;
5928 u8 unused_2; 6185};
5929 u8 unused_3; 6186
5930 u8 valid; 6187/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
5931};
5932
5933/* Command specific Error Codes (8 bytes) */
5934struct hwrm_nvm_set_variable_cmd_err { 6188struct hwrm_nvm_set_variable_cmd_err {
5935 u8 code; 6189 u8 code;
5936 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 6190 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
5937 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 6191 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
5938 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 6192 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
5939 u8 unused_0[7]; 6193 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
6194 u8 unused_0[7];
5940}; 6195};
5941 6196
5942/* hwrm_selftest_qlist */ 6197/* hwrm_selftest_qlist_input (size:128b/16B) */
5943/* Input (16 bytes) */
5944struct hwrm_selftest_qlist_input { 6198struct hwrm_selftest_qlist_input {
5945 __le16 req_type; 6199 __le16 req_type;
5946 __le16 cmpl_ring; 6200 __le16 cmpl_ring;
5947 __le16 seq_id; 6201 __le16 seq_id;
5948 __le16 target_id; 6202 __le16 target_id;
5949 __le64 resp_addr; 6203 __le64 resp_addr;
5950}; 6204};
5951 6205
5952/* Output (280 bytes) */ 6206/* hwrm_selftest_qlist_output (size:2240b/280B) */
5953struct hwrm_selftest_qlist_output { 6207struct hwrm_selftest_qlist_output {
5954 __le16 error_code; 6208 __le16 error_code;
5955 __le16 req_type; 6209 __le16 req_type;
5956 __le16 seq_id; 6210 __le16 seq_id;
5957 __le16 resp_len; 6211 __le16 resp_len;
5958 u8 num_tests; 6212 u8 num_tests;
5959 u8 available_tests; 6213 u8 available_tests;
5960 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 6214 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL
5961 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 6215 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL
5962 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 6216 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL
5963 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 6217 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL
5964 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 6218 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL
5965 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 6219 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL
5966 u8 offline_tests; 6220 u8 offline_tests;
5967 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 6221 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL
5968 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 6222 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL
5969 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 6223 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL
5970 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 6224 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL
5971 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 6225 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL
5972 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 6226 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL
5973 u8 unused_0; 6227 u8 unused_0;
5974 __le16 test_timeout; 6228 __le16 test_timeout;
5975 u8 unused_1; 6229 u8 unused_1[2];
5976 u8 unused_2; 6230 char test0_name[32];
5977 char test0_name[32]; 6231 char test1_name[32];
5978 char test1_name[32]; 6232 char test2_name[32];
5979 char test2_name[32]; 6233 char test3_name[32];
5980 char test3_name[32]; 6234 char test4_name[32];
5981 char test4_name[32]; 6235 char test5_name[32];
5982 char test5_name[32]; 6236 char test6_name[32];
5983 char test6_name[32]; 6237 char test7_name[32];
5984 char test7_name[32]; 6238 u8 unused_2[7];
5985 __le32 unused_3; 6239 u8 valid;
5986 u8 unused_4; 6240};
5987 u8 unused_5; 6241
5988 u8 unused_6; 6242/* hwrm_selftest_exec_input (size:192b/24B) */
5989 u8 valid;
5990};
5991
5992/* hwrm_selftest_exec */
5993/* Input (24 bytes) */
5994struct hwrm_selftest_exec_input { 6243struct hwrm_selftest_exec_input {
5995 __le16 req_type; 6244 __le16 req_type;
5996 __le16 cmpl_ring; 6245 __le16 cmpl_ring;
5997 __le16 seq_id; 6246 __le16 seq_id;
5998 __le16 target_id; 6247 __le16 target_id;
5999 __le64 resp_addr; 6248 __le64 resp_addr;
6000 u8 flags; 6249 u8 flags;
6001 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 6250 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL
6002 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 6251 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL
6003 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 6252 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL
6004 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 6253 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL
6005 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 6254 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL
6006 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 6255 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL
6007 u8 unused_0[7]; 6256 u8 pcie_lane_num;
6008}; 6257 u8 unused_0[6];
6009 6258};
6010/* Output (16 bytes) */ 6259
6260/* hwrm_selftest_exec_output (size:128b/16B) */
6011struct hwrm_selftest_exec_output { 6261struct hwrm_selftest_exec_output {
6012 __le16 error_code; 6262 __le16 error_code;
6013 __le16 req_type; 6263 __le16 req_type;
6014 __le16 seq_id; 6264 __le16 seq_id;
6015 __le16 resp_len; 6265 __le16 resp_len;
6016 u8 requested_tests; 6266 u8 requested_tests;
6017 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 6267 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL
6018 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 6268 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL
6019 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 6269 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL
6020 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 6270 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL
6021 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 6271 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL
6022 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 6272 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL
6023 u8 test_success; 6273 u8 test_success;
6024 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 6274 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL
6025 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 6275 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL
6026 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 6276 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL
6027 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 6277 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL
6028 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 6278 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL
6029 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 6279 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL
6030 u8 unused_0; 6280 u8 unused_0[5];
6031 u8 unused_1; 6281 u8 valid;
6032 u8 unused_2; 6282};
6033 u8 unused_3; 6283
6034 u8 unused_4; 6284/* hwrm_selftest_irq_input (size:128b/16B) */
6035 u8 valid;
6036};
6037
6038/* hwrm_selftest_irq */
6039/* Input (16 bytes) */
6040struct hwrm_selftest_irq_input { 6285struct hwrm_selftest_irq_input {
6041 __le16 req_type; 6286 __le16 req_type;
6042 __le16 cmpl_ring; 6287 __le16 cmpl_ring;
6043 __le16 seq_id; 6288 __le16 seq_id;
6044 __le16 target_id; 6289 __le16 target_id;
6045 __le64 resp_addr; 6290 __le64 resp_addr;
6046}; 6291};
6047 6292
6048/* Output (16 bytes) */ 6293/* hwrm_selftest_irq_output (size:128b/16B) */
6049struct hwrm_selftest_irq_output { 6294struct hwrm_selftest_irq_output {
6050 __le16 error_code; 6295 __le16 error_code;
6051 __le16 req_type; 6296 __le16 req_type;
6052 __le16 seq_id; 6297 __le16 seq_id;
6053 __le16 resp_len; 6298 __le16 resp_len;
6054 __le32 unused_0; 6299 u8 unused_0[7];
6055 u8 unused_1; 6300 u8 valid;
6056 u8 unused_2;
6057 u8 unused_3;
6058 u8 valid;
6059};
6060
6061/* hwrm_selftest_retrieve_serdes_data */
6062/* Input (32 bytes) */
6063struct hwrm_selftest_retrieve_serdes_data_input {
6064 __le16 req_type;
6065 __le16 cmpl_ring;
6066 __le16 seq_id;
6067 __le16 target_id;
6068 __le64 resp_addr;
6069 __le64 resp_data_addr;
6070 __le32 resp_data_offset;
6071 __le16 data_len;
6072 u8 flags;
6073 #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_UNUSED_TEST_MASK 0xfUL
6074 #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_UNUSED_TEST_SFT 0
6075 #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL
6076 #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL
6077 u8 unused_0;
6078};
6079
6080/* Output (16 bytes) */
6081struct hwrm_selftest_retrieve_serdes_data_output {
6082 __le16 error_code;
6083 __le16 req_type;
6084 __le16 seq_id;
6085 __le16 resp_len;
6086 __le16 total_data_len;
6087 __le16 copied_data_len;
6088 u8 unused_0;
6089 u8 unused_1;
6090 u8 unused_2;
6091 u8 valid;
6092};
6093
6094/* Hardware Resource Manager Specification */
6095/* Input (16 bytes) */
6096struct input {
6097 __le16 req_type;
6098 __le16 cmpl_ring;
6099 __le16 seq_id;
6100 __le16 target_id;
6101 __le64 resp_addr;
6102};
6103
6104/* Output (8 bytes) */
6105struct output {
6106 __le16 error_code;
6107 __le16 req_type;
6108 __le16 seq_id;
6109 __le16 resp_len;
6110};
6111
6112/* Short Command Structure (16 bytes) */
6113struct hwrm_short_input {
6114 __le16 req_type;
6115 __le16 signature;
6116 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
6117 __le16 unused_0;
6118 __le16 size;
6119 __le64 req_addr;
6120};
6121
6122/* Command numbering (8 bytes) */
6123struct cmd_nums {
6124 __le16 req_type;
6125 #define HWRM_VER_GET (0x0UL)
6126 #define HWRM_FUNC_BUF_UNRGTR (0xeUL)
6127 #define HWRM_FUNC_VF_CFG (0xfUL)
6128 #define RESERVED1 (0x10UL)
6129 #define HWRM_FUNC_RESET (0x11UL)
6130 #define HWRM_FUNC_GETFID (0x12UL)
6131 #define HWRM_FUNC_VF_ALLOC (0x13UL)
6132 #define HWRM_FUNC_VF_FREE (0x14UL)
6133 #define HWRM_FUNC_QCAPS (0x15UL)
6134 #define HWRM_FUNC_QCFG (0x16UL)
6135 #define HWRM_FUNC_CFG (0x17UL)
6136 #define HWRM_FUNC_QSTATS (0x18UL)
6137 #define HWRM_FUNC_CLR_STATS (0x19UL)
6138 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL)
6139 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL)
6140 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL)
6141 #define HWRM_FUNC_DRV_RGTR (0x1dUL)
6142 #define HWRM_FUNC_DRV_QVER (0x1eUL)
6143 #define HWRM_FUNC_BUF_RGTR (0x1fUL)
6144 #define HWRM_PORT_PHY_CFG (0x20UL)
6145 #define HWRM_PORT_MAC_CFG (0x21UL)
6146 #define HWRM_PORT_TS_QUERY (0x22UL)
6147 #define HWRM_PORT_QSTATS (0x23UL)
6148 #define HWRM_PORT_LPBK_QSTATS (0x24UL)
6149 #define HWRM_PORT_CLR_STATS (0x25UL)
6150 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL)
6151 #define HWRM_PORT_PHY_QCFG (0x27UL)
6152 #define HWRM_PORT_MAC_QCFG (0x28UL)
6153 #define HWRM_PORT_MAC_PTP_QCFG (0x29UL)
6154 #define HWRM_PORT_PHY_QCAPS (0x2aUL)
6155 #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL)
6156 #define HWRM_PORT_PHY_I2C_READ (0x2cUL)
6157 #define HWRM_PORT_LED_CFG (0x2dUL)
6158 #define HWRM_PORT_LED_QCFG (0x2eUL)
6159 #define HWRM_PORT_LED_QCAPS (0x2fUL)
6160 #define HWRM_QUEUE_QPORTCFG (0x30UL)
6161 #define HWRM_QUEUE_QCFG (0x31UL)
6162 #define HWRM_QUEUE_CFG (0x32UL)
6163 #define HWRM_FUNC_VLAN_CFG (0x33UL)
6164 #define HWRM_FUNC_VLAN_QCFG (0x34UL)
6165 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL)
6166 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL)
6167 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL)
6168 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL)
6169 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL)
6170 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL)
6171 #define HWRM_QUEUE_DSCP_QCAPS (0x3bUL)
6172 #define HWRM_QUEUE_DSCP2PRI_QCFG (0x3cUL)
6173 #define HWRM_QUEUE_DSCP2PRI_CFG (0x3dUL)
6174 #define HWRM_VNIC_ALLOC (0x40UL)
6175 #define HWRM_VNIC_FREE (0x41UL)
6176 #define HWRM_VNIC_CFG (0x42UL)
6177 #define HWRM_VNIC_QCFG (0x43UL)
6178 #define HWRM_VNIC_TPA_CFG (0x44UL)
6179 #define HWRM_VNIC_TPA_QCFG (0x45UL)
6180 #define HWRM_VNIC_RSS_CFG (0x46UL)
6181 #define HWRM_VNIC_RSS_QCFG (0x47UL)
6182 #define HWRM_VNIC_PLCMODES_CFG (0x48UL)
6183 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL)
6184 #define HWRM_VNIC_QCAPS (0x4aUL)
6185 #define HWRM_RING_ALLOC (0x50UL)
6186 #define HWRM_RING_FREE (0x51UL)
6187 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL)
6188 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL)
6189 #define HWRM_RING_RESET (0x5eUL)
6190 #define HWRM_RING_GRP_ALLOC (0x60UL)
6191 #define HWRM_RING_GRP_FREE (0x61UL)
6192 #define RESERVED5 (0x64UL)
6193 #define RESERVED6 (0x65UL)
6194 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL)
6195 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL)
6196 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL)
6197 #define HWRM_CFA_L2_FILTER_FREE (0x91UL)
6198 #define HWRM_CFA_L2_FILTER_CFG (0x92UL)
6199 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL)
6200 #define HWRM_CFA_VLAN_ANTISPOOF_CFG (0x94UL)
6201 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL)
6202 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL)
6203 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL)
6204 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL)
6205 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL)
6206 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL)
6207 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL)
6208 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL)
6209 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL)
6210 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL)
6211 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL)
6212 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL)
6213 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL)
6214 #define HWRM_STAT_CTX_ALLOC (0xb0UL)
6215 #define HWRM_STAT_CTX_FREE (0xb1UL)
6216 #define HWRM_STAT_CTX_QUERY (0xb2UL)
6217 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL)
6218 #define HWRM_FW_RESET (0xc0UL)
6219 #define HWRM_FW_QSTATUS (0xc1UL)
6220 #define HWRM_FW_SET_TIME (0xc8UL)
6221 #define HWRM_FW_GET_TIME (0xc9UL)
6222 #define HWRM_FW_SET_STRUCTURED_DATA (0xcaUL)
6223 #define HWRM_FW_GET_STRUCTURED_DATA (0xcbUL)
6224 #define HWRM_FW_IPC_MAILBOX (0xccUL)
6225 #define HWRM_EXEC_FWD_RESP (0xd0UL)
6226 #define HWRM_REJECT_FWD_RESP (0xd1UL)
6227 #define HWRM_FWD_RESP (0xd2UL)
6228 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL)
6229 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL)
6230 #define HWRM_WOL_FILTER_ALLOC (0xf0UL)
6231 #define HWRM_WOL_FILTER_FREE (0xf1UL)
6232 #define HWRM_WOL_FILTER_QCFG (0xf2UL)
6233 #define HWRM_WOL_REASON_QCFG (0xf3UL)
6234 #define HWRM_CFA_METER_PROFILE_ALLOC (0xf5UL)
6235 #define HWRM_CFA_METER_PROFILE_FREE (0xf6UL)
6236 #define HWRM_CFA_METER_PROFILE_CFG (0xf7UL)
6237 #define HWRM_CFA_METER_INSTANCE_ALLOC (0xf8UL)
6238 #define HWRM_CFA_METER_INSTANCE_FREE (0xf9UL)
6239 #define HWRM_CFA_VFR_ALLOC (0xfdUL)
6240 #define HWRM_CFA_VFR_FREE (0xfeUL)
6241 #define HWRM_CFA_VF_PAIR_ALLOC (0x100UL)
6242 #define HWRM_CFA_VF_PAIR_FREE (0x101UL)
6243 #define HWRM_CFA_VF_PAIR_INFO (0x102UL)
6244 #define HWRM_CFA_FLOW_ALLOC (0x103UL)
6245 #define HWRM_CFA_FLOW_FREE (0x104UL)
6246 #define HWRM_CFA_FLOW_FLUSH (0x105UL)
6247 #define HWRM_CFA_FLOW_STATS (0x106UL)
6248 #define HWRM_CFA_FLOW_INFO (0x107UL)
6249 #define HWRM_CFA_DECAP_FILTER_ALLOC (0x108UL)
6250 #define HWRM_CFA_DECAP_FILTER_FREE (0x109UL)
6251 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG (0x10aUL)
6252 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC (0x10bUL)
6253 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE (0x10cUL)
6254 #define HWRM_CFA_PAIR_ALLOC (0x10dUL)
6255 #define HWRM_CFA_PAIR_FREE (0x10eUL)
6256 #define HWRM_CFA_PAIR_INFO (0x10fUL)
6257 #define HWRM_FW_IPC_MSG (0x110UL)
6258 #define HWRM_SELFTEST_QLIST (0x200UL)
6259 #define HWRM_SELFTEST_EXEC (0x201UL)
6260 #define HWRM_SELFTEST_IRQ (0x202UL)
6261 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA (0x203UL)
6262 #define HWRM_DBG_READ_DIRECT (0xff10UL)
6263 #define HWRM_DBG_READ_INDIRECT (0xff11UL)
6264 #define HWRM_DBG_WRITE_DIRECT (0xff12UL)
6265 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL)
6266 #define HWRM_DBG_DUMP (0xff14UL)
6267 #define HWRM_DBG_ERASE_NVM (0xff15UL)
6268 #define HWRM_DBG_CFG (0xff16UL)
6269 #define HWRM_DBG_COREDUMP_LIST (0xff17UL)
6270 #define HWRM_DBG_COREDUMP_INITIATE (0xff18UL)
6271 #define HWRM_DBG_COREDUMP_RETRIEVE (0xff19UL)
6272 #define HWRM_NVM_FACTORY_DEFAULTS (0xffeeUL)
6273 #define HWRM_NVM_VALIDATE_OPTION (0xffefUL)
6274 #define HWRM_NVM_FLUSH (0xfff0UL)
6275 #define HWRM_NVM_GET_VARIABLE (0xfff1UL)
6276 #define HWRM_NVM_SET_VARIABLE (0xfff2UL)
6277 #define HWRM_NVM_INSTALL_UPDATE (0xfff3UL)
6278 #define HWRM_NVM_MODIFY (0xfff4UL)
6279 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL)
6280 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL)
6281 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL)
6282 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL)
6283 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL)
6284 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL)
6285 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL)
6286 #define HWRM_NVM_RAW_DUMP (0xfffcUL)
6287 #define HWRM_NVM_READ (0xfffdUL)
6288 #define HWRM_NVM_WRITE (0xfffeUL)
6289 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL)
6290 __le16 unused_0[3];
6291};
6292
6293/* Return Codes (8 bytes) */
6294struct ret_codes {
6295 __le16 error_code;
6296 #define HWRM_ERR_CODE_SUCCESS (0x0UL)
6297 #define HWRM_ERR_CODE_FAIL (0x1UL)
6298 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL)
6299 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL)
6300 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL)
6301 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL)
6302 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL)
6303 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL)
6304 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL)
6305 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL)
6306 __le16 unused_0[3];
6307};
6308
6309/* Output (16 bytes) */
6310struct hwrm_err_output {
6311 __le16 error_code;
6312 __le16 req_type;
6313 __le16 seq_id;
6314 __le16 resp_len;
6315 __le32 opaque_0;
6316 __le16 opaque_1;
6317 u8 cmd_err;
6318 u8 valid;
6319};
6320
6321/* Port Tx Statistics Formats (408 bytes) */
6322struct tx_port_stats {
6323 __le64 tx_64b_frames;
6324 __le64 tx_65b_127b_frames;
6325 __le64 tx_128b_255b_frames;
6326 __le64 tx_256b_511b_frames;
6327 __le64 tx_512b_1023b_frames;
6328 __le64 tx_1024b_1518_frames;
6329 __le64 tx_good_vlan_frames;
6330 __le64 tx_1519b_2047_frames;
6331 __le64 tx_2048b_4095b_frames;
6332 __le64 tx_4096b_9216b_frames;
6333 __le64 tx_9217b_16383b_frames;
6334 __le64 tx_good_frames;
6335 __le64 tx_total_frames;
6336 __le64 tx_ucast_frames;
6337 __le64 tx_mcast_frames;
6338 __le64 tx_bcast_frames;
6339 __le64 tx_pause_frames;
6340 __le64 tx_pfc_frames;
6341 __le64 tx_jabber_frames;
6342 __le64 tx_fcs_err_frames;
6343 __le64 tx_control_frames;
6344 __le64 tx_oversz_frames;
6345 __le64 tx_single_dfrl_frames;
6346 __le64 tx_multi_dfrl_frames;
6347 __le64 tx_single_coll_frames;
6348 __le64 tx_multi_coll_frames;
6349 __le64 tx_late_coll_frames;
6350 __le64 tx_excessive_coll_frames;
6351 __le64 tx_frag_frames;
6352 __le64 tx_err;
6353 __le64 tx_tagged_frames;
6354 __le64 tx_dbl_tagged_frames;
6355 __le64 tx_runt_frames;
6356 __le64 tx_fifo_underruns;
6357 __le64 tx_pfc_ena_frames_pri0;
6358 __le64 tx_pfc_ena_frames_pri1;
6359 __le64 tx_pfc_ena_frames_pri2;
6360 __le64 tx_pfc_ena_frames_pri3;
6361 __le64 tx_pfc_ena_frames_pri4;
6362 __le64 tx_pfc_ena_frames_pri5;
6363 __le64 tx_pfc_ena_frames_pri6;
6364 __le64 tx_pfc_ena_frames_pri7;
6365 __le64 tx_eee_lpi_events;
6366 __le64 tx_eee_lpi_duration;
6367 __le64 tx_llfc_logical_msgs;
6368 __le64 tx_hcfc_msgs;
6369 __le64 tx_total_collisions;
6370 __le64 tx_bytes;
6371 __le64 tx_xthol_frames;
6372 __le64 tx_stat_discard;
6373 __le64 tx_stat_error;
6374};
6375
6376/* Port Rx Statistics Formats (528 bytes) */
6377struct rx_port_stats {
6378 __le64 rx_64b_frames;
6379 __le64 rx_65b_127b_frames;
6380 __le64 rx_128b_255b_frames;
6381 __le64 rx_256b_511b_frames;
6382 __le64 rx_512b_1023b_frames;
6383 __le64 rx_1024b_1518_frames;
6384 __le64 rx_good_vlan_frames;
6385 __le64 rx_1519b_2047b_frames;
6386 __le64 rx_2048b_4095b_frames;
6387 __le64 rx_4096b_9216b_frames;
6388 __le64 rx_9217b_16383b_frames;
6389 __le64 rx_total_frames;
6390 __le64 rx_ucast_frames;
6391 __le64 rx_mcast_frames;
6392 __le64 rx_bcast_frames;
6393 __le64 rx_fcs_err_frames;
6394 __le64 rx_ctrl_frames;
6395 __le64 rx_pause_frames;
6396 __le64 rx_pfc_frames;
6397 __le64 rx_unsupported_opcode_frames;
6398 __le64 rx_unsupported_da_pausepfc_frames;
6399 __le64 rx_wrong_sa_frames;
6400 __le64 rx_align_err_frames;
6401 __le64 rx_oor_len_frames;
6402 __le64 rx_code_err_frames;
6403 __le64 rx_false_carrier_frames;
6404 __le64 rx_ovrsz_frames;
6405 __le64 rx_jbr_frames;
6406 __le64 rx_mtu_err_frames;
6407 __le64 rx_match_crc_frames;
6408 __le64 rx_promiscuous_frames;
6409 __le64 rx_tagged_frames;
6410 __le64 rx_double_tagged_frames;
6411 __le64 rx_trunc_frames;
6412 __le64 rx_good_frames;
6413 __le64 rx_pfc_xon2xoff_frames_pri0;
6414 __le64 rx_pfc_xon2xoff_frames_pri1;
6415 __le64 rx_pfc_xon2xoff_frames_pri2;
6416 __le64 rx_pfc_xon2xoff_frames_pri3;
6417 __le64 rx_pfc_xon2xoff_frames_pri4;
6418 __le64 rx_pfc_xon2xoff_frames_pri5;
6419 __le64 rx_pfc_xon2xoff_frames_pri6;
6420 __le64 rx_pfc_xon2xoff_frames_pri7;
6421 __le64 rx_pfc_ena_frames_pri0;
6422 __le64 rx_pfc_ena_frames_pri1;
6423 __le64 rx_pfc_ena_frames_pri2;
6424 __le64 rx_pfc_ena_frames_pri3;
6425 __le64 rx_pfc_ena_frames_pri4;
6426 __le64 rx_pfc_ena_frames_pri5;
6427 __le64 rx_pfc_ena_frames_pri6;
6428 __le64 rx_pfc_ena_frames_pri7;
6429 __le64 rx_sch_crc_err_frames;
6430 __le64 rx_undrsz_frames;
6431 __le64 rx_frag_frames;
6432 __le64 rx_eee_lpi_events;
6433 __le64 rx_eee_lpi_duration;
6434 __le64 rx_llfc_physical_msgs;
6435 __le64 rx_llfc_logical_msgs;
6436 __le64 rx_llfc_msgs_with_crc_err;
6437 __le64 rx_hcfc_msgs;
6438 __le64 rx_hcfc_msgs_with_crc_err;
6439 __le64 rx_bytes;
6440 __le64 rx_runt_bytes;
6441 __le64 rx_runt_frames;
6442 __le64 rx_stat_discard;
6443 __le64 rx_stat_err;
6444};
6445
6446/* VXLAN IPv4 encapsulation structure (16 bytes) */
6447struct hwrm_vxlan_ipv4_hdr {
6448 u8 ver_hlen;
6449 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
6450 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
6451 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL
6452 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
6453 u8 tos;
6454 __be16 ip_id;
6455 __be16 flags_frag_offset;
6456 u8 ttl;
6457 u8 protocol;
6458 __be32 src_ip_addr;
6459 __be32 dest_ip_addr;
6460};
6461
6462/* VXLAN IPv6 encapsulation structure (32 bytes) */
6463struct hwrm_vxlan_ipv6_hdr {
6464 __be32 ver_tc_flow_label;
6465 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL
6466 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL
6467 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL
6468 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL
6469 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL
6470 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
6471 __be16 payload_len;
6472 u8 next_hdr;
6473 u8 ttl;
6474 __be32 src_ip_addr[4];
6475 __be32 dest_ip_addr[4];
6476};
6477
6478/* VXLAN encapsulation structure (72 bytes) */
6479struct hwrm_cfa_encap_data_vxlan {
6480 u8 src_mac_addr[6];
6481 __le16 unused_0;
6482 u8 dst_mac_addr[6];
6483 u8 num_vlan_tags;
6484 u8 unused_1;
6485 __be16 ovlan_tpid;
6486 __be16 ovlan_tci;
6487 __be16 ivlan_tpid;
6488 __be16 ivlan_tci;
6489 __le32 l3[10];
6490 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
6491 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
6492 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
6493 __be16 src_port;
6494 __be16 dst_port;
6495 __be32 vni;
6496};
6497
6498/* Periodic Statistics Context DMA to host (160 bytes) */
6499struct ctx_hw_stats {
6500 __le64 rx_ucast_pkts;
6501 __le64 rx_mcast_pkts;
6502 __le64 rx_bcast_pkts;
6503 __le64 rx_discard_pkts;
6504 __le64 rx_drop_pkts;
6505 __le64 rx_ucast_bytes;
6506 __le64 rx_mcast_bytes;
6507 __le64 rx_bcast_bytes;
6508 __le64 tx_ucast_pkts;
6509 __le64 tx_mcast_pkts;
6510 __le64 tx_bcast_pkts;
6511 __le64 tx_discard_pkts;
6512 __le64 tx_drop_pkts;
6513 __le64 tx_ucast_bytes;
6514 __le64 tx_mcast_bytes;
6515 __le64 tx_bcast_bytes;
6516 __le64 tpa_pkts;
6517 __le64 tpa_bytes;
6518 __le64 tpa_events;
6519 __le64 tpa_aborts;
6520};
6521
6522/* Structure data header (16 bytes) */
6523struct hwrm_struct_hdr {
6524 __le16 struct_id;
6525 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
6526 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
6527 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
6528 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
6529 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
6530 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
6531 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
6532 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
6533 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
6534 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
6535 __le16 len;
6536 u8 version;
6537 u8 count;
6538 __le16 subtype;
6539 __le16 next_offset;
6540 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
6541 __le16 unused_0[3];
6542};
6543
6544/* DCBX Application configuration structure (1057) (8 bytes) */
6545struct hwrm_struct_data_dcbx_app {
6546 __be16 protocol_id;
6547 u8 protocol_selector;
6548 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
6549 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
6550 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
6551 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
6552 u8 priority;
6553 u8 valid;
6554 u8 unused_0[3];
6555}; 6301};
6556 6302
6557#endif 6303#endif /* _BNXT_HSI_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 21:28:09 -0400