clk: tegra: Have EMC clock implement determine_rate()

As opposed to round_rate(), determine_rate() can take rate constraints
into account when choosing the best rate.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

1 files changed, 23 insertions, 12 deletions

diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c
index 32e5563711ac..7649685c86bc 100644
--- a/drivers/clk/tegra/clk-emc.c
+++ b/drivers/clk/tegra/clk-emc.c
@@ -116,8 +116,11 @@ static unsigned long emc_recalc_rate(struct clk_hw *hw,
  * safer since things have EMC rate floors. Also don't touch parent_rate
  * since we don't want the CCF to play with our parent clocks.
  */
-static long emc_round_rate(struct clk_hw *hw, unsigned long rate,
-                    unsigned long *parent_rate)
+static long emc_determine_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long min_rate,
+                               unsigned long max_rate,
+                               unsigned long *best_parent_rate,
+                               struct clk_hw **best_parent_hw)
 {
         struct tegra_clk_emc *tegra;
         u8 ram_code = tegra_read_ram_code();
@@ -126,18 +129,26 @@ static long emc_round_rate(struct clk_hw *hw, unsigned long rate,
 
         tegra = container_of(hw, struct tegra_clk_emc, hw);
 
-         for (i = 0; i < tegra->num_timings; i++) {
-                if (tegra->timings[i].ram_code != ram_code)
-                        continue;
+        for (i = 0; i < tegra->num_timings; i++) {
+                if (tegra->timings[i].ram_code != ram_code)
+                        continue;
+
+                timing = tegra->timings + i;
 
-                timing = tegra->timings + i;
+                if (timing->rate > max_rate) {
+                        i = min(i, 1);
+                        return tegra->timings[i - 1].rate;
+                }
+
+                if (timing->rate < min_rate)
+                        continue;
 
-                if (timing->rate >= rate)
-                        return timing->rate;
-        }
+                if (timing->rate >= rate)
+                        return timing->rate;
+        }
 
-        if (timing)
-                return timing->rate;
+        if (timing)
+                return timing->rate;
 
         return __clk_get_rate(hw->clk);
 }
@@ -451,7 +462,7 @@ static int load_timings_from_dt(struct tegra_clk_emc *tegra,
 
 static const struct clk_ops tegra_clk_emc_ops = {
         .recalc_rate = emc_recalc_rate,
-        .round_rate = emc_round_rate,
+        .determine_rate = emc_determine_rate,
         .set_rate = emc_set_rate,
         .get_parent = emc_get_parent,
 };