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authorLinus Torvalds <torvalds@linux-foundation.org>2019-05-15 11:31:21 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2019-05-15 11:31:21 -0400
commit88f76bc31b93cc228f5a43d5b565dc53615970ae (patch)
treefe991a0d047a4fa0c05ce59e0d95e7fb937a631a
parent89963adcdb430e047f4c03ac3ed6ce9aa42a595c (diff)
parentcbc22b062106993980df43a7ffa93351d3218844 (diff)
Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto fixes from Herbert Xu: "This fixes a number of issues in the chelsio and caam drivers" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: Revert "crypto: caam/jr - Remove extra memory barrier during job ring dequeue" crypto: caam - fix caam_dump_sg that iterates through scatterlist crypto: caam - fix DKP detection logic MAINTAINERS: Maintainer for Chelsio crypto driver crypto: chelsio - count incomplete block in IV crypto: chelsio - Fix softlockup with heavy I/O crypto: chelsio - Fix NULL pointer dereference
-rw-r--r--MAINTAINERS2
-rw-r--r--drivers/crypto/caam/caamalg.c9
-rw-r--r--drivers/crypto/caam/caamalg_qi.c7
-rw-r--r--drivers/crypto/caam/caamalg_qi2.c8
-rw-r--r--drivers/crypto/caam/error.c2
-rw-r--r--drivers/crypto/caam/jr.c2
-rw-r--r--drivers/crypto/caam/regs.h8
-rw-r--r--drivers/crypto/chelsio/chcr_algo.c17
-rw-r--r--drivers/crypto/chelsio/chcr_core.c4
-rw-r--r--drivers/crypto/chelsio/chcr_ipsec.c3
10 files changed, 29 insertions, 33 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index ce573aaa04df..0d31d2b58d8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4316,7 +4316,7 @@ F: drivers/infiniband/hw/cxgb3/
4316F: include/uapi/rdma/cxgb3-abi.h 4316F: include/uapi/rdma/cxgb3-abi.h
4317 4317
4318CXGB4 CRYPTO DRIVER (chcr) 4318CXGB4 CRYPTO DRIVER (chcr)
4319M: Harsh Jain <harsh@chelsio.com> 4319M: Atul Gupta <atul.gupta@chelsio.com>
4320L: linux-crypto@vger.kernel.org 4320L: linux-crypto@vger.kernel.org
4321W: http://www.chelsio.com 4321W: http://www.chelsio.com
4322S: Supported 4322S: Supported
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 3e23d4b2cce2..c0ece44f303b 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -89,6 +89,7 @@ struct caam_alg_entry {
89 int class2_alg_type; 89 int class2_alg_type;
90 bool rfc3686; 90 bool rfc3686;
91 bool geniv; 91 bool geniv;
92 bool nodkp;
92}; 93};
93 94
94struct caam_aead_alg { 95struct caam_aead_alg {
@@ -2052,6 +2053,7 @@ static struct caam_aead_alg driver_aeads[] = {
2052 }, 2053 },
2053 .caam = { 2054 .caam = {
2054 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, 2055 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
2056 .nodkp = true,
2055 }, 2057 },
2056 }, 2058 },
2057 { 2059 {
@@ -2070,6 +2072,7 @@ static struct caam_aead_alg driver_aeads[] = {
2070 }, 2072 },
2071 .caam = { 2073 .caam = {
2072 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, 2074 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
2075 .nodkp = true,
2073 }, 2076 },
2074 }, 2077 },
2075 /* Galois Counter Mode */ 2078 /* Galois Counter Mode */
@@ -2089,6 +2092,7 @@ static struct caam_aead_alg driver_aeads[] = {
2089 }, 2092 },
2090 .caam = { 2093 .caam = {
2091 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, 2094 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
2095 .nodkp = true,
2092 }, 2096 },
2093 }, 2097 },
2094 /* single-pass ipsec_esp descriptor */ 2098 /* single-pass ipsec_esp descriptor */
@@ -3334,6 +3338,7 @@ static struct caam_aead_alg driver_aeads[] = {
3334 OP_ALG_AAI_AEAD, 3338 OP_ALG_AAI_AEAD,
3335 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 | 3339 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 |
3336 OP_ALG_AAI_AEAD, 3340 OP_ALG_AAI_AEAD,
3341 .nodkp = true,
3337 }, 3342 },
3338 }, 3343 },
3339 { 3344 {
@@ -3356,6 +3361,7 @@ static struct caam_aead_alg driver_aeads[] = {
3356 OP_ALG_AAI_AEAD, 3361 OP_ALG_AAI_AEAD,
3357 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 | 3362 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 |
3358 OP_ALG_AAI_AEAD, 3363 OP_ALG_AAI_AEAD,
3364 .nodkp = true,
3359 }, 3365 },
3360 }, 3366 },
3361}; 3367};
@@ -3417,8 +3423,7 @@ static int caam_aead_init(struct crypto_aead *tfm)
3417 container_of(alg, struct caam_aead_alg, aead); 3423 container_of(alg, struct caam_aead_alg, aead);
3418 struct caam_ctx *ctx = crypto_aead_ctx(tfm); 3424 struct caam_ctx *ctx = crypto_aead_ctx(tfm);
3419 3425
3420 return caam_init_common(ctx, &caam_alg->caam, 3426 return caam_init_common(ctx, &caam_alg->caam, !caam_alg->caam.nodkp);
3421 alg->setkey == aead_setkey);
3422} 3427}
3423 3428
3424static void caam_exit_common(struct caam_ctx *ctx) 3429static void caam_exit_common(struct caam_ctx *ctx)
diff --git a/drivers/crypto/caam/caamalg_qi.c b/drivers/crypto/caam/caamalg_qi.c
index 70af211d2d01..d290d6b41825 100644
--- a/drivers/crypto/caam/caamalg_qi.c
+++ b/drivers/crypto/caam/caamalg_qi.c
@@ -36,6 +36,7 @@ struct caam_alg_entry {
36 int class2_alg_type; 36 int class2_alg_type;
37 bool rfc3686; 37 bool rfc3686;
38 bool geniv; 38 bool geniv;
39 bool nodkp;
39}; 40};
40 41
41struct caam_aead_alg { 42struct caam_aead_alg {
@@ -1523,6 +1524,7 @@ static struct caam_aead_alg driver_aeads[] = {
1523 }, 1524 },
1524 .caam = { 1525 .caam = {
1525 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, 1526 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
1527 .nodkp = true,
1526 }, 1528 },
1527 }, 1529 },
1528 { 1530 {
@@ -1541,6 +1543,7 @@ static struct caam_aead_alg driver_aeads[] = {
1541 }, 1543 },
1542 .caam = { 1544 .caam = {
1543 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, 1545 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
1546 .nodkp = true,
1544 }, 1547 },
1545 }, 1548 },
1546 /* Galois Counter Mode */ 1549 /* Galois Counter Mode */
@@ -1560,6 +1563,7 @@ static struct caam_aead_alg driver_aeads[] = {
1560 }, 1563 },
1561 .caam = { 1564 .caam = {
1562 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, 1565 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
1566 .nodkp = true,
1563 } 1567 }
1564 }, 1568 },
1565 /* single-pass ipsec_esp descriptor */ 1569 /* single-pass ipsec_esp descriptor */
@@ -2433,8 +2437,7 @@ static int caam_aead_init(struct crypto_aead *tfm)
2433 aead); 2437 aead);
2434 struct caam_ctx *ctx = crypto_aead_ctx(tfm); 2438 struct caam_ctx *ctx = crypto_aead_ctx(tfm);
2435 2439
2436 return caam_init_common(ctx, &caam_alg->caam, 2440 return caam_init_common(ctx, &caam_alg->caam, !caam_alg->caam.nodkp);
2437 alg->setkey == aead_setkey);
2438} 2441}
2439 2442
2440static void caam_exit_common(struct caam_ctx *ctx) 2443static void caam_exit_common(struct caam_ctx *ctx)
diff --git a/drivers/crypto/caam/caamalg_qi2.c b/drivers/crypto/caam/caamalg_qi2.c
index 33a4df6b81de..2b2980a8a9b9 100644
--- a/drivers/crypto/caam/caamalg_qi2.c
+++ b/drivers/crypto/caam/caamalg_qi2.c
@@ -42,6 +42,7 @@ struct caam_alg_entry {
42 int class2_alg_type; 42 int class2_alg_type;
43 bool rfc3686; 43 bool rfc3686;
44 bool geniv; 44 bool geniv;
45 bool nodkp;
45}; 46};
46 47
47struct caam_aead_alg { 48struct caam_aead_alg {
@@ -1480,7 +1481,7 @@ static int caam_cra_init_aead(struct crypto_aead *tfm)
1480 1481
1481 crypto_aead_set_reqsize(tfm, sizeof(struct caam_request)); 1482 crypto_aead_set_reqsize(tfm, sizeof(struct caam_request));
1482 return caam_cra_init(crypto_aead_ctx(tfm), &caam_alg->caam, 1483 return caam_cra_init(crypto_aead_ctx(tfm), &caam_alg->caam,
1483 alg->setkey == aead_setkey); 1484 !caam_alg->caam.nodkp);
1484} 1485}
1485 1486
1486static void caam_exit_common(struct caam_ctx *ctx) 1487static void caam_exit_common(struct caam_ctx *ctx)
@@ -1641,6 +1642,7 @@ static struct caam_aead_alg driver_aeads[] = {
1641 }, 1642 },
1642 .caam = { 1643 .caam = {
1643 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, 1644 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
1645 .nodkp = true,
1644 }, 1646 },
1645 }, 1647 },
1646 { 1648 {
@@ -1659,6 +1661,7 @@ static struct caam_aead_alg driver_aeads[] = {
1659 }, 1661 },
1660 .caam = { 1662 .caam = {
1661 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, 1663 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
1664 .nodkp = true,
1662 }, 1665 },
1663 }, 1666 },
1664 /* Galois Counter Mode */ 1667 /* Galois Counter Mode */
@@ -1678,6 +1681,7 @@ static struct caam_aead_alg driver_aeads[] = {
1678 }, 1681 },
1679 .caam = { 1682 .caam = {
1680 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, 1683 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
1684 .nodkp = true,
1681 } 1685 }
1682 }, 1686 },
1683 /* single-pass ipsec_esp descriptor */ 1687 /* single-pass ipsec_esp descriptor */
@@ -2755,6 +2759,7 @@ static struct caam_aead_alg driver_aeads[] = {
2755 OP_ALG_AAI_AEAD, 2759 OP_ALG_AAI_AEAD,
2756 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 | 2760 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 |
2757 OP_ALG_AAI_AEAD, 2761 OP_ALG_AAI_AEAD,
2762 .nodkp = true,
2758 }, 2763 },
2759 }, 2764 },
2760 { 2765 {
@@ -2777,6 +2782,7 @@ static struct caam_aead_alg driver_aeads[] = {
2777 OP_ALG_AAI_AEAD, 2782 OP_ALG_AAI_AEAD,
2778 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 | 2783 .class2_alg_type = OP_ALG_ALGSEL_POLY1305 |
2779 OP_ALG_AAI_AEAD, 2784 OP_ALG_AAI_AEAD,
2785 .nodkp = true,
2780 }, 2786 },
2781 }, 2787 },
2782 { 2788 {
diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c
index a4129a35a330..4da844e4b61d 100644
--- a/drivers/crypto/caam/error.c
+++ b/drivers/crypto/caam/error.c
@@ -22,7 +22,7 @@ void caam_dump_sg(const char *level, const char *prefix_str, int prefix_type,
22 size_t len; 22 size_t len;
23 void *buf; 23 void *buf;
24 24
25 for (it = sg; it && tlen > 0 ; it = sg_next(sg)) { 25 for (it = sg; it && tlen > 0 ; it = sg_next(it)) {
26 /* 26 /*
27 * make sure the scatterlist's page 27 * make sure the scatterlist's page
28 * has a valid virtual memory mapping 28 * has a valid virtual memory mapping
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index 044a69b526f7..1de2562d0982 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -213,7 +213,7 @@ static void caam_jr_dequeue(unsigned long devarg)
213 mb(); 213 mb();
214 214
215 /* set done */ 215 /* set done */
216 wr_reg32_relaxed(&jrp->rregs->outring_rmvd, 1); 216 wr_reg32(&jrp->rregs->outring_rmvd, 1);
217 217
218 jrp->out_ring_read_index = (jrp->out_ring_read_index + 1) & 218 jrp->out_ring_read_index = (jrp->out_ring_read_index + 1) &
219 (JOBR_DEPTH - 1); 219 (JOBR_DEPTH - 1);
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index c1fa1ec701d9..8591914d5c51 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -96,14 +96,6 @@ cpu_to_caam(16)
96cpu_to_caam(32) 96cpu_to_caam(32)
97cpu_to_caam(64) 97cpu_to_caam(64)
98 98
99static inline void wr_reg32_relaxed(void __iomem *reg, u32 data)
100{
101 if (caam_little_end)
102 writel_relaxed(data, reg);
103 else
104 writel_relaxed(cpu_to_be32(data), reg);
105}
106
107static inline void wr_reg32(void __iomem *reg, u32 data) 99static inline void wr_reg32(void __iomem *reg, u32 data)
108{ 100{
109 if (caam_little_end) 101 if (caam_little_end)
diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c
index 8a76fce22943..177f572b9589 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -200,17 +200,10 @@ void chcr_verify_tag(struct aead_request *req, u8 *input, int *err)
200 200
201static int chcr_inc_wrcount(struct chcr_dev *dev) 201static int chcr_inc_wrcount(struct chcr_dev *dev)
202{ 202{
203 int err = 0;
204
205 spin_lock_bh(&dev->lock_chcr_dev);
206 if (dev->state == CHCR_DETACH) 203 if (dev->state == CHCR_DETACH)
207 err = 1; 204 return 1;
208 else 205 atomic_inc(&dev->inflight);
209 atomic_inc(&dev->inflight); 206 return 0;
210
211 spin_unlock_bh(&dev->lock_chcr_dev);
212
213 return err;
214} 207}
215 208
216static inline void chcr_dec_wrcount(struct chcr_dev *dev) 209static inline void chcr_dec_wrcount(struct chcr_dev *dev)
@@ -1101,8 +1094,8 @@ static int chcr_final_cipher_iv(struct ablkcipher_request *req,
1101 int ret = 0; 1094 int ret = 0;
1102 1095
1103 if (subtype == CRYPTO_ALG_SUB_TYPE_CTR) 1096 if (subtype == CRYPTO_ALG_SUB_TYPE_CTR)
1104 ctr_add_iv(iv, req->info, (reqctx->processed / 1097 ctr_add_iv(iv, req->info, DIV_ROUND_UP(reqctx->processed,
1105 AES_BLOCK_SIZE)); 1098 AES_BLOCK_SIZE));
1106 else if (subtype == CRYPTO_ALG_SUB_TYPE_XTS) 1099 else if (subtype == CRYPTO_ALG_SUB_TYPE_XTS)
1107 ret = chcr_update_tweak(req, iv, 1); 1100 ret = chcr_update_tweak(req, iv, 1);
1108 else if (subtype == CRYPTO_ALG_SUB_TYPE_CBC) { 1101 else if (subtype == CRYPTO_ALG_SUB_TYPE_CBC) {
diff --git a/drivers/crypto/chelsio/chcr_core.c b/drivers/crypto/chelsio/chcr_core.c
index 239b933d6df6..029a7354f541 100644
--- a/drivers/crypto/chelsio/chcr_core.c
+++ b/drivers/crypto/chelsio/chcr_core.c
@@ -243,15 +243,11 @@ static void chcr_detach_device(struct uld_ctx *u_ctx)
243{ 243{
244 struct chcr_dev *dev = &u_ctx->dev; 244 struct chcr_dev *dev = &u_ctx->dev;
245 245
246 spin_lock_bh(&dev->lock_chcr_dev);
247 if (dev->state == CHCR_DETACH) { 246 if (dev->state == CHCR_DETACH) {
248 spin_unlock_bh(&dev->lock_chcr_dev);
249 pr_debug("Detached Event received for already detach device\n"); 247 pr_debug("Detached Event received for already detach device\n");
250 return; 248 return;
251 } 249 }
252 dev->state = CHCR_DETACH; 250 dev->state = CHCR_DETACH;
253 spin_unlock_bh(&dev->lock_chcr_dev);
254
255 if (atomic_read(&dev->inflight) != 0) { 251 if (atomic_read(&dev->inflight) != 0) {
256 schedule_delayed_work(&dev->detach_work, WQ_DETACH_TM); 252 schedule_delayed_work(&dev->detach_work, WQ_DETACH_TM);
257 wait_for_completion(&dev->detach_comp); 253 wait_for_completion(&dev->detach_comp);
diff --git a/drivers/crypto/chelsio/chcr_ipsec.c b/drivers/crypto/chelsio/chcr_ipsec.c
index 2f60049361ef..f429aae72542 100644
--- a/drivers/crypto/chelsio/chcr_ipsec.c
+++ b/drivers/crypto/chelsio/chcr_ipsec.c
@@ -575,7 +575,8 @@ inline void *chcr_crypto_wreq(struct sk_buff *skb,
575 if (unlikely(credits < ETHTXQ_STOP_THRES)) { 575 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
576 netif_tx_stop_queue(q->txq); 576 netif_tx_stop_queue(q->txq);
577 q->q.stops++; 577 q->q.stops++;
578 wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F; 578 if (!q->dbqt)
579 wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F;
579 } 580 }
580 wr_mid |= FW_ULPTX_WR_DATA_F; 581 wr_mid |= FW_ULPTX_WR_DATA_F;
581 wr->wreq.flowid_len16 = htonl(wr_mid); 582 wr->wreq.flowid_len16 = htonl(wr_mid);