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authorMaxime Ripard <maxime.ripard@free-electrons.com>2015-10-12 16:21:49 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2015-10-21 16:43:25 -0400
commit88a86aaa613032e0d5cf70a3d0777302ec2ed40b (patch)
tree06628a666d19a6e8ebe6bfd1a2a0f5f128b68bf9
parent6f87abb8cd7dc00701f0a732962420fddbf4b79b (diff)
ARM: sun7i: Add audio PLL
The A20 uses the PLL2 as the audio PLL, which is the parent of all the other audio clocks in the system (i2s, codec, etc.). Add it to the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 3a68852f6706..433ec1415e56 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -199,6 +199,15 @@
199 clock-output-names = "pll1"; 199 clock-output-names = "pll1";
200 }; 200 };
201 201
202 pll2: clk@01c20008 {
203 #clock-cells = <1>;
204 compatible = "allwinner,sun4i-a10-pll2-clk";
205 reg = <0x01c20008 0x8>;
206 clocks = <&osc24M>;
207 clock-output-names = "pll2-1x", "pll2-2x",
208 "pll2-4x", "pll2-8x";
209 };
210
202 pll4: clk@01c20018 { 211 pll4: clk@01c20018 {
203 #clock-cells = <0>; 212 #clock-cells = <0>;
204 compatible = "allwinner,sun7i-a20-pll4-clk"; 213 compatible = "allwinner,sun7i-a20-pll4-clk";