diff options
author | Stephen Boyd <sboyd@codeaurora.org> | 2014-01-17 14:42:48 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-02-10 06:48:03 -0500 |
commit | 889f172d920b6f275408199ec836df62979bcd52 (patch) | |
tree | 55188b29a2c8248fb0ee1066c76d838ae9e92de1 | |
parent | ddb2ff731b53ae28ec3a2af0da96a108b8bad814 (diff) |
ARM: 7945/1: footbridge: Switch to sched_clock_register()
The 32 bit sched_clock interface supports 64 bits since 3.13-rc1.
Upgrade to the 64 bit function to allow us to remove the 32 bit
registration interface.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r-- | arch/arm/mach-footbridge/dc21285-timer.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index 3971104d32d4..5d2725fd878c 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c | |||
@@ -125,7 +125,7 @@ void __init footbridge_timer_init(void) | |||
125 | clockevents_config_and_register(ce, rate, 0x4, 0xffffff); | 125 | clockevents_config_and_register(ce, rate, 0x4, 0xffffff); |
126 | } | 126 | } |
127 | 127 | ||
128 | static u32 notrace footbridge_read_sched_clock(void) | 128 | static u64 notrace footbridge_read_sched_clock(void) |
129 | { | 129 | { |
130 | return ~*CSR_TIMER3_VALUE; | 130 | return ~*CSR_TIMER3_VALUE; |
131 | } | 131 | } |
@@ -138,5 +138,5 @@ void __init footbridge_sched_clock(void) | |||
138 | *CSR_TIMER3_CLR = 0; | 138 | *CSR_TIMER3_CLR = 0; |
139 | *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; | 139 | *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; |
140 | 140 | ||
141 | setup_sched_clock(footbridge_read_sched_clock, 24, rate); | 141 | sched_clock_register(footbridge_read_sched_clock, 24, rate); |
142 | } | 142 | } |