Merge tag 'drm-intel-fixes-2016-02-04' of git://anongit.freedesktop.org/drm-intel into drm-fixes

misc i915 fixes.

* tag 'drm-intel-fixes-2016-02-04' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: refine qemu south bridge detection
  drm/i915: Remove select to deleted STOP_MACHINE from Kconfig
  drm/i915: Fix NULL plane->fb oops on SKL
  drm/i915: Don't reject primary plane windowing with color keying enabled on SKL+
  drm/i915/dp: fall back to 18 bpp when sink capability is unknown
  drm/i915: Make sure DC writes are coherent on flush.

5 files changed, 28 insertions, 13 deletions

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index fcd77b27514d..051eab33e4c7 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -10,7 +10,6 @@ config DRM_I915
         # the shmem_readpage() which depends upon tmpfs
         select SHMEM
         select TMPFS
-        select STOP_MACHINE
         select DRM_KMS_HELPER
         select DRM_PANEL
         select DRM_MIPI_DSI
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3ac616d7363b..f357058c74d9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -501,7 +501,9 @@ void intel_detect_pch(struct drm_device *dev)
                                 WARN_ON(!IS_SKYLAKE(dev) &&
                                         !IS_KABYLAKE(dev));
                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
-                                   (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)) {
+                                   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
+                                    pch->subsystem_vendor == 0x1af4 &&
+                                    pch->subsystem_device == 0x1100)) {
                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
                         } else
                                 continue;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2f00828ccc6e..5feb65725c04 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2946,7 +2946,7 @@ u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
         struct i915_vma *vma;
         u64 offset;
 
-        intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
+        intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
                                 intel_plane->base.state);
 
         vma = i915_gem_obj_to_ggtt_view(obj, &view);
@@ -12075,11 +12075,21 @@ connected_sink_compute_bpp(struct intel_connector *connector,
                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
         }
 
-        /* Clamp bpp to 8 on screens without EDID 1.4 */
-        if (connector->base.display_info.bpc == 0 && bpp > 24) {
-                DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
-                              bpp);
-                pipe_config->pipe_bpp = 24;
+        /* Clamp bpp to default limit on screens without EDID 1.4 */
+        if (connector->base.display_info.bpc == 0) {
+                int type = connector->base.connector_type;
+                int clamp_bpp = 24;
+
+                /* Fall back to 18 bpp when DP sink capability is unknown. */
+                if (type == DRM_MODE_CONNECTOR_DisplayPort ||
+                    type == DRM_MODE_CONNECTOR_eDP)
+                        clamp_bpp = 18;
+
+                if (bpp > clamp_bpp) {
+                        DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
+                                      bpp, clamp_bpp);
+                        pipe_config->pipe_bpp = clamp_bpp;
+                }
         }
 }
 
@@ -13883,11 +13893,12 @@ intel_check_primary_plane(struct drm_plane *plane,
         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
         bool can_position = false;
 
-        /* use scaler when colorkey is not required */
-        if (INTEL_INFO(plane->dev)->gen >= 9 &&
-            state->ckey.flags == I915_SET_COLORKEY_NONE) {
-                min_scale = 1;
-                max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+        if (INTEL_INFO(plane->dev)->gen >= 9) {
+                /* use scaler when colorkey is not required */
+                if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
+                        min_scale = 1;
+                        max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+                }
                 can_position = true;
         }
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3aa614731d7e..f1fa756c5d5d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1707,6 +1707,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
         if (flush_domains) {
                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+                flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
         }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 339701d7a9a5..40c6aff57256 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -331,6 +331,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
         if (flush_domains) {
                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+                flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
         }
         if (invalidate_domains) {
@@ -403,6 +404,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
         if (flush_domains) {
                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+                flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
         }
         if (invalidate_domains) {