diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2016-04-18 21:10:38 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2016-05-20 00:43:04 -0400 |
commit | 87ac331e3f9aca9bdc3697bb936b3b2b43cbf5a0 (patch) | |
tree | c0c099ee68c276c698a77010472f39fd72eee11b | |
parent | 4d3df19a8e6c9e60eed7f3c6e2025362b3ca2da5 (diff) |
drm/nouveau/gr/gk104-: move rop_active_fbps init to nonctx
Matches newer RM.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | 1 |
15 files changed, 36 insertions, 28 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h index e01aa1ac9ab5..ac895edce164 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h | |||
@@ -81,8 +81,6 @@ void gk104_grctx_generate_bundle(struct gf100_grctx *); | |||
81 | void gk104_grctx_generate_pagepool(struct gf100_grctx *); | 81 | void gk104_grctx_generate_pagepool(struct gf100_grctx *); |
82 | void gk104_grctx_generate_unkn(struct gf100_gr *); | 82 | void gk104_grctx_generate_unkn(struct gf100_gr *); |
83 | void gk104_grctx_generate_r418bb8(struct gf100_gr *); | 83 | void gk104_grctx_generate_r418bb8(struct gf100_gr *); |
84 | void gk104_grctx_generate_rop_active_fbps(struct gf100_gr *); | ||
85 | |||
86 | 84 | ||
87 | void gm107_grctx_generate_bundle(struct gf100_grctx *); | 85 | void gm107_grctx_generate_bundle(struct gf100_grctx *); |
88 | void gm107_grctx_generate_pagepool(struct gf100_grctx *); | 86 | void gm107_grctx_generate_pagepool(struct gf100_grctx *); |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c index 0c99f3c3a376..9ba337778ef5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c | |||
@@ -943,15 +943,6 @@ gk104_grctx_generate_r418bb8(struct gf100_gr *gr) | |||
943 | } | 943 | } |
944 | 944 | ||
945 | void | 945 | void |
946 | gk104_grctx_generate_rop_active_fbps(struct gf100_gr *gr) | ||
947 | { | ||
948 | struct nvkm_device *device = gr->base.engine.subdev.device; | ||
949 | const u32 fbp_count = nvkm_rd32(device, 0x120074); | ||
950 | nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ | ||
951 | nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ | ||
952 | } | ||
953 | |||
954 | void | ||
955 | gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) | 946 | gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) |
956 | { | 947 | { |
957 | struct nvkm_device *device = gr->base.engine.subdev.device; | 948 | struct nvkm_device *device = gr->base.engine.subdev.device; |
@@ -983,7 +974,6 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) | |||
983 | nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); | 974 | nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); |
984 | 975 | ||
985 | nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); | 976 | nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); |
986 | gk104_grctx_generate_rop_active_fbps(gr); | ||
987 | nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000); | 977 | nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000); |
988 | 978 | ||
989 | gf100_gr_icmd(gr, grctx->icmd); | 979 | gf100_gr_icmd(gr, grctx->icmd); |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index 7625d6f73e8a..da7c35a6a3d2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c | |||
@@ -52,8 +52,6 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) | |||
52 | 52 | ||
53 | nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); | 53 | nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); |
54 | 54 | ||
55 | gk104_grctx_generate_rop_active_fbps(gr); | ||
56 | |||
57 | nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000); | 55 | nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000); |
58 | 56 | ||
59 | gf100_gr_wait_idle(gr); | 57 | gf100_gr_wait_idle(gr); |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c index e77fb3d290d8..053ff2f850b9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c | |||
@@ -985,8 +985,6 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) | |||
985 | 985 | ||
986 | nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); | 986 | nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); |
987 | 987 | ||
988 | gk104_grctx_generate_rop_active_fbps(gr); | ||
989 | |||
990 | gf100_gr_icmd(gr, grctx->icmd); | 988 | gf100_gr_icmd(gr, grctx->icmd); |
991 | nvkm_wr32(device, 0x404154, idle_timeout); | 989 | nvkm_wr32(device, 0x404154, idle_timeout); |
992 | gf100_gr_mthd(gr, grctx->mthd); | 990 | gf100_gr_mthd(gr, grctx->mthd); |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c index e65b70a01a88..db209d33f486 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c | |||
@@ -45,15 +45,6 @@ gm200_grctx_generate_tpcid(struct gf100_gr *gr) | |||
45 | } | 45 | } |
46 | } | 46 | } |
47 | 47 | ||
48 | static void | ||
49 | gm200_grctx_generate_rop_active_fbps(struct gf100_gr *gr) | ||
50 | { | ||
51 | struct nvkm_device *device = gr->base.engine.subdev.device; | ||
52 | const u32 fbp_count = nvkm_rd32(device, 0x12006c); | ||
53 | nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ | ||
54 | nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ | ||
55 | } | ||
56 | |||
57 | void | 48 | void |
58 | gm200_grctx_generate_405b60(struct gf100_gr *gr) | 49 | gm200_grctx_generate_405b60(struct gf100_gr *gr) |
59 | { | 50 | { |
@@ -113,8 +104,6 @@ gm200_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) | |||
113 | 104 | ||
114 | nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); | 105 | nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); |
115 | 106 | ||
116 | gm200_grctx_generate_rop_active_fbps(gr); | ||
117 | |||
118 | for (tmp = 0, i = 0; i < gr->gpc_nr; i++) | 107 | for (tmp = 0, i = 0; i < gr->gpc_nr; i++) |
119 | tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4); | 108 | tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4); |
120 | nvkm_wr32(device, 0x4041c4, tmp); | 109 | nvkm_wr32(device, 0x4041c4, tmp); |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c index ba30d94a2ffc..e5702e3e0a5a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c | |||
@@ -62,7 +62,6 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) | |||
62 | 62 | ||
63 | nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); | 63 | nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); |
64 | 64 | ||
65 | gk104_grctx_generate_rop_active_fbps(gr); | ||
66 | nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000); | 65 | nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000); |
67 | 66 | ||
68 | for (tmp = 0, i = 0; i < gr->gpc_nr; i++) | 67 | for (tmp = 0, i = 0; i < gr->gpc_nr; i++) |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index 90c70e777dff..611888c0dbac 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | |||
@@ -119,6 +119,7 @@ struct gf100_gr_func { | |||
119 | void (*dtor)(struct gf100_gr *); | 119 | void (*dtor)(struct gf100_gr *); |
120 | int (*init)(struct gf100_gr *); | 120 | int (*init)(struct gf100_gr *); |
121 | void (*init_gpc_mmu)(struct gf100_gr *); | 121 | void (*init_gpc_mmu)(struct gf100_gr *); |
122 | void (*init_rop_active_fbps)(struct gf100_gr *); | ||
122 | void (*set_hww_esr_report_mask)(struct gf100_gr *); | 123 | void (*set_hww_esr_report_mask)(struct gf100_gr *); |
123 | const struct gf100_gr_pack *mmio; | 124 | const struct gf100_gr_pack *mmio; |
124 | struct { | 125 | struct { |
@@ -137,6 +138,7 @@ int gf100_gr_init(struct gf100_gr *); | |||
137 | int gf100_gr_rops(struct gf100_gr *); | 138 | int gf100_gr_rops(struct gf100_gr *); |
138 | 139 | ||
139 | int gk104_gr_init(struct gf100_gr *); | 140 | int gk104_gr_init(struct gf100_gr *); |
141 | void gk104_gr_init_rop_active_fbps(struct gf100_gr *); | ||
140 | 142 | ||
141 | int gk20a_gr_init(struct gf100_gr *); | 143 | int gk20a_gr_init(struct gf100_gr *); |
142 | 144 | ||
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index 2aebae4df2fd..c6a3f6d8a8ca 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c | |||
@@ -179,6 +179,15 @@ gk104_gr_pack_mmio[] = { | |||
179 | * PGRAPH engine/subdev functions | 179 | * PGRAPH engine/subdev functions |
180 | ******************************************************************************/ | 180 | ******************************************************************************/ |
181 | 181 | ||
182 | void | ||
183 | gk104_gr_init_rop_active_fbps(struct gf100_gr *gr) | ||
184 | { | ||
185 | struct nvkm_device *device = gr->base.engine.subdev.device; | ||
186 | const u32 fbp_count = nvkm_rd32(device, 0x120074); | ||
187 | nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ | ||
188 | nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ | ||
189 | } | ||
190 | |||
182 | int | 191 | int |
183 | gk104_gr_init(struct gf100_gr *gr) | 192 | gk104_gr_init(struct gf100_gr *gr) |
184 | { | 193 | { |
@@ -230,6 +239,8 @@ gk104_gr_init(struct gf100_gr *gr) | |||
230 | nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); | 239 | nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); |
231 | nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); | 240 | nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); |
232 | 241 | ||
242 | gr->func->init_rop_active_fbps(gr); | ||
243 | |||
233 | nvkm_wr32(device, 0x400500, 0x00010001); | 244 | nvkm_wr32(device, 0x400500, 0x00010001); |
234 | 245 | ||
235 | nvkm_wr32(device, 0x400100, 0xffffffff); | 246 | nvkm_wr32(device, 0x400100, 0xffffffff); |
@@ -312,6 +323,7 @@ gk104_gr_gpccs_ucode = { | |||
312 | static const struct gf100_gr_func | 323 | static const struct gf100_gr_func |
313 | gk104_gr = { | 324 | gk104_gr = { |
314 | .init = gk104_gr_init, | 325 | .init = gk104_gr_init, |
326 | .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, | ||
315 | .mmio = gk104_gr_pack_mmio, | 327 | .mmio = gk104_gr_pack_mmio, |
316 | .fecs.ucode = &gk104_gr_fecs_ucode, | 328 | .fecs.ucode = &gk104_gr_fecs_ucode, |
317 | .gpccs.ucode = &gk104_gr_gpccs_ucode, | 329 | .gpccs.ucode = &gk104_gr_gpccs_ucode, |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c index de1685c625c3..f18af8974103 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c | |||
@@ -183,6 +183,7 @@ gk110_gr_gpccs_ucode = { | |||
183 | static const struct gf100_gr_func | 183 | static const struct gf100_gr_func |
184 | gk110_gr = { | 184 | gk110_gr = { |
185 | .init = gk104_gr_init, | 185 | .init = gk104_gr_init, |
186 | .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, | ||
186 | .mmio = gk110_gr_pack_mmio, | 187 | .mmio = gk110_gr_pack_mmio, |
187 | .fecs.ucode = &gk110_gr_fecs_ucode, | 188 | .fecs.ucode = &gk110_gr_fecs_ucode, |
188 | .gpccs.ucode = &gk110_gr_gpccs_ucode, | 189 | .gpccs.ucode = &gk110_gr_gpccs_ucode, |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c index f5f53e6c03e3..2f029cad40cd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c | |||
@@ -103,6 +103,7 @@ gk110b_gr_pack_mmio[] = { | |||
103 | static const struct gf100_gr_func | 103 | static const struct gf100_gr_func |
104 | gk110b_gr = { | 104 | gk110b_gr = { |
105 | .init = gk104_gr_init, | 105 | .init = gk104_gr_init, |
106 | .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, | ||
106 | .mmio = gk110b_gr_pack_mmio, | 107 | .mmio = gk110b_gr_pack_mmio, |
107 | .fecs.ucode = &gk110_gr_fecs_ucode, | 108 | .fecs.ucode = &gk110_gr_fecs_ucode, |
108 | .gpccs.ucode = &gk110_gr_gpccs_ucode, | 109 | .gpccs.ucode = &gk110_gr_gpccs_ucode, |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c index ca66e9e62650..01eb0e8cd4d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c | |||
@@ -162,6 +162,7 @@ gk208_gr_gpccs_ucode = { | |||
162 | static const struct gf100_gr_func | 162 | static const struct gf100_gr_func |
163 | gk208_gr = { | 163 | gk208_gr = { |
164 | .init = gk104_gr_init, | 164 | .init = gk104_gr_init, |
165 | .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, | ||
165 | .mmio = gk208_gr_pack_mmio, | 166 | .mmio = gk208_gr_pack_mmio, |
166 | .fecs.ucode = &gk208_gr_fecs_ucode, | 167 | .fecs.ucode = &gk208_gr_fecs_ucode, |
167 | .gpccs.ucode = &gk208_gr_gpccs_ucode, | 168 | .gpccs.ucode = &gk208_gr_gpccs_ucode, |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index 62f40b9aaec7..4ca8ed15191c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | |||
@@ -272,6 +272,8 @@ gk20a_gr_init(struct gf100_gr *gr) | |||
272 | 272 | ||
273 | nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); | 273 | nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); |
274 | 274 | ||
275 | gr->func->init_rop_active_fbps(gr); | ||
276 | |||
275 | /* Enable FIFO access */ | 277 | /* Enable FIFO access */ |
276 | nvkm_wr32(device, 0x400500, 0x00010001); | 278 | nvkm_wr32(device, 0x400500, 0x00010001); |
277 | 279 | ||
@@ -309,6 +311,7 @@ gk20a_gr_init(struct gf100_gr *gr) | |||
309 | static const struct gf100_gr_func | 311 | static const struct gf100_gr_func |
310 | gk20a_gr = { | 312 | gk20a_gr = { |
311 | .init = gk20a_gr_init, | 313 | .init = gk20a_gr_init, |
314 | .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, | ||
312 | .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask, | 315 | .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask, |
313 | .rops = gf100_gr_rops, | 316 | .rops = gf100_gr_rops, |
314 | .ppc_nr = 1, | 317 | .ppc_nr = 1, |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index 487bd65b167d..56b9669f076a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c | |||
@@ -358,6 +358,8 @@ gm107_gr_init(struct gf100_gr *gr) | |||
358 | nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); | 358 | nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); |
359 | nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); | 359 | nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); |
360 | 360 | ||
361 | gr->func->init_rop_active_fbps(gr); | ||
362 | |||
361 | nvkm_wr32(device, 0x400500, 0x00010001); | 363 | nvkm_wr32(device, 0x400500, 0x00010001); |
362 | 364 | ||
363 | nvkm_wr32(device, 0x400100, 0xffffffff); | 365 | nvkm_wr32(device, 0x400100, 0xffffffff); |
@@ -440,6 +442,7 @@ gm107_gr_gpccs_ucode = { | |||
440 | static const struct gf100_gr_func | 442 | static const struct gf100_gr_func |
441 | gm107_gr = { | 443 | gm107_gr = { |
442 | .init = gm107_gr_init, | 444 | .init = gm107_gr_init, |
445 | .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, | ||
443 | .mmio = gm107_gr_pack_mmio, | 446 | .mmio = gm107_gr_pack_mmio, |
444 | .fecs.ucode = &gm107_gr_fecs_ucode, | 447 | .fecs.ucode = &gm107_gr_fecs_ucode, |
445 | .gpccs.ucode = &gm107_gr_gpccs_ucode, | 448 | .gpccs.ucode = &gm107_gr_gpccs_ucode, |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c index 28002a606ac8..d9f320fa7dce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c | |||
@@ -52,6 +52,15 @@ gm200_gr_init_gpc_mmu(struct gf100_gr *gr) | |||
52 | nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); | 52 | nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); |
53 | } | 53 | } |
54 | 54 | ||
55 | static void | ||
56 | gm200_gr_init_rop_active_fbps(struct gf100_gr *gr) | ||
57 | { | ||
58 | struct nvkm_device *device = gr->base.engine.subdev.device; | ||
59 | const u32 fbp_count = nvkm_rd32(device, 0x12006c); | ||
60 | nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ | ||
61 | nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ | ||
62 | } | ||
63 | |||
55 | int | 64 | int |
56 | gm200_gr_init(struct gf100_gr *gr) | 65 | gm200_gr_init(struct gf100_gr *gr) |
57 | { | 66 | { |
@@ -98,6 +107,8 @@ gm200_gr_init(struct gf100_gr *gr) | |||
98 | nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); | 107 | nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); |
99 | nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804)); | 108 | nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804)); |
100 | 109 | ||
110 | gr->func->init_rop_active_fbps(gr); | ||
111 | |||
101 | nvkm_wr32(device, 0x400500, 0x00010001); | 112 | nvkm_wr32(device, 0x400500, 0x00010001); |
102 | nvkm_wr32(device, 0x400100, 0xffffffff); | 113 | nvkm_wr32(device, 0x400100, 0xffffffff); |
103 | nvkm_wr32(device, 0x40013c, 0xffffffff); | 114 | nvkm_wr32(device, 0x40013c, 0xffffffff); |
@@ -199,6 +210,7 @@ static const struct gf100_gr_func | |||
199 | gm200_gr = { | 210 | gm200_gr = { |
200 | .init = gm200_gr_init, | 211 | .init = gm200_gr_init, |
201 | .init_gpc_mmu = gm200_gr_init_gpc_mmu, | 212 | .init_gpc_mmu = gm200_gr_init_gpc_mmu, |
213 | .init_rop_active_fbps = gm200_gr_init_rop_active_fbps, | ||
202 | .rops = gm200_gr_rops, | 214 | .rops = gm200_gr_rops, |
203 | .ppc_nr = 2, | 215 | .ppc_nr = 2, |
204 | .grctx = &gm200_grctx, | 216 | .grctx = &gm200_grctx, |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index 712f036d09f3..69479af1d829 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | |||
@@ -66,6 +66,7 @@ static const struct gf100_gr_func | |||
66 | gm20b_gr = { | 66 | gm20b_gr = { |
67 | .init = gk20a_gr_init, | 67 | .init = gk20a_gr_init, |
68 | .init_gpc_mmu = gm20b_gr_init_gpc_mmu, | 68 | .init_gpc_mmu = gm20b_gr_init_gpc_mmu, |
69 | .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, | ||
69 | .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask, | 70 | .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask, |
70 | .rops = gm200_gr_rops, | 71 | .rops = gm200_gr_rops, |
71 | .ppc_nr = 1, | 72 | .ppc_nr = 1, |