Merge tag 'qcom-arm64-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64

Qualcomm ARM64 Updates for v4.8

* Enable assorted peripherals on APQ8016 SBC
* Update reserved memory on MSM8916
* Add MSM8996 peripheral support
* Add SCM firmware node on MSM8916
* Add PMU node on MSM8916
* Add PSCI cpuidle support on MSM8916

* tag 'qcom-arm64-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (22 commits)
  arm64: dts: msm8996: add sdc2 support
  arm64: dts: msm8996: add sdc2 pinctrl
  arm64: dts: msm8996: add support to blsp2_spi5
  arm64: dts: msm8996: add support to blsp2_spi5 pinctrl
  arm64: dts: msm8996: add support to blsp1_spi0
  arm64: dts: msm8996: add support to blsp1_spi0 pinctrl
  arm64: dts: msm8996: add support to blsp2_i2c0
  arm64: dts: msm8996: add support to blsp2_i2c0 pinctrl
  arm64: dts: msm8996: add support to blsp2_i2c1
  arm64: dts: msm8996: add blsp2_i2c1 pinctrl
  arm64: dts: msm8996: add support to blsp1_i2c2 device
  arm64: dts: msm8996: add blsp1_i2c2 pinctrl nodes.
  arm64: dts: msm8996: add support blsp2_uart2
  arm64: dts: msm8996: add blsp2_uart2 pinctrl nodes.
  arm64: dts: msm8996: add blsp2_uart1 pinctrl
  arm64: dts: msm8996: add msmgpio label
  ARM: dts: msm8916: Update reserved-memory
  arm64: dts: msm8916: Add SCM firmware node
  arm64: dts: qcom: Add msm8916 PMU node
  ARM64: dts: Add PSCI cpuidle support for MSM8916
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>

4 files changed, 496 insertions, 4 deletions

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 205ef89b8ca0..18639bc0a506 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -33,6 +33,10 @@
         };
 
         soc {
+                dma@7884000 {
+                        status = "okay";
+                };
+
                 serial@78af000 {
                         label = "LS-UART0";
                         status = "okay";
@@ -140,6 +144,18 @@
                         status = "okay";
                 };
 
+                sdhci@07864000 {
+                        vmmc-supply = <&pm8916_l11>;
+                        vqmmc-supply = <&pm8916_l12>;
+
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+                        pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+                        cd-gpios = <&msmgpio 38 0x1>;
+                        status = "okay";
+                };
+
                 usb@78d9000 {
                         extcon = <&usb_id>, <&usb_id>;
                         status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 96812007850e..11bdc24cfc74 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -42,13 +42,48 @@
                 #size-cells = <2>;
                 ranges;
 
-                reserve_aligned@86000000 {
-                        reg = <0x0 0x86000000 0x0 0x0300000>;
+                tz-apps@86000000 {
+                        reg = <0x0 0x86000000 0x0 0x300000>;
                         no-map;
                 };
 
                 smem_mem: smem_region@86300000 {
-                        reg = <0x0 0x86300000 0x0 0x0100000>;
+                        reg = <0x0 0x86300000 0x0 0x100000>;
+                        no-map;
+                };
+
+                hypervisor@86400000 {
+                        reg = <0x0 0x86400000 0x0 0x100000>;
+                        no-map;
+                };
+
+                tz@86500000 {
+                        reg = <0x0 0x86500000 0x0 0x180000>;
+                        no-map;
+                };
+
+                reserved@8668000 {
+                        reg = <0x0 0x86680000 0x0 0x80000>;
+                        no-map;
+                };
+
+                rmtfs@86700000 {
+                        reg = <0x0 0x86700000 0x0 0xe0000>;
+                        no-map;
+                };
+
+                rfsa@867e00000 {
+                        reg = <0x0 0x867e0000 0x0 0x20000>;
+                        no-map;
+                };
+
+                mpss@86800000 {
+                        reg = <0x0 0x86800000 0x0 0x2b00000>;
+                        no-map;
+                };
+
+                wcnss@89300000 {
+                        reg = <0x0 0x89300000 0x0 0x600000>;
                         no-map;
                 };
         };
@@ -62,6 +97,8 @@
                         compatible = "arm,cortex-a53", "arm,armv8";
                         reg = <0x0>;
                         next-level-cache = <&L2_0>;
+                        enable-method = "psci";
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 CPU1: cpu@1 {
@@ -69,6 +106,8 @@
                         compatible = "arm,cortex-a53", "arm,armv8";
                         reg = <0x1>;
                         next-level-cache = <&L2_0>;
+                        enable-method = "psci";
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 CPU2: cpu@2 {
@@ -76,6 +115,8 @@
                         compatible = "arm,cortex-a53", "arm,armv8";
                         reg = <0x2>;
                         next-level-cache = <&L2_0>;
+                        enable-method = "psci";
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 CPU3: cpu@3 {
@@ -83,12 +124,35 @@
                         compatible = "arm,cortex-a53", "arm,armv8";
                         reg = <0x3>;
                         next-level-cache = <&L2_0>;
+                        enable-method = "psci";
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 L2_0: l2-cache {
                       compatible = "cache";
                       cache-level = <2>;
                 };
+
+                idle-states {
+                        CPU_SPC: spc {
+                                compatible = "arm,idle-state";
+                                arm,psci-suspend-param = <0x40000002>;
+                                entry-latency-us = <130>;
+                                exit-latency-us = <150>;
+                                min-residency-us = <2000>;
+                                local-timer-stop;
+                        };
+                };
+        };
+
+        psci {
+                compatible = "arm,psci-1.0";
+                method = "smc";
+        };
+
+        pmu {
+                compatible = "arm,armv8-pmuv3";
+                interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
         };
 
         timer {
@@ -122,6 +186,14 @@
                 hwlocks = <&tcsr_mutex 3>;
         };
 
+        firmware {
+                scm {
+                        compatible = "qcom,scm";
+                        clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
+                        clock-names = "core", "bus", "iface";
+                };
+        };
+
         soc: soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
new file mode 100644
index 000000000000..659940434842
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&msmgpio {
+
+        blsp1_spi0_default: blsp1_spi0_default {
+                pinmux {
+                        function = "blsp_spi1";
+                        pins = "gpio0", "gpio1", "gpio3";
+                };
+                pinmux_cs {
+                        function = "gpio";
+                        pins = "gpio2";
+                };
+                pinconf {
+                        pins = "gpio0", "gpio1", "gpio3";
+                        drive-strength = <12>;
+                        bias-disable;
+                };
+                pinconf_cs {
+                        pins = "gpio2";
+                        drive-strength = <16>;
+                        bias-disable;
+                        output-high;
+                };
+        };
+
+        blsp1_spi0_sleep: blsp1_spi0_sleep {
+                pinmux {
+                        function = "gpio";
+                        pins = "gpio0", "gpio1", "gpio2", "gpio3";
+                };
+                pinconf {
+                        pins = "gpio0", "gpio1", "gpio2", "gpio3";
+                        drive-strength = <2>;
+                        bias-pull-down;
+                };
+        };
+
+        blsp1_i2c2_default: blsp1_i2c2_default {
+                pinmux {
+                        function = "blsp_i2c3";
+                        pins = "gpio47", "gpio48";
+                };
+                pinconf {
+                        pins = "gpio47", "gpio48";
+                        drive-strength = <16>;
+                        bias-disable = <0>;
+                };
+        };
+
+        blsp1_i2c2_sleep: blsp1_i2c2_sleep {
+                pinmux {
+                        function = "gpio";
+                        pins = "gpio47", "gpio48";
+                };
+                pinconf {
+                        pins = "gpio47", "gpio48";
+                        drive-strength = <2>;
+                        bias-disable = <0>;
+                };
+        };
+
+        blsp2_i2c0_default: blsp2_i2c0 {
+                pinmux {
+                        function = "blsp_i2c7";
+                        pins = "gpio55", "gpio56";
+                };
+                pinconf {
+                        pins = "gpio55", "gpio56";
+                        drive-strength = <16>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_i2c0_sleep: blsp2_i2c0_sleep {
+                pinmux {
+                        function = "gpio";
+                        pins = "gpio55", "gpio56";
+                };
+                pinconf {
+                        pins = "gpio55", "gpio56";
+                        drive-strength = <2>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_uart1_2pins_default: blsp2_uart1_2pins {
+                pinmux {
+                        function = "blsp_uart8";
+                        pins = "gpio4", "gpio5";
+                };
+                pinconf {
+                        pins = "gpio4", "gpio5";
+                        drive-strength = <16>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep {
+                pinmux {
+                        function = "gpio";
+                        pins = "gpio4", "gpio5";
+                };
+                pinconf {
+                        pins = "gpio4", "gpio5";
+                        drive-strength = <2>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_uart1_4pins_default: blsp2_uart1_4pins {
+                pinmux {
+                        function = "blsp_uart8";
+                        pins = "gpio4", "gpio5", "gpio6", "gpio7";
+                };
+
+                pinconf {
+                        pins = "gpio4", "gpio5", "gpio6", "gpio7";
+                        drive-strength = <16>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep {
+                pinmux {
+                        function = "gpio";
+                        pins = "gpio4", "gpio5", "gpio6", "gpio7";
+                };
+
+                pinconf {
+                        pins = "gpio4", "gpiio5", "gpio6", "gpio7";
+                        drive-strength = <2>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_i2c1_default: blsp2_i2c1 {
+                pinmux {
+                        function = "blsp_i2c8";
+                        pins = "gpio6", "gpio7";
+                };
+                pinconf {
+                        pins = "gpio6", "gpio7";
+                        drive-strength = <16>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_i2c1_sleep: blsp2_i2c1_sleep {
+                pinmux {
+                        function = "gpio";
+                        pins = "gpio6", "gpio7";
+                };
+                pinconf {
+                        pins = "gpio6", "gpio7";
+                        drive-strength = <2>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_uart2_2pins_default: blsp2_uart2_2pins {
+                pinmux {
+                        function = "blsp_uart9";
+                        pins = "gpio49", "gpio50";
+                };
+                pinconf {
+                        pins = "gpio49", "gpio50";
+                        drive-strength = <16>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep {
+                pinmux {
+                        function = "gpio";
+                        pins = "gpio49", "gpio50";
+                };
+                pinconf {
+                        pins = "gpio49", "gpio50";
+                        drive-strength = <2>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_uart2_4pins_default: blsp2_uart2_4pins {
+                pinmux {
+                        function = "blsp_uart9";
+                        pins = "gpio49", "gpio50", "gpio51", "gpio52";
+                };
+
+                pinconf {
+                        pins = "gpio49", "gpio50", "gpio51", "gpio52";
+                        drive-strength = <16>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep {
+                pinmux {
+                        function = "gpio";
+                        pins = "gpio49", "gpio50", "gpio51", "gpio52";
+                };
+
+                pinconf {
+                        pins = "gpio49", "gpio50", "gpio51", "gpio52";
+                        drive-strength = <2>;
+                        bias-disable;
+                };
+        };
+
+        blsp2_spi5_default: blsp2_spi5_default {
+                pinmux {
+                        function = "blsp_spi12";
+                        pins = "gpio85", "gpio86", "gpio88";
+                };
+                pinmux_cs {
+                        function = "gpio";
+                        pins = "gpio87";
+                };
+                pinconf {
+                        pins = "gpio85", "gpio86", "gpio88";
+                        drive-strength = <12>;
+                        bias-disable;
+                };
+                pinconf_cs {
+                        pins = "gpio87";
+                        drive-strength = <16>;
+                        bias-disable;
+                        output-high;
+                };
+        };
+
+        blsp2_spi5_sleep: blsp2_spi5_sleep {
+                pinmux {
+                        function = "gpio";
+                        pins = "gpio85", "gpio86", "gpio87", "gpio88";
+                };
+                pinconf {
+                        pins = "gpio85", "gpio86", "gpio87", "gpio88";
+                        drive-strength = <2>;
+                        bias-pull-down;
+                };
+        };
+
+        sdc2_clk_on: sdc2_clk_on {
+                config {
+                        pins = "sdc2_clk";
+                        bias-disable;           /* NO pull */
+                        drive-strength = <16>;  /* 16 MA */
+                };
+        };
+
+        sdc2_clk_off: sdc2_clk_off {
+                config {
+                        pins = "sdc2_clk";
+                        bias-disable;           /* NO pull */
+                        drive-strength = <2>;   /* 2 MA */
+                };
+        };
+
+        sdc2_cmd_on: sdc2_cmd_on {
+                config {
+                        pins = "sdc2_cmd";
+                        bias-pull-up;           /* pull up */
+                        drive-strength = <10>;  /* 10 MA */
+                };
+        };
+
+        sdc2_cmd_off: sdc2_cmd_off {
+                config {
+                        pins = "sdc2_cmd";
+                        bias-pull-up;           /* pull up */
+                        drive-strength = <2>;   /* 2 MA */
+                };
+        };
+
+        sdc2_data_on: sdc2_data_on {
+                config {
+                        pins = "sdc2_data";
+                        bias-pull-up;           /* pull up */
+                        drive-strength = <10>;  /* 10 MA */
+                };
+        };
+
+        sdc2_data_off: sdc2_data_off {
+                config {
+                        pins = "sdc2_data";
+                        bias-pull-up;           /* pull up */
+                        drive-strength = <2>;   /* 2 MA */
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0506fb808c56..55ec3e8326b7 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -151,6 +151,36 @@
                         reg = <0x300000 0x90000>;
                 };
 
+                blsp1_spi0: spi@07575000 {
+                        compatible = "qcom,spi-qup-v2.2.1";
+                        reg = <0x07575000 0x600>;
+                        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+                                 <&gcc GCC_BLSP1_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&blsp1_spi0_default>;
+                        pinctrl-1 = <&blsp1_spi0_sleep>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                blsp2_i2c0: i2c@075b5000 {
+                        compatible = "qcom,i2c-qup-v2.2.1";
+                        reg = <0x075b5000 0x1000>;
+                        interrupts = <GIC_SPI 101 0>;
+                        clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+                                <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
+                        clock-names = "iface", "core";
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&blsp2_i2c0_default>;
+                        pinctrl-1 = <&blsp2_i2c0_sleep>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
                 blsp2_uart1: serial@75b0000 {
                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
                         reg = <0x75b0000 0x1000>;
@@ -161,7 +191,77 @@
                         status = "disabled";
                 };
 
-                pinctrl@1010000 {
+                blsp2_i2c1: i2c@075b6000 {
+                        compatible = "qcom,i2c-qup-v2.2.1";
+                        reg = <0x075b6000 0x1000>;
+                        interrupts = <GIC_SPI 102 0>;
+                        clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+                                <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
+                        clock-names = "iface", "core";
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&blsp2_i2c1_default>;
+                        pinctrl-1 = <&blsp2_i2c1_sleep>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                blsp2_uart2: serial@75b1000 {
+                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                        reg = <0x075b1000 0x1000>;
+                        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
+                                 <&gcc GCC_BLSP2_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
+
+                blsp1_i2c2: i2c@07577000 {
+                        compatible = "qcom,i2c-qup-v2.2.1";
+                        reg = <0x07577000 0x1000>;
+                        interrupts = <GIC_SPI 97 0>;
+                        clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+                                <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+                        clock-names = "iface", "core";
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&blsp1_i2c2_default>;
+                        pinctrl-1 = <&blsp1_i2c2_sleep>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                blsp2_spi5: spi@075ba000{
+                        compatible = "qcom,spi-qup-v2.2.1";
+                        reg = <0x075ba000 0x600>;
+                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
+                                 <&gcc GCC_BLSP2_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&blsp2_spi5_default>;
+                        pinctrl-1 = <&blsp2_spi5_sleep>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                sdhc2: sdhci@74a4900 {
+                         status = "disabled";
+                         compatible = "qcom,sdhci-msm-v4";
+                         reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
+                         reg-names = "hc_mem", "core_mem";
+
+                         interrupts = <0 125 0>, <0 221 0>;
+                         interrupt-names = "hc_irq", "pwr_irq";
+
+                         clock-names = "iface", "core";
+                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+                         <&gcc GCC_SDCC2_APPS_CLK>;
+                         bus-width = <4>;
+                 };
+
+                msmgpio: pinctrl@1010000 {
                         compatible = "qcom,msm8996-pinctrl";
                         reg = <0x01010000 0x300000>;
                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@@ -267,3 +367,4 @@
                 };
         };
 };
+#include "msm8996-pins.dtsi"