Merge tag 'mvebu-dt-3.20' of git://git.infradead.org/linux-mvebu into next/dt

Merge "mvebu: dt for v3.20" from Andrew Lunn:

mvebu dt changes for v3.20 (part #1)

- Add Armada 388 General Purpose Development Board support
- Add Device Tree description of the Armada 388 SoC
- Document the Device Tree binding for the Armada 388 SoC
- a38x: Add missing labels
- a38x: Add more pinctrl functions
- Add Armada 385 Access Point Development Board support
- Add a number of pinctrl functions
- A38x: Remove redundant pinctrl informations
- a38x: Fix node names
- Add support for Seagate BlackArmor NAS220
- kirkwood: enable phy driver for SATA controller on 88f6192
- gpio_poweroff support for Iomega ix2-200
- Use all remaining MTD space foor rootfs of Iomega ix2-200

* tag 'mvebu-dt-3.20' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: Add Armada 388 General Purpose Development Board support
  ARM: mvebu: Add Device Tree description of the Armada 388 SoC
  ARM: mvebu: Document the Device Tree binding for the Armada 388 SoC
  ARM: mvebu: a38x: Add missing labels
  ARM: mvebu: a38x: Add more pinctrl functions
  ARM: mvebu: Add Armada 385 Access Point Development Board support
  ARM: mvebu: Add a number of pinctrl functions
  ARM: mvebu: A38x: Remove redundant pinctrl informations
  ARM: mvebu: a38x: Fix node names
  Kirkwood: add support for Seagate BlackArmor NAS220
  ARM: dts: kirkwood: enable phy driver for SATA controller on 88f6192
  ARM: dts: add gpio_poweroff support for Iomega ix2-200
  ARM: dts: use all remaining MTD space foor rootfs of Iomega ix2-200

Signed-off-by: Olof Johansson <olof@lixom.net>

Signed-off-by: Olof Johansson <olof@lixom.net>

13 files changed, 830 insertions, 20 deletions

diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt b/Documentation/devicetree/bindings/arm/armada-38x.txt
index ad9f8ed4d9bd..202953f1887e 100644
--- a/Documentation/devicetree/bindings/arm/armada-38x.txt
+++ b/Documentation/devicetree/bindings/arm/armada-38x.txt
@@ -15,6 +15,13 @@ Required root node property:
 
 compatible: must contain "marvell,armada385"
 
+In addition, boards using the Marvell Armada 388 SoC shall have the
+following property before the previous one:
+
+Required root node property:
+
+compatible: must contain "marvell,armada388"
+
 Example:
 
 compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1e626f6d45c9..43ae1918c1f5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_KEYSTONE) += \
         k2e-evm.dtb
 dtb-$(CONFIG_MACH_KIRKWOOD) += \
         kirkwood-b3.dtb \
+        kirkwood-blackarmor-nas220.dtb \
         kirkwood-cloudbox.dtb \
         kirkwood-d2net.dtb \
         kirkwood-db-88f6281.dtb \
@@ -602,8 +603,10 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
 dtb-$(CONFIG_MACH_ARMADA_375) += \
         armada-375-db.dtb
 dtb-$(CONFIG_MACH_ARMADA_38X) += \
-        armada-385-db.dtb \
-        armada-385-rd.dtb
+        armada-385-db-ap.dtb \
+        armada-388-db.dtb \
+        armada-388-gp.dtb \
+        armada-388-rd.dtb
 dtb-$(CONFIG_MACH_ARMADA_XP) += \
         armada-xp-axpwifiap.dtb \
         armada-xp-db.dtb \
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
index 4173a8ab34e7..7e509d2d74d0 100644
--- a/arch/arm/boot/dts/armada-380.dtsi
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -32,9 +32,8 @@
 
         soc {
                 internal-regs {
-                        pinctrl {
+                        pinctrl@18000 {
                                 compatible = "marvell,mv88f6810-pinctrl";
-                                reg = <0x18000 0x20>;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
new file mode 100644
index 000000000000..57b9119fb3e0
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -0,0 +1,178 @@
+/*
+ * Device Tree file for Marvell Armada 385 Access Point Development board
+ * (DB-88F6820-AP)
+ *
+ *  Copyright (C) 2014 Marvell
+ *
+ * Nadav Haklai <nadavh@marvell.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ *     License version 2.  This program is licensed "as is" without
+ *     any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "Marvell Armada 385 Access Point Development Board";
+        compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart1;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000>; /* 2GB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+                internal-regs {
+                        spi1: spi@10680 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi1_pins>;
+                                status = "okay";
+
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "st,m25p128";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <54000000>;
+                                };
+                        };
+
+                        i2c0: i2c@11000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins>;
+                                status = "okay";
+
+                                /*
+                                 * This bus is wired to two EEPROM
+                                 * sockets, one of which holding the
+                                 * board ID used by the bootloader.
+                                 * Erasing this EEPROM's content will
+                                 * brick the board.
+                                 * Use this bus with caution.
+                                 */
+                        };
+
+                        mdio@72004 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mdio_pins>;
+
+                                phy0: ethernet-phy@1 {
+                                        reg = <1>;
+                                };
+
+                                phy1: ethernet-phy@4 {
+                                        reg = <4>;
+                                };
+
+                                phy2: ethernet-phy@6 {
+                                        reg = <6>;
+                                };
+                        };
+
+                        /* UART0 is exposed through the JP8 connector */
+                        uart0: serial@12000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&uart0_pins>;
+                                status = "okay";
+                        };
+
+                        /*
+                         * UART1 is exposed through a FTDI chip
+                         * wired to the mini-USB connector
+                         */
+                        uart1: serial@12100 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&uart1_pins>;
+                                status = "okay";
+                        };
+
+                        ethernet@30000 {
+                                status = "okay";
+                                phy = <&phy2>;
+                                phy-mode = "sgmii";
+                        };
+
+                        ethernet@34000 {
+                                status = "okay";
+                                phy = <&phy1>;
+                                phy-mode = "sgmii";
+                        };
+
+                        ethernet@70000 {
+                                pinctrl-names = "default";
+
+                                /*
+                                 * The Reference Clock 0 is used to
+                                 * provide a clock to the PHY
+                                 */
+                                pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /*
+                         * The three PCIe units are accessible through
+                         * standard mini-PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+
+                        pcie@3,0 {
+                                /* Port 2, Lane 0 */
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index 6283d7912f71..a54a252ddb4c 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -37,9 +37,8 @@
 
         soc {
                 internal-regs {
-                        pinctrl {
+                        pinctrl@18000 {
                                 compatible = "marvell,mv88f6820-pinctrl";
-                                reg = <0x18000 0x20>;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-388-db.dts
index 2aaa9d2ac284..e200836c30be 100644
--- a/arch/arm/boot/dts/armada-385-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -1,5 +1,5 @@
 /*
- * Device Tree file for Marvell Armada 385 evaluation board
+ * Device Tree file for Marvell Armada 388 evaluation board
  * (DB-88F6820)
  *
  *  Copyright (C) 2014 Marvell
@@ -12,11 +12,12 @@
  */
 
 /dts-v1/;
-#include "armada-385.dtsi"
+#include "armada-388.dtsi"
 
 / {
         model = "Marvell Armada 385 Development Board";
-        compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada380";
+        compatible = "marvell,a385-db", "marvell,armada388",
+                "marvell,armada385", "marvell,armada380";
 
         chosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
@@ -74,7 +75,7 @@
                                 phy-mode = "rgmii-id";
                         };
 
-                        mdio {
+                        mdio@72004 {
                                 phy0: ethernet-phy@0 {
                                         reg = <0>;
                                 };
diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
new file mode 100644
index 000000000000..4df22bf91683
--- /dev/null
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -0,0 +1,288 @@
+/*
+ * Device Tree file for Marvell Armada 385 development board
+ * (RD-88F6820-GP)
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ *     License version 2.  This program is licensed "as is" without
+ *     any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-388.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "Marvell Armada 385 GP";
+        compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000>; /* 2 GB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+                internal-regs {
+                        spi@10600 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi0_pins>;
+                                status = "okay";
+
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "st,m25p128";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <50000000>;
+                                        m25p,fast-read;
+                                };
+                        };
+
+                        i2c@11000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins>;
+                                status = "okay";
+                                clock-frequency = <100000>;
+                                /*
+                                 * The EEPROM located at adresse 54 is needed
+                                 * for the boot - DO NOT ERASE IT -
+                                 */
+
+                                expander0: pca9555@20 {
+                                        compatible = "nxp,pca9555";
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pca0_pins>;
+                                        interrupt-parent = <&gpio0>;
+                                        interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        reg = <0x20>;
+                                };
+
+                                expander1: pca9555@21 {
+                                        compatible = "nxp,pca9555";
+                                        pinctrl-names = "default";
+                                        interrupt-parent = <&gpio0>;
+                                        interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        reg = <0x21>;
+                                };
+
+                        };
+
+                        serial@12000 {
+                                /*
+                                 * Exported on the micro USB connector CON16
+                                 * through an FTDI
+                                 */
+
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&uart0_pins>;
+                                status = "okay";
+                        };
+
+                        /* GE1 CON15 */
+                        ethernet@30000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&ge1_rgmii_pins>;
+                                status = "okay";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii-id";
+                        };
+
+                        /* CON4 */
+                        usb@50000 {
+                                vcc-supply = <&reg_usb2_0_vbus>;
+                                status = "okay";
+                        };
+
+                        /* GE0 CON1 */
+                        ethernet@70000 {
+                                pinctrl-names = "default";
+                                /*
+                                 * The Reference Clock 0 is used to provide a
+                                 * clock to the PHY
+                                 */
+                                pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+
+
+                        mdio@72004 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mdio_pins>;
+
+                                phy0: ethernet-phy@1 {
+                                        reg = <1>;
+                                };
+
+                                phy1: ethernet-phy@0 {
+                                        reg = <0>;
+                                };
+                        };
+
+                        sata@a8000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
+                                status = "okay";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        sata@e0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
+                                status = "okay";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        sdhci@d8000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&sdhci_pins>;
+                                cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
+                                no-1-8-v;
+                                wp-inverted;
+                                bus-width = <8>;
+                                status = "okay";
+                        };
+
+                        /* CON5 */
+                        usb3@f0000 {
+                                vcc-supply = <&reg_usb2_1_vbus>;
+                                status = "okay";
+                        };
+
+                        /* CON7 */
+                        usb3@f8000 {
+                                vcc-supply = <&reg_usb3_vbus>;
+                                status = "okay";
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+                        /*
+                         * One PCIe units is accessible through
+                         * standard PCIe slot on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /*
+                         * The two other PCIe units are accessible
+                         * through mini PCIe slot on the board.
+                         */
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@3,0 {
+                                /* Port 2, Lane 0 */
+                                status = "okay";
+                        };
+                };
+
+                gpio-fan {
+                        compatible = "gpio-fan";
+                        gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
+                        gpio-fan,speed-map = <   0 0
+                                              3000 1>;
+                };
+        };
+
+        reg_usb3_vbus: usb3-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb3-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                regulator-always-on;
+                gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
+        };
+
+        reg_usb2_0_vbus: v5-vbus0 {
+                compatible = "regulator-fixed";
+                regulator-name = "v5.0-vbus0";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                regulator-always-on;
+                gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
+        };
+
+        reg_usb2_1_vbus: v5-vbus1 {
+                compatible = "regulator-fixed";
+                regulator-name = "v5.0-vbus1";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                regulator-always-on;
+                gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
+        };
+
+        reg_usb2_1_vbus: v5-vbus1 {
+                compatible = "regulator-fixed";
+                regulator-name = "v5.0-vbus1";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                regulator-always-on;
+                gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
+        };
+};
+
+&pinctrl {
+        pca0_pins: pca0_pins {
+                marvell,pins = "mpp18";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
index aaca2861dc87..c98a8f8d01a9 100644
--- a/arch/arm/boot/dts/armada-385-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -1,5 +1,5 @@
 /*
- * Device Tree file for Marvell Armada 385 Reference Design board
+ * Device Tree file for Marvell Armada 388 Reference Design board
  * (RD-88F6820-AP)
  *
  *  Copyright (C) 2014 Marvell
@@ -13,11 +13,12 @@
  */
 
 /dts-v1/;
-#include "armada-385.dtsi"
+#include "armada-388.dtsi"
 
 / {
         model = "Marvell Armada 385 Reference Design";
-        compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";
+        compatible = "marvell,a385-rd", "marvell,armada388",
+                "marvell,armada385","marvell,armada380";
 
         chosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
@@ -67,7 +68,7 @@
                         };
 
 
-                        mdio {
+                        mdio@72004 {
                                 phy0: ethernet-phy@0 {
                                         reg = <0>;
                                 };
diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/armada-388.dtsi
new file mode 100644
index 000000000000..564fa5937e25
--- /dev/null
+++ b/arch/arm/boot/dts/armada-388.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Include file for Marvell Armada 388 SoC.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ *     License version 2.  This program is licensed "as is" without
+ *     any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ * The main difference with the Armada 385 is that the 388 can handle two more
+ * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
+ * property and the name of the SoC, and add the second SATA host which control
+ * the 2 other ports.
+ */
+
+#include "armada-385.dtsi"
+
+/ {
+        model = "Marvell Armada 388 family SoC";
+        compatible = "marvell,armada388", "marvell,armada385",
+                "marvell,armada380";
+
+        soc {
+                internal-regs {
+                        pinctrl@18000 {
+                                compatible = "marvell,mv88f6828-pinctrl";
+                        };
+
+                        sata@e0000 {
+                                compatible = "marvell,armada-380-ahci";
+                                reg = <0xe0000 0x2000>;
+                                interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 30>;
+                                status = "disabled";
+                        };
+
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 74391dace9e7..04fe80d101f8 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -173,7 +173,7 @@
                                 status = "disabled";
                         };
 
-                        serial@12000 {
+                        uart0: serial@12000 {
                                 compatible = "snps,dw-apb-uart";
                                 reg = <0x12000 0x100>;
                                 reg-shift = <2>;
@@ -193,9 +193,94 @@
                                 status = "disabled";
                         };
 
-                        pinctrl {
-                                compatible = "marvell,mv88f6820-pinctrl";
+                        pinctrl: pinctrl@18000 {
                                 reg = <0x18000 0x20>;
+
+                                ge0_rgmii_pins: ge-rgmii-pins-0 {
+                                        marvell,pins = "mpp6", "mpp7", "mpp8",
+                                                       "mpp9", "mpp10", "mpp11",
+                                                       "mpp12", "mpp13", "mpp14",
+                                                       "mpp15", "mpp16", "mpp17";
+                                        marvell,function = "ge0";
+                                };
+
+                                ge1_rgmii_pins: ge-rgmii-pins-1 {
+                                        marvell,pins = "mpp21", "mpp27", "mpp28",
+                                                       "mpp29", "mpp30", "mpp31",
+                                                       "mpp32", "mpp37", "mpp38",
+                                                       "mpp39", "mpp40", "mpp41";
+                                        marvell,function = "ge1";
+                                };
+
+                                i2c0_pins: i2c-pins-0 {
+                                        marvell,pins = "mpp2", "mpp3";
+                                        marvell,function = "i2c0";
+                                };
+
+                                mdio_pins: mdio-pins {
+                                        marvell,pins = "mpp4", "mpp5";
+                                        marvell,function = "ge";
+                                };
+
+                                ref_clk0_pins: ref-clk-pins-0 {
+                                        marvell,pins = "mpp45";
+                                        marvell,function = "ref";
+                                };
+
+                                ref_clk1_pins: ref-clk-pins-1 {
+                                        marvell,pins = "mpp46";
+                                        marvell,function = "ref";
+                                };
+
+                                spi0_pins: spi-pins-0 {
+                                        marvell,pins = "mpp22", "mpp23", "mpp24",
+                                                       "mpp25";
+                                        marvell,function = "spi0";
+                                };
+
+                                spi1_pins: spi-pins-1 {
+                                        marvell,pins = "mpp56", "mpp57", "mpp58",
+                                                       "mpp59";
+                                        marvell,function = "spi1";
+                                };
+
+                                uart0_pins: uart-pins-0 {
+                                        marvell,pins = "mpp0", "mpp1";
+                                        marvell,function = "ua0";
+                                };
+
+                                uart1_pins: uart-pins-1 {
+                                        marvell,pins = "mpp19", "mpp20";
+                                        marvell,function = "ua1";
+                                };
+
+                                sdhci_pins: sdhci-pins {
+                                        marvell,pins = "mpp48", "mpp49", "mpp50",
+                                                       "mpp52", "mpp53", "mpp54",
+                                                       "mpp55", "mpp57", "mpp58",
+                                                       "mpp59";
+                                        marvell,function = "sd0";
+                                };
+
+                                sata0_pins: sata-pins-0 {
+                                        marvell,pins = "mpp20";
+                                        marvell,function = "sata0";
+                                };
+
+                                sata1_pins: sata-pins-1 {
+                                        marvell,pins = "mpp19";
+                                        marvell,function = "sata1";
+                                };
+
+                                sata2_pins: sata-pins-2 {
+                                        marvell,pins = "mpp47";
+                                        marvell,function = "sata2";
+                                };
+
+                                sata3_pins: sata-pins-3 {
+                                        marvell,pins = "mpp44";
+                                        marvell,function = "sata3";
+                                };
                         };
 
                         gpio0: gpio@18100 {
@@ -373,7 +458,7 @@
                                 status = "disabled";
                         };
 
-                        mdio {
+                        mdio@72004 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "marvell,orion-mdio";
diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi
index dd81508b919b..9e6e9e2691d5 100644
--- a/arch/arm/boot/dts/kirkwood-6192.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6192.dtsi
@@ -66,6 +66,8 @@
                         interrupts = <21>;
                         clocks = <&gate_clk 14>, <&gate_clk 15>;
                         clock-names = "0", "1";
+                        phys = <&sata_phy0>, <&sata_phy1>;
+                        phy-names = "port0", "port1";
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts
new file mode 100644
index 000000000000..fa02a9aff05e
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts
@@ -0,0 +1,173 @@
+/*
+ * Device Tree file for Seagate Blackarmor NAS220
+ *
+ * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "kirkwood.dtsi"
+#include "kirkwood-6192.dtsi"
+
+/ {
+        model = "Seagate Blackarmor NAS220";
+        compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192",
+                     "marvell,kirkwood";
+
+        memory { /* 128 MB */
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
+        };
+
+        gpio_poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                button@1{
+                        label = "Reset";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+                };
+
+                button@2{
+                        label = "Power";
+                        linux,code = <KEY_SLEEP>;
+                        gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                blue-power {
+                        label = "nas220:blue:power";
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
+                pinctrl-names = "default";
+
+                sata0_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "SATA0 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
+                };
+
+                sata1_power: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "SATA1 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 28 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+/*
+ * Serial port routed to connector CN5
+ *
+ * pin 1 - TX (CPU's TX)
+ * pin 4 - RX (CPU's RX)
+ * pin 6 - GND
+ */
+&uart0 {
+        status = "okay";
+};
+
+&pinctrl {
+        pinctrl-0 = <&pmx_button_reset &pmx_button_power>;
+        pinctrl-names = "default";
+
+        pmx_act_sata0: pmx-act-sata0 {
+                marvell,pins = "mpp15";
+                marvell,function = "sata0";
+        };
+
+        pmx_act_sata1: pmx-act-sata1 {
+                marvell,pins = "mpp16";
+                marvell,function = "sata1";
+        };
+
+        pmx_power_sata0: pmx-power-sata0 {
+                marvell,pins = "mpp24";
+                marvell,function = "gpio";
+        };
+
+        pmx_power_sata1: pmx-power-sata1 {
+                marvell,pins = "mpp28";
+                marvell,function = "gpio";
+        };
+
+        pmx_button_reset: pmx-button-reset {
+                marvell,pins = "mpp29";
+                marvell,function = "gpio";
+        };
+
+        pmx_button_power: pmx-button-power {
+                marvell,pins = "mpp26";
+                marvell,function = "gpio";
+        };
+};
+
+&sata {
+        status = "okay";
+        nr-ports = <2>;
+};
+
+&i2c0 {
+        status = "okay";
+
+        adt7476: thermal@2e {
+                compatible = "adi,adt7476";
+                reg = <0x2e>;
+        };
+};
+
+&nand {
+        status = "okay";
+};
+
+&mdio {
+        status = "okay";
+
+        ethphy0: ethernet-phy@8 {
+                 reg = <8>;
+        };
+};
+
+&eth0 {
+        status = "okay";
+
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 05291f3990d0..8474bffec0ca 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -169,6 +169,10 @@
                         gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
                 };
         };
+        gpio-poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
+        };
 };
 
 &nand {
@@ -192,8 +196,8 @@
         };
 
         partition@400000 {
-                label = "uInitrd";
-                reg = <0x540000 0x1000000>;
+                label = "rootfs";
+                reg = <0x400000 0x1C00000>;
         };
 };