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authorChen-Yu Tsai <wens@csie.org>2017-04-25 11:25:04 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-05-14 02:31:58 -0400
commit86cf6788a661b8cb459f259e373c5daf09221abe (patch)
tree51f077d2af690b223e1a9d04d05697ec2a659570
parentd281c862de30381c144145a75ec1f0d5efc307ae (diff)
drm/sun4i: Set TCON clock inside sun4i_tconX_mode_set
Currently we are configuring the TCON's dot clock or special clock directly from the encoder mode_set functions. Since we already provide mode_set helper functions for the TCON's 2 channels, we can set the respective clock from those helpers, and reduce the exposure of the TCON's internals. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--drivers/gpu/drm/sun4i/sun4i_rgb.c2
-rw-r--r--drivers/gpu/drm/sun4i/sun4i_tcon.c6
-rw-r--r--drivers/gpu/drm/sun4i/sun4i_tv.c2
3 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index 67f0b91a99de..c9bbb3b560a5 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -176,8 +176,6 @@ static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder,
176 176
177 sun4i_tcon0_mode_set(tcon, mode); 177 sun4i_tcon0_mode_set(tcon, mode);
178 178
179 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
180
181 /* FIXME: This seems to be board specific */ 179 /* FIXME: This seems to be board specific */
182 clk_set_phase(tcon->dclk, 120); 180 clk_set_phase(tcon->dclk, 120);
183} 181}
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 5d7866fce78b..8b6aaa60037d 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -130,6 +130,9 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
130 u8 clk_delay; 130 u8 clk_delay;
131 u32 val = 0; 131 u32 val = 0;
132 132
133 /* Configure the dot clock */
134 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
135
133 /* Adjust clock delay */ 136 /* Adjust clock delay */
134 clk_delay = sun4i_tcon_get_clk_delay(mode, 0); 137 clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
135 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 138 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
@@ -205,6 +208,9 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
205 208
206 WARN_ON(!tcon->quirks->has_channel_1); 209 WARN_ON(!tcon->quirks->has_channel_1);
207 210
211 /* Configure the dot clock */
212 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
213
208 /* Adjust clock delay */ 214 /* Adjust clock delay */
209 clk_delay = sun4i_tcon_get_clk_delay(mode, 1); 215 clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
210 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 216 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 49c49431a053..542da220818b 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -486,8 +486,6 @@ static void sun4i_tv_mode_set(struct drm_encoder *encoder,
486 SUN4I_TVE_RESYNC_FIELD : 0)); 486 SUN4I_TVE_RESYNC_FIELD : 0));
487 487
488 regmap_write(tv->regs, SUN4I_TVE_SLAVE_REG, 0); 488 regmap_write(tv->regs, SUN4I_TVE_SLAVE_REG, 0);
489
490 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
491} 489}
492 490
493static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = { 491static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {