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authorCorey Minyard <cminyard@mvista.com>2017-08-10 14:27:39 -0400
committerRalf Baechle <ralf@linux-mips.org>2017-09-06 05:01:52 -0400
commit866b6a89c6d1876fce25c152ef9f887b41ffcf7f (patch)
treeee1d5a144e4ca31cfbc6d569bbce8cc493d53a2e
parent9fef68686317bc9f85fb4e84e225d26ea2cb1cac (diff)
MIPS: Add DWARF unwinding to assembly
This will allow kdump dumps to work correclty with MIPS and future DWARF unwinding of the stack to give accurate tracebacks. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/16990/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/Makefile4
-rw-r--r--arch/mips/include/asm/asm.h3
-rw-r--r--arch/mips/include/asm/stackframe.h231
-rw-r--r--arch/mips/kernel/genex.S13
-rw-r--r--arch/mips/mm/tlbex-fault.S7
-rw-r--r--arch/mips/vdso/sigreturn.S10
6 files changed, 151 insertions, 117 deletions
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 3db0df37d66a..a96d97a806c9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -299,6 +299,10 @@ ifdef CONFIG_64BIT
299bootvars-y += ADDR_BITS=64 299bootvars-y += ADDR_BITS=64
300endif 300endif
301 301
302# This is required to get dwarf unwinding tables into .debug_frame
303# instead of .eh_frame so we don't discard them.
304KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
305
302LDFLAGS += -m $(ld-emul) 306LDFLAGS += -m $(ld-emul)
303 307
304ifdef CONFIG_MIPS 308ifdef CONFIG_MIPS
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 859cf7048347..81fae23ce7cd 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -55,6 +55,7 @@
55 .type symbol, @function; \ 55 .type symbol, @function; \
56 .ent symbol, 0; \ 56 .ent symbol, 0; \
57symbol: .frame sp, 0, ra; \ 57symbol: .frame sp, 0, ra; \
58 .cfi_startproc; \
58 .insn 59 .insn
59 60
60/* 61/*
@@ -66,12 +67,14 @@ symbol: .frame sp, 0, ra; \
66 .type symbol, @function; \ 67 .type symbol, @function; \
67 .ent symbol, 0; \ 68 .ent symbol, 0; \
68symbol: .frame sp, framesize, rpc; \ 69symbol: .frame sp, framesize, rpc; \
70 .cfi_startproc; \
69 .insn 71 .insn
70 72
71/* 73/*
72 * END - mark end of function 74 * END - mark end of function
73 */ 75 */
74#define END(function) \ 76#define END(function) \
77 .cfi_endproc; \
75 .end function; \ 78 .end function; \
76 .size function, .-function 79 .size function, .-function
77 80
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index d2fb919fb235..5d3563c55e0c 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -19,20 +19,43 @@
19#include <asm/asm-offsets.h> 19#include <asm/asm-offsets.h>
20#include <asm/thread_info.h> 20#include <asm/thread_info.h>
21 21
22/* Make the addition of cfi info a little easier. */
23 .macro cfi_rel_offset reg offset=0 docfi=0
24 .if \docfi
25 .cfi_rel_offset \reg, \offset
26 .endif
27 .endm
28
29 .macro cfi_st reg offset=0 docfi=0
30 LONG_S \reg, \offset(sp)
31 cfi_rel_offset \reg, \offset, \docfi
32 .endm
33
34 .macro cfi_restore reg offset=0 docfi=0
35 .if \docfi
36 .cfi_restore \reg
37 .endif
38 .endm
39
40 .macro cfi_ld reg offset=0 docfi=0
41 LONG_L \reg, \offset(sp)
42 cfi_restore \reg \offset \docfi
43 .endm
44
22#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 45#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
23#define STATMASK 0x3f 46#define STATMASK 0x3f
24#else 47#else
25#define STATMASK 0x1f 48#define STATMASK 0x1f
26#endif 49#endif
27 50
28 .macro SAVE_AT 51 .macro SAVE_AT docfi=0
29 .set push 52 .set push
30 .set noat 53 .set noat
31 LONG_S $1, PT_R1(sp) 54 cfi_st $1, PT_R1, \docfi
32 .set pop 55 .set pop
33 .endm 56 .endm
34 57
35 .macro SAVE_TEMP 58 .macro SAVE_TEMP docfi=0
36#ifdef CONFIG_CPU_HAS_SMARTMIPS 59#ifdef CONFIG_CPU_HAS_SMARTMIPS
37 mflhxu v1 60 mflhxu v1
38 LONG_S v1, PT_LO(sp) 61 LONG_S v1, PT_LO(sp)
@@ -44,20 +67,20 @@
44 mfhi v1 67 mfhi v1
45#endif 68#endif
46#ifdef CONFIG_32BIT 69#ifdef CONFIG_32BIT
47 LONG_S $8, PT_R8(sp) 70 cfi_st $8, PT_R8, \docfi
48 LONG_S $9, PT_R9(sp) 71 cfi_st $9, PT_R9, \docfi
49#endif 72#endif
50 LONG_S $10, PT_R10(sp) 73 cfi_st $10, PT_R10, \docfi
51 LONG_S $11, PT_R11(sp) 74 cfi_st $11, PT_R11, \docfi
52 LONG_S $12, PT_R12(sp) 75 cfi_st $12, PT_R12, \docfi
53#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6) 76#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
54 LONG_S v1, PT_HI(sp) 77 LONG_S v1, PT_HI(sp)
55 mflo v1 78 mflo v1
56#endif 79#endif
57 LONG_S $13, PT_R13(sp) 80 cfi_st $13, PT_R13, \docfi
58 LONG_S $14, PT_R14(sp) 81 cfi_st $14, PT_R14, \docfi
59 LONG_S $15, PT_R15(sp) 82 cfi_st $15, PT_R15, \docfi
60 LONG_S $24, PT_R24(sp) 83 cfi_st $24, PT_R24, \docfi
61#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6) 84#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
62 LONG_S v1, PT_LO(sp) 85 LONG_S v1, PT_LO(sp)
63#endif 86#endif
@@ -71,16 +94,16 @@
71#endif 94#endif
72 .endm 95 .endm
73 96
74 .macro SAVE_STATIC 97 .macro SAVE_STATIC docfi=0
75 LONG_S $16, PT_R16(sp) 98 cfi_st $16, PT_R16, \docfi
76 LONG_S $17, PT_R17(sp) 99 cfi_st $17, PT_R17, \docfi
77 LONG_S $18, PT_R18(sp) 100 cfi_st $18, PT_R18, \docfi
78 LONG_S $19, PT_R19(sp) 101 cfi_st $19, PT_R19, \docfi
79 LONG_S $20, PT_R20(sp) 102 cfi_st $20, PT_R20, \docfi
80 LONG_S $21, PT_R21(sp) 103 cfi_st $21, PT_R21, \docfi
81 LONG_S $22, PT_R22(sp) 104 cfi_st $22, PT_R22, \docfi
82 LONG_S $23, PT_R23(sp) 105 cfi_st $23, PT_R23, \docfi
83 LONG_S $30, PT_R30(sp) 106 cfi_st $30, PT_R30, \docfi
84 .endm 107 .endm
85 108
86/* 109/*
@@ -168,7 +191,7 @@
168 .endm 191 .endm
169#endif 192#endif
170 193
171 .macro SAVE_SOME 194 .macro SAVE_SOME docfi=0
172 .set push 195 .set push
173 .set noat 196 .set noat
174 .set reorder 197 .set reorder
@@ -203,8 +226,11 @@
203#endif 226#endif
204 .set reorder 227 .set reorder
205 move k0, sp 228 move k0, sp
229 .if \docfi
230 .cfi_register sp, k0
231 .endif
206 /* Called from user mode, new stack. */ 232 /* Called from user mode, new stack. */
207 get_saved_sp 233 get_saved_sp docfi=\docfi tosp=1
2088: 2348:
209#ifdef CONFIG_CPU_DADDI_WORKAROUNDS 235#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
210 .set at=k1 236 .set at=k1
@@ -213,8 +239,12 @@
213#ifdef CONFIG_CPU_DADDI_WORKAROUNDS 239#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
214 .set noat 240 .set noat
215#endif 241#endif
216 LONG_S k0, PT_R29(sp) 242 .if \docfi
217 LONG_S $3, PT_R3(sp) 243 .cfi_def_cfa sp,0
244 .endif
245 cfi_st k0, PT_R29, \docfi
246 cfi_rel_offset sp, PT_R29, \docfi
247 cfi_st v1, PT_R3, \docfi
218 /* 248 /*
219 * You might think that you don't need to save $0, 249 * You might think that you don't need to save $0,
220 * but the FPU emulator and gdb remote debug stub 250 * but the FPU emulator and gdb remote debug stub
@@ -222,23 +252,26 @@
222 */ 252 */
223 LONG_S $0, PT_R0(sp) 253 LONG_S $0, PT_R0(sp)
224 mfc0 v1, CP0_STATUS 254 mfc0 v1, CP0_STATUS
225 LONG_S $2, PT_R2(sp) 255 cfi_st v0, PT_R2, \docfi
226 LONG_S v1, PT_STATUS(sp) 256 LONG_S v1, PT_STATUS(sp)
227 LONG_S $4, PT_R4(sp) 257 cfi_st $4, PT_R4, \docfi
228 mfc0 v1, CP0_CAUSE 258 mfc0 v1, CP0_CAUSE
229 LONG_S $5, PT_R5(sp) 259 cfi_st $5, PT_R5, \docfi
230 LONG_S v1, PT_CAUSE(sp) 260 LONG_S v1, PT_CAUSE(sp)
231 LONG_S $6, PT_R6(sp) 261 cfi_st $6, PT_R6, \docfi
232 LONG_S ra, PT_R31(sp) 262 cfi_st ra, PT_R31, \docfi
233 MFC0 ra, CP0_EPC 263 MFC0 ra, CP0_EPC
234 LONG_S $7, PT_R7(sp) 264 cfi_st $7, PT_R7, \docfi
235#ifdef CONFIG_64BIT 265#ifdef CONFIG_64BIT
236 LONG_S $8, PT_R8(sp) 266 cfi_st $8, PT_R8, \docfi
237 LONG_S $9, PT_R9(sp) 267 cfi_st $9, PT_R9, \docfi
238#endif 268#endif
239 LONG_S ra, PT_EPC(sp) 269 LONG_S ra, PT_EPC(sp)
240 LONG_S $25, PT_R25(sp) 270 .if \docfi
241 LONG_S $28, PT_R28(sp) 271 .cfi_rel_offset ra, PT_EPC
272 .endif
273 cfi_st $25, PT_R25, \docfi
274 cfi_st $28, PT_R28, \docfi
242 275
243 /* Set thread_info if we're coming from user mode */ 276 /* Set thread_info if we're coming from user mode */
244 mfc0 k0, CP0_STATUS 277 mfc0 k0, CP0_STATUS
@@ -255,21 +288,21 @@
255 .set pop 288 .set pop
256 .endm 289 .endm
257 290
258 .macro SAVE_ALL 291 .macro SAVE_ALL docfi=0
259 SAVE_SOME 292 SAVE_SOME \docfi
260 SAVE_AT 293 SAVE_AT \docfi
261 SAVE_TEMP 294 SAVE_TEMP \docfi
262 SAVE_STATIC 295 SAVE_STATIC \docfi
263 .endm 296 .endm
264 297
265 .macro RESTORE_AT 298 .macro RESTORE_AT docfi=0
266 .set push 299 .set push
267 .set noat 300 .set noat
268 LONG_L $1, PT_R1(sp) 301 cfi_ld $1, PT_R1, \docfi
269 .set pop 302 .set pop
270 .endm 303 .endm
271 304
272 .macro RESTORE_TEMP 305 .macro RESTORE_TEMP docfi=0
273#ifdef CONFIG_CPU_CAVIUM_OCTEON 306#ifdef CONFIG_CPU_CAVIUM_OCTEON
274 /* Restore the Octeon multiplier state */ 307 /* Restore the Octeon multiplier state */
275 jal octeon_mult_restore 308 jal octeon_mult_restore
@@ -288,33 +321,37 @@
288 mthi $24 321 mthi $24
289#endif 322#endif
290#ifdef CONFIG_32BIT 323#ifdef CONFIG_32BIT
291 LONG_L $8, PT_R8(sp) 324 cfi_ld $8, PT_R8, \docfi
292 LONG_L $9, PT_R9(sp) 325 cfi_ld $9, PT_R9, \docfi
293#endif 326#endif
294 LONG_L $10, PT_R10(sp) 327 cfi_ld $10, PT_R10, \docfi
295 LONG_L $11, PT_R11(sp) 328 cfi_ld $11, PT_R11, \docfi
296 LONG_L $12, PT_R12(sp) 329 cfi_ld $12, PT_R12, \docfi
297 LONG_L $13, PT_R13(sp) 330 cfi_ld $13, PT_R13, \docfi
298 LONG_L $14, PT_R14(sp) 331 cfi_ld $14, PT_R14, \docfi
299 LONG_L $15, PT_R15(sp) 332 cfi_ld $15, PT_R15, \docfi
300 LONG_L $24, PT_R24(sp) 333 cfi_ld $24, PT_R24, \docfi
301 .endm 334 .endm
302 335
303 .macro RESTORE_STATIC 336 .macro RESTORE_STATIC docfi=0
304 LONG_L $16, PT_R16(sp) 337 cfi_ld $16, PT_R16, \docfi
305 LONG_L $17, PT_R17(sp) 338 cfi_ld $17, PT_R17, \docfi
306 LONG_L $18, PT_R18(sp) 339 cfi_ld $18, PT_R18, \docfi
307 LONG_L $19, PT_R19(sp) 340 cfi_ld $19, PT_R19, \docfi
308 LONG_L $20, PT_R20(sp) 341 cfi_ld $20, PT_R20, \docfi
309 LONG_L $21, PT_R21(sp) 342 cfi_ld $21, PT_R21, \docfi
310 LONG_L $22, PT_R22(sp) 343 cfi_ld $22, PT_R22, \docfi
311 LONG_L $23, PT_R23(sp) 344 cfi_ld $23, PT_R23, \docfi
312 LONG_L $30, PT_R30(sp) 345 cfi_ld $30, PT_R30, \docfi
346 .endm
347
348 .macro RESTORE_SP docfi=0
349 cfi_ld sp, PT_R29, \docfi
313 .endm 350 .endm
314 351
315#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 352#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
316 353
317 .macro RESTORE_SOME 354 .macro RESTORE_SOME docfi=0
318 .set push 355 .set push
319 .set reorder 356 .set reorder
320 .set noat 357 .set noat
@@ -329,30 +366,30 @@
329 and v0, v1 366 and v0, v1
330 or v0, a0 367 or v0, a0
331 mtc0 v0, CP0_STATUS 368 mtc0 v0, CP0_STATUS
332 LONG_L $31, PT_R31(sp) 369 cfi_ld $31, PT_R31, \docfi
333 LONG_L $28, PT_R28(sp) 370 cfi_ld $28, PT_R28, \docfi
334 LONG_L $25, PT_R25(sp) 371 cfi_ld $25, PT_R25, \docfi
335 LONG_L $7, PT_R7(sp) 372 cfi_ld $7, PT_R7, \docfi
336 LONG_L $6, PT_R6(sp) 373 cfi_ld $6, PT_R6, \docfi
337 LONG_L $5, PT_R5(sp) 374 cfi_ld $5, PT_R5, \docfi
338 LONG_L $4, PT_R4(sp) 375 cfi_ld $4, PT_R4, \docfi
339 LONG_L $3, PT_R3(sp) 376 cfi_ld $3, PT_R3, \docfi
340 LONG_L $2, PT_R2(sp) 377 cfi_ld $2, PT_R2, \docfi
341 .set pop 378 .set pop
342 .endm 379 .endm
343 380
344 .macro RESTORE_SP_AND_RET 381 .macro RESTORE_SP_AND_RET docfi=0
345 .set push 382 .set push
346 .set noreorder 383 .set noreorder
347 LONG_L k0, PT_EPC(sp) 384 LONG_L k0, PT_EPC(sp)
348 LONG_L sp, PT_R29(sp) 385 RESTORE_SP \docfi
349 jr k0 386 jr k0
350 rfe 387 rfe
351 .set pop 388 .set pop
352 .endm 389 .endm
353 390
354#else 391#else
355 .macro RESTORE_SOME 392 .macro RESTORE_SOME docfi=0
356 .set push 393 .set push
357 .set reorder 394 .set reorder
358 .set noat 395 .set noat
@@ -369,24 +406,24 @@
369 mtc0 v0, CP0_STATUS 406 mtc0 v0, CP0_STATUS
370 LONG_L v1, PT_EPC(sp) 407 LONG_L v1, PT_EPC(sp)
371 MTC0 v1, CP0_EPC 408 MTC0 v1, CP0_EPC
372 LONG_L $31, PT_R31(sp) 409 cfi_ld $31, PT_R31, \docfi
373 LONG_L $28, PT_R28(sp) 410 cfi_ld $28, PT_R28, \docfi
374 LONG_L $25, PT_R25(sp) 411 cfi_ld $25, PT_R25, \docfi
375#ifdef CONFIG_64BIT 412#ifdef CONFIG_64BIT
376 LONG_L $8, PT_R8(sp) 413 cfi_ld $8, PT_R8, \docfi
377 LONG_L $9, PT_R9(sp) 414 cfi_ld $9, PT_R9, \docfi
378#endif 415#endif
379 LONG_L $7, PT_R7(sp) 416 cfi_ld $7, PT_R7, \docfi
380 LONG_L $6, PT_R6(sp) 417 cfi_ld $6, PT_R6, \docfi
381 LONG_L $5, PT_R5(sp) 418 cfi_ld $5, PT_R5, \docfi
382 LONG_L $4, PT_R4(sp) 419 cfi_ld $4, PT_R4, \docfi
383 LONG_L $3, PT_R3(sp) 420 cfi_ld $3, PT_R3, \docfi
384 LONG_L $2, PT_R2(sp) 421 cfi_ld $2, PT_R2, \docfi
385 .set pop 422 .set pop
386 .endm 423 .endm
387 424
388 .macro RESTORE_SP_AND_RET 425 .macro RESTORE_SP_AND_RET docfi=0
389 LONG_L sp, PT_R29(sp) 426 RESTORE_SP \docfi
390#ifdef CONFIG_CPU_MIPSR6 427#ifdef CONFIG_CPU_MIPSR6
391 eretnc 428 eretnc
392#else 429#else
@@ -398,16 +435,12 @@
398 435
399#endif 436#endif
400 437
401 .macro RESTORE_SP 438 .macro RESTORE_ALL docfi=0
402 LONG_L sp, PT_R29(sp) 439 RESTORE_TEMP \docfi
403 .endm 440 RESTORE_STATIC \docfi
404 441 RESTORE_AT \docfi
405 .macro RESTORE_ALL 442 RESTORE_SOME \docfi
406 RESTORE_TEMP 443 RESTORE_SP \docfi
407 RESTORE_STATIC
408 RESTORE_AT
409 RESTORE_SOME
410 RESTORE_SP
411 .endm 444 .endm
412 445
413/* 446/*
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index ae810da4d499..37b9383eacd3 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -150,6 +150,7 @@ LEAF(__r4k_wait)
150 .align 5 150 .align 5
151BUILD_ROLLBACK_PROLOGUE handle_int 151BUILD_ROLLBACK_PROLOGUE handle_int
152NESTED(handle_int, PT_SIZE, sp) 152NESTED(handle_int, PT_SIZE, sp)
153 .cfi_signal_frame
153#ifdef CONFIG_TRACE_IRQFLAGS 154#ifdef CONFIG_TRACE_IRQFLAGS
154 /* 155 /*
155 * Check to see if the interrupted code has just disabled 156 * Check to see if the interrupted code has just disabled
@@ -181,7 +182,7 @@ NESTED(handle_int, PT_SIZE, sp)
1811: 1821:
182 .set pop 183 .set pop
183#endif 184#endif
184 SAVE_ALL 185 SAVE_ALL docfi=1
185 CLI 186 CLI
186 TRACE_IRQS_OFF 187 TRACE_IRQS_OFF
187 188
@@ -269,8 +270,8 @@ NESTED(except_vec_ejtag_debug, 0, sp)
269 */ 270 */
270BUILD_ROLLBACK_PROLOGUE except_vec_vi 271BUILD_ROLLBACK_PROLOGUE except_vec_vi
271NESTED(except_vec_vi, 0, sp) 272NESTED(except_vec_vi, 0, sp)
272 SAVE_SOME 273 SAVE_SOME docfi=1
273 SAVE_AT 274 SAVE_AT docfi=1
274 .set push 275 .set push
275 .set noreorder 276 .set noreorder
276 PTR_LA v1, except_vec_vi_handler 277 PTR_LA v1, except_vec_vi_handler
@@ -396,6 +397,7 @@ NESTED(except_vec_nmi, 0, sp)
396 __FINIT 397 __FINIT
397 398
398NESTED(nmi_handler, PT_SIZE, sp) 399NESTED(nmi_handler, PT_SIZE, sp)
400 .cfi_signal_frame
399 .set push 401 .set push
400 .set noat 402 .set noat
401 /* 403 /*
@@ -478,6 +480,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
478 .macro __BUILD_HANDLER exception handler clear verbose ext 480 .macro __BUILD_HANDLER exception handler clear verbose ext
479 .align 5 481 .align 5
480 NESTED(handle_\exception, PT_SIZE, sp) 482 NESTED(handle_\exception, PT_SIZE, sp)
483 .cfi_signal_frame
481 .set noat 484 .set noat
482 SAVE_ALL 485 SAVE_ALL
483 FEXPORT(handle_\exception\ext) 486 FEXPORT(handle_\exception\ext)
@@ -485,8 +488,8 @@ NESTED(nmi_handler, PT_SIZE, sp)
485 .set at 488 .set at
486 __BUILD_\verbose \exception 489 __BUILD_\verbose \exception
487 move a0, sp 490 move a0, sp
488 PTR_LA ra, ret_from_exception 491 jal do_\handler
489 j do_\handler 492 j ret_from_exception
490 END(handle_\exception) 493 END(handle_\exception)
491 .endm 494 .endm
492 495
diff --git a/arch/mips/mm/tlbex-fault.S b/arch/mips/mm/tlbex-fault.S
index 318855eb5f80..77db401fc620 100644
--- a/arch/mips/mm/tlbex-fault.S
+++ b/arch/mips/mm/tlbex-fault.S
@@ -12,14 +12,15 @@
12 12
13 .macro tlb_do_page_fault, write 13 .macro tlb_do_page_fault, write
14 NESTED(tlb_do_page_fault_\write, PT_SIZE, sp) 14 NESTED(tlb_do_page_fault_\write, PT_SIZE, sp)
15 SAVE_ALL 15 .cfi_signal_frame
16 SAVE_ALL docfi=1
16 MFC0 a2, CP0_BADVADDR 17 MFC0 a2, CP0_BADVADDR
17 KMODE 18 KMODE
18 move a0, sp 19 move a0, sp
19 REG_S a2, PT_BVADDR(sp) 20 REG_S a2, PT_BVADDR(sp)
20 li a1, \write 21 li a1, \write
21 PTR_LA ra, ret_from_exception 22 jal do_page_fault
22 j do_page_fault 23 j ret_from_exception
23 END(tlb_do_page_fault_\write) 24 END(tlb_do_page_fault_\write)
24 .endm 25 .endm
25 26
diff --git a/arch/mips/vdso/sigreturn.S b/arch/mips/vdso/sigreturn.S
index 715bf5993529..30c6219912ac 100644
--- a/arch/mips/vdso/sigreturn.S
+++ b/arch/mips/vdso/sigreturn.S
@@ -19,31 +19,21 @@
19 .cfi_sections .debug_frame 19 .cfi_sections .debug_frame
20 20
21LEAF(__vdso_rt_sigreturn) 21LEAF(__vdso_rt_sigreturn)
22 .cfi_startproc
23 .frame sp, 0, ra
24 .mask 0x00000000, 0
25 .fmask 0x00000000, 0
26 .cfi_signal_frame 22 .cfi_signal_frame
27 23
28 li v0, __NR_rt_sigreturn 24 li v0, __NR_rt_sigreturn
29 syscall 25 syscall
30 26
31 .cfi_endproc
32 END(__vdso_rt_sigreturn) 27 END(__vdso_rt_sigreturn)
33 28
34#if _MIPS_SIM == _MIPS_SIM_ABI32 29#if _MIPS_SIM == _MIPS_SIM_ABI32
35 30
36LEAF(__vdso_sigreturn) 31LEAF(__vdso_sigreturn)
37 .cfi_startproc
38 .frame sp, 0, ra
39 .mask 0x00000000, 0
40 .fmask 0x00000000, 0
41 .cfi_signal_frame 32 .cfi_signal_frame
42 33
43 li v0, __NR_sigreturn 34 li v0, __NR_sigreturn
44 syscall 35 syscall
45 36
46 .cfi_endproc
47 END(__vdso_sigreturn) 37 END(__vdso_sigreturn)
48 38
49#endif 39#endif