Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM Device-tree updates from Olof Johansson:
 "Device-tree continues to see lots of updates. The majority of patches
  here are smaller changes for new hardware on existing platforms, and
  there are a few larger changes worth pointing out.

  Major new platforms:

   - Gemini has been ported to DT, so a handful of "new" platforms moved
     over from board files

   - Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288
     SoM and RDK

   - A bunch of embedded platforms, several Linksys platforms, Synology
     DS116,

   - Motorola Droid4 (really old OMAP-based phone) support is added.

  Some refactorings, i.e. Allwinner H3/H5 support is commonalized.

  And lots of smaller changes, cleanups, etc. See shortlog for more
  description

  We're adding ability to cross-include DT files between arm and arm64,
  by creating appropriate links in the dt-include directory, and using
  arm/ and arm64/ as include prefixes. This will avoid other local hacks
  such as per-file links between the two arch trees (this broke for
  external mirroring of DT contents). Now they can just provide their
  own appropriate dt-include hierarcy per platform"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (349 commits)
  ARM: dts: exynos: Use - instead of @ for DT OPP entries
  arm: spear6xx: add DT description of the ADC on SPEAr600
  arm: spear6xx: remove unneeded pinctrl properties in spear600-evb
  arm: spear6xx: switch spear600-evb to the new flash partition DT binding
  arm: spear6xx: fix spaces in spear600-evb.dts
  arm: spear6xx: use node labels in spear600-evb.dts
  arm: spear6xx: add labels to various nodes in spear600.dtsi
  ARM: dts: vexpress: fix few unit address format warnings
  ARM: dts: at91: sama5d3_xplained: not all ADC channels are available
  ARM: dts: at91: sama5d3_xplained: fix ADC vref
  ARM: dts: at91: add envelope detector mux to the Axentia TSE-850
  ARM: dts: armada-38x: label USB and SATA nodes
  ARM: dts: imx6q-utilite-pro: add hpd gpio
  ARM: dts: imx6qp-sabresd: Set reg_arm regulator supply
  ARM: dts: imx6qdl-sabresd: Set LDO regulator supply
  ARM: dts: imx: add Gateworks Ventana GW5903 support
  ARM: dts: i.MX25: add AIPS control registers
  ARM: dts: imx7-colibri: add Carrier Board 3.3V/5V regulators
  ARM: dts: imx7-colibri: remove 1.8V fixed regulator
  ARM: dts: imx7-colibri: allow to disable Ethernet rail
  ...

378 files changed, 13121 insertions, 2800 deletions

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 29737b9b616e..799af90dd75b 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -217,7 +217,8 @@ memory, bridge implementations, processor and other functionality not controlled
 elsewhere.
 
 required properties:
-- compatible: Should be "atmel,<chip>-sfr", "syscon".
+- compatible: Should be "atmel,<chip>-sfr", "syscon" or
+        "atmel,<chip>-sfrbu", "syscon"
   <chip> can be "sama5d3", "sama5d4" or "sama5d2".
 - reg: Should contain registers location and length
 
diff --git a/Documentation/devicetree/bindings/arm/gemini.txt b/Documentation/devicetree/bindings/arm/gemini.txt
new file mode 100644
index 000000000000..0041eb031116
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/gemini.txt
@@ -0,0 +1,86 @@
+Cortina systems Gemini platforms
+
+The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
+produced by Storlink Semiconductor around 2005. The company was renamed
+later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
+It was derived from earlier products from Storm named SL3316 (Centroid) and
+SL3512 (Bulverde).
+
+Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
+produced and used for NAS and similar usecases. In 2014 Cortina Systems was
+in turn acquired by Inphi, who seem to have discontinued this product family.
+
+Many of the IP blocks used in the SoC comes from Faraday Technology.
+
+Required properties (in root node):
+        compatible = "cortina,gemini";
+
+Required nodes:
+
+- soc: the SoC should be represented by a simple bus encompassing all the
+  onchip devices, this is referred to as the soc bus node.
+
+- syscon: the soc bus node must have a system controller node pointing to the
+  global control registers, with the compatible string
+  "cortina,gemini-syscon", "syscon";
+
+- timer: the soc bus node must have a timer node pointing to the SoC timer
+  block, with the compatible string "cortina,gemini-timer"
+  See: clocksource/cortina,gemini-timer.txt
+
+- interrupt-controller: the sob bus node must have an interrupt controller
+  node pointing to the SoC interrupt controller block, with the compatible
+  string "cortina,gemini-interrupt-controller"
+  See interrupt-controller/cortina,gemini-interrupt-controller.txt
+
+Example:
+
+/ {
+        model = "Foo Gemini Machine";
+        compatible = "cortina,gemini";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                compatible = "simple-bus";
+                interrupt-parent = <&intcon>;
+
+                syscon: syscon@40000000 {
+                        compatible = "cortina,gemini-syscon", "syscon";
+                        reg = <0x40000000 0x1000>;
+                };
+
+                uart0: serial@42000000 {
+                        compatible = "ns16550a";
+                        reg = <0x42000000 0x100>;
+                        clock-frequency = <48000000>;
+                        interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                };
+
+                timer@43000000 {
+                        compatible = "cortina,gemini-timer";
+                        reg = <0x43000000 0x1000>;
+                        interrupt-parent = <&intcon>;
+                        interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
+                                     <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
+                                     <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
+                        syscon = <&syscon>;
+                };
+
+                intcon: interrupt-controller@48000000 {
+                        compatible = "cortina,gemini-interrupt-controller";
+                        reg = <0x48000000 0x1000>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/arm/i2se.txt b/Documentation/devicetree/bindings/arm/i2se.txt
new file mode 100644
index 000000000000..dbd54a3aa07d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/i2se.txt
@@ -0,0 +1,22 @@
+I2SE Device Tree Bindings
+-------------------------
+
+Duckbill Board
+Required root node properties:
+    - compatible = "i2se,duckbill", "fsl,imx28";
+
+Duckbill 2 Board
+Required root node properties:
+    - compatible = "i2se,duckbill-2", "fsl,imx28";
+
+Duckbill 2 485 Board
+Required root node properties:
+    - compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
+
+Duckbill 2 EnOcean Board
+Required root node properties:
+    - compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
+
+Duckbill 2 SPI Board
+Required root node properties:
+    - compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28";
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index cc4ace6397ab..6b8d50a0ee78 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -1,5 +1,8 @@
 Rockchip platforms device tree bindings
 ---------------------------------------
+- Asus Tinker board
+    Required root node properties:
+      - compatible = "asus,rk3288-tinker", "rockchip,rk3288";
 
 - Kylin RK3036 board:
     Required root node properties:
@@ -103,6 +106,10 @@ Rockchip platforms device tree bindings
     Required root node properties:
       - compatible = "mqmaker,miqi", "rockchip,rk3288";
 
+- Phytec phyCORE-RK3288: Rapid Development Kit
+    Required root node properties:
+     - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
+
 - Rockchip PX3 Evaluation board:
     Required root node properties:
       - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index c9502634316d..170fe0562c63 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -13,8 +13,12 @@ SoCs:
     compatible = "renesas,r8a73a4"
   - R-Mobile A1 (R8A77400)
     compatible = "renesas,r8a7740"
+  - RZ/G1H (R8A77420)
+    compatible = "renesas,r8a7742"
   - RZ/G1M (R8A77430)
     compatible = "renesas,r8a7743"
+  - RZ/G1N (R8A77440)
+    compatible = "renesas,r8a7744"
   - RZ/G1E (R8A77450)
     compatible = "renesas,r8a7745"
   - R-Car M1A (R8A77781)
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
index ccf0adddc820..a855c1bffc0f 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
@@ -1,7 +1,13 @@
 NVIDIA Tegra Flow Controller
 
 Required properties:
-- compatible: Should be "nvidia,tegra<chip>-flowctrl"
+- compatible: Should contain one of the following:
+  - "nvidia,tegra20-flowctrl": for Tegra20
+  - "nvidia,tegra30-flowctrl": for Tegra30
+  - "nvidia,tegra114-flowctrl": for Tegra114
+  - "nvidia,tegra124-flowctrl": for Tegra124
+  - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132
+  - "nvidia,tegra210-flowctrl": for Tegra210
 - reg: Should contain one register range (address and length)
 
 Example:
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index eb985a633d59..796c260c183d 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -31,6 +31,12 @@ The following is a list of provided IDs and clock names on Armada 39x:
  4 = dclk    (SDRAM Interface Clock)
  5 = refclk  (Reference Clock)
 
+The following is a list of provided IDs and clock names on 98dx3236:
+ 0 = tclk    (Internal Bus clock)
+ 1 = cpuclk  (CPU clock)
+ 2 = ddrclk   (DDR clock)
+ 3 = mpll    (MPLL Clock)
+
 The following is a list of provided IDs and clock names on Kirkwood and Dove:
  0 = tclk   (Internal Bus clock)
  1 = cpuclk (CPU0 clock)
@@ -49,6 +55,7 @@ Required properties:
         "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
         "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
         "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
+        "marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
         "marvell,dove-core-clock" - for Dove SoC core clocks
         "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
         "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index 5142efc8099d..de562da2ae77 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -119,6 +119,16 @@ ID	Clock	Peripheral
 29      sata1lnk
 30      sata1   SATA Host 1
 
+The following is a list of provided IDs for 98dx3236:
+ID      Clock   Peripheral
+-----------------------------------
+3       ge1     Gigabit Ethernet 1
+4       ge0     Gigabit Ethernet 0
+5       pex0    PCIe Cntrl 0
+17      sdio    SDHCI Host
+18      usb0    USB Host 0
+22      xor0    XOR DMA 0
+
 The following is a list of provided IDs for Dove:
 ID      Clock   Peripheral
 -----------------------------------
@@ -169,6 +179,7 @@ Required properties:
         "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
         "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
         "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
+        "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
         "marvell,dove-gating-clock" - for Dove SoC clock gating
         "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
 - reg : shall be the register address of the Clock Gating Control register
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index d085ef90d27c..f8e946471a58 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -202,23 +202,23 @@ Example2 :
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@50000000 {
+                opp-50000000 {
                         opp-hz = /bits/ 64 <50000000>;
                         opp-microvolt = <800000>;
                 };
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                         opp-microvolt = <800000>;
                 };
-                opp@134000000 {
+                opp-134000000 {
                         opp-hz = /bits/ 64 <134000000>;
                         opp-microvolt = <800000>;
                 };
-                opp@200000000 {
+                opp-200000000 {
                         opp-hz = /bits/ 64 <200000000>;
                         opp-microvolt = <825000>;
                 };
-                opp@400000000 {
+                opp-400000000 {
                         opp-hz = /bits/ 64 <400000000>;
                         opp-microvolt = <875000>;
                 };
@@ -292,23 +292,23 @@ Example2 :
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@50000000 {
+                opp-50000000 {
                         opp-hz = /bits/ 64 <50000000>;
                         opp-microvolt = <900000>;
                 };
-                opp@80000000 {
+                opp-80000000 {
                         opp-hz = /bits/ 64 <80000000>;
                         opp-microvolt = <900000>;
                 };
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                         opp-microvolt = <1000000>;
                 };
-                opp@134000000 {
+                opp-134000000 {
                         opp-hz = /bits/ 64 <134000000>;
                         opp-microvolt = <1000000>;
                 };
-                opp@200000000 {
+                opp-200000000 {
                         opp-hz = /bits/ 64 <200000000>;
                         opp-microvolt = <1000000>;
                 };
@@ -318,19 +318,19 @@ Example2 :
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@50000000 {
+                opp-50000000 {
                         opp-hz = /bits/ 64 <50000000>;
                 };
-                opp@80000000 {
+                opp-80000000 {
                         opp-hz = /bits/ 64 <80000000>;
                 };
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                 };
-                opp@200000000 {
+                opp-200000000 {
                         opp-hz = /bits/ 64 <200000000>;
                 };
-                opp@400000000 {
+                opp-400000000 {
                         opp-hz = /bits/ 64 <400000000>;
                 };
         };
@@ -339,19 +339,19 @@ Example2 :
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@50000000 {
+                opp-50000000 {
                         opp-hz = /bits/ 64 <50000000>;
                 };
-                opp@80000000 {
+                opp-80000000 {
                         opp-hz = /bits/ 64 <80000000>;
                 };
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                 };
-                opp@200000000 {
+                opp-200000000 {
                         opp-hz = /bits/ 64 <200000000>;
                 };
-                opp@300000000 {
+                opp-300000000 {
                         opp-hz = /bits/ 64 <300000000>;
                 };
         };
@@ -360,13 +360,13 @@ Example2 :
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@50000000 {
+                opp-50000000 {
                         opp-hz = /bits/ 64 <50000000>;
                 };
-                opp@80000000 {
+                opp-80000000 {
                         opp-hz = /bits/ 64 <80000000>;
                 };
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                 };
         };
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index b82c00449468..57a8d0610062 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -94,6 +94,7 @@ Required properties:
     * allwinner,sun6i-a31-display-backend
     * allwinner,sun8i-a33-display-backend
   - reg: base address and size of the memory-mapped region.
+  - interrupts: interrupt associated to this IP
   - clocks: phandles to the clocks feeding the frontend and backend
     * ahb: the backend interface clock
     * mod: the backend module clock
@@ -265,6 +266,7 @@ fe0: display-frontend@1e00000 {
 be0: display-backend@1e60000 {
         compatible = "allwinner,sun5i-a13-display-backend";
         reg = <0x01e60000 0x10000>;
+        interrupts = <47>;
         clocks = <&ahb_gates 44>, <&de_be_clk>,
                  <&dram_gates 26>;
         clock-names = "ahb", "mod",
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
index 476f5ea6c627..2b6243e730f6 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -35,6 +35,14 @@ Optional properties:
   - interrupt-names and interrupts:
     * pmu: Power Management Unit interrupt, if implemented in hardware
 
+  - memory-region:
+    Memory region to allocate from, as defined in
+    Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
+
+  - operating-points-v2:
+    Operating Points for the GPU, as defined in
+    Documentation/devicetree/bindings/opp/opp.txt
+
 Vendor-specific bindings
 ------------------------
 
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
index ff3db65e50de..b7e4c7444510 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
@@ -5,6 +5,7 @@ Required properties:
   Currently recognized values:
   - nvidia,gk20a
   - nvidia,gm20b
+  - nvidia,gp10b
 - reg: Physical base address and length of the controller's registers.
   Must contain two entries:
   - first entry for bar0
@@ -14,7 +15,8 @@ Required properties:
 - interrupt-names: Must include the following entries:
   - stall
   - nonstall
-- vdd-supply: regulator for supply voltage.
+- vdd-supply: regulator for supply voltage. Only required for GPUs not using
+  power domains.
 - clocks: Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
 - clock-names: Must include the following entries:
@@ -27,6 +29,8 @@ is also required:
   See ../reset/reset.txt for details.
 - reset-names: Must include the following entries:
   - gpu
+- power-domains: GPUs that make use of power domains can define this property
+  instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
 
 Optional properties:
 - iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
@@ -68,3 +72,22 @@ Example for GM20B:
                 iommus = <&mc TEGRA_SWGROUP_GPU>;
                 status = "disabled";
         };
+
+Example for GP10B:
+
+        gpu@17000000 {
+                compatible = "nvidia,gp10b";
+                reg = <0x0 0x17000000 0x0 0x1000000>,
+                      <0x0 0x18000000 0x0 0x1000000>;
+                interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+                              GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "stall", "nonstall";
+                clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
+                         <&bpmp TEGRA186_CLK_GPU>;
+                clock-names = "gpu", "pwr";
+                resets = <&bpmp TEGRA186_RESET_GPU>;
+                reset-names = "gpu";
+                power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
+                iommus = <&smmu TEGRA186_SID_GPU>;
+                status = "disabled";
+        };
diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
index 3e920ec5c4d3..9ce35af8507c 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
@@ -40,6 +40,7 @@ Required properties:
                  w25x80
                  w25x32
                  w25q32
+                 w25q64
                  w25q32dw
                  w25q80bl
                  w25q128
diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt b/Documentation/devicetree/bindings/net/marvell,prestera.txt
index 5fbab29718e8..c329608fa887 100644
--- a/Documentation/devicetree/bindings/net/marvell,prestera.txt
+++ b/Documentation/devicetree/bindings/net/marvell,prestera.txt
@@ -32,19 +32,16 @@ DFX Server bindings
 -------------------
 
 Required properties:
-- compatible: must be "marvell,dfx-server"
+- compatible: must be "marvell,dfx-server", "simple-bus"
+- ranges: describes the address mapping of a memory-mapped bus.
 - reg: address and length of the register set for the device.
 
 Example:
 
-dfx-registers {
-        compatible = "simple-bus";
+dfx-server {
+        compatible = "marvell,dfx-server", "simple-bus";
         #address-cells = <1>;
         #size-cells = <1>;
         ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
-
-        dfx: dfx@0 {
-                compatible = "marvell,dfx-server";
-                reg = <0 0x100000>;
-        };
+        reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
 };
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 6c7c2bce6d0c..00bea038639e 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -14,6 +14,10 @@ Required properties:
   - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
   - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
   - snps,dwc2: A generic DWC2 USB controller with default parameters.
+  - "st,stm32f4x9-fsotg": The DWC2 USB FS/HS controller instance in STM32F4x9 SoCs
+  configured in FS mode;
+  - "st,stm32f4x9-hsotg": The DWC2 USB HS controller instance in STM32F4x9 SoCs
+  configured in HS mode;
 - reg : Should contain 1 register range (address and length)
 - interrupts : Should contain 1 interrupt
 - clocks: clock provider specifier
diff --git a/Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt b/Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt
new file mode 100644
index 000000000000..bc4b865d178b
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/cortina,gemini-watchdog.txt
@@ -0,0 +1,17 @@
+Cortina Systems Gemini SoC Watchdog
+
+Required properties:
+- compatible : must be "cortina,gemini-watchdog"
+- reg : shall contain base register location and length
+- interrupts : shall contain the interrupt for the watchdog
+
+Optional properties:
+- timeout-sec : the default watchdog timeout in seconds.
+
+Example:
+
+watchdog@41000000 {
+        compatible = "cortina,gemini-watchdog";
+        reg = <0x41000000 0x1000>;
+        interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 011808490fed..9c5e1d944d1c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
         bcm4708-asus-rt-ac56u.dtb \
         bcm4708-asus-rt-ac68u.dtb \
         bcm4708-buffalo-wzr-1750dhp.dtb \
+        bcm4708-linksys-ea6300-v1.dtb \
         bcm4708-luxul-xap-1510.dtb \
         bcm4708-luxul-xwc-1000.dtb \
         bcm4708-netgear-r6250.dtb \
@@ -87,17 +88,21 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
         bcm47081-buffalo-wzr-900dhp.dtb \
         bcm47081-luxul-xap-1410.dtb \
         bcm47081-luxul-xwr-1200.dtb \
+        bcm47081-tplink-archer-c5-v2.dtb \
         bcm4709-asus-rt-ac87u.dtb \
         bcm4709-buffalo-wxr-1900dhp.dtb \
+        bcm4709-linksys-ea9200.dtb \
         bcm4709-netgear-r7000.dtb \
         bcm4709-netgear-r8000.dtb \
         bcm4709-tplink-archer-c9-v1.dtb \
         bcm47094-dlink-dir-885l.dtb \
+        bcm47094-linksys-panamera.dtb \
         bcm47094-luxul-xwr-3100.dtb \
         bcm47094-netgear-r8500.dtb \
         bcm94708.dtb \
         bcm94709.dtb \
         bcm953012er.dtb \
+        bcm953012hr.dtb \
         bcm953012k.dtb
 dtb-$(CONFIG_ARCH_BCM_53573) += \
         bcm47189-tenda-ac9.dtb
@@ -173,6 +178,12 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
         exynos5440-sd5v1.dtb \
         exynos5440-ssdk5440.dtb \
         exynos5800-peach-pi.dtb
+dtb-$(CONFIG_ARCH_GEMINI) += \
+        gemini-nas4220b.dtb \
+        gemini-rut1xx.dtb \
+        gemini-sq201.dtb \
+        gemini-wbd111.dtb \
+        gemini-wbd222.dtb
 dtb-$(CONFIG_ARCH_HI3xxx) += \
         hi3620-hi4511.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += \
@@ -352,6 +363,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6dl-gw551x.dtb \
         imx6dl-gw552x.dtb \
         imx6dl-gw553x.dtb \
+        imx6dl-gw5903.dtb \
+        imx6dl-gw5904.dtb \
         imx6dl-hummingboard.dtb \
         imx6dl-icore.dtb \
         imx6dl-icore-rqs.dtb \
@@ -395,9 +408,13 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6q-gw551x.dtb \
         imx6q-gw552x.dtb \
         imx6q-gw553x.dtb \
+        imx6q-gw5903.dtb \
+        imx6q-gw5904.dtb \
         imx6q-h100.dtb \
         imx6q-hummingboard.dtb \
         imx6q-icore.dtb \
+        imx6q-icore-ofcap10.dtb \
+        imx6q-icore-ofcap12.dtb \
         imx6q-icore-rqs.dtb \
         imx6q-marsboard.dtb \
         imx6q-mccmon6.dtb \
@@ -425,9 +442,12 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6q-utilite-pro.dtb \
         imx6q-wandboard.dtb \
         imx6q-wandboard-revb1.dtb \
+        imx6q-zii-rdu2.dtb \
         imx6qp-nitrogen6_max.dtb \
+        imx6qp-nitrogen6_som2.dtb \
         imx6qp-sabreauto.dtb \
-        imx6qp-sabresd.dtb
+        imx6qp-sabresd.dtb \
+        imx6qp-zii-rdu2.dtb
 dtb-$(CONFIG_SOC_IMX6SL) += \
         imx6sl-evk.dtb \
         imx6sl-warp.dtb
@@ -458,6 +478,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
         imx7d-nitrogen7.dtb \
         imx7d-sbc-imx7.dtb \
         imx7d-sdb.dtb \
+        imx7d-sdb-sht11.dtb \
         imx7s-colibri-eval-v3.dtb \
         imx7s-warp.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
@@ -488,6 +509,10 @@ dtb-$(CONFIG_ARCH_MXS) += \
         imx28-cfa10056.dtb \
         imx28-cfa10057.dtb \
         imx28-cfa10058.dtb \
+        imx28-duckbill-2-485.dtb \
+        imx28-duckbill-2.dtb \
+        imx28-duckbill-2-enocean.dtb \
+        imx28-duckbill-2-spi.dtb \
         imx28-duckbill.dtb \
         imx28-eukrea-mbmx283lc.dtb \
         imx28-eukrea-mbmx287lc.dtb \
@@ -673,6 +698,25 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
         arm-realview-eb-a9mp-bbrevd.dtb \
         arm-realview-pba8.dtb \
         arm-realview-pbx-a9.dtb
+dtb-$(CONFIG_ARCH_RENESAS) += \
+        emev2-kzm9d.dtb \
+        r7s72100-genmai.dtb \
+        r7s72100-rskrza1.dtb \
+        r8a73a4-ape6evm.dtb \
+        r8a7740-armadillo800eva.dtb \
+        r8a7743-sk-rzg1m.dtb \
+        r8a7745-sk-rzg1e.dtb \
+        r8a7778-bockw.dtb \
+        r8a7779-marzen.dtb \
+        r8a7790-lager.dtb \
+        r8a7791-koelsch.dtb \
+        r8a7791-porter.dtb \
+        r8a7792-blanche.dtb \
+        r8a7792-wheat.dtb \
+        r8a7793-gose.dtb \
+        r8a7794-alt.dtb \
+        r8a7794-silk.dtb \
+        sh73a0-kzm9g.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
         rk1108-evb.dtb \
         rk3036-evb.dtb \
@@ -692,9 +736,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
         rk3288-firefly.dtb \
         rk3288-firefly-reload.dtb \
         rk3288-miqi.dtb \
+        rk3288-phycore-rdk.dtb \
         rk3288-popmetal.dtb \
         rk3288-r89.dtb \
         rk3288-rock2-square.dtb \
+        rk3288-tinker.dtb \
         rk3288-veyron-brain.dtb \
         rk3288-veyron-jaq.dtb \
         rk3288-veyron-jerry.dtb \
@@ -713,25 +759,6 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
         s5pv210-smdkc110.dtb \
         s5pv210-smdkv210.dtb \
         s5pv210-torbreck.dtb
-dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
-        emev2-kzm9d.dtb \
-        r7s72100-genmai.dtb \
-        r7s72100-rskrza1.dtb \
-        r8a73a4-ape6evm.dtb \
-        r8a7740-armadillo800eva.dtb \
-        r8a7743-sk-rzg1m.dtb \
-        r8a7745-sk-rzg1e.dtb \
-        r8a7778-bockw.dtb \
-        r8a7779-marzen.dtb \
-        r8a7790-lager.dtb \
-        r8a7791-koelsch.dtb \
-        r8a7791-porter.dtb \
-        r8a7792-blanche.dtb \
-        r8a7792-wheat.dtb \
-        r8a7793-gose.dtb \
-        r8a7794-alt.dtb \
-        r8a7794-silk.dtb \
-        sh73a0-kzm9g.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += \
         socfpga_arria5_socdk.dtb \
         socfpga_arria10_socdk_nand.dtb \
@@ -764,7 +791,8 @@ dtb-$(CONFIG_ARCH_STM32)+= \
         stm32f429-disco.dtb \
         stm32f469-disco.dtb \
         stm32429i-eval.dtb \
-        stm32746g-eval.dtb
+        stm32746g-eval.dtb \
+        stm32h743i-eval.dtb
 dtb-$(CONFIG_MACH_SUN4I) += \
         sun4i-a10-a1000.dtb \
         sun4i-a10-ba10-tvbox.dtb \
@@ -868,6 +896,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
         sun8i-h3-beelink-x2.dtb \
         sun8i-h3-nanopi-m1.dtb  \
         sun8i-h3-nanopi-neo.dtb \
+        sun8i-h3-nanopi-neo-air.dtb \
         sun8i-h3-orangepi-2.dtb \
         sun8i-h3-orangepi-lite.dtb \
         sun8i-h3-orangepi-one.dtb \
@@ -970,6 +999,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
         armada-385-db-ap.dtb \
         armada-385-linksys-caiman.dtb \
         armada-385-linksys-cobra.dtb \
+        armada-385-linksys-shelby.dtb \
+        armada-385-synology-ds116.dtb \
         armada-385-turris-omnia.dtb \
         armada-388-clearfog.dtb \
         armada-388-clearfog-base.dtb \
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
index d0eefc3b886c..731df7a8c4e6 100644
--- a/arch/arm/boot/dts/alpine.dtsi
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -41,28 +41,28 @@
                         compatible = "arm,cortex-a15";
                         device_type = "cpu";
                         reg = <0>;
-                        clock-frequency = <0>; /* Filled by loader */
+                        clock-frequency = <1700000000>;
                 };
 
                 cpu@1 {
                         compatible = "arm,cortex-a15";
                         device_type = "cpu";
                         reg = <1>;
-                        clock-frequency = <0>; /* Filled by loader */
+                        clock-frequency = <1700000000>;
                 };
 
                 cpu@2 {
                         compatible = "arm,cortex-a15";
                         device_type = "cpu";
                         reg = <2>;
-                        clock-frequency = <0>; /* Filled by loader */
+                        clock-frequency = <1700000000>;
                 };
 
                 cpu@3 {
                         compatible = "arm,cortex-a15";
                         device_type = "cpu";
                         reg = <3>;
-                        clock-frequency = <0>; /* Filled by loader */
+                        clock-frequency = <1700000000>;
                 };
         };
 
@@ -81,7 +81,7 @@
                                 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
                                 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
                                 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-                        clock-frequency = <0>; /* Filled by loader */
+                        clock-frequency = <50000000>;
                 };
 
                 /* Interrupt Controller */
@@ -120,26 +120,26 @@
                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
-                uart0:uart@fd883000 {
+                uart0: uart@fd883000 {
                         compatible = "ns16550a";
                         reg = <0x0 0xfd883000 0x0 0x1000>;
-                        clock-frequency = <0>; /* Filled by loader */
+                        clock-frequency = <375000000>;
                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
                 };
 
-                uart1:uart@0xfd884000 {
+                uart1: uart@fd884000 {
                         compatible = "ns16550a";
                         reg = <0x0 0xfd884000 0x0 0x1000>;
-                        clock-frequency = <0>; /* Filled by loader */
+                        clock-frequency = <375000000>;
                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
                 };
 
                 /* Internal PCIe Controller */
-                pcie-internal@0xfbc00000 {
+                pcie@fbc00000 {
                         compatible = "pci-host-ecam-generic";
                         device_type = "pci";
                         #size-cells = <2>;
diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
index 501c7527121b..75de1e723303 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
@@ -14,6 +14,7 @@
 /dts-v1/;
 
 #include "am335x-baltos.dtsi"
+#include "am335x-baltos-leds.dtsi"
 
 / {
         model = "OnRISC Baltos iR 2110";
diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
index 19f53b8569e1..46df1b22022c 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
@@ -14,6 +14,7 @@
 /dts-v1/;
 
 #include "am335x-baltos.dtsi"
+#include "am335x-baltos-leds.dtsi"
 
 / {
         model = "OnRISC Baltos iR 3220";
diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
index 2b9d7f4db23f..5d56355ba040 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
@@ -14,6 +14,7 @@
 /dts-v1/;
 
 #include "am335x-baltos.dtsi"
+#include "am335x-baltos-leds.dtsi"
 
 / {
         model = "OnRISC Baltos iR 5221";
diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/am335x-baltos-leds.dtsi
new file mode 100644
index 000000000000..3ab1767d5c13
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-baltos-leds.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * VScom OnRISC
+ * http://www.vscom.de
+ */
+
+/*#include "am33xx.dtsi"*/
+
+/ {
+        leds {
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_leds>;
+
+                compatible = "gpio-leds";
+
+                power {
+                        label = "onrisc:red:power";
+                        linux,default-trigger = "default-on";
+                        gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+                        default-state = "on";
+                };
+                wlan {
+                        label = "onrisc:blue:wlan";
+                        gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+                app {
+                        label = "onrisc:green:app";
+                        gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+        };
+};
+
+&am33xx_pinmux {
+        user_leds: pinmux_user_leds {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* mii1_col.gpio3_0 PWR LED */
+                        AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* mii1_txd3.gpio0_16 WLAN LED */
+                        AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* mii1_txd2.gpio0_17 APP LED */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 77273df1a028..935ed17d22e4 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -15,3 +15,14 @@
         model = "TI AM335x BeagleBone Black";
         compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
 };
+
+&cpu0_opp_table {
+        /*
+         * All PG 2.0 silicon may not support 1GHz but some of the early
+         * BeagleBone Blacks have PG 2.0 silicon which is guaranteed
+         * to support 1GHz OPP so enable it for PG 2.0 on this board.
+         */
+        oppnitro@1000000000 {
+                opp-supported-hw = <0x06 0x0100>;
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index a2ad076822db..f2005ecca74f 100644
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -201,6 +201,69 @@
                         AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
                 >;
         };
+
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 1, RMII mode */
+                        AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_crs.rmii1_crs_dv */
+                        AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0))     /* rmii1_refclk.rmii1_refclk */
+                        AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_rxd0.rmii1_rxd0 */
+                        AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_rxd1.rmii1_rxd1 */
+                        AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_rxerr.rmii1_rxerr */
+                        AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))  /* mii1_txd0.rmii1_txd0 */
+                        AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))  /* mii1_txd1.rmii1_txd1 */
+                        AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))  /* mii1_txen.rmii1_txen */
+                        /* Slave 2, RMII mode */
+                        AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_wait0.rmii2_crs_dv */
+                        AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1))     /* mii1_col.rmii2_refclk */
+                        AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_a11.rmii2_rxd0 */
+                        AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_a10.rmii2_rxd1 */
+                        AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3))     /* gpmc_wpn.rmii2_rxerr */
+                        AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))  /* gpmc_a5.rmii2_txd0 */
+                        AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))  /* gpmc_a4.rmii2_txd1 */
+                        AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))  /* gpmc_a0.rmii2_txen */
+                >;
+        };
+
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 1 reset value */
+                        AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+
+                        /* Slave 2 reset value */
+                        AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                >;
+        };
+
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        /* MDIO */
+                        AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0))     /* mdio_data.mdio_data */
+                        AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0))                    /* mdio_clk.mdio_clk */
+                >;
+        };
+
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        /* MDIO reset value */
+                        AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                        AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+                >;
+        };
 };
 
 &i2c0 {
@@ -245,6 +308,39 @@
                 spi-max-frequency = <1000000>;
                 spi-cpol;
         };
+
+        spi_nor: flash@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "winbond,w25q64", "jedec,spi-nor";
+                spi-max-frequency = <80000000>;
+                m25p,fast-read;
+                reg = <0>;
+
+                partition@0 {
+                        label = "u-boot-spl";
+                        reg = <0x0 0x80000>;
+                        read-only;
+                };
+
+                partition@1 {
+                        label = "u-boot";
+                        reg = <0x80000 0x100000>;
+                        read-only;
+                };
+
+                partition@2 {
+                        label = "u-boot-env";
+                        reg = <0x180000 0x20000>;
+                        read-only;
+                };
+
+                partition@3 {
+                        label = "misc";
+                        reg = <0x1A0000 0x660000>;
+                };
+        };
+
 };
 
 &tscadc {
@@ -350,3 +446,61 @@
         pinctrl-0 = <&uart3_pins_default>;
         status = "okay";
 };
+
+&gpio3 {
+        p4 {
+                gpio-hog;
+                gpios = <4 GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "PR1_MII_CTRL";
+        };
+
+        p10 {
+                gpio-hog;
+                gpios = <10 GPIO_ACTIVE_HIGH>;
+                /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
+                output-high;
+                line-name = "MUX_MII_CTL1";
+        };
+};
+
+&cpsw_emac0 {
+        phy-handle = <&ethphy0>;
+        phy-mode = "rmii";
+        dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+        phy-handle = <&ethphy1>;
+        phy-mode = "rmii";
+        dual_emac_res_vlan = <2>;
+};
+
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+        status = "okay";
+        dual_emac;
+};
+
+&phy_sel {
+        rmii-clock-ext;
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+        status = "okay";
+        reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+        reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
+
+        ethphy0: ethernet-phy@1 {
+                reg = <1>;
+        };
+
+        ethphy1: ethernet-phy@3 {
+                reg = <3>;
+        };
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 9e96d60976b7..9e242943dcec 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -46,19 +46,7 @@
                         device_type = "cpu";
                         reg = <0>;
 
-                        /*
-                         * To consider voltage drop between PMIC and SoC,
-                         * tolerance value is reduced to 2% from 4% and
-                         * voltage value is increased as a precaution.
-                         */
-                        operating-points = <
-                                /* kHz    uV */
-                                720000  1285000
-                                600000  1225000
-                                500000  1125000
-                                275000  1125000
-                        >;
-                        voltage-tolerance = <2>; /* 2 percentage */
+                        operating-points-v2 = <&cpu0_opp_table>;
 
                         clocks = <&dpll_mpu_ck>;
                         clock-names = "cpu";
@@ -67,6 +55,79 @@
                 };
         };
 
+        cpu0_opp_table: opp-table {
+                compatible = "operating-points-v2-ti-cpu";
+                syscon = <&scm_conf>;
+
+                /*
+                 * The three following nodes are marked with opp-suspend
+                 * because the can not be enabled simultaneously on a
+                 * single SoC.
+                 */
+                opp50@300000000 {
+                        opp-hz = /bits/ 64 <300000000>;
+                        opp-microvolt = <950000 931000 969000>;
+                        opp-supported-hw = <0x06 0x0010>;
+                        opp-suspend;
+                };
+
+                opp100@275000000 {
+                        opp-hz = /bits/ 64 <275000000>;
+                        opp-microvolt = <1100000 1078000 1122000>;
+                        opp-supported-hw = <0x01 0x00FF>;
+                        opp-suspend;
+                };
+
+                opp100@300000000 {
+                        opp-hz = /bits/ 64 <300000000>;
+                        opp-microvolt = <1100000 1078000 1122000>;
+                        opp-supported-hw = <0x06 0x0020>;
+                        opp-suspend;
+                };
+
+                opp100@500000000 {
+                        opp-hz = /bits/ 64 <500000000>;
+                        opp-microvolt = <1100000 1078000 1122000>;
+                        opp-supported-hw = <0x01 0xFFFF>;
+                };
+
+                opp100@600000000 {
+                        opp-hz = /bits/ 64 <600000000>;
+                        opp-microvolt = <1100000 1078000 1122000>;
+                        opp-supported-hw = <0x06 0x0040>;
+                };
+
+                opp120@600000000 {
+                        opp-hz = /bits/ 64 <600000000>;
+                        opp-microvolt = <1200000 1176000 1224000>;
+                        opp-supported-hw = <0x01 0xFFFF>;
+                };
+
+                opp120@720000000 {
+                        opp-hz = /bits/ 64 <720000000>;
+                        opp-microvolt = <1200000 1176000 1224000>;
+                        opp-supported-hw = <0x06 0x0080>;
+                };
+
+                oppturbo@720000000 {
+                        opp-hz = /bits/ 64 <720000000>;
+                        opp-microvolt = <1260000 1234800 1285200>;
+                        opp-supported-hw = <0x01 0xFFFF>;
+                };
+
+                oppturbo@800000000 {
+                        opp-hz = /bits/ 64 <800000000>;
+                        opp-microvolt = <1260000 1234800 1285200>;
+                        opp-supported-hw = <0x06 0x0100>;
+                };
+
+                oppnitro@1000000000 {
+                        opp-hz = /bits/ 64 <1000000000>;
+                        opp-microvolt = <1325000 1298500 1351500>;
+                        opp-supported-hw = <0x04 0x0200>;
+                };
+        };
+
         pmu {
                 compatible = "arm,cortex-a8-pmu";
                 interrupts = <3>;
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 9fe545dbfa89..00da3f2c4072 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -13,6 +13,7 @@
 / {
         aliases {
                 serial3 = &uart4;
+                can = &hecc;
         };
 
         ocp@68000000 {
@@ -72,6 +73,17 @@
                         pinctrl-single,register-width = <16>;
                         pinctrl-single,function-mask = <0xff1f>;
                 };
+
+                hecc: can@5c050000 {
+                        compatible = "ti,am3517-hecc";
+                        status = "disabled";
+                        reg = <0x5c050000 0x80>,
+                              <0x5c053000 0x180>,
+                              <0x5c052000 0x200>;
+                        reg-names = "hecc", "hecc-ram", "mbx";
+                        interrupts = <24>;
+                        clocks = <&hecc_ck>;
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 97fcaf415de1..176e09e9a45e 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -50,15 +50,14 @@
                         clock-names = "cpu";
 
                         operating-points-v2 = <&cpu0_opp_table>;
-                        ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>;
-                        ti,syscon-rev = <&scm_conf 0x600>;
 
                         clock-latency = <300000>; /* From omap-cpufreq driver */
                 };
         };
 
-        cpu0_opp_table: opp_table0 {
-                compatible = "operating-points-v2";
+        cpu0_opp_table: opp-table {
+                compatible = "operating-points-v2-ti-cpu";
+                syscon = <&scm_conf>;
 
                 opp50@300000000 {
                         opp-hz = /bits/ 64 <300000000>;
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index a4f31739057f..397e98b7e246 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -501,6 +501,21 @@
                         AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
                 >;
         };
+
+        uart0_pins_default: uart0_pins_default {
+                pinctrl-single,pins = <
+                        AM4372_IOPAD(0x968, PIN_INPUT | MUX_MODE0)              /* uart0_ctsn.uart0_ctsn */
+                        AM4372_IOPAD(0x96C, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_rtsn.uart0_rtsn */
+                        AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
+                        AM4372_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                >;
+        };
+};
+
+&uart0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins_default>;
 };
 
 &i2c0 {
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index e5ac1d81d15c..c536b2f5389f 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -101,6 +101,22 @@
         };
 };
 
+&dra7_pmx_core {
+        dcan1_pins_default: dcan1_pins_default {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0)        /* dcan1_tx */
+                        DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0)         /* dcan1_rx */
+                >;
+        };
+
+        dcan1_pins_sleep: dcan1_pins_sleep {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
+                        DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */
+                >;
+        };
+};
+
 &i2c1 {
         status = "okay";
         clock-frequency = <400000>;
@@ -391,6 +407,14 @@
         max-frequency = <96000000>;
 };
 
+&dcan1 {
+        status = "okay";
+        pinctrl-names = "default", "sleep", "active";
+        pinctrl-0 = <&dcan1_pins_sleep>;
+        pinctrl-1 = <&dcan1_pins_sleep>;
+        pinctrl-2 = <&dcan1_pins_default>;
+};
+
 &qspi {
         status = "okay";
 
diff --git a/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
new file mode 100644
index 000000000000..c7a8ddd7f9a5
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
@@ -0,0 +1,114 @@
+/*
+ * Device Tree file for the Linksys WRT1900ACS (Shelby)
+ *
+ * Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ *     License version 2.  This program is licensed "as is" without
+ *     any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-385-linksys.dtsi"
+
+/ {
+        model = "Linksys WRT1900ACS";
+        compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
+                     "marvell,armada380";
+
+        soc {
+                internal-regs{
+                        i2c@11000 {
+
+                                pca9635@68 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                        wan_amber@0 {
+                                                label = "shelby:amber:wan";
+                                                reg = <0x0>;
+                                        };
+
+                                        wan_white@1 {
+                                                label = "shelby:white:wan";
+                                                reg = <0x1>;
+                                        };
+
+                                        wlan_2g@2 {
+                                                label = "shelby:white:wlan_2g";
+                                                reg = <0x2>;
+                                        };
+
+                                        wlan_5g@3 {
+                                                label = "shelby:white:wlan_5g";
+                                                reg = <0x3>;
+                                        };
+
+                                        usb2@5 {
+                                                label = "shelby:white:usb2";
+                                                reg = <0x5>;
+                                        };
+
+                                        usb3_1@6 {
+                                                label = "shelby:white:usb3_1";
+                                                reg = <0x6>;
+                                        };
+
+                                        usb3_2@7 {
+                                                label = "shelby:white:usb3_2";
+                                                reg = <0x7>;
+                                        };
+
+                                        wps_white@8 {
+                                                label = "shelby:white:wps";
+                                                reg = <0x8>;
+                                        };
+
+                                        wps_amber@9 {
+                                                label = "shelby:amber:wps";
+                                                reg = <0x9>;
+                                        };
+                                };
+                        };
+                };
+        };
+
+        gpio-leds {
+                power {
+                        label = "shelby:white:power";
+                };
+
+                sata {
+                        label = "shelby:white:sata";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi
index df47bf1ea5eb..2306c45685b1 100644
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -59,7 +59,8 @@
                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
-                          MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+                          MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+                          MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
 
                 internal-regs {
                         i2c@11000 {
@@ -88,6 +89,9 @@
                         ethernet@70000 {
                                 status = "okay";
                                 phy-mode = "rgmii-id";
+                                buffer-manager = <&bm>;
+                                bm,pool-long = <2>;
+                                bm,pool-short = <3>;
                                 fixed-link {
                                         speed = <1000>;
                                         full-duplex;
@@ -97,6 +101,9 @@
                         ethernet@34000 {
                                 status = "okay";
                                 phy-mode = "sgmii";
+                                buffer-manager = <&bm>;
+                                bm,pool-long = <0>;
+                                bm,pool-short = <1>;
                                 fixed-link {
                                         speed = <1000>;
                                         full-duplex;
@@ -159,6 +166,10 @@
                                 status = "okay";
                         };
 
+                        bm@c8000 {
+                                status = "okay";
+                        };
+
                         /* USB part of the eSATA/USB 2.0 port */
                         usb@58000 {
                                 status = "okay";
@@ -241,6 +252,10 @@
                         };
                 };
 
+                bm-bppi {
+                        status = "okay";
+                };
+
                 pcie-controller {
                         status = "okay";
 
@@ -305,6 +320,7 @@
                 sata {
                         gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
                         default-state = "off";
+                        linux,default-trigger = "disk-activity";
                 };
         };
 
diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts
new file mode 100644
index 000000000000..31510eb56f10
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-synology-ds116.dts
@@ -0,0 +1,321 @@
+/*
+ * Device Tree file for Synology DS116 NAS
+ *
+ * Copyright (C) 2017 Willy Tarreau <w@1wt.eu>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ *     License version 2.  This program is licensed "as is" without
+ *     any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "Synology DS116";
+        compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380";
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>; /* 1 GB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+                          MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+                          MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+                          MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+
+                internal-regs {
+                        i2c@11000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins>;
+                                status = "okay";
+                                clock-frequency = <100000>;
+
+                                eeprom@57 {
+                                        compatible = "atmel,24c64";
+                                        reg = <0x57>;
+                                };
+                        };
+
+                        serial@12000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&uart0_pins>;
+                                status = "okay";
+                        };
+
+                        serial@12100 {
+                                /* A PIC16F1829 is connected to uart1 at 9600 bps,
+                                 * and takes single-character orders :
+                                 *   "1" : power off // already handled by the poweroff node
+                                 *   "2" : short beep
+                                 *   "3" : long beep
+                                 *   "4" : turn the power LED ON
+                                 *   "5" : flash the power LED
+                                 *   "6" : turn the power LED OFF
+                                 *   "7" : turn the status LED OFF
+                                 *   "8" : turn the status LED ON
+                                 *   "9" : flash the status LED
+                                 *   "A" : flash the motherboard LED (D8)
+                                 *   "B" : turn the motherboard LED OFF
+                                 *   "C" : hard reset
+                                 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&uart1_pins>;
+                                status = "okay";
+                        };
+
+                        poweroff@12100 {
+                                compatible = "synology,power-off";
+                                reg = <0x12100 0x100>;
+                                clocks = <&coreclk 0>;
+                        };
+
+                        ethernet@70000 {
+                                pinctrl-names = "default";
+                                phy = <&phy0>;
+                                phy-mode = "sgmii";
+                                buffer-manager = <&bm>;
+                                bm,pool-long = <0>;
+                                status = "okay";
+                        };
+
+
+                        mdio@72004 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mdio_pins>;
+
+                                phy0: ethernet-phy@1 {
+                                        reg = <1>;
+                                };
+                        };
+
+                        sata@a8000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&sata0_pins>;
+                                status = "okay";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                sata0: sata-port@0 {
+                                        reg = <0>;
+                                        target-supply = <&reg_5v_sata0>;
+                                };
+                        };
+
+                        bm@c8000 {
+                                status = "okay";
+                        };
+
+                        usb3@f0000 {
+                                usb-phy = <&usb3_0_phy>;
+                                status = "okay";
+                        };
+
+                        usb3@f8000 {
+                                usb-phy = <&usb3_1_phy>;
+                                status = "okay";
+                        };
+                };
+
+                bm-bppi {
+                        status = "okay";
+                };
+
+                gpio-fan {
+                        compatible = "gpio-fan";
+                        gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>,
+                                <&gpio1 17 GPIO_ACTIVE_HIGH>,
+                                <&gpio1 16 GPIO_ACTIVE_HIGH>;
+                        gpio-fan,speed-map = <   0 0
+                                              1500 1
+                                              2500 2
+                                              3000 3
+                                              3400 4
+                                              3700 5
+                                              3900 6
+                                              4000 7>;
+                        cooling-cells = <2>;
+                };
+
+                gpio-leds {
+                        compatible = "gpio-leds";
+
+                        /* The green part is on gpio0.20 which is also used by
+                         * sata0, and accesses to SATA disk 0 make it blink so it
+                         * doesn't need to be declared here.
+                         */
+                        orange {
+                                gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+                                label = "ds116:orange:disk";
+                                default-state = "off";
+                        };
+                };
+        };
+
+        usb3_0_phy: usb3_0_phy {
+                compatible = "usb-nop-xceiv";
+                vcc-supply = <&reg_usb3_0_vbus>;
+        };
+
+        usb3_1_phy: usb3_1_phy {
+                compatible = "usb-nop-xceiv";
+                vcc-supply = <&reg_usb3_1_vbus>;
+        };
+
+        reg_usb3_0_vbus: usb3-vbus0 {
+                compatible = "regulator-fixed";
+                regulator-name = "usb3-vbus0";
+                pinctrl-names = "default";
+                pinctrl-0 = <&xhci0_vbus_pins>;
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+        };
+
+        reg_usb3_1_vbus: usb3-vbus1 {
+                compatible = "regulator-fixed";
+                regulator-name = "usb3-vbus1";
+                pinctrl-names = "default";
+                pinctrl-0 = <&xhci1_vbus_pins>;
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+        };
+
+        reg_sata0: pwr-sata0 {
+                compatible = "regulator-fixed";
+                regulator-name = "pwr_en_sata0";
+                regulator-min-microvolt = <12000000>;
+                regulator-max-microvolt = <12000000>;
+                enable-active-high;
+                regulator-boot-on;
+                gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+        };
+
+        reg_5v_sata0: v5-sata0 {
+                compatible = "regulator-fixed";
+                regulator-name = "v5.0-sata0";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                vin-supply = <&reg_sata0>;
+        };
+
+        reg_12v_sata0: v12-sata0 {
+                compatible = "regulator-fixed";
+                regulator-name = "v12.0-sata0";
+                regulator-min-microvolt = <12000000>;
+                regulator-max-microvolt = <12000000>;
+                vin-supply = <&reg_sata0>;
+        };
+};
+
+&spi0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi0_pins>;
+        status = "okay";
+
+        spi-flash@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "macronix,mx25l6405d", "jedec,spi-nor";
+                reg = <0>; /* Chip select 0 */
+                spi-max-frequency = <50000000>;
+                m25p,fast-read;
+
+                /* Note: there is a redboot partition table despite u-boot
+                 * being used. The names presented here are the same as those
+                 * found in the FIS directory. There is also a small device
+                 * tree in the last 64kB of the RedBoot partition which is not
+                 * enumerated. The MAC address and the serial number are listed
+                 * in the "vendor" partition.
+                 */
+                partition@00000000 {
+                        label = "RedBoot";
+                        reg = <0x00000000 0x000f0000>;
+                        read-only;
+                };
+
+                partition@000c0000 {
+                        label = "zImage";
+                        reg = <0x000f0000 0x002d0000>;
+                };
+
+                partition@00390000 {
+                        label = "rd.gz";
+                        reg = <0x003c0000 0x00410000>;
+                };
+
+                partition@007d0000 {
+                        label = "vendor";
+                        reg = <0x007d0000 0x00010000>;
+                        read-only;
+                };
+
+                partition@007e0000 {
+                        label = "RedBoot config";
+                        reg = <0x007e0000 0x00010000>;
+                        read-only;
+                };
+
+                partition@007f0000 {
+                        label = "FIS directory";
+                        reg = <0x007f0000 0x00010000>;
+                        read-only;
+                };
+        };
+};
+
+&pinctrl {
+        /* use only one pin for UART1, as mpp20 is used by sata0 */
+        uart1_pins: uart-pins-1 {
+                marvell,pins = "mpp19";
+                marvell,function = "ua1";
+        };
+
+        xhci0_vbus_pins: xhci0_vbus_pins {
+                marvell,pins = "mpp58";
+                marvell,function = "gpio";
+        };
+        xhci1_vbus_pins: xhci1_vbus_pins {
+                marvell,pins = "mpp59";
+                marvell,function = "gpio";
+        };
+};
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index 8e63be33472e..7fcc4c4885cf 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -70,13 +70,7 @@
         };
 
         soc {
-                internal-regs {
-                        pinctrl@18000 {
-                                compatible = "marvell,mv88f6820-pinctrl";
-                        };
-                };
-
-                pcie-controller {
+                pciec: pcie-controller {
                         compatible = "marvell,armada-370-pcie";
                         status = "disabled";
                         device_type = "pci";
@@ -106,7 +100,7 @@
                          * configured in x4 by the bootloader, then
                          * pcie@4,0 is not available.
                          */
-                        pcie@1,0 {
+                        pcie1: pcie@1,0 {
                                 device_type = "pci";
                                 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
                                 reg = <0x0800 0 0 0 0>;
@@ -124,7 +118,7 @@
                         };
 
                         /* x1 port */
-                        pcie@2,0 {
+                        pcie2: pcie@2,0 {
                                 device_type = "pci";
                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
                                 reg = <0x1000 0 0 0 0>;
@@ -142,7 +136,7 @@
                         };
 
                         /* x1 port */
-                        pcie@3,0 {
+                        pcie3: pcie@3,0 {
                                 device_type = "pci";
                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
                                 reg = <0x1800 0 0 0 0>;
@@ -163,7 +157,7 @@
                          * x1 port only available when pcie@1,0 is
                          * configured as a x1 port
                          */
-                        pcie@4,0 {
+                        pcie4: pcie@4,0 {
                                 device_type = "pci";
                                 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
                                 reg = <0x2000 0 0 0 0>;
@@ -182,3 +176,7 @@
                 };
         };
 };
+
+&pinctrl {
+        compatible = "marvell,mv88f6820-pinctrl";
+};
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 2745b7416313..0d5f1f062275 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -186,25 +186,6 @@
         };
 };
 
-&pinctrl {
-        clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
-                marvell,pins = "mpp46";
-                marvell,function = "ref";
-        };
-        clearfog_dsa0_pins: clearfog-dsa0-pins {
-                marvell,pins = "mpp23", "mpp41";
-                marvell,function = "gpio";
-        };
-        clearfog_spi1_cs_pins: spi1-cs-pins {
-                marvell,pins = "mpp55";
-                marvell,function = "spi1";
-        };
-        rear_button_pins: rear-button-pins {
-                marvell,pins = "mpp34";
-                marvell,function = "gpio";
-        };
-};
-
 &mdio {
         status = "okay";
 
@@ -268,6 +249,25 @@
         };
 };
 
+&pinctrl {
+        clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
+                marvell,pins = "mpp46";
+                marvell,function = "ref";
+        };
+        clearfog_dsa0_pins: clearfog-dsa0-pins {
+                marvell,pins = "mpp23", "mpp41";
+                marvell,function = "gpio";
+        };
+        clearfog_spi1_cs_pins: spi1-cs-pins {
+                marvell,pins = "mpp55";
+                marvell,function = "spi1";
+        };
+        rear_button_pins: rear-button-pins {
+                marvell,pins = "mpp34";
+                marvell,function = "gpio";
+        };
+};
+
 &spi1 {
         /*
          * Add SPI CS pins for clearfog:
diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/armada-388.dtsi
index 564fa5937e25..1c0d151b2aaa 100644
--- a/arch/arm/boot/dts/armada-388.dtsi
+++ b/arch/arm/boot/dts/armada-388.dtsi
@@ -50,13 +50,8 @@
         model = "Marvell Armada 388 family SoC";
         compatible = "marvell,armada388", "marvell,armada385",
                 "marvell,armada380";
-
         soc {
                 internal-regs {
-                        pinctrl@18000 {
-                                compatible = "marvell,mv88f6828-pinctrl";
-                        };
-
                         sata@e0000 {
                                 compatible = "marvell,armada-380-ahci";
                                 reg = <0xe0000 0x2000>;
@@ -68,3 +63,7 @@
                 };
         };
 };
+
+&pinctrl {
+        compatible = "marvell,mv88f6828-pinctrl";
+};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 79b767507eab..8b165c31de1e 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -82,7 +82,7 @@
                         reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
                 };
 
-                devbus-bootcs {
+                devbus_bootcs: devbus-bootcs {
                         compatible = "marvell,mvebu-devbus";
                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@@ -92,7 +92,7 @@
                         status = "disabled";
                 };
 
-                devbus-cs0 {
+                devbus_cs0: devbus-cs0 {
                         compatible = "marvell,mvebu-devbus";
                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@@ -102,7 +102,7 @@
                         status = "disabled";
                 };
 
-                devbus-cs1 {
+                devbus_cs1: devbus-cs1 {
                         compatible = "marvell,mvebu-devbus";
                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@@ -112,7 +112,7 @@
                         status = "disabled";
                 };
 
-                devbus-cs2 {
+                devbus_cs2: devbus-cs2 {
                         compatible = "marvell,mvebu-devbus";
                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@@ -122,7 +122,7 @@
                         status = "disabled";
                 };
 
-                devbus-cs3 {
+                devbus_cs3: devbus-cs3 {
                         compatible = "marvell,mvebu-devbus";
                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@@ -339,7 +339,7 @@
                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                         };
 
-                        system-controller@18200 {
+                        systemc: system-controller@18200 {
                                 compatible = "marvell,armada-380-system-controller",
                                              "marvell,armada-370-xp-system-controller";
                                 reg = <0x18200 0x100>;
@@ -360,7 +360,8 @@
 
                         mbusc: mbus-controller@20000 {
                                 compatible = "marvell,mbus-controller";
-                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                                reg = <0x20000 0x100>, <0x20180 0x20>,
+                                      <0x20250 0x8>;
                         };
 
                         mpic: interrupt-controller@20a00 {
@@ -373,7 +374,7 @@
                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
                         };
 
-                        timer@20300 {
+                        timer: timer@20300 {
                                 compatible = "marvell,armada-380-timer",
                                              "marvell,armada-xp-timer";
                                 reg = <0x20300 0x30>, <0x21040 0x30>;
@@ -387,14 +388,14 @@
                                 clock-names = "nbclk", "fixed";
                         };
 
-                        watchdog@20300 {
+                        watchdog: watchdog@20300 {
                                 compatible = "marvell,armada-380-wdt";
                                 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
                                 clocks = <&coreclk 2>, <&refclk>;
                                 clock-names = "nbclk", "fixed";
                         };
 
-                        cpurst@20800 {
+                        cpurst: cpurst@20800 {
                                 compatible = "marvell,armada-370-cpu-reset";
                                 reg = <0x20800 0x10>;
                         };
@@ -404,12 +405,12 @@
                                 reg = <0x20d20 0x6c>;
                         };
 
-                        coherency-fabric@21010 {
+                        coherencyfab: coherency-fabric@21010 {
                                 compatible = "marvell,armada-380-coherency-fabric";
                                 reg = <0x21010 0x1c>;
                         };
 
-                        pmsu@22000 {
+                        pmsu: pmsu@22000 {
                                 compatible = "marvell,armada-380-pmsu";
                                 reg = <0x22000 0x1000>;
                         };
@@ -451,7 +452,7 @@
                                 status = "disabled";
                         };
 
-                        usb@58000 {
+                        usb0: usb@58000 {
                                 compatible = "marvell,orion-ehci";
                                 reg = <0x58000 0x500>;
                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -459,7 +460,7 @@
                                 status = "disabled";
                         };
 
-                        xor@60800 {
+                        xor0: xor@60800 {
                                 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
                                 reg = <0x60800 0x100
                                        0x60a00 0x100>;
@@ -479,7 +480,7 @@
                                 };
                         };
 
-                        xor@60900 {
+                        xor1: xor@60900 {
                                 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
                                 reg = <0x60900 0x100
                                        0x60b00 0x100>;
@@ -507,7 +508,7 @@
                                 clocks = <&gateclk 4>;
                         };
 
-                        crypto@90000 {
+                        cesa: crypto@90000 {
                                 compatible = "marvell,armada-38x-crypto";
                                 reg = <0x90000 0x10000>;
                                 reg-names = "regs";
@@ -522,14 +523,14 @@
                                 marvell,crypto-sram-size = <0x800>;
                         };
 
-                        rtc@a3800 {
+                        rtc: rtc@a3800 {
                                 compatible = "marvell,armada-380-rtc";
                                 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
                                 reg-names = "rtc", "rtc-soc";
                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
                         };
 
-                        sata@a8000 {
+                        ahci0: sata@a8000 {
                                 compatible = "marvell,armada-380-ahci";
                                 reg = <0xa8000 0x2000>;
                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -545,7 +546,7 @@
                                 status = "disabled";
                         };
 
-                        sata@e0000 {
+                        ahci1: sata@e0000 {
                                 compatible = "marvell,armada-380-ahci";
                                 reg = <0xe0000 0x2000>;
                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
@@ -561,13 +562,13 @@
                                 clock-output-names = "nand";
                         };
 
-                        thermal@e8078 {
+                        thermal: thermal@e8078 {
                                 compatible = "marvell,armada380-thermal";
                                 reg = <0xe4078 0x4>, <0xe4074 0x4>;
                                 status = "okay";
                         };
 
-                        flash@d0000 {
+                        nand: flash@d0000 {
                                 compatible = "marvell,armada370-nand";
                                 reg = <0xd0000 0x54>;
                                 #address-cells = <1>;
@@ -577,7 +578,7 @@
                                 status = "disabled";
                         };
 
-                        sdhci@d8000 {
+                        sdhci: sdhci@d8000 {
                                 compatible = "marvell,armada-380-sdhci";
                                 reg-names = "sdhci", "mbus", "conf-sdio3";
                                 reg = <0xd8000 0x1000>,
@@ -589,7 +590,7 @@
                                 status = "disabled";
                         };
 
-                        usb3@f0000 {
+                        usb3_0: usb3@f0000 {
                                 compatible = "marvell,armada-380-xhci";
                                 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -597,7 +598,7 @@
                                 status = "disabled";
                         };
 
-                        usb3@f8000 {
+                        usb3_1: usb3@f8000 {
                                 compatible = "marvell,armada-380-xhci";
                                 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index f6a03dcee5ef..84cc232a29e9 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -45,11 +45,14 @@
  * common to all Armada XP SoCs.
  */
 
-#include "armada-xp.dtsi"
+#include "armada-370-xp.dtsi"
 
 / {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
         model = "Marvell 98DX3236 SoC";
-        compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+        compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
 
         aliases {
                 gpio0 = &gpio0;
@@ -72,12 +75,19 @@
         };
 
         soc {
+                compatible = "marvell,armadaxp-mbus", "simple-bus";
+
                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
                           MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
                           MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
 
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+                };
+
                 /*
                  * 98DX3236 has 1 x1 PCIe unit Gen2.0
                  */
@@ -95,8 +105,7 @@
                         ranges =
                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
-                                0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
-                                0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
+                                0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */>;
 
                         pcie1: pcie@1,0 {
                                 device_type = "pci";
@@ -117,31 +126,86 @@
                 };
 
                 internal-regs {
-                        coreclk: mvebu-sar@18230 {
-                                compatible = "marvell,mv98dx3236-core-clock";
+                        sdramc@1400 {
+                                compatible = "marvell,armada-xp-sdram-controller";
+                                reg = <0x1400 0x500>;
+                        };
+
+                        L2: l2-cache@8000 {
+                                compatible = "marvell,aurora-system-cache";
+                                reg = <0x08000 0x1000>;
+                                cache-id-part = <0x100>;
+                                cache-level = <2>;
+                                cache-unified;
+                                wt-override;
+                        };
+
+                        gpio0: gpio@18100 {
+                                compatible = "marvell,orion-gpio";
+                                reg = <0x18100 0x40>;
+                                ngpios = <32>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <82>, <83>, <84>, <85>;
+                        };
+
+                        /* does not exist */
+                        gpio1: gpio@18140 {
+                                compatible = "marvell,orion-gpio";
+                                reg = <0x18140 0x40>;
+                                status = "disabled";
+                        };
+
+                        gpio2: gpio@18180 { /* rework some properties */
+                                compatible = "marvell,orion-gpio";
+                                reg = <0x18180 0x40>;
+                                ngpios = <1>; /* only gpio #32 */
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <87>;
+                        };
+
+                        systemc: system-controller@18200 {
+                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0x18200 0x500>;
+                        };
+
+                        gateclk: clock-gating-control@18220 {
+                                compatible = "marvell,mv98dx3236-gating-clock";
+                                reg = <0x18220 0x4>;
+                                clocks = <&coreclk 0>;
+                                #clock-cells = <1>;
                         };
 
                         cpuclk: clock-complex@18700 {
+                                #clock-cells = <1>;
                                 compatible = "marvell,mv98dx3236-cpu-clock";
+                                reg = <0x18700 0x24>, <0x1c054 0x10>;
+                                clocks = <&coreclk 1>;
                         };
 
                         corediv-clock@18740 {
                                 status = "disabled";
                         };
 
-                        xor@60900 {
-                                status = "disabled";
+                        cpu-config@21000 {
+                                compatible = "marvell,armada-xp-cpu-config";
+                                reg = <0x21000 0x8>;
                         };
 
-                        crypto@90000 {
-                                status = "disabled";
+                        ethernet@70000 {
+                                compatible = "marvell,armada-xp-neta";
                         };
 
-                        xor@f0900 {
-                                status = "disabled";
+                        ethernet@74000 {
+                                compatible = "marvell,armada-xp-neta";
                         };
 
-                        xor@f0800 {
+                        xor1: xor@f0800 {
                                 compatible = "marvell,orion-xor";
                                 reg = <0xf0800 0x100
                                        0xf0a00 0x100>;
@@ -161,45 +225,43 @@
                                 };
                         };
 
-                        gpio0: gpio@18100 {
-                                compatible = "marvell,orion-gpio";
-                                reg = <0x18100 0x40>;
-                                ngpios = <32>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                interrupts = <82>, <83>, <84>, <85>;
-                        };
-
-                        /* does not exist */
-                        gpio1: gpio@18140 {
-                                compatible = "marvell,orion-gpio";
-                                reg = <0x18140 0x40>;
-                                status = "disabled";
+                        nand: nand@d0000 {
+                                clocks = <&dfx_coredivclk 0>;
                         };
 
-                        gpio2: gpio@18180 { /* rework some properties */
-                                compatible = "marvell,orion-gpio";
-                                reg = <0x18180 0x40>;
-                                ngpios = <1>; /* only gpio #32 */
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                interrupts = <87>;
-                        };
+                        xor0: xor@f0900 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0xF0900 0x100
+                                       0xF0B00 0x100>;
+                                clocks = <&gateclk 28>;
+                                status = "okay";
 
-                        nand: nand@d0000 {
-                                clocks = <&dfx_coredivclk 0>;
+                                xor00 {
+                                        interrupts = <94>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                                xor01 {
+                                        interrupts = <95>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                        dmacap,memset;
+                                };
                         };
                 };
 
-                dfxr: dfx-registers@ac000000 {
-                        compatible = "simple-bus";
+                dfx: dfx-server@ac000000 {
+                        compatible = "marvell,dfx-server", "simple-bus";
                         #address-cells = <1>;
                         #size-cells = <1>;
                         ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+                        reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+                        coreclk: mvebu-sar@f8204 {
+                                compatible = "marvell,mv98dx3236-core-clock";
+                                reg = <0xf8204 0x4>;
+                                #clock-cells = <1>;
+                        };
 
                         dfx_coredivclk: corediv-clock@f8268 {
                                 compatible = "marvell,mv98dx3236-corediv-clock";
@@ -208,11 +270,6 @@
                                 clocks = <&mainpll>;
                                 clock-output-names = "nand";
                         };
-
-                        dfx: dfx@0 {
-                                compatible = "marvell,dfx-server";
-                                reg = <0 0x100000>;
-                        };
                 };
 
                 switch: switch@a8000000 {
@@ -229,6 +286,53 @@
                         };
                 };
         };
+
+        clocks {
+                /* 25 MHz reference crystal */
+                refclk: oscillator {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                };
+        };
+};
+
+&i2c0 {
+        compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+        reg = <0x11000 0x100>;
+};
+
+&i2c1 {
+        compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+        reg = <0x11100 0x100>;
+};
+
+&mpic {
+        reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+};
+
+&timer {
+        compatible = "marvell,armada-xp-timer";
+        clocks = <&coreclk 2>, <&refclk>;
+        clock-names = "nbclk", "fixed";
+};
+
+&watchdog {
+        compatible = "marvell,armada-xp-wdt";
+        clocks = <&coreclk 2>, <&refclk>;
+        clock-names = "nbclk", "fixed";
+};
+
+&cpurst {
+        reg = <0x20800 0x20>;
+};
+
+&usb0 {
+        clocks = <&gateclk 18>;
+};
+
+&usb1 {
+        clocks = <&gateclk 19>;
 };
 
 &pinctrl {
@@ -241,14 +345,13 @@
         };
 };
 
-&sdio {
-        status = "disabled";
+&spi0 {
+        compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
+        pinctrl-0 = <&spi0_pins>;
+        pinctrl-names = "default";
 };
 
-&crypto_sram0 {
+&sdio {
         status = "disabled";
 };
 
-&crypto_sram1 {
-        status = "disabled";
-};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
index e1580afdc260..a0d81bd7312b 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
@@ -49,7 +49,7 @@
 
 / {
         model = "Marvell 98DX3336 SoC";
-        compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+        compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
 
         cpus {
                 cpu@1 {
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
index b9d9b269efb4..51de91b31a9d 100644
--- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
@@ -49,7 +49,7 @@
 
 / {
         model = "Marvell 98DX4251 SoC";
-        compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+        compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
 
         cpus {
                 cpu@1 {
diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
index a8130805074e..1b1ff17fdd9c 100644
--- a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
+++ b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
@@ -58,7 +58,7 @@
 
 / {
         model = "Marvell Bobcat2 Evaluation Board";
-        compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armadaxp", "marvell,armada-370-xp";
+        compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
 
         chosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
index 4e07cb6ed800..06fce35d7491 100644
--- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
+++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
@@ -58,7 +58,7 @@
 
 / {
         model = "DB-XC3-24G4XG";
-        compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armadaxp", "marvell,armada-370-xp";
+        compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
 
         chosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 42ea8764814c..9efcf59c9b44 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -71,7 +71,8 @@
                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
                           MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
-                          MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
+                          MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
+                          MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
 
                 internal-regs {
 
@@ -95,6 +96,9 @@
                                 pinctrl-names = "default";
                                 status = "okay";
                                 phy-mode = "rgmii-id";
+                                buffer-manager = <&bm>;
+                                bm,pool-long = <0>;
+                                bm,pool-short = <1>;
                                 fixed-link {
                                         speed = <1000>;
                                         full-duplex;
@@ -106,6 +110,9 @@
                                 pinctrl-names = "default";
                                 status = "okay";
                                 phy-mode = "rgmii-id";
+                                buffer-manager = <&bm>;
+                                bm,pool-long = <2>;
+                                bm,pool-short = <3>;
                                 fixed-link {
                                         speed = <1000>;
                                         full-duplex;
@@ -156,6 +163,7 @@
                                         esata@4 {
                                                 label = "mamba:white:esata";
                                                 reg = <0x4>;
+                                                linux,default-trigger = "disk-activity";
                                         };
 
                                         usb2@5 {
@@ -185,6 +193,10 @@
                                 };
                         };
 
+                        bm@c8000 {
+                                status = "okay";
+                        };
+
                         nand@d0000 {
                                 status = "okay";
                                 num-cs = <1>;
@@ -258,6 +270,10 @@
                                 };
                         };
                 };
+
+                bm-bppi {
+                        status = "okay";
+                };
         };
 
         gpio_keys {
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index d967603dade8..7c90dac99822 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -20,6 +20,28 @@
         };
 };
 
+&fmc {
+        status = "okay";
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+                label = "bmc";
+        };
+};
+
+&spi1 {
+        status = "okay";
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+                label = "pnor";
+        };
+};
+
+&spi2 {
+        status = "okay";
+};
+
 &uart5 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index 1d2fc1e1dc29..112551766275 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -31,6 +31,24 @@
         };
 };
 
+&fmc {
+        status = "okay";
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+                label = "bmc";
+        };
+};
+
+&spi {
+        status = "okay";
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+                label = "pnor";
+        };
+};
+
 &uart5 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 7a3b2b50c884..1190fec1b5d0 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -31,6 +31,42 @@
         };
 };
 
+&fmc {
+        status = "okay";
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+                label = "bmc";
+        };
+};
+
+&spi1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_spi1_default>;
+
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+                label = "pnor";
+        };
+};
+
+&uart1 {
+        /* Rear RS-232 connector */
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_txd1_default
+                        &pinctrl_rxd1_default
+                        &pinctrl_nrts1_default
+                        &pinctrl_ndtr1_default
+                        &pinctrl_ndsr1_default
+                        &pinctrl_ncts1_default
+                        &pinctrl_ndcd1_default
+                        &pinctrl_nri1_default>;
+};
+
 &uart5 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index c79c937b0a8a..8c6bc29eb7f6 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -18,21 +18,41 @@
                 };
         };
 
-        clocks {
-                clk_clkin: clk_clkin {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <48000000>;
-                };
-
-        };
-
         ahb {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <1>;
                 ranges;
 
+                fmc: flash-controller@1e620000 {
+                        reg = < 0x1e620000 0x94
+                                0x20000000 0x02000000 >;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "aspeed,ast2400-fmc";
+                        status = "disabled";
+                        interrupts = <19>;
+                        flash@0 {
+                                reg = < 0 >;
+                                compatible = "jedec,spi-nor";
+                                status = "disabled";
+                        };
+                };
+
+                spi: flash-controller@1e630000 {
+                        reg = < 0x1e630000 0x18
+                                0x30000000 0x02000000 >;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "aspeed,ast2400-spi";
+                        status = "disabled";
+                        flash@0 {
+                                reg = < 0 >;
+                                compatible = "jedec,spi-nor";
+                                status = "disabled";
+                        };
+                };
+
                 vic: interrupt-controller@1e6c0080 {
                         compatible = "aspeed,ast2400-vic";
                         interrupt-controller;
@@ -61,16 +81,48 @@
                         #size-cells = <1>;
                         ranges;
 
-                        clk_hpll: clk_hpll@1e6e2070 {
-                                #clock-cells = <0>;
-                                compatible = "aspeed,g4-hpll-clock";
-                                reg = <0x1e6e2070 0x4>;
-                                clocks = <&clk_clkin>;
-                        };
-
                         syscon: syscon@1e6e2000 {
                                 compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
                                 reg = <0x1e6e2000 0x1a8>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                clk_clkin: clk_clkin {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <48000000>;
+                                };
+
+                                clk_hpll: clk_hpll@70 {
+                                        #clock-cells = <0>;
+                                        compatible = "aspeed,g4-hpll-clock", "fixed-clock";
+                                        reg = <0x70>;
+                                        clocks = <&clk_clkin>;
+                                        clock-frequency = <384000000>;
+                                };
+
+                                clk_ahb: clk_ahb@70 {
+                                        #clock-cells = <0>;
+                                        compatible = "aspeed,g4-ahb-clock", "fixed-clock";
+                                        reg = <0x70>;
+                                        clocks = <&clk_hpll>;
+                                        clock-frequency = <192000000>;
+                                };
+
+                                clk_apb: clk_apb@08 {
+                                        #clock-cells = <0>;
+                                        compatible = "aspeed,g4-apb-clock", "fixed-clock";
+                                        reg = <0x08>;
+                                        clocks = <&clk_hpll>;
+                                        clock-frequency = <48000000>;
+                                };
+
+                                clk_uart: clk_uart@2c{
+                                        #clock-cells = <0>;
+                                        compatible = "aspeed,g4-uart-clock", "fixed-clock";
+                                        reg = <0x2c>;
+                                        clock-frequency = <24000000>;
+                                };
 
                                 pinctrl: pinctrl {
                                         compatible = "aspeed,g4-pinctrl";
@@ -818,19 +870,6 @@
                                 };
                         };
 
-                        clk_apb: clk_apb@1e6e2008 {
-                                #clock-cells = <0>;
-                                compatible = "aspeed,g4-apb-clock";
-                                reg = <0x1e6e2008 0x4>;
-                                clocks = <&clk_hpll>;
-                        };
-
-                        clk_uart: clk_uart@1e6e2008 {
-                                #clock-cells = <0>;
-                                compatible = "aspeed,uart-clock";
-                                reg = <0x1e6e202c 0x4>;
-                        };
-
                         sram@1e720000 {
                                 compatible = "mmio-sram";
                                 reg = <0x1e720000 0x8000>;      // 32K
@@ -857,13 +896,13 @@
                         };
 
                         wdt1: wdt@1e785000 {
-                                compatible = "aspeed,wdt";
+                                compatible = "aspeed,ast2400-wdt";
                                 reg = <0x1e785000 0x1c>;
                                 interrupts = <27>;
                         };
 
                         wdt2: wdt@1e785020 {
-                                compatible = "aspeed,wdt";
+                                compatible = "aspeed,ast2400-wdt";
                                 reg = <0x1e785020 0x1c>;
                                 interrupts = <27>;
                                 clocks = <&clk_apb>;
@@ -930,6 +969,14 @@
                                 no-loopback-test;
                                 status = "disabled";
                         };
+
+                        adc: adc@1e6e9000 {
+                                compatible = "aspeed,ast2400-adc";
+                                reg = <0x1e6e9000 0xb0>;
+                                clocks = <&clk_apb>;
+                                #io-channel-cells = <1>;
+                                status = "disabled";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index b6596633036c..a0bea4a6ec77 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -24,6 +24,69 @@
                 #size-cells = <1>;
                 ranges;
 
+                fmc: flash-controller@1e620000 {
+                        reg = < 0x1e620000 0xc4
+                                0x20000000 0x10000000 >;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "aspeed,ast2500-fmc";
+                        status = "disabled";
+                        interrupts = <19>;
+                        flash@0 {
+                                reg = < 0 >;
+                                compatible = "jedec,spi-nor";
+                                status = "disabled";
+                        };
+                        flash@1 {
+                                reg = < 1 >;
+                                compatible = "jedec,spi-nor";
+                                status = "disabled";
+                        };
+                        flash@2 {
+                                reg = < 2 >;
+                                compatible = "jedec,spi-nor";
+                                status = "disabled";
+                        };
+                };
+
+                spi1: flash-controller@1e630000 {
+                        reg = < 0x1e630000 0xc4
+                                0x30000000 0x08000000 >;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "aspeed,ast2500-spi";
+                        status = "disabled";
+                        flash@0 {
+                                reg = < 0 >;
+                                compatible = "jedec,spi-nor";
+                                status = "disabled";
+                        };
+                        flash@1 {
+                                reg = < 1 >;
+                                compatible = "jedec,spi-nor";
+                                status = "disabled";
+                        };
+                };
+
+                spi2: flash-controller@1e631000 {
+                        reg = < 0x1e631000 0xc4
+                                0x38000000 0x08000000 >;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "aspeed,ast2500-spi";
+                        status = "disabled";
+                        flash@0 {
+                                reg = < 0 >;
+                                compatible = "jedec,spi-nor";
+                                status = "disabled";
+                        };
+                        flash@1 {
+                                reg = < 1 >;
+                                compatible = "jedec,spi-nor";
+                                status = "disabled";
+                        };
+                };
+
                 vic: interrupt-controller@1e6c0080 {
                         compatible = "aspeed,ast2400-vic";
                         interrupt-controller;
@@ -52,15 +115,49 @@
                         #size-cells = <1>;
                         ranges;
 
-                        clk_clkin: clk_clkin@1e6e2070 {
-                                #clock-cells = <0>;
-                                compatible = "aspeed,g5-clkin-clock";
-                                reg = <0x1e6e2070 0x04>;
-                        };
-
                         syscon: syscon@1e6e2000 {
                                 compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
                                 reg = <0x1e6e2000 0x1a8>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                clk_clkin: clk_clkin@70 {
+                                        #clock-cells = <0>;
+                                        compatible = "aspeed,g5-clkin-clock", "fixed-clock";
+                                        reg = <0x70>;
+                                        clock-frequency = <24000000>;
+                                };
+
+                                clk_hpll: clk_hpll@24 {
+                                        #clock-cells = <0>;
+                                        compatible = "aspeed,g5-hpll-clock", "fixed-clock";
+                                        reg = <0x24>;
+                                        clocks = <&clk_clkin>;
+                                        clock-frequency = <792000000>;
+                                };
+
+                                clk_ahb: clk_ahb@70 {
+                                        #clock-cells = <0>;
+                                        compatible = "aspeed,g5-ahb-clock", "fixed-clock";
+                                        reg = <0x70>;
+                                        clocks = <&clk_hpll>;
+                                        clock-frequency = <198000000>;
+                                };
+
+                                clk_apb: clk_apb@08 {
+                                        #clock-cells = <0>;
+                                        compatible = "aspeed,g5-apb-clock", "fixed-clock";
+                                        reg = <0x08>;
+                                        clocks = <&clk_hpll>;
+                                        clock-frequency = <24750000>;
+                                };
+
+                                clk_uart: clk_uart@2c {
+                                        #clock-cells = <0>;
+                                        compatible = "aspeed,uart-clock", "fixed-clock";
+                                        reg = <0x2c>;
+                                        clock-frequency = <24000000>;
+                                };
 
                                 pinctrl: pinctrl {
                                         compatible = "aspeed,g5-pinctrl";
@@ -285,7 +382,6 @@
                                                 function = "LAD0";
                                                 groups = "LAD0";
                                         };
-
                                         pinctrl_lad1_default: lad1_default {
                                                 function = "LAD1";
                                                 groups = "LAD1";
@@ -872,33 +968,7 @@
                                         };
 
                                 };
-                        };
-
-                        clk_hpll: clk_hpll@1e6e2024 {
-                                #clock-cells = <0>;
-                                compatible = "aspeed,g5-hpll-clock";
-                                reg = <0x1e6e2024 0x4>;
-                                clocks = <&clk_clkin>;
-                        };
-
-                        clk_ahb: clk_ahb@1e6e2070 {
-                                #clock-cells = <0>;
-                                compatible = "aspeed,g5-ahb-clock";
-                                reg = <0x1e6e2070 0x4>;
-                                clocks = <&clk_hpll>;
-                        };
 
-                        clk_apb: clk_apb@1e6e2008 {
-                                #clock-cells = <0>;
-                                compatible = "aspeed,g5-apb-clock";
-                                reg = <0x1e6e2008 0x4>;
-                                clocks = <&clk_hpll>;
-                        };
-
-                        clk_uart: clk_uart@1e6e2008 {
-                                #clock-cells = <0>;
-                                compatible = "aspeed,uart-clock";
-                                reg = <0x1e6e202c 0x4>;
                         };
 
                         gfx: display@1e6e6000 {
@@ -934,21 +1004,21 @@
 
 
                         wdt1: wdt@1e785000 {
-                                compatible = "aspeed,wdt";
-                                reg = <0x1e785000 0x1c>;
+                                compatible = "aspeed,ast2500-wdt";
+                                reg = <0x1e785000 0x20>;
                                 interrupts = <27>;
                         };
 
                         wdt2: wdt@1e785020 {
-                                compatible = "aspeed,wdt";
-                                reg = <0x1e785020 0x1c>;
+                                compatible = "aspeed,ast2500-wdt";
+                                reg = <0x1e785020 0x20>;
                                 interrupts = <27>;
                                 status = "disabled";
                         };
 
                         wdt3: wdt@1e785040 {
-                                compatible = "aspeed,wdt";
-                                reg = <0x1e785074 0x1c>;
+                                compatible = "aspeed,ast2500-wdt";
+                                reg = <0x1e785040 0x20>;
                                 status = "disabled";
                         };
 
@@ -1042,6 +1112,14 @@
                                 no-loopback-test;
                                 status = "disabled";
                         };
+
+                        adc: adc@1e6e9000 {
+                                compatible = "aspeed,ast2500-adc";
+                                reg = <0x1e6e9000 0xb0>;
+                                clocks = <&clk_apb>;
+                                #io-channel-cells = <1>;
+                                status = "disabled";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index 9f7f8a7d8ff9..0bef9e0b89c6 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -246,6 +246,7 @@
 
                         shdwc@f8048010 {
                                 atmel,shdwc-debouncer = <976>;
+                                atmel,wakeup-rtc-timer;
 
                                 input@0 {
                                         reg = <0>;
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index c51fc652f6c7..5a53fcf542ab 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -162,9 +162,10 @@
                         };
 
                         adc0: adc@f8018000 {
+                                atmel,adc-vref = <3300>;
+                                atmel,adc-channels-used = <0xfe>;
                                 pinctrl-0 = <
                                         &pinctrl_adc0_adtrg
-                                        &pinctrl_adc0_ad0
                                         &pinctrl_adc0_ad1
                                         &pinctrl_adc0_ad2
                                         &pinctrl_adc0_ad3
@@ -172,8 +173,6 @@
                                         &pinctrl_adc0_ad5
                                         &pinctrl_adc0_ad6
                                         &pinctrl_adc0_ad7
-                                        &pinctrl_adc0_ad8
-                                        &pinctrl_adc0_ad9
                                         >;
                                 status = "okay";
                         };
diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts
index 669a2c6bdefc..498fba3e52b5 100644
--- a/arch/arm/boot/dts/at91-tse850-3.dts
+++ b/arch/arm/boot/dts/at91-tse850-3.dts
@@ -86,16 +86,43 @@
                 #io-channel-cells = <1>;
         };
 
-        envelope-detector {
+        env_det: envelope-detector {
                 compatible = "axentia,tse850-envelope-detector";
                 io-channels = <&dac 0>;
                 io-channel-names = "dac";
+                #io-channel-cells = <1>;
 
                 interrupt-parent = <&pioA>;
                 interrupts = <3 IRQ_TYPE_EDGE_RISING>;
                 interrupt-names = "comp";
         };
 
+        mux: mux-controller {
+                compatible = "gpio-mux";
+                #mux-control-cells = <0>;
+
+                mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+                            <&pioA 1 GPIO_ACTIVE_HIGH>,
+                            <&pioA 2 GPIO_ACTIVE_HIGH>;
+                idle-state = <0>;
+        };
+
+        envelope-detector-mux {
+                compatible = "io-channel-mux";
+                io-channels = <&env_det 0>;
+                io-channel-names = "parent";
+
+                mux-controls = <&mux>;
+
+                channels = "", "",
+                         "sync-1",
+                         "in",
+                         "out",
+                         "sync-2",
+                         "sys-reg",
+                         "ana-reg";
+        };
+
         leds {
                 compatible = "gpio-leds";
 
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 3fe77c38bd0d..7e80acda8f69 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -263,7 +263,7 @@
                         };
 
                         matrix: matrix@ffffee00 {
-                                compatible = "atmel,at91sam9260-bus-matrix", "syscon";
+                                compatible = "atmel,at91sam9261-matrix", "syscon";
                                 reg = <0xffffee00 0x200>;
                         };
 
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 696b8ba064a6..9d2bbc41a7b0 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -116,7 +116,7 @@
                         };
 
                         spi0: spi@f0000000 {
-                                status = "okay";
+                                status = "disabled"; /* conflicts with mmc1 */
                                 cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
                                 m25p80@0 {
                                         compatible = "atmel,at25df321a";
diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi
index 675bb0f30825..9677dd5cf6b6 100644
--- a/arch/arm/boot/dts/axp209.dtsi
+++ b/arch/arm/boot/dts/axp209.dtsi
@@ -53,6 +53,11 @@
         interrupt-controller;
         #interrupt-cells = <1>;
 
+        ac_power_supply: ac-power-supply {
+                compatible = "x-powers,axp202-ac-power-supply";
+                status = "disabled";
+        };
+
         axp_gpio: gpio {
                 compatible = "x-powers,axp209-gpio";
                 gpio-controller;
diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi
index 458b6681e3ec..67331c5f1714 100644
--- a/arch/arm/boot/dts/axp22x.dtsi
+++ b/arch/arm/boot/dts/axp22x.dtsi
@@ -52,6 +52,11 @@
         interrupt-controller;
         #interrupt-cells = <1>;
 
+        ac_power_supply: ac-power-supply {
+                compatible = "x-powers,axp221-ac-power-supply";
+                status = "disabled";
+        };
+
         regulators {
                 /* Default work frequency for buck regulators */
                 x-powers,dcdc-freq = <3000>;
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 8833a4c3cd96..9644fddb5e3c 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -205,7 +205,7 @@
                         status = "disabled";
 
                         msi-parent = <&msi0>;
-                        msi0: msi@18012000 {
+                        msi0: msi-controller {
                                 compatible = "brcm,iproc-msi";
                                 msi-controller;
                                 interrupt-parent = <&gic>;
@@ -240,7 +240,7 @@
                         status = "disabled";
 
                         msi-parent = <&msi1>;
-                        msi1: msi@18013000 {
+                        msi1: msi-controller {
                                 compatible = "brcm,iproc-msi";
                                 msi-controller;
                                 interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 832795b0fd0f..fe6cba994a97 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -245,6 +245,15 @@
                         status = "disabled";
                 };
 
+                mailbox: mailbox@25000 {
+                        compatible = "brcm,iproc-fa2-mbox";
+                        reg = <0x25000 0x445>;
+                        interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+                        #mbox-cells = <1>;
+                        brcm,rx-status-len = <32>;
+                        brcm,use-bcm-hdr;
+                };
+
                 nand: nand@26000 {
                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
                         reg = <0x026000 0x600>,
@@ -288,6 +297,12 @@
                         #size-cells = <0>;
                 };
 
+                crypto@2f000 {
+                        compatible = "brcm,spum-nsp-crypto";
+                        reg = <0x2f000 0x900>;
+                        mboxes = <&mailbox 0>;
+                };
+
                 gpiob: gpio@30000 {
                         compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
                         reg = <0x30000 0x50>;
@@ -306,6 +321,20 @@
                         status = "disabled";
                 };
 
+                ehci0: usb@2a000 {
+                        compatible = "generic-ehci";
+                        reg = <0x2a000 0x100>;
+                        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@2b000 {
+                        compatible = "generic-ohci";
+                        reg = <0x2b000 0x100>;
+                        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
                 rng: rng@33000 {
                         compatible = "brcm,bcm-nsp-rng";
                         reg = <0x33000 0x14>;
@@ -347,6 +376,7 @@
                         #size-cells = <0>;
                         interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
                         clock-frequency = <100000>;
+                        status = "disabled";
                 };
 
                 watchdog@39000 {
@@ -450,7 +480,7 @@
                 status = "disabled";
 
                 msi-parent = <&msi0>;
-                msi0: msi@18012000 {
+                msi0: msi-controller {
                         compatible = "brcm,iproc-msi";
                         msi-controller;
                         interrupt-parent = <&gic>;
@@ -486,7 +516,7 @@
                 status = "disabled";
 
                 msi-parent = <&msi1>;
-                msi1: msi@18013000 {
+                msi1: msi-controller {
                         compatible = "brcm,iproc-msi";
                         msi-controller;
                         interrupt-parent = <&gic>;
@@ -522,7 +552,7 @@
                 status = "disabled";
 
                 msi-parent = <&msi2>;
-                msi2: msi@18014000 {
+                msi2: msi-controller {
                         compatible = "brcm,iproc-msi";
                         msi-controller;
                         interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 38e6050035bc..a7b5ce133784 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -69,6 +69,12 @@
         bus-width = <4>;
 };
 
+&sdhost {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdhost_gpio48>;
+        bus-width = <4>;
+};
+
 &pwm {
         pinctrl-names = "default";
         pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
@@ -92,3 +98,11 @@
         power-domains = <&power RPI_POWER_DOMAIN_VEC>;
         status = "okay";
 };
+
+&dsi0 {
+        power-domains = <&power RPI_POWER_DOMAIN_DSI0>;
+};
+
+&dsi1 {
+        power-domains = <&power RPI_POWER_DOMAIN_DSI1>;
+};
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index a3106aa446c6..35cea3fcaf5c 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -93,10 +93,13 @@
                         #clock-cells = <1>;
                         reg = <0x7e101000 0x2000>;
 
-                        /* CPRMAN derives everything from the platform's
-                         * oscillator.
+                        /* CPRMAN derives almost everything from the
+                         * platform's oscillator.  However, the DSI
+                         * pixel clocks come from the DSI analog PHY.
                          */
-                        clocks = <&clk_osc>;
+                        clocks = <&clk_osc>,
+                                <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
+                                <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
                 };
 
                 rng@7e104000 {
@@ -347,6 +350,16 @@
                         arm,primecell-periphid = <0x00241011>;
                 };
 
+                sdhost: mmc@7e202000 {
+                        compatible = "brcm,bcm2835-sdhost";
+                        reg = <0x7e202000 0x100>;
+                        interrupts = <2 24>;
+                        clocks = <&clocks BCM2835_CLOCK_VPU>;
+                        dmas = <&dma 13>;
+                        dma-names = "rx-tx";
+                        status = "disabled";
+                };
+
                 i2s: i2s@7e203000 {
                         compatible = "brcm,bcm2835-i2s";
                         reg = <0x7e203000 0x20>,
@@ -390,6 +403,25 @@
                         interrupts = <2 14>; /* pwa1 */
                 };
 
+                dsi0: dsi@7e209000 {
+                        compatible = "brcm,bcm2835-dsi0";
+                        reg = <0x7e209000 0x78>;
+                        interrupts = <2 4>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #clock-cells = <1>;
+
+                        clocks = <&clocks BCM2835_PLLA_DSI0>,
+                                 <&clocks BCM2835_CLOCK_DSI0E>,
+                                 <&clocks BCM2835_CLOCK_DSI0P>;
+                        clock-names = "phy", "escape", "pixel";
+
+                        clock-output-names = "dsi0_byte",
+                                             "dsi0_ddr2",
+                                             "dsi0_ddr";
+
+                };
+
                 thermal: thermal@7e212000 {
                         compatible = "brcm,bcm2835-thermal";
                         reg = <0x7e212000 0x8>;
@@ -456,6 +488,26 @@
                         interrupts = <2 1>;
                 };
 
+                dsi1: dsi@7e700000 {
+                        compatible = "brcm,bcm2835-dsi1";
+                        reg = <0x7e700000 0x8c>;
+                        interrupts = <2 12>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #clock-cells = <1>;
+
+                        clocks = <&clocks BCM2835_PLLD_DSI1>,
+                                 <&clocks BCM2835_CLOCK_DSI1E>,
+                                 <&clocks BCM2835_CLOCK_DSI1P>;
+                        clock-names = "phy", "escape", "pixel";
+
+                        clock-output-names = "dsi1_byte",
+                                             "dsi1_ddr2",
+                                             "dsi1_ddr";
+
+                        status = "disabled";
+                };
+
                 i2c1: i2c@7e804000 {
                         compatible = "brcm,bcm2835-i2c";
                         reg = <0x7e804000 0x1000>;
@@ -499,6 +551,8 @@
                         clocks = <&clocks BCM2835_PLLH_PIX>,
                                  <&clocks BCM2835_CLOCK_HSM>;
                         clock-names = "pixel", "hdmi";
+                        dmas = <&dma 17>;
+                        dma-names = "audio-rx";
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
index d241cee4bfcc..4175174e589a 100644
--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
@@ -4,7 +4,17 @@
  *
  * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
  *
- * Licensed under the GNU/GPL. See COPYING for details.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 /dts-v1/;
@@ -31,19 +41,16 @@
                 usb3 {
                         label = "bcm53xx:blue:usb3";
                         gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan {
                         label = "bcm53xx:blue:wan";
                         gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 lan {
                         label = "bcm53xx:blue:lan";
                         gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 power {
@@ -61,14 +68,12 @@
                 2ghz {
                         label = "bcm53xx:blue:2ghz";
                         gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
 
                 usb2 {
                         label = "bcm53xx:blue:usb2";
                         gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
index b0e62042f62f..8fa033fea959 100644
--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
@@ -4,7 +4,17 @@
  *
  * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
  *
- * Licensed under the GNU/GPL. See COPYING for details.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 /dts-v1/;
@@ -31,7 +41,6 @@
                 usb2 {
                         label = "bcm53xx:blue:usb2";
                         gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 power {
@@ -49,7 +58,6 @@
                 usb3 {
                         label = "bcm53xx:blue:usb3";
                         gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
index c9ba6b964b38..62e1427b3f10 100644
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
@@ -52,13 +52,11 @@
                 usb {
                         label = "bcm53xx:blue:usb";
                         gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 power0 {
                         label = "bcm53xx:red:power";
                         gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 power1 {
@@ -76,7 +74,6 @@
                 router1 {
                         label = "bcm53xx:amber:router";
                         gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan {
@@ -88,13 +85,11 @@
                 wireless0 {
                         label = "bcm53xx:blue:wireless";
                         gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wireless1 {
                         label = "bcm53xx:amber:wireless";
                         gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
new file mode 100644
index 000000000000..126ab5867772
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2017 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+        compatible = "linksys,ea6300-v1", "brcm,bcm4708";
+        model = "Linksys EA6300 V1";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+                };
+
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index b9f66c0fae27..a5647efe4118 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -43,19 +43,16 @@
                 power1 {
                         label = "bcm53xx:amber:power";
                         gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb {
                         label = "bcm53xx:blue:usb";
                         gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wireless {
                         label = "bcm53xx:blue:wireless";
                         gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
index ae0199f6c7a2..bb66cebe0bd8 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
@@ -4,7 +4,17 @@
  *
  * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
  *
- * Licensed under the GNU/GPL. See COPYING for details.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 /dts-v1/;
@@ -37,7 +47,6 @@
                 power0 {
                         label = "bcm53xx:green:power";
                         gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 power1 {
@@ -49,13 +58,11 @@
                 usb {
                         label = "bcm53xx:blue:usb";
                         gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wireless {
                         label = "bcm53xx:blue:wireless";
                         gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
index 36b628b190d7..19ee924d7d53 100644
--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
@@ -37,61 +37,51 @@
                 power-amber {
                         label = "bcm53xx:amber:power";
                         gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb2 {
                         label = "bcm53xx:white:usb2";
                         gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb3-white {
                         label = "bcm53xx:white:usb3";
                         gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb3-green {
                         label = "bcm53xx:green:usb3";
                         gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wps {
                         label = "bcm53xx:white:wps";
                         gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 status-red {
                         label = "bcm53xx:red:status";
                         gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 status-green {
                         label = "bcm53xx:green:status";
                         gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 status-blue {
                         label = "bcm53xx:blue:status";
                         gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan-white {
                         label = "bcm53xx:white:wan";
                         gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan-red {
                         label = "bcm53xx:red:wan";
                         gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
index d0eec099f1f8..1a19e97a987d 100644
--- a/arch/arm/boot/dts/bcm4708.dtsi
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -12,6 +12,14 @@
 / {
         compatible = "brcm,bcm4708";
 
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
index db8608be0ee7..0800a964f2fe 100644
--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
@@ -4,7 +4,17 @@
  *
  * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
  *
- * Licensed under the GNU/GPL. See COPYING for details.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 /dts-v1/;
@@ -37,7 +47,6 @@
                 usb2 {
                         label = "bcm53xx:blue:usb2";
                         gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan {
@@ -55,7 +64,6 @@
                 usb3 {
                         label = "bcm53xx:blue:usb3";
                         gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
index d51586d95b9a..c2af33eb47de 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
@@ -4,7 +4,17 @@
  *
  * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
  *
- * Licensed under the GNU/GPL. See COPYING for details.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 /dts-v1/;
@@ -58,7 +68,6 @@
                 power1 {
                         label = "bcm53xx:red:power";
                         gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 router0 {
@@ -70,7 +79,6 @@
                 router1 {
                         label = "bcm53xx:amber:router";
                         gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan {
@@ -82,13 +90,11 @@
                 wireless0 {
                         label = "bcm53xx:green:wireless";
                         gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wireless1 {
                         label = "bcm53xx:amber:wireless";
                         gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
index de041b8c3342..8bef6429feee 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
@@ -4,7 +4,17 @@
  *
  * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
  *
- * Licensed under the GNU/GPL. See COPYING for details.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
new file mode 100644
index 000000000000..a854a5174b7f
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2017 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm47081.dtsi"
+
+/ {
+        compatible = "tplink,archer-c5-v2", "brcm,bcm47081", "brcm,bcm4708";
+        model = "TP-LINK Archer C5 V2";
+
+        chosen {
+                bootargs = "earlycon";
+        };
+
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                2ghz {
+                        label = "bcm53xx:green:2ghz";
+                        gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
+                };
+
+                lan {
+                        label = "bcm53xx:green:lan";
+                        gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
+                };
+
+                usb2-port1 {
+                        label = "bcm53xx:green:usb2-port1";
+                        gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
+                };
+
+                power {
+                        label = "bcm53xx:green:power";
+                        gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                wan-green {
+                        label = "bcm53xx:green:wan";
+                        gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
+                };
+
+                wps {
+                        label = "bcm53xx:green:wps";
+                        gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
+                };
+
+                wan-amber {
+                        label = "bcm53xx:amber:wan";
+                        gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
+                };
+
+                5ghz {
+                        label = "bcm53xx:green:5ghz";
+                        gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
+                };
+
+                usb2-port2 {
+                        label = "bcm53xx:green:usb2-port2";
+                        gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                rfkill {
+                        label = "WiFi";
+                        linux,code = <KEY_RFKILL>;
+                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+                };
+
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&spi_nor {
+        status = "okay";
+};
+
+&usb2 {
+        vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/boot/dts/bcm47081.dtsi b/arch/arm/boot/dts/bcm47081.dtsi
index c5f7619af4a6..9829d044aaf4 100644
--- a/arch/arm/boot/dts/bcm47081.dtsi
+++ b/arch/arm/boot/dts/bcm47081.dtsi
@@ -4,7 +4,17 @@
  *
  * Copyright © 2014 Rafał Miłecki <zajec5@gmail.com>
  *
- * Licensed under the GNU/GPL. See COPYING for details.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 #include "bcm5301x.dtsi"
@@ -12,6 +22,14 @@
 / {
         compatible = "brcm,bcm47081";
 
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
index eaca6876db0f..df473cc41572 100644
--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
@@ -4,7 +4,17 @@
  *
  * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
  *
- * Licensed under the GNU/GPL. See COPYING for details.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 /dts-v1/;
@@ -31,7 +41,6 @@
                 wps {
                         label = "bcm53xx:blue:wps";
                         gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 power {
@@ -43,7 +52,6 @@
                 wan {
                         label = "bcm53xx:red:wan";
                         gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
index b32957ca9443..92058c73ee59 100644
--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
@@ -31,13 +31,11 @@
                 usb {
                         label = "bcm53xx:green:usb";
                         gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 power-amber {
                         label = "bcm53xx:amber:power";
                         gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 power-white {
@@ -49,37 +47,31 @@
                 router-amber {
                         label = "bcm53xx:amber:router";
                         gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 router-white {
                         label = "bcm53xx:white:router";
                         gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan-amber {
                         label = "bcm53xx:amber:wan";
                         gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan-white {
                         label = "bcm53xx:white:wan";
                         gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wireless-amber {
                         label = "bcm53xx:amber:wireless";
                         gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wireless-white {
                         label = "bcm53xx:white:wireless";
                         gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
new file mode 100644
index 000000000000..3d1d9c2c4efc
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2017 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm4709.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+        compatible = "linksys,ea9200", "brcm,bcm4709", "brcm,bcm4708";
+        model = "Linksys EA9200";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                reg = <0x00000000 0x08000000
+                       0x88000000 0x08000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+                };
+
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
index f459a98a72c6..f43ab4721456 100644
--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
@@ -4,7 +4,17 @@
  *
  * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
  *
- * Licensed under the GNU/GPL. See COPYING for details.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 /dts-v1/;
@@ -37,43 +47,36 @@
                 power-amber {
                         label = "bcm53xx:amber:power";
                         gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 5ghz {
                         label = "bcm53xx:white:5ghz";
                         gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 2ghz {
                         label = "bcm53xx:white:2ghz";
                         gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wps {
                         label = "bcm53xx:white:wps";
                         gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wireless {
                         label = "bcm53xx:white:wireless";
                         gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb3 {
                         label = "bcm53xx:white:usb3";
                         gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb2 {
                         label = "bcm53xx:white:usb2";
                         gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
index 8e39a84e5bf9..d266131652ad 100644
--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
@@ -4,7 +4,17 @@
  *
  * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
  *
- * Licensed under the GNU/GPL. See COPYING for details.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 /dts-v1/;
@@ -28,58 +38,61 @@
         leds {
                 compatible = "gpio-leds";
 
-                power0 {
+                power-white {
                         label = "bcm53xx:white:power";
                         gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "default-on";
                 };
 
-                power1 {
+                power-amber {
                         label = "bcm53xx:amber:power";
                         gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
+                };
+
+                wan-white {
+                        label = "bcm53xx:white:wan";
+                        gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+
+                wan-amber {
+                        label = "bcm53xx:amber:wan";
+                        gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
                 };
 
                 5ghz-1 {
                         label = "bcm53xx:white:5ghz-1";
                         gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 2ghz {
                         label = "bcm53xx:white:2ghz";
                         gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wireless {
                         label = "bcm53xx:white:wireless";
                         gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wps {
                         label = "bcm53xx:white:wps";
                         gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 5ghz-2 {
                         label = "bcm53xx:white:5ghz-2";
                         gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb3 {
                         label = "bcm53xx:white:usb3";
                         gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb2 {
                         label = "bcm53xx:white:usb2";
                         gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
@@ -105,6 +118,12 @@
                         linux,code = <KEY_RESTART>;
                         gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
                 };
+
+                brightness {
+                        label = "Backlight";
+                        linux,code = <KEY_BRIGHTNESS_ZERO>;
+                        gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
index c67bfaa0c8e8..97aa5d59a1d8 100644
--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
@@ -26,49 +26,41 @@
                 lan {
                         label = "bcm53xx:blue:lan";
                         gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wps {
                         label = "bcm53xx:blue:wps";
                         gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 2ghz {
                         label = "bcm53xx:blue:2ghz";
                         gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 5ghz {
                         label = "bcm53xx:blue:5ghz";
                         gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb3 {
                         label = "bcm53xx:blue:usb3";
                         gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb2 {
                         label = "bcm53xx:blue:usb2";
                         gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan-blue {
                         label = "bcm53xx:blue:wan";
                         gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan-amber {
                         label = "bcm53xx:amber:wan";
                         gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 power {
diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
index 64ded7643e9f..51b0641b5f79 100644
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
@@ -4,7 +4,17 @@
  *
  * Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>
  *
- * Licensed under the GNU/GPL. See COPYING for details.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+ * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+ * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
+ * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 /dts-v1/;
@@ -46,37 +56,31 @@
                 wan-white {
                         label = "bcm53xx:white:wan";
                         gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 power-amber {
                         label = "bcm53xx:amber:power";
                         gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan-amber {
                         label = "bcm53xx:amber:wan";
                         gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb3-white {
                         label = "bcm53xx:white:usb3";
                         gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 2ghz {
                         label = "bcm53xx:white:2ghz";
                         gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 5ghz {
                         label = "bcm53xx:white:5ghz";
                         gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
new file mode 100644
index 000000000000..b6750f70dffb
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017 Rafał Miłecki <rafal@milecki.pl>
+ *
+ * Licensed under the ISC license.
+ */
+
+/dts-v1/;
+
+#include "bcm47094.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+        compatible = "linksys,panamera", "brcm,bcm47094", "brcm,bcm4708";
+        model = "Linksys EA9500";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                reg = <0x00000000 0x08000000
+                       0x88000000 0x08000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
index 5cf4ab1ebe85..5f8621d00c50 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
@@ -34,37 +34,31 @@
                 lan3    {
                         label = "bcm53xx:green:lan3";
                         gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 lan4    {
                         label = "bcm53xx:green:lan4";
                         gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wan     {
                         label = "bcm53xx:green:wan";
                         gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 lan1    {
                         label = "bcm53xx:green:lan1";
                         gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 lan2    {
                         label = "bcm53xx:green:lan2";
                         gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb3    {
                         label = "bcm53xx:green:usb3";
                         gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 status  {
@@ -76,13 +70,11 @@
                 2ghz {
                         label = "bcm53xx:green:2ghz";
                         gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 5ghz {
                         label = "bcm53xx:green:5ghz";
                         gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
index 600795ee1aed..859929973158 100644
--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
@@ -34,37 +34,31 @@
                 power1 {
                         label = "bcm53xx:amber:power";
                         gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 5ghz-1 {
                         label = "bcm53xx:white:5ghz-1";
                         gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 5ghz-2 {
                         label = "bcm53xx:white:5ghz-2";
                         gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 2ghz {
                         label = "bcm53xx:white:2ghz";
                         gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb2 {
                         label = "bcm53xx:white:usb2";
                         gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
 
                 usb3 {
                         label = "bcm53xx:white:usb3";
                         gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
-                        linux,default-trigger = "default-off";
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
index 4403ae8790c2..34417dac1cd0 100644
--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
@@ -26,19 +26,16 @@
                 usb {
                         label = "bcm53xx:blue:usb";
                         gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 wps {
                         label = "bcm53xx:blue:wps";
                         gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 5ghz {
                         label = "bcm53xx:blue:5ghz";
                         gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-off";
                 };
 
                 system {
@@ -48,6 +45,15 @@
                 };
         };
 
+        pcie0_leds {
+                compatible = "gpio-leds";
+
+                2ghz {
+                        label = "bcm53xx:blue:2ghz";
+                        gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
                 #address-cells = <1>;
@@ -72,3 +78,30 @@
                 };
         };
 };
+
+&pcie0 {
+        ranges = <0x00000000 0 0 0 0 0x00100000>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+
+        bridge@0,0,0 {
+                reg = <0x0000 0 0 0 0>;
+                ranges = <0x00000000 0 0 0 0 0 0 0x00100000>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+
+                wifi@0,1,0 {
+                        reg = <0x0000 0 0 0 0>;
+                        ranges = <0x00000000 0 0 0 0x00100000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        pcie0_chipcommon: chipcommon@0 {
+                                reg = <0 0x1000>;
+
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 00de62dc0042..acee36a61004 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -18,10 +18,6 @@
 / {
         interrupt-parent = <&gic>;
 
-        chosen {
-                stdout-path = &uart0;
-        };
-
         chipcommonA {
                 compatible = "simple-bus";
                 ranges = <0x00000000 0x18000000 0x00001000>;
@@ -70,10 +66,19 @@
                         clocks = <&periph_clk>;
                 };
 
-                local-timer@20600 {
+                timer@20600 {
                         compatible = "arm,cortex-a9-twd-timer";
-                        reg = <0x20600 0x100>;
-                        interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
+                        reg = <0x20600 0x20>;
+                        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+                                                  IRQ_TYPE_EDGE_RISING)>;
+                        clocks = <&periph_clk>;
+                };
+
+                watchdog@20620 {
+                        compatible = "arm,cortex-a9-twd-wdt";
+                        reg = <0x20620 0x20>;
+                        interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+                                                  IRQ_TYPE_EDGE_RISING)>;
                         clocks = <&periph_clk>;
                 };
 
@@ -298,20 +303,6 @@
                         };
                 };
 
-                spi@29000 {
-                        reg = <0x00029000 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        spi_nor: spi-nor@0 {
-                                compatible = "jedec,spi-nor";
-                                reg = <0>;
-                                spi-max-frequency = <20000000>;
-                                linux,part-probe = "ofpart", "bcm47xxpart";
-                                status = "disabled";
-                        };
-                };
-
                 gmac0: ethernet@24000 {
                         reg = <0x24000 0x800>;
                 };
@@ -329,6 +320,16 @@
                 };
         };
 
+        i2c0: i2c@18009000 {
+                compatible = "brcm,iproc-i2c";
+                reg = <0x18009000 0x50>;
+                interrupts = <GIC_SPI 121 IRQ_TYPE_NONE>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clock-frequency = <100000>;
+                status = "disabled";
+        };
+
         lcpll0: lcpll0@1800c100 {
                 #clock-cells = <1>;
                 compatible = "brcm,nsp-lcpll0";
@@ -375,4 +376,40 @@
 
                 brcm,nand-has-wp;
         };
+
+        spi@18029200 {
+                compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
+                reg = <0x18029200 0x184>,
+                      <0x18029000 0x124>,
+                      <0x1811b408 0x004>,
+                      <0x180293a0 0x01c>;
+                reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
+                interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "spi_lr_fullness_reached",
+                                  "spi_lr_session_aborted",
+                                  "spi_lr_impatient",
+                                  "spi_lr_session_done",
+                                  "spi_lr_overhead",
+                                  "mspi_done",
+                                  "mspi_halted";
+                clocks = <&iprocmed>;
+                clock-names = "iprocmed";
+                num-cs = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                spi_nor: spi-nor@0 {
+                        compatible = "jedec,spi-nor";
+                        reg = <0>;
+                        spi-max-frequency = <20000000>;
+                        linux,part-probe = "ofpart", "bcm47xxpart";
+                        status = "disabled";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi
index 2da04d0a7348..eae623f76401 100644
--- a/arch/arm/boot/dts/bcm53573.dtsi
+++ b/arch/arm/boot/dts/bcm53573.dtsi
@@ -13,8 +13,12 @@
 / {
         interrupt-parent = <&gic>;
 
+        aliases {
+                serial0 = &uart0;
+        };
+
         chosen {
-                stdout-path = &uart0;
+                stdout-path = "serial0:115200n8";
         };
 
         cpus {
@@ -113,6 +117,10 @@
                         };
                 };
 
+                pcie0: pcie@2000 {
+                        reg = <0x00002000 0x1000>;
+                };
+
                 usb2: usb2@4000 {
                         reg = <0x4000 0x1000>;
                         ranges;
diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts
index 42855a7c1bfa..2e08c895f281 100644
--- a/arch/arm/boot/dts/bcm94708.dts
+++ b/arch/arm/boot/dts/bcm94708.dts
@@ -38,14 +38,6 @@
         model = "NorthStar SVK (BCM94708)";
         compatible = "brcm,bcm94708", "brcm,bcm4708";
 
-        aliases {
-                serial0 = &uart0;
-        };
-
-        chosen {
-                stdout-path = "serial0:115200n8";
-        };
-
         memory {
                 reg = <0x00000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/bcm94709.dts
index 95e8be65f2f1..c37616c67edc 100644
--- a/arch/arm/boot/dts/bcm94709.dts
+++ b/arch/arm/boot/dts/bcm94709.dts
@@ -38,14 +38,6 @@
         model = "NorthStar SVK (BCM94709)";
         compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708";
 
-        aliases {
-                serial0 = &uart0;
-        };
-
-        chosen {
-                stdout-path = "serial0:115200n8";
-        };
-
         memory {
                 reg = <0x00000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts
index decd86bae901..40e694bfe5ca 100644
--- a/arch/arm/boot/dts/bcm953012er.dts
+++ b/arch/arm/boot/dts/bcm953012er.dts
@@ -39,14 +39,6 @@
         model = "NorthStar Enterprise Router (BCM953012ER)";
         compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708";
 
-        aliases {
-                serial0 = &uart0;
-        };
-
-        chosen {
-                stdout-path = "serial0:115200n8";
-        };
-
         memory {
                 reg = <0x00000000 0x8000000>;
         };
diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts
new file mode 100644
index 000000000000..3076e81699cf
--- /dev/null
+++ b/arch/arm/boot/dts/bcm953012hr.dts
@@ -0,0 +1,97 @@
+/*
+ *  SPDX-License-Identifier: BSD-3-Clause
+ *
+ *  Copyright(c) 2017 Broadcom
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom nor the names of its contributors
+ *      may be used to endorse or promote products derived from this
+ *      software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+#include "bcm5301x-nand-cs0-bch4.dtsi"
+
+/ {
+        model = "NorthStar HR (BCM953012HR)";
+        compatible = "brcm,bcm953012hr", "brcm,brcm53012", "brcm,bcm4708";
+
+        aliases {
+                ethernet0 = &gmac0;
+                ethernet1 = &gmac1;
+                ethernet2 = &gmac2;
+        };
+
+        memory@80000000 {
+                reg = <0x80000000 0x10000000>;
+        };
+};
+
+&nandcs {
+        partition@0 {
+                label = "nboot";
+                reg = <0x00000000 0x00200000>;
+                read-only;
+        };
+        partition@200000 {
+                label = "nenv";
+                reg = <0x00200000 0x00400000>;
+        };
+        partition@600000 {
+                label = "nsystem";
+                reg = <0x00600000 0x00a00000>;
+        };
+        partition@1000000 {
+                label = "nrootfs";
+                reg = <0x01000000 0x07000000>;
+        };
+};
+
+&spi_nor {
+        status = "okay";
+        spi-max-frequency = <62500000>;
+        m25p,default-addr-width = <3>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        partition@0 {
+                label = "boot";
+                reg = <0x00000000 0x000d0000>;
+        };
+        partition@d000 {
+                label = "env";
+                reg = <0x000d0000 0x00030000>;
+        };
+        partition@100000 {
+                label = "system";
+                reg = <0x00100000 0x00600000>;
+        };
+        partition@700000 {
+                label = "rootfs";
+                reg = <0x00700000 0x00900000>;
+        };
+};
diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts
index ae31a5826e91..79c168e2714b 100644
--- a/arch/arm/boot/dts/bcm953012k.dts
+++ b/arch/arm/boot/dts/bcm953012k.dts
@@ -43,15 +43,69 @@
                 serial1 = &uart1;
         };
 
-        chosen {
-                stdout-path = "serial0:115200n8";
-        };
-
         memory {
                 reg = <0x80000000 0x10000000>;
         };
 };
 
+&nand {
+        nandcs@0 {
+                compatible = "brcm,nandcs";
+                reg = <0>;
+                nand-on-flash-bbt;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                nand-ecc-strength = <4>;
+                nand-ecc-step-size = <512>;
+
+                partition@0 {
+                        label = "nboot";
+                        reg = <0x00000000 0x00200000>;
+                        read-only;
+                };
+                partition@200000 {
+                        label = "nenv";
+                        reg = <0x00200000 0x00400000>;
+                };
+                partition@600000 {
+                        label = "nsystem";
+                        reg = <0x00600000 0x00a00000>;
+                };
+                partition@1000000 {
+                        label = "nrootfs";
+                        reg = <0x01000000 0x07000000>;
+                };
+        };
+};
+
+&spi_nor {
+        status = "okay";
+        spi-max-frequency = <62500000>;
+        m25p,default-addr-width = <3>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        partition@0 {
+                label = "boot";
+                reg = <0x00000000 0x000d0000>;
+        };
+        partition@d000 {
+                label = "env";
+                reg = <0x000d0000 0x00030000>;
+        };
+        partition@100000 {
+                label = "system";
+                reg = <0x00100000 0x00600000>;
+        };
+        partition@700000 {
+                label = "rootfs";
+                reg = <0x00700000 0x00900000>;
+        };
+};
+
 &uart0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts
index df05e7f568af..f5c42962c201 100644
--- a/arch/arm/boot/dts/bcm958522er.dts
+++ b/arch/arm/boot/dts/bcm958522er.dts
@@ -60,7 +60,7 @@
         };
 };
 
-/* USB 2/3 support needed to be complete */
+/* USB 3 support needed to be complete */
 
 &amac0 {
         status = "okay";
@@ -70,6 +70,10 @@
         status = "okay";
 };
 
+&ehci0 {
+        status = "okay";
+};
+
 &nand {
         nandcs@0 {
                 compatible = "brcm,nandcs";
@@ -108,6 +112,10 @@
         };
 };
 
+&ohci0 {
+        status = "okay";
+};
+
 &pcie0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts
index 4a3ab19c6281..efcb1f67bdad 100644
--- a/arch/arm/boot/dts/bcm958525er.dts
+++ b/arch/arm/boot/dts/bcm958525er.dts
@@ -60,7 +60,7 @@
         };
 };
 
-/* USB 2/3 support needed to be complete */
+/* USB 3 support needed to be complete */
 
 &amac0 {
         status = "okay";
@@ -70,6 +70,10 @@
         status = "okay";
 };
 
+&ehci0 {
+        status = "okay";
+};
+
 &nand {
         nandcs@0 {
                 compatible = "brcm,nandcs";
@@ -108,6 +112,10 @@
         };
 };
 
+&ohci0 {
+        status = "okay";
+};
+
 &pcie0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index 81f78435d8c7..b335ce02e32f 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -66,7 +66,13 @@
         status = "okay";
 };
 
+&ehci0 {
+        status = "okay";
+};
+
 &i2c0 {
+        status = "okay";
+
         temperature-sensor@4c {
                 compatible = "adi,adt7461a";
                 reg = <0x4c>;
@@ -122,6 +128,10 @@
         };
 };
 
+&ohci0 {
+        status = "okay";
+};
+
 &pcie0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index c88b8fefcb2f..16ab2d82a14b 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -60,7 +60,7 @@
         };
 };
 
-/* USB 2/3 and SLIC support needed to be complete */
+/* USB 3 and SLIC support needed to be complete */
 
 &amac0 {
         status = "okay";
@@ -74,6 +74,10 @@
         status = "okay";
 };
 
+&ehci0 {
+        status = "okay";
+};
+
 &nand {
         nandcs@0 {
                 compatible = "brcm,nandcs";
@@ -112,6 +116,10 @@
         };
 };
 
+&ohci0 {
+        status = "okay";
+};
+
 &pcie0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index d503fa0dde31..9b921c6aa8f8 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -60,7 +60,7 @@
         };
 };
 
-/* USB 2/3 and SLIC support needed to be complete */
+/* USB 3 and SLIC support needed to be complete */
 
 &amac0 {
         status = "okay";
@@ -74,6 +74,10 @@
         status = "okay";
 };
 
+&ehci0 {
+        status = "okay";
+};
+
 &nand {
         nandcs@0 {
                 compatible = "brcm,nandcs";
@@ -112,6 +116,10 @@
         };
 };
 
+&ohci0 {
+        status = "okay";
+};
+
 &pcie0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index cc0363b843c1..006b08e41a3b 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -72,6 +72,10 @@
         status = "okay";
 };
 
+&ehci0 {
+        status = "okay";
+};
+
 &nand {
         nandcs@0 {
                 compatible = "brcm,nandcs";
@@ -110,6 +114,10 @@
         };
 };
 
+&ohci0 {
+        status = "okay";
+};
+
 &pcie0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index f8d47e517e18..64740f85cf4c 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -65,6 +65,10 @@
         status = "okay";
 };
 
+&ehci0 {
+        status = "okay";
+};
+
 &nand {
         nandcs@0 {
                 compatible = "brcm,nandcs";
@@ -103,6 +107,10 @@
         };
 };
 
+&ohci0 {
+        status = "okay";
+};
+
 &pcie0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts
index 74e15a3cd9f8..bce251a68591 100644
--- a/arch/arm/boot/dts/bcm988312hr.dts
+++ b/arch/arm/boot/dts/bcm988312hr.dts
@@ -60,7 +60,7 @@
         };
 };
 
-/* USB 2/3 support needed to be complete */
+/* USB 3 support needed to be complete */
 
 &amac0 {
         status = "okay";
@@ -74,6 +74,10 @@
         status = "okay";
 };
 
+&ehci0 {
+        status = "okay";
+};
+
 &nand {
         nandcs@0 {
                 compatible = "brcm,nandcs";
@@ -112,6 +116,10 @@
         };
 };
 
+&ohci0 {
+        status = "okay";
+};
+
 &pcie0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index d15107cba765..8d244cd76c36 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -9,6 +9,7 @@
  */
 /dts-v1/;
 #include "da850.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         compatible = "ti,da850-evm", "ti,da850";
@@ -78,7 +79,10 @@
                                 DRVDD-supply = <&vbat>;
                                 DVDD-supply = <&vbat>;
                         };
-
+                        tca6416: gpio@20 {
+                                compatible = "ti,tca6416";
+                                reg = <0x20>;
+                        };
                 };
                 wdt: wdt@21000 {
                         status = "okay";
@@ -293,20 +297,27 @@
 
 &vpif {
         pinctrl-names = "default";
-        pinctrl-0 = <&vpif_capture_pins>;
+        pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
         status = "okay";
 
         /* VPIF capture port */
-        port {
-                vpif_ch0: endpoint@0 {
-                          reg = <0>;
-                          bus-width = <8>;
+        port@0 {
+                vpif_input_ch0: endpoint@0 {
+                        reg = <0>;
+                        bus-width = <8>;
                 };
 
-                vpif_ch1: endpoint@1 {
-                          reg = <1>;
-                          bus-width = <8>;
-                          data-shift = <8>;
+                vpif_input_ch1: endpoint@1 {
+                        reg = <1>;
+                        bus-width = <8>;
+                        data-shift = <8>;
+                };
+        };
+
+        /* VPIF display port */
+        port@1 {
+                vpif_output_ch0: endpoint {
+                        bus-width = <8>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts
index 112ec92064ce..512604ad8b71 100644
--- a/arch/arm/boot/dts/da850-lego-ev3.dts
+++ b/arch/arm/boot/dts/da850-lego-ev3.dts
@@ -123,6 +123,14 @@
                 pinctrl-0 = <&system_power_pin>;
         };
 
+        sound {
+                compatible = "pwm-beeper";
+                pinctrl-names = "default";
+                pinctrl-0 = <&ehrpwm0b_pins>;
+                pwms = <&ehrpwm0 1 1000000 0>;
+                amp-supply = <&amp>;
+        };
+
         /*
          * This is a 5V current limiting regulator that is shared by USB,
          * the sensor (input) ports, the motor (output) ports and the A/DC.
@@ -139,18 +147,36 @@
                 enable-active-high;
                 regulator-boot-on;
         };
+
+        /*
+         * This is a simple voltage divider on VCC5V to provide a 2.5V
+         * reference signal to the ADC.
+         */
+        adc_ref: regulator2 {
+                compatible = "regulator-fixed";
+                regulator-name = "adc ref";
+                regulator-min-microvolt = <2500000>;
+                regulator-max-microvolt = <2500000>;
+                regulator-boot-on;
+                vin-supply = <&vcc5v>;
+        };
+
+        /*
+         * This is the amplifier for the speaker.
+         */
+        amp: regulator3 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&amp_pins>;
+                compatible = "regulator-fixed";
+                regulator-name = "amp";
+                gpio = <&gpio 111 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
 };
 
 &pmx_core {
         status = "okay";
 
-        spi0_cs3_pin: pinmux_spi0_cs3_pin {
-                pinctrl-single,bits = <
-                        /* CS3 */
-                        0xc 0x01000000 0x0f000000
-                >;
-        };
-
         mmc0_cd_pin: pinmux_mmc0_cd {
                 pinctrl-single,bits = <
                         /* GP5[14] */
@@ -195,6 +221,13 @@
                         0x4c 0x00008000 0x0000f000
                 >;
         };
+
+        amp_pins: pinmux_amp_pins {
+                pinctrl-single,bits = <
+                        /* GP6[15] */
+                        0x34 0x00000008 0x0000000f
+                >;
+        };
 };
 
 &pinconf {
@@ -293,6 +326,18 @@
                         };
                 };
         };
+
+        adc: adc@3 {
+                compatible = "ti,ads7957";
+                reg = <3>;
+                #io-channel-cells = <1>;
+                spi-max-frequency = <10000000>;
+                vref-supply = <&adc_ref>;
+        };
+};
+
+&ehrpwm0 {
+        status = "okay";
 };
 
 &gpio {
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 92d633d1da68..941d455000a7 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -153,6 +153,12 @@
                                         0x10 0x00000010 0x000000f0
                                 >;
                         };
+                        spi0_cs3_pin: pinmux_spi0_cs3_pin {
+                                pinctrl-single,bits = <
+                                        /* CS3 */
+                                        0xc 0x01000000 0x0f000000
+                                >;
+                        };
                         spi1_pins: pinmux_spi1_pins {
                                 pinctrl-single,bits = <
                                         /* SIMO, SOMI, CLK */
@@ -216,8 +222,21 @@
                                         0x3c 0x11111111 0xffffffff
                                         /* VP_DIN[8..9] */
                                         0x40 0x00000011 0x000000ff
-                                        /* VP_CLKIN3, VP_CLKIN2 */
-                                        0x4c 0x00010100 0x000f0f00
+                                >;
+                        };
+                        vpif_display_pins: vpif_display_pins {
+                                pinctrl-single,bits = <
+                                        /* VP_DOUT[2..7] */
+                                        0x40 0x11111100 0xffffff00
+                                        /* VP_DOUT[10..15,0..1] */
+                                        0x44 0x11111111 0xffffffff
+                                        /*  VP_DOUT[8..9] */
+                                        0x48 0x00000011 0x000000ff
+                                        /*
+                                         * VP_CLKOUT3, VP_CLKIN3,
+                                         * VP_CLKOUT2, VP_CLKIN2
+                                         */
+                                        0x4c 0x00111100 0x00ffff00
                                 >;
                         };
                 };
@@ -345,7 +364,13 @@
                         status = "disabled";
 
                         /* VPIF capture port */
-                        port {
+                        port@0 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        /* VPIF display port */
+                        port@1 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                         };
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index 0bf55fa72dea..1865976db5f9 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -25,6 +25,12 @@
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
         };
+
+        sata_refclk: fixedclock0 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <100000000>;
+        };
 };
 
 &dm816x_pinmux {
@@ -173,3 +179,7 @@
         pinctrl-0 = <&usb1_pins>;
         mentor,multipoint = <0>;
 };
+
+&sata {
+        clocks = <&sysclk5_ck>, <&sata_refclk>;
+};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 276211e1ee53..59cbf958fcc3 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -293,6 +293,13 @@
                         phy-handle = <&phy1>;
                 };
 
+                sata: sata@4a140000 {
+                        compatible = "ti,dm816-ahci";
+                        reg = <0x4a140000 0x10000>;
+                        interrupts = <16>;
+                        ti,hwmods = "sata";
+                };
+
                 mcspi1: spi@48030000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x48030000 0x1000>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index bbfb9d5a70a9..57892f264cea 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -81,11 +81,7 @@
                         compatible = "arm,cortex-a15";
                         reg = <0>;
 
-                        operating-points = <
-                                /* kHz    uV */
-                                1000000 1060000
-                                1176000 1160000
-                                >;
+                        operating-points-v2 = <&cpu0_opp_table>;
 
                         clocks = <&dpll_mpu_ck>;
                         clock-names = "cpu";
@@ -99,6 +95,24 @@
                 };
         };
 
+        cpu0_opp_table: opp-table {
+                compatible = "operating-points-v2-ti-cpu";
+                syscon = <&scm_wkup>;
+
+                opp_nom@1000000000 {
+                        opp-hz = /bits/ 64 <1000000000>;
+                        opp-microvolt = <1060000 850000 1150000>;
+                        opp-supported-hw = <0xFF 0x01>;
+                        opp-suspend;
+                };
+
+                opp_od@1176000000 {
+                        opp-hz = /bits/ 64 <1176000000>;
+                        opp-microvolt = <1160000 885000 1160000>;
+                        opp-supported-hw = <0xFF 0x02>;
+                };
+        };
+
         /*
          * The soc node represents the soc top level view. It is used for IPs
          * that are not memory mapped in the MPU view or for the MPU itself.
@@ -1984,6 +1998,23 @@
 
 &cpu_thermal {
         polling-delay = <500>; /* milliseconds */
+        coefficients = <0 2000>;
+};
+
+&gpu_thermal {
+        coefficients = <0 2000>;
+};
+
+&core_thermal {
+        coefficients = <0 2000>;
+};
+
+&dspeve_thermal {
+        coefficients = <0 2000>;
+};
+
+&iva_thermal {
+        coefficients = <0 2000>;
 };
 
 /include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 0a78347e6615..24e6746c5b26 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -17,6 +17,7 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <1>;
+                        operating-points-v2 = <&cpu0_opp_table>;
                 };
         };
 
@@ -79,6 +80,10 @@
         };
 };
 
+&cpu0_opp_table {
+        opp-shared;
+};
+
 &dss {
         reg = <0x58000000 0x80>,
               <0x58004054 0x4>,
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 548413e23c47..c9f191ca7b9c 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -215,6 +215,8 @@
 &dsi_0 {
         vddcore-supply = <&ldo6_reg>;
         vddio-supply = <&ldo6_reg>;
+        samsung,burst-clock-frequency = <250000000>;
+        samsung,esc-clock-frequency = <20000000>;
         samsung,pll-clock-frequency = <24000000>;
         status = "okay";
 
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 9c28ef4508e0..590ee442d0ae 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -745,23 +745,23 @@
                         compatible = "operating-points-v2";
                         opp-shared;
 
-                        opp@50000000 {
+                        opp-50000000 {
                                 opp-hz = /bits/ 64 <50000000>;
                                 opp-microvolt = <800000>;
                         };
-                        opp@100000000 {
+                        opp-100000000 {
                                 opp-hz = /bits/ 64 <100000000>;
                                 opp-microvolt = <800000>;
                         };
-                        opp@134000000 {
+                        opp-134000000 {
                                 opp-hz = /bits/ 64 <134000000>;
                                 opp-microvolt = <800000>;
                         };
-                        opp@200000000 {
+                        opp-200000000 {
                                 opp-hz = /bits/ 64 <200000000>;
                                 opp-microvolt = <825000>;
                         };
-                        opp@400000000 {
+                        opp-400000000 {
                                 opp-hz = /bits/ 64 <400000000>;
                                 opp-microvolt = <875000>;
                         };
@@ -835,23 +835,23 @@
                         compatible = "operating-points-v2";
                         opp-shared;
 
-                        opp@50000000 {
+                        opp-50000000 {
                                 opp-hz = /bits/ 64 <50000000>;
                                 opp-microvolt = <900000>;
                         };
-                        opp@80000000 {
+                        opp-80000000 {
                                 opp-hz = /bits/ 64 <80000000>;
                                 opp-microvolt = <900000>;
                         };
-                        opp@100000000 {
+                        opp-100000000 {
                                 opp-hz = /bits/ 64 <100000000>;
                                 opp-microvolt = <1000000>;
                         };
-                        opp@134000000 {
+                        opp-134000000 {
                                 opp-hz = /bits/ 64 <134000000>;
                                 opp-microvolt = <1000000>;
                         };
-                        opp@200000000 {
+                        opp-200000000 {
                                 opp-hz = /bits/ 64 <200000000>;
                                 opp-microvolt = <1000000>;
                         };
@@ -861,19 +861,19 @@
                         compatible = "operating-points-v2";
                         opp-shared;
 
-                        opp@50000000 {
+                        opp-50000000 {
                                 opp-hz = /bits/ 64 <50000000>;
                         };
-                        opp@80000000 {
+                        opp-80000000 {
                                 opp-hz = /bits/ 64 <80000000>;
                         };
-                        opp@100000000 {
+                        opp-100000000 {
                                 opp-hz = /bits/ 64 <100000000>;
                         };
-                        opp@200000000 {
+                        opp-200000000 {
                                 opp-hz = /bits/ 64 <200000000>;
                         };
-                        opp@400000000 {
+                        opp-400000000 {
                                 opp-hz = /bits/ 64 <400000000>;
                         };
                 };
@@ -882,19 +882,19 @@
                         compatible = "operating-points-v2";
                         opp-shared;
 
-                        opp@50000000 {
+                        opp-50000000 {
                                 opp-hz = /bits/ 64 <50000000>;
                         };
-                        opp@80000000 {
+                        opp-80000000 {
                                 opp-hz = /bits/ 64 <80000000>;
                         };
-                        opp@100000000 {
+                        opp-100000000 {
                                 opp-hz = /bits/ 64 <100000000>;
                         };
-                        opp@200000000 {
+                        opp-200000000 {
                                 opp-hz = /bits/ 64 <200000000>;
                         };
-                        opp@300000000 {
+                        opp-300000000 {
                                 opp-hz = /bits/ 64 <300000000>;
                         };
                 };
@@ -903,13 +903,13 @@
                         compatible = "operating-points-v2";
                         opp-shared;
 
-                        opp@50000000 {
+                        opp-50000000 {
                                 opp-hz = /bits/ 64 <50000000>;
                         };
-                        opp@80000000 {
+                        opp-80000000 {
                                 opp-hz = /bits/ 64 <80000000>;
                         };
-                        opp@100000000 {
+                        opp-100000000 {
                                 opp-hz = /bits/ 64 <100000000>;
                         };
                 };
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 84fcdff140ae..497a9470c888 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -283,15 +283,6 @@
                 };
         };
 
-        watchdog: watchdog@10060000 {
-                compatible = "samsung,s3c2410-wdt";
-                reg = <0x10060000 0x100>;
-                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_WDT>;
-                clock-names = "watchdog";
-                status = "disabled";
-        };
-
         rtc: rtc@10070000 {
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x10070000 0x100>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index a2c6a13fe67b..312650e2450f 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -328,7 +328,3 @@
 &tmu {
         status = "okay";
 };
-
-&watchdog {
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 0ca1b4d355f2..1743ca850070 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -197,6 +197,8 @@
 &dsi_0 {
         vddcore-supply = <&vusb_reg>;
         vddio-supply = <&vmipi_reg>;
+        samsung,burst-clock-frequency = <500000000>;
+        samsung,esc-clock-frequency = <20000000>;
         samsung,pll-clock-frequency = <24000000>;
         status = "okay";
 
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index f9408188f97f..768fb075b1fd 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -119,6 +119,14 @@
                 };
         };
 
+        watchdog: watchdog@10060000 {
+                compatible = "samsung,s3c6410-wdt";
+                reg = <0x10060000 0x100>;
+                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clock CLK_WDT>;
+                clock-names = "watchdog";
+        };
+
         clock: clock-controller@10030000 {
                 compatible = "samsung,exynos4210-clock";
                 reg = <0x10030000 0x20000>;
@@ -335,15 +343,15 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@134000000 {
+                opp-134000000 {
                         opp-hz = /bits/ 64 <134000000>;
                         opp-microvolt = <1025000>;
                 };
-                opp@267000000 {
+                opp-267000000 {
                         opp-hz = /bits/ 64 <267000000>;
                         opp-microvolt = <1050000>;
                 };
-                opp@400000000 {
+                opp-400000000 {
                         opp-hz = /bits/ 64 <400000000>;
                         opp-microvolt = <1150000>;
                 };
@@ -353,13 +361,13 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@134000000 {
+                opp-134000000 {
                         opp-hz = /bits/ 64 <134000000>;
                 };
-                opp@160000000 {
+                opp-160000000 {
                         opp-hz = /bits/ 64 <160000000>;
                 };
-                opp@200000000 {
+                opp-200000000 {
                         opp-hz = /bits/ 64 <200000000>;
                 };
         };
@@ -368,10 +376,10 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@5000000 {
+                opp-5000000 {
                         opp-hz = /bits/ 64 <5000000>;
                 };
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                 };
         };
@@ -380,10 +388,10 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@10000000 {
+                opp-10000000 {
                         opp-hz = /bits/ 64 <10000000>;
                 };
-                opp@134000000 {
+                opp-134000000 {
                         opp-hz = /bits/ 64 <134000000>;
                 };
         };
@@ -392,13 +400,13 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                 };
-                opp@134000000 {
+                opp-134000000 {
                         opp-hz = /bits/ 64 <134000000>;
                 };
-                opp@160000000 {
+                opp-160000000 {
                         opp-hz = /bits/ 64 <160000000>;
                 };
         };
@@ -407,13 +415,13 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                 };
-                opp@160000000 {
+                opp-160000000 {
                         opp-hz = /bits/ 64 <160000000>;
                 };
-                opp@200000000 {
+                opp-200000000 {
                         opp-hz = /bits/ 64 <200000000>;
                 };
         };
diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
index a36cd36a26b8..4cd62487bb16 100644
--- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
+++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
@@ -495,7 +495,3 @@
         vtmu-supply = <&ldo16_reg>;
         status = "okay";
 };
-
-&watchdog {
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 78f118cb73d4..0f1ff792fe44 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -555,7 +555,3 @@
         vtmu-supply = <&ldo10_reg>;
         status = "okay";
 };
-
-&watchdog {
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index a1ab6f94bb64..7a83e2df18a6 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -541,7 +541,3 @@
 &serial_3 {
         status = "okay";
 };
-
-&watchdog {
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/exynos4412-prime.dtsi b/arch/arm/boot/dts/exynos4412-prime.dtsi
index e75bc170c89c..a67bd953d754 100644
--- a/arch/arm/boot/dts/exynos4412-prime.dtsi
+++ b/arch/arm/boot/dts/exynos4412-prime.dtsi
@@ -20,12 +20,12 @@
 };
 
 &cpu0_opp_table {
-        opp@1600000000 {
+        opp-1600000000 {
                 opp-hz = /bits/ 64 <1600000000>;
                 opp-microvolt = <1350000>;
                 clock-latency-ns = <200000>;
         };
-        opp@1704000000 {
+        opp-1704000000 {
                 opp-hz = /bits/ 64 <1704000000>;
                 opp-microvolt = <1350000>;
                 clock-latency-ns = <200000>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 41ecd6d465a7..82221a00444d 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -385,6 +385,8 @@
 &dsi_0 {
         vddcore-supply = <&ldo8_reg>;
         vddio-supply = <&ldo10_reg>;
+        samsung,burst-clock-frequency = <500000000>;
+        samsung,esc-clock-frequency = <20000000>;
         samsung,pll-clock-frequency = <24000000>;
         status = "okay";
 
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 235bbb69ad7c..7ff03a7e8fb9 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -76,73 +76,73 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@200000000 {
+                opp-200000000 {
                         opp-hz = /bits/ 64 <200000000>;
                         opp-microvolt = <900000>;
                         clock-latency-ns = <200000>;
                 };
-                opp@300000000 {
+                opp-300000000 {
                         opp-hz = /bits/ 64 <300000000>;
                         opp-microvolt = <900000>;
                         clock-latency-ns = <200000>;
                 };
-                opp@400000000 {
+                opp-400000000 {
                         opp-hz = /bits/ 64 <400000000>;
                         opp-microvolt = <925000>;
                         clock-latency-ns = <200000>;
                 };
-                opp@500000000 {
+                opp-500000000 {
                         opp-hz = /bits/ 64 <500000000>;
                         opp-microvolt = <950000>;
                         clock-latency-ns = <200000>;
                 };
-                opp@600000000 {
+                opp-600000000 {
                         opp-hz = /bits/ 64 <600000000>;
                         opp-microvolt = <975000>;
                         clock-latency-ns = <200000>;
                 };
-                opp@700000000 {
+                opp-700000000 {
                         opp-hz = /bits/ 64 <700000000>;
                         opp-microvolt = <987500>;
                         clock-latency-ns = <200000>;
                 };
-                opp@800000000 {
+                opp-800000000 {
                         opp-hz = /bits/ 64 <800000000>;
                         opp-microvolt = <1000000>;
                         clock-latency-ns = <200000>;
                         opp-suspend;
                 };
-                opp@900000000 {
+                opp-900000000 {
                         opp-hz = /bits/ 64 <900000000>;
                         opp-microvolt = <1037500>;
                         clock-latency-ns = <200000>;
                 };
-                opp@1000000000 {
+                opp-1000000000 {
                         opp-hz = /bits/ 64 <1000000000>;
                         opp-microvolt = <1087500>;
                         clock-latency-ns = <200000>;
                 };
-                opp@1100000000 {
+                opp-1100000000 {
                         opp-hz = /bits/ 64 <1100000000>;
                         opp-microvolt = <1137500>;
                         clock-latency-ns = <200000>;
                 };
-                opp@1200000000 {
+                opp-1200000000 {
                         opp-hz = /bits/ 64 <1200000000>;
                         opp-microvolt = <1187500>;
                         clock-latency-ns = <200000>;
                 };
-                opp@1300000000 {
+                opp-1300000000 {
                         opp-hz = /bits/ 64 <1300000000>;
                         opp-microvolt = <1250000>;
                         clock-latency-ns = <200000>;
                 };
-                opp@1400000000 {
+                opp-1400000000 {
                         opp-hz = /bits/ 64 <1400000000>;
                         opp-microvolt = <1287500>;
                         clock-latency-ns = <200000>;
                 };
-                cpu0_opp_1500: opp@1500000000 {
+                cpu0_opp_1500: opp-1500000000 {
                         opp-hz = /bits/ 64 <1500000000>;
                         opp-microvolt = <1350000>;
                         clock-latency-ns = <200000>;
@@ -215,6 +215,15 @@
                 };
         };
 
+        watchdog: watchdog@10060000 {
+                compatible = "samsung,exynos5250-wdt";
+                reg = <0x10060000 0x100>;
+                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clock CLK_WDT>;
+                clock-names = "watchdog";
+                samsung,syscon-phandle = <&pmu_system_controller>;
+        };
+
         adc: adc@126C0000 {
                 compatible = "samsung,exynos-adc-v1";
                 reg = <0x126C0000 0x100>;
@@ -433,23 +442,23 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                         opp-microvolt = <900000>;
                 };
-                opp@134000000 {
+                opp-134000000 {
                         opp-hz = /bits/ 64 <134000000>;
                         opp-microvolt = <900000>;
                 };
-                opp@160000000 {
+                opp-160000000 {
                         opp-hz = /bits/ 64 <160000000>;
                         opp-microvolt = <900000>;
                 };
-                opp@267000000 {
+                opp-267000000 {
                         opp-hz = /bits/ 64 <267000000>;
                         opp-microvolt = <950000>;
                 };
-                opp@400000000 {
+                opp-400000000 {
                         opp-hz = /bits/ 64 <400000000>;
                         opp-microvolt = <1050000>;
                 };
@@ -459,16 +468,16 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                 };
-                opp@134000000 {
+                opp-134000000 {
                         opp-hz = /bits/ 64 <134000000>;
                 };
-                opp@160000000 {
+                opp-160000000 {
                         opp-hz = /bits/ 64 <160000000>;
                 };
-                opp@267000000 {
+                opp-267000000 {
                         opp-hz = /bits/ 64 <267000000>;
                 };
         };
@@ -525,19 +534,19 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                         opp-microvolt = <900000>;
                 };
-                opp@134000000 {
+                opp-134000000 {
                         opp-hz = /bits/ 64 <134000000>;
                         opp-microvolt = <925000>;
                 };
-                opp@160000000 {
+                opp-160000000 {
                         opp-hz = /bits/ 64 <160000000>;
                         opp-microvolt = <950000>;
                 };
-                opp@200000000 {
+                opp-200000000 {
                         opp-hz = /bits/ 64 <200000000>;
                         opp-microvolt = <1000000>;
                 };
@@ -547,10 +556,10 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@160000000 {
+                opp-160000000 {
                         opp-hz = /bits/ 64 <160000000>;
                 };
-                opp@200000000 {
+                opp-200000000 {
                         opp-hz = /bits/ 64 <200000000>;
                 };
         };
@@ -559,10 +568,10 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                 };
-                opp@134000000 {
+                opp-134000000 {
                         opp-hz = /bits/ 64 <134000000>;
                 };
         };
@@ -571,10 +580,10 @@
                 compatible = "operating-points-v2";
                 opp-shared;
 
-                opp@50000000 {
+                opp-50000000 {
                         opp-hz = /bits/ 64 <50000000>;
                 };
-                opp@100000000 {
+                opp-100000000 {
                         opp-hz = /bits/ 64 <100000000>;
                 };
         };
diff --git a/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi
new file mode 100644
index 000000000000..c8771c660550
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Device tree sources for Exynos5420 TMU sensor configuration
+ *
+ * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
+ * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <dt-bindings/thermal/thermal_exynos.h>
+
+#thermal-sensor-cells = <0>;
+samsung,tmu_gain = <8>;
+samsung,tmu_reference_voltage = <16>;
+samsung,tmu_noise_cancel_mode = <4>;
+samsung,tmu_efuse_value = <55>;
+samsung,tmu_min_efuse_value = <0>;
+samsung,tmu_max_efuse_value = <100>;
+samsung,tmu_first_point_trim = <25>;
+samsung,tmu_second_point_trim = <85>;
+samsung,tmu_default_temp_offset = <50>;
+samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 7dc9dc82afd8..0db0bcf8da36 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -49,62 +49,62 @@
                 cluster_a15_opp_table: opp_table0 {
                         compatible = "operating-points-v2";
                         opp-shared;
-                        opp@1800000000 {
+                        opp-1800000000 {
                                 opp-hz = /bits/ 64 <1800000000>;
                                 opp-microvolt = <1250000>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@1700000000 {
+                        opp-1700000000 {
                                 opp-hz = /bits/ 64 <1700000000>;
                                 opp-microvolt = <1212500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@1600000000 {
+                        opp-1600000000 {
                                 opp-hz = /bits/ 64 <1600000000>;
                                 opp-microvolt = <1175000>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@1500000000 {
+                        opp-1500000000 {
                                 opp-hz = /bits/ 64 <1500000000>;
                                 opp-microvolt = <1137500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@1400000000 {
+                        opp-1400000000 {
                                 opp-hz = /bits/ 64 <1400000000>;
                                 opp-microvolt = <1112500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@1300000000 {
+                        opp-1300000000 {
                                 opp-hz = /bits/ 64 <1300000000>;
                                 opp-microvolt = <1062500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@1200000000 {
+                        opp-1200000000 {
                                 opp-hz = /bits/ 64 <1200000000>;
                                 opp-microvolt = <1037500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@1100000000 {
+                        opp-1100000000 {
                                 opp-hz = /bits/ 64 <1100000000>;
                                 opp-microvolt = <1012500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@1000000000 {
+                        opp-1000000000 {
                                 opp-hz = /bits/ 64 <1000000000>;
                                 opp-microvolt = < 987500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@900000000 {
+                        opp-900000000 {
                                 opp-hz = /bits/ 64 <900000000>;
                                 opp-microvolt = < 962500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@800000000 {
+                        opp-800000000 {
                                 opp-hz = /bits/ 64 <800000000>;
                                 opp-microvolt = < 937500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@700000000 {
+                        opp-700000000 {
                                 opp-hz = /bits/ 64 <700000000>;
                                 opp-microvolt = < 912500>;
                                 clock-latency-ns = <140000>;
@@ -114,42 +114,42 @@
                 cluster_a7_opp_table: opp_table1 {
                         compatible = "operating-points-v2";
                         opp-shared;
-                        opp@1300000000 {
+                        opp-1300000000 {
                                 opp-hz = /bits/ 64 <1300000000>;
                                 opp-microvolt = <1275000>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@1200000000 {
+                        opp-1200000000 {
                                 opp-hz = /bits/ 64 <1200000000>;
                                 opp-microvolt = <1212500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@1100000000 {
+                        opp-1100000000 {
                                 opp-hz = /bits/ 64 <1100000000>;
                                 opp-microvolt = <1162500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@1000000000 {
+                        opp-1000000000 {
                                 opp-hz = /bits/ 64 <1000000000>;
                                 opp-microvolt = <1112500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@900000000 {
+                        opp-900000000 {
                                 opp-hz = /bits/ 64 <900000000>;
                                 opp-microvolt = <1062500>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@800000000 {
+                        opp-800000000 {
                                 opp-hz = /bits/ 64 <800000000>;
                                 opp-microvolt = <1025000>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@700000000 {
+                        opp-700000000 {
                                 opp-hz = /bits/ 64 <700000000>;
                                 opp-microvolt = <975000>;
                                 clock-latency-ns = <140000>;
                         };
-                        opp@600000000 {
+                        opp-600000000 {
                                 opp-hz = /bits/ 64 <600000000>;
                                 opp-microvolt = <937500>;
                                 clock-latency-ns = <140000>;
@@ -699,7 +699,7 @@
                         interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&clock CLK_TMU>;
                         clock-names = "tmu_apbif";
-                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                        #include "exynos5420-tmu-sensor-conf.dtsi"
                 };
 
                 tmu_cpu1: tmu@10064000 {
@@ -708,7 +708,7 @@
                         interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&clock CLK_TMU>;
                         clock-names = "tmu_apbif";
-                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                        #include "exynos5420-tmu-sensor-conf.dtsi"
                 };
 
                 tmu_cpu2: tmu@10068000 {
@@ -717,7 +717,7 @@
                         interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
-                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                        #include "exynos5420-tmu-sensor-conf.dtsi"
                 };
 
                 tmu_cpu3: tmu@1006c000 {
@@ -726,7 +726,7 @@
                         interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
-                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                        #include "exynos5420-tmu-sensor-conf.dtsi"
                 };
 
                 tmu_gpu: tmu@100a0000 {
@@ -735,7 +735,7 @@
                         interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
-                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                        #include "exynos5420-tmu-sensor-conf.dtsi"
                 };
 
                 sysmmu_g2dr: sysmmu@0x10A60000 {
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 77d35bb92950..a4ea018464fc 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -189,7 +189,7 @@
         };
 
         watchdog@110000 {
-                compatible = "samsung,s3c2410-wdt";
+                compatible = "samsung,s3c6410-wdt";
                 reg = <0x110000 0x1000>;
                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_B_125>;
@@ -290,11 +290,22 @@
                 clock-names = "usbhost";
         };
 
+        pcie_phy0: pcie-phy@270000 {
+                #phy-cells = <0>;
+                compatible = "samsung,exynos5440-pcie-phy";
+                reg = <0x270000 0x1000>, <0x271000 0x40>;
+        };
+
+        pcie_phy1: pcie-phy@272000 {
+                #phy-cells = <0>;
+                compatible = "samsung,exynos5440-pcie-phy";
+                reg = <0x272000 0x1000>, <0x271040 0x40>;
+        };
+
         pcie_0: pcie@290000 {
                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-                reg = <0x290000 0x1000
-                        0x270000 0x1000
-                        0x271000 0x40>;
+                reg = <0x290000 0x1000>, <0x40000000 0x1000>;
+                reg-names = "elbi", "config";
                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -303,8 +314,8 @@
                 #address-cells = <3>;
                 #size-cells = <2>;
                 device_type = "pci";
-                ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
-                          0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
+                phys = <&pcie_phy0>;
+                ranges = <0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
                           0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
                 #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 0 0>;
@@ -315,9 +326,8 @@
 
         pcie_1: pcie@2a0000 {
                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-                reg = <0x2a0000 0x1000
-                        0x272000 0x1000
-                        0x271040 0x40>;
+                reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
+                reg-names = "elbi", "config";
                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -326,8 +336,8 @@
                 #address-cells = <3>;
                 #size-cells = <2>;
                 device_type = "pci";
-                ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
-                          0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
+                phys = <&pcie_phy1>;
+                ranges = <0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
                           0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
                 #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 0 0>;
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 8213016803e5..9ddb6bacac5a 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -24,60 +24,60 @@
 };
 
 &cluster_a15_opp_table {
-        opp@1700000000 {
+        opp-1700000000 {
                 opp-microvolt = <1250000>;
         };
-        opp@1600000000 {
+        opp-1600000000 {
                 opp-microvolt = <1250000>;
         };
-        opp@1500000000 {
+        opp-1500000000 {
                 opp-microvolt = <1100000>;
         };
-        opp@1400000000 {
+        opp-1400000000 {
                 opp-microvolt = <1100000>;
         };
-        opp@1300000000 {
+        opp-1300000000 {
                 opp-microvolt = <1100000>;
         };
-        opp@1200000000 {
+        opp-1200000000 {
                 opp-microvolt = <1000000>;
         };
-        opp@1100000000 {
+        opp-1100000000 {
                 opp-microvolt = <1000000>;
         };
-        opp@1000000000 {
+        opp-1000000000 {
                 opp-microvolt = <1000000>;
         };
-        opp@900000000 {
+        opp-900000000 {
                 opp-microvolt = <1000000>;
         };
-        opp@800000000 {
+        opp-800000000 {
                 opp-microvolt = <900000>;
         };
-        opp@700000000 {
+        opp-700000000 {
                 opp-microvolt = <900000>;
         };
-        opp@600000000 {
+        opp-600000000 {
                 opp-hz = /bits/ 64 <600000000>;
                 opp-microvolt = <900000>;
                 clock-latency-ns = <140000>;
         };
-        opp@500000000 {
+        opp-500000000 {
                 opp-hz = /bits/ 64 <500000000>;
                 opp-microvolt = <900000>;
                 clock-latency-ns = <140000>;
         };
-        opp@400000000 {
+        opp-400000000 {
                 opp-hz = /bits/ 64 <400000000>;
                 opp-microvolt = <900000>;
                 clock-latency-ns = <140000>;
         };
-        opp@300000000 {
+        opp-300000000 {
                 opp-hz = /bits/ 64 <300000000>;
                 opp-microvolt = <900000>;
                 clock-latency-ns = <140000>;
         };
-        opp@200000000 {
+        opp-200000000 {
                 opp-hz = /bits/ 64 <200000000>;
                 opp-microvolt = <900000>;
                 clock-latency-ns = <140000>;
@@ -85,46 +85,46 @@
 };
 
 &cluster_a7_opp_table {
-        opp@1300000000 {
+        opp-1300000000 {
                 opp-microvolt = <1250000>;
         };
-        opp@1200000000 {
+        opp-1200000000 {
                 opp-microvolt = <1250000>;
         };
-        opp@1100000000 {
+        opp-1100000000 {
                 opp-microvolt = <1250000>;
         };
-        opp@1000000000 {
+        opp-1000000000 {
                 opp-microvolt = <1100000>;
         };
-        opp@900000000 {
+        opp-900000000 {
                 opp-microvolt = <1100000>;
         };
-        opp@800000000 {
+        opp-800000000 {
                 opp-microvolt = <1100000>;
         };
-        opp@700000000 {
+        opp-700000000 {
                 opp-microvolt = <1000000>;
         };
-        opp@600000000 {
+        opp-600000000 {
                 opp-microvolt = <1000000>;
         };
-        opp@500000000 {
+        opp-500000000 {
                 opp-hz = /bits/ 64 <500000000>;
                 opp-microvolt = <1000000>;
                 clock-latency-ns = <140000>;
         };
-        opp@400000000 {
+        opp-400000000 {
                 opp-hz = /bits/ 64 <400000000>;
                 opp-microvolt = <1000000>;
                 clock-latency-ns = <140000>;
         };
-        opp@300000000 {
+        opp-300000000 {
                 opp-hz = /bits/ 64 <300000000>;
                 opp-microvolt = <900000>;
                 clock-latency-ns = <140000>;
         };
-        opp@200000000 {
+        opp-200000000 {
                 opp-hz = /bits/ 64 <200000000>;
                 opp-microvolt = <900000>;
                 clock-latency-ns = <140000>;
diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts
new file mode 100644
index 000000000000..7668ba52158e
--- /dev/null
+++ b/arch/arm/boot/dts/gemini-nas4220b.dts
@@ -0,0 +1,102 @@
+/*
+ * Device Tree file for the Gemini-based Raidsonic NAS IB-4220-B
+ */
+
+/dts-v1/;
+
+#include "gemini.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Raidsonic NAS IB-4220-B";
+        compatible = "raidsonic,ib-4220-b", "cortina,gemini";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory { /* 128 MB */
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,19200n8";
+                stdout-path = &uart0;
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@29 {
+                        debounce_interval = <50>;
+                        wakeup-source;
+                        linux,code = <KEY_SETUP>;
+                        label = "Backup button";
+                        gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+                };
+                button@31 {
+                        debounce_interval = <50>;
+                        wakeup-source;
+                        linux,code = <KEY_RESTART>;
+                        label = "Softreset button";
+                        gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led@28 {
+                        label = "nas4220b:orange:hdd";
+                        gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+                led@30 {
+                        label = "nas4220b:green:os";
+                        gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        soc {
+                flash@30000000 {
+                        status = "okay";
+                        /* 16MB of flash */
+                        reg = <0x30000000 0x01000000>;
+
+                        partition@0 {
+                                label = "RedBoot";
+                                reg = <0x00000000 0x00020000>;
+                                read-only;
+                        };
+                        partition@20000 {
+                                label = "Kernel";
+                                reg = <0x00020000 0x00300000>;
+                        };
+                        partition@320000 {
+                                label = "Ramdisk";
+                                reg = <0x00320000 0x00600000>;
+                        };
+                        partition@920000 {
+                                label = "Application";
+                                reg = <0x00920000 0x00600000>;
+                        };
+                        partition@f20000 {
+                                label = "VCTL";
+                                reg = <0x00f20000 0x00020000>;
+                                read-only;
+                        };
+                        partition@f40000 {
+                                label = "CurConf";
+                                reg = <0x00f40000 0x000a0000>;
+                                read-only;
+                        };
+                        partition@fe0000 {
+                                label = "FIS directory";
+                                reg = <0x00fe0000 0x00020000>;
+                                read-only;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts
new file mode 100644
index 000000000000..7b920bfbda32
--- /dev/null
+++ b/arch/arm/boot/dts/gemini-rut1xx.dts
@@ -0,0 +1,65 @@
+/*
+ * Device Tree file for Teltonika RUT1xx
+ */
+
+/dts-v1/;
+
+#include "gemini.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Teltonika RUT1xx";
+        compatible = "teltonika,rut1xx", "cortina,gemini";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory { /* 128 MB */
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@28 {
+                        debounce_interval = <50>;
+                        wakeup-source;
+                        linux,code = <KEY_SETUP>;
+                        label = "Reset to defaults";
+                        gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led@7 {
+                        /* FIXME: add the LED color */
+                        label = "rut1xx::gsm";
+                        gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+                led@31 {
+                        /* FIXME: add the LED color */
+                        label = "rut1xx::power";
+                        gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        soc {
+                flash@30000000 {
+                        status = "okay";
+                        /* 8MB of flash */
+                        reg = <0x30000000 0x00800000>;
+                        /* TODO: add flash partitions here */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts
new file mode 100644
index 000000000000..46309e79cc7b
--- /dev/null
+++ b/arch/arm/boot/dts/gemini-sq201.dts
@@ -0,0 +1,118 @@
+/*
+ * Device Tree file for ITian Square One SQ201 NAS
+ */
+
+/dts-v1/;
+
+#include "gemini.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "ITian Square One SQ201";
+        compatible = "itian,sq201", "cortina,gemini";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory { /* 128 MB */
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@18 {
+                        debounce_interval = <50>;
+                        wakeup-source;
+                        linux,code = <KEY_SETUP>;
+                        label = "factory reset";
+                        gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led@20 {
+                        label = "sq201:green:info";
+                        gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led@31 {
+                        label = "sq201:green:usb";
+                        gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                        linux,default-trigger = "usb-host";
+                };
+        };
+
+        soc {
+                flash@30000000 {
+                        status = "okay";
+                        /* 16MB of flash */
+                        reg = <0x30000000 0x01000000>;
+
+                        partition@0 {
+                                label = "RedBoot";
+                                reg = <0x00000000 0x00120000>;
+                                read-only;
+                        };
+                        partition@120000 {
+                                label = "Kernel";
+                                reg = <0x00120000 0x00200000>;
+                        };
+                        partition@320000 {
+                                label = "Ramdisk";
+                                reg = <0x00320000 0x00600000>;
+                        };
+                        partition@920000 {
+                                label = "Application";
+                                reg = <0x00920000 0x00600000>;
+                        };
+                        partition@f20000 {
+                                label = "VCTL";
+                                reg = <0x00f20000 0x00020000>;
+                                read-only;
+                        };
+                        partition@f40000 {
+                                label = "CurConf";
+                                reg = <0x00f40000 0x000a0000>;
+                                read-only;
+                        };
+                        partition@fe0000 {
+                                label = "FIS directory";
+                                reg = <0x00fe0000 0x00020000>;
+                                read-only;
+                        };
+                };
+
+                pci@50000000 {
+                        status = "okay";
+                        interrupt-map-mask = <0xf800 0 0 7>;
+                        interrupt-map =
+                                <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
+                                <0x4800 0 0 2 &pci_intc 1>,
+                                <0x4800 0 0 3 &pci_intc 2>,
+                                <0x4800 0 0 4 &pci_intc 3>,
+                                <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
+                                <0x5000 0 0 2 &pci_intc 2>,
+                                <0x5000 0 0 3 &pci_intc 3>,
+                                <0x5000 0 0 4 &pci_intc 0>,
+                                <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
+                                <0x5800 0 0 2 &pci_intc 3>,
+                                <0x5800 0 0 3 &pci_intc 0>,
+                                <0x5800 0 0 4 &pci_intc 1>,
+                                <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
+                                <0x6000 0 0 2 &pci_intc 0>,
+                                <0x6000 0 0 3 &pci_intc 1>,
+                                <0x6000 0 0 4 &pci_intc 2>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts
new file mode 100644
index 000000000000..63b756e3bf5a
--- /dev/null
+++ b/arch/arm/boot/dts/gemini-wbd111.dts
@@ -0,0 +1,102 @@
+/*
+ * Device Tree file for Wiliboard WBD-111
+ */
+
+/dts-v1/;
+
+#include "gemini.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Wiliboard WBD-111";
+        compatible = "wiliboard,wbd111", "cortina,gemini";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory { /* 128 MB */
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@5 {
+                        debounce_interval = <50>;
+                        wakeup-source;
+                        linux,code = <KEY_SETUP>;
+                        label = "reset";
+                        gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                led@1 {
+                        label = "wbd111:red:L3";
+                        gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+                led@2 {
+                        label = "wbd111:green:L4";
+                        gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+                led@3 {
+                        label = "wbd111:red:L4";
+                        gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+                led@5 {
+                        label = "wbd111:green:L3";
+                        gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        soc {
+                flash@30000000 {
+                        status = "okay";
+                        /* 8MB of flash */
+                        reg = <0x30000000 0x00800000>;
+
+                        partition@0 {
+                                label = "RedBoot";
+                                reg = <0x00000000 0x00020000>;
+                                read-only;
+                        };
+                        partition@20000 {
+                                label = "kernel";
+                                reg = <0x00020000 0x00100000>;
+                        };
+                        partition@120000 {
+                                label = "rootfs";
+                                reg = <0x00120000 0x006a0000>;
+                        };
+                        partition@7c0000 {
+                                label = "VCTL";
+                                reg = <0x007c0000 0x00010000>;
+                                read-only;
+                        };
+                        partition@7d0000 {
+                                label = "cfg";
+                                reg = <0x007d0000 0x00010000>;
+                                read-only;
+                        };
+                        partition@7e0000 {
+                                label = "FIS";
+                                reg = <0x007e0000 0x00010000>;
+                                read-only;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts
new file mode 100644
index 000000000000..9747f5a47807
--- /dev/null
+++ b/arch/arm/boot/dts/gemini-wbd222.dts
@@ -0,0 +1,102 @@
+/*
+ * Device Tree file for Wiliboard WBD-222
+ */
+
+/dts-v1/;
+
+#include "gemini.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Wiliboard WBD-222";
+        compatible = "wiliboard,wbd222", "cortina,gemini";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory { /* 128 MB */
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@5 {
+                        debounce_interval = <50>;
+                        wakeup-source;
+                        linux,code = <KEY_SETUP>;
+                        label = "reset";
+                        gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                led@1 {
+                        label = "wbd111:red:L3";
+                        gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+                led@2 {
+                        label = "wbd111:green:L4";
+                        gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+                led@3 {
+                        label = "wbd111:red:L4";
+                        gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+                led@5 {
+                        label = "wbd111:green:L3";
+                        gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        soc {
+                flash@30000000 {
+                        status = "okay";
+                        /* 8MB of flash */
+                        reg = <0x30000000 0x00800000>;
+
+                        partition@0 {
+                                label = "RedBoot";
+                                reg = <0x00000000 0x00020000>;
+                                read-only;
+                        };
+                        partition@20000 {
+                                label = "kernel";
+                                reg = <0x00020000 0x00100000>;
+                        };
+                        partition@120000 {
+                                label = "rootfs";
+                                reg = <0x00120000 0x006a0000>;
+                        };
+                        partition@7c0000 {
+                                label = "VCTL";
+                                reg = <0x007c0000 0x00010000>;
+                                read-only;
+                        };
+                        partition@7d0000 {
+                                label = "cfg";
+                                reg = <0x007d0000 0x00010000>;
+                                read-only;
+                        };
+                        partition@7e0000 {
+                                label = "FIS";
+                                reg = <0x007e0000 0x00010000>;
+                                read-only;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi
new file mode 100644
index 000000000000..b8d011bdcc76
--- /dev/null
+++ b/arch/arm/boot/dts/gemini.dtsi
@@ -0,0 +1,156 @@
+/*
+ * Device Tree file for Cortina systems Gemini SoC
+ */
+
+/include/ "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                compatible = "simple-bus";
+                interrupt-parent = <&intcon>;
+
+                flash@30000000 {
+                        compatible = "cortina,gemini-flash", "cfi-flash";
+                        syscon = <&syscon>;
+                        bank-width = <2>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                };
+
+                syscon: syscon@40000000 {
+                        compatible = "cortina,gemini-syscon", "syscon", "simple-mfd";
+                        reg = <0x40000000 0x1000>;
+
+                        syscon-reboot {
+                                compatible = "syscon-reboot";
+                                regmap = <&syscon>;
+                                /* GLOBAL_RESET register */
+                                offset = <0x0c>;
+                                /* RESET_GLOBAL | RESET_CPU1 */
+                                mask = <0xC0000000>;
+                        };
+                };
+
+                watchdog@41000000 {
+                        compatible = "cortina,gemini-watchdog";
+                        reg = <0x41000000 0x1000>;
+                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                uart0: serial@42000000 {
+                        compatible = "ns16550a";
+                        reg = <0x42000000 0x100>;
+                        clock-frequency = <48000000>;
+                        interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                };
+
+                timer@43000000 {
+                        compatible = "cortina,gemini-timer";
+                        reg = <0x43000000 0x1000>;
+                        interrupt-parent = <&intcon>;
+                        interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
+                                     <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
+                                     <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
+                        syscon = <&syscon>;
+                };
+
+                rtc@45000000 {
+                        compatible = "cortina,gemini-rtc";
+                        reg = <0x45000000 0x100>;
+                        interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                intcon: interrupt-controller@48000000 {
+                        compatible = "faraday,ftintc010";
+                        reg = <0x48000000 0x1000>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                power-controller@4b000000 {
+                        compatible = "cortina,gemini-power-controller";
+                        reg = <0x4b000000 0x100>;
+                        interrupts = <26 IRQ_TYPE_EDGE_RISING>;
+                };
+
+                gpio0: gpio@4d000000 {
+                        compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
+                        reg = <0x4d000000 0x100>;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio1: gpio@4e000000 {
+                        compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
+                        reg = <0x4e000000 0x100>;
+                        interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio2: gpio@4f000000 {
+                        compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
+                        reg = <0x4f000000 0x100>;
+                        interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                pci@50000000 {
+                        compatible = "cortina,gemini-pci", "faraday,ftpci100";
+                        /*
+                         * The first 256 bytes in the IO range is actually used
+                         * to configure the host bridge.
+                         */
+                        reg = <0x50000000 0x100>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        status = "disabled";
+
+                        bus-range = <0x00 0xff>;
+                        /* PCI ranges mappings */
+                        ranges =
+                        /* 1MiB I/O space 0x50000000-0x500fffff */
+                        <0x01000000 0 0          0x50000000 0 0x00100000>,
+                        /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
+                        <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
+
+                        /* DMA ranges */
+                        dma-ranges =
+                        /* 128MiB at 0x00000000-0x07ffffff */
+                        <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
+                        /* 64MiB at 0x00000000-0x03ffffff */
+                        <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
+                        /* 64MiB at 0x00000000-0x03ffffff */
+                        <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
+
+                        /*
+                         * This PCI host bridge variant has a cascaded interrupt
+                         * controller embedded in the host bridge.
+                         */
+                        pci_intc: interrupt-controller {
+                                interrupt-parent = <&intcon>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-controller;
+                                #address-cells = <0>;
+                                #interrupt-cells = <1>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 9300711f1ea3..db39bd6b8e00 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -179,8 +179,6 @@
 };
 
 &usbotg {
-        phy_type = "utmi";
-        dr_mode = "otg";
         external-vbus-divider;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 70292101ba03..d921dd2ed676 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -309,8 +309,6 @@
 };
 
 &usbotg {
-        phy_type = "utmi";
-        dr_mode = "otg";
         external-vbus-divider;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index f840f03ad171..6c63dca1b9b8 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -17,8 +17,6 @@
  * <mux_reg conf_reg input_reg mux_mode input_val>
  */
 
-#define MX25_PAD_TDO__TDO                       0x000 0x3e8 0x000 0x00 0x000
-
 #define MX25_PAD_A10__A10                       0x008 0x000 0x000 0x00 0x000
 #define MX25_PAD_A10__GPIO_4_0                  0x008 0x000 0x000 0x05 0x000
 
@@ -68,7 +66,6 @@
 
 #define MX25_PAD_A22__A22                       0x030 0x000 0x000 0x00 0x000
 #define MX25_PAD_A22__GPIO_2_8                  0x030 0x000 0x000 0x05 0x000
-#define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x07 0x000
 #define MX25_PAD_A22__SIM2_VEN1                 0x030 0x000 0x000 0x06 0x000
 #define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x07 0x000
 
@@ -542,6 +539,8 @@
 #define MX25_PAD_RTCK__OWIRE                    0x1ec 0x3e4 0x000 0x01 0x000
 #define MX25_PAD_RTCK__GPIO_3_14                0x1ec 0x3e4 0x000 0x05 0x000
 
+#define MX25_PAD_TDO__TDO                       0x000 0x3e8 0x000 0x00 0x000
+
 #define MX25_PAD_DE_B__DE_B                     0x1f0 0x3ec 0x000 0x00 0x000
 #define MX25_PAD_DE_B__GPIO_2_20                0x1f0 0x3ec 0x000 0x05 0x000
 
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index e0ba55016a04..0cdf333336cd 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -93,6 +93,11 @@
                         reg = <0x43f00000 0x100000>;
                         ranges;
 
+                        aips1: bridge@43f00000 {
+                                compatible = "fsl,imx25-aips";
+                                reg = <0x43f00000 0x4000>;
+                        };
+
                         i2c1: i2c@43f80000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -342,6 +347,11 @@
                         reg = <0x53f00000 0x100000>;
                         ranges;
 
+                        aips2: bridge@53f00000 {
+                                compatible = "fsl,imx25-aips";
+                                reg = <0x53f00000 0x4000>;
+                        };
+
                         clks: ccm@53f80000 {
                                 compatible = "fsl,imx25-ccm";
                                 reg = <0x53f80000 0x4000>;
@@ -544,6 +554,8 @@
                                 clock-names = "ipg", "ahb", "per";
                                 fsl,usbmisc = <&usbmisc 0>;
                                 fsl,usbphy = <&usbphy0>;
+                                phy_type = "utmi";
+                                dr_mode = "otg";
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
new file mode 100644
index 000000000000..bd3fd470f9c3
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2015-2017 I2SE GmbH <info@i2se.com>
+ * Copyright (C) 2016 Michael Heimpold <mhei@heimpold.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx28.dtsi"
+
+/ {
+        model = "I2SE Duckbill 2 485";
+        compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
+
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_8bit_pins_a
+                                        &mmc0_cd_cfg &mmc0_sck_cfg>;
+                                bus-width = <8>;
+                                vmmc-supply = <&reg_3p3v>;
+                                status = "okay";
+                                non-removable;
+                        };
+
+                        ssp2: ssp@80014000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc2_4bit_pins_b
+                                        &mmc2_cd_cfg &mmc2_sck_cfg_b>;
+                                bus-width = <4>;
+                                vmmc-supply = <&reg_3p3v>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_LCD_D17__GPIO_1_17    /* Revision detection */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                mac0_phy_reset_pin: mac0-phy-reset@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_GPMI_ALE__GPIO_0_26    /* PHY Reset */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                mac0_phy_int_pin: mac0-phy-int@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_GPMI_D07__GPIO_0_7    /* PHY Interrupt */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                led_pins: leds@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_SAIF0_MCLK__GPIO_3_20
+                                                MX28_PAD_SAIF0_LRCLK__GPIO_3_21
+                                                MX28_PAD_I2C0_SCL__GPIO_3_24
+                                                MX28_PAD_I2C0_SDA__GPIO_3_25
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_2pins_a>;
+                                status = "okay";
+                        };
+
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        status = "okay";
+                        dr_mode = "peripheral";
+                };
+
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
+                        phy-supply = <&reg_3p3v>;
+                        phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+                        phy-reset-duration = <25>;
+                        phy-handle = <&ethphy>;
+                        status = "okay";
+
+                        mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ethphy: ethernet-phy@0 {
+                                        compatible = "ethernet-phy-ieee802.3-c22";
+                                        reg = <0>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&mac0_phy_int_pin>;
+                                        interrupt-parent = <&gpio0>;
+                                        interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+                                        max-speed = <100>;
+                                };
+                        };
+                };
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+
+                status-red {
+                        label = "duckbill:red:status";
+                        gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                status-green {
+                        label = "duckbill:green:status";
+                        gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                rs485-red {
+                        label = "duckbill:red:rs485";
+                        gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+                };
+
+                rs485-green {
+                        label = "duckbill:green:rs485";
+                        gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
new file mode 100644
index 000000000000..4450047885eb
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2015-2017 I2SE GmbH <info@i2se.com>
+ * Copyright (C) 2016 Michael Heimpold <mhei@heimpold.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx28.dtsi"
+
+/ {
+        model = "I2SE Duckbill 2 EnOcean";
+        compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
+
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_8bit_pins_a
+                                        &mmc0_cd_cfg &mmc0_sck_cfg>;
+                                bus-width = <8>;
+                                vmmc-supply = <&reg_3p3v>;
+                                status = "okay";
+                                non-removable;
+                        };
+
+                        ssp2: ssp@80014000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc2_4bit_pins_b
+                                        &mmc2_cd_cfg &mmc2_sck_cfg_b>;
+                                bus-width = <4>;
+                                vmmc-supply = <&reg_3p3v>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_LCD_D17__GPIO_1_17    /* Revision detection */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                mac0_phy_reset_pin: mac0-phy-reset@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_GPMI_ALE__GPIO_0_26    /* PHY Reset */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                mac0_phy_int_pin: mac0-phy-int@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_GPMI_D07__GPIO_0_7    /* PHY Interrupt */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                led_pins: leds@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_SAIF0_MCLK__GPIO_3_20
+                                                MX28_PAD_SAIF0_LRCLK__GPIO_3_21
+                                                MX28_PAD_AUART0_CTS__GPIO_3_2
+                                                MX28_PAD_I2C0_SCL__GPIO_3_24
+                                                MX28_PAD_I2C0_SDA__GPIO_3_25
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                enocean_button: enocean-button@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_AUART0_RTS__GPIO_3_3
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_2pins_a>;
+                                status = "okay";
+                        };
+
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        status = "okay";
+                        dr_mode = "peripheral";
+                };
+
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
+                        phy-supply = <&reg_3p3v>;
+                        phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+                        phy-reset-duration = <25>;
+                        phy-handle = <&ethphy>;
+                        status = "okay";
+
+                        mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ethphy: ethernet-phy@0 {
+                                        compatible = "ethernet-phy-ieee802.3-c22";
+                                        reg = <0>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&mac0_phy_int_pin>;
+                                        interrupt-parent = <&gpio0>;
+                                        interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+                                        max-speed = <100>;
+                                };
+                        };
+                };
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+
+                status-red {
+                        label = "duckbill:red:status";
+                        gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                status-green {
+                        label = "duckbill:green:status";
+                        gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                enocean-blue {
+                        label = "duckbill:blue:enocean";
+                        gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+                };
+
+                enocean-red {
+                        label = "duckbill:red:enocean";
+                        gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+                };
+
+                enocean-green {
+                        label = "duckbill:green:enocean";
+                        gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&enocean_button>;
+
+                enocean {
+                        label = "EnOcean";
+                        linux,code = <KEY_NEW>;
+                        gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
new file mode 100644
index 000000000000..927732efca98
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2015-2017 I2SE GmbH <info@i2se.com>
+ * Copyright (C) 2016 Michael Heimpold <mhei@heimpold.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx28.dtsi"
+
+/ {
+        model = "I2SE Duckbill 2 SPI";
+        compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28";
+
+        aliases {
+                ethernet1 = &qca7000;
+        };
+
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_8bit_pins_a
+                                        &mmc0_cd_cfg &mmc0_sck_cfg>;
+                                bus-width = <8>;
+                                vmmc-supply = <&reg_3p3v>;
+                                status = "okay";
+                                non-removable;
+                        };
+
+                        ssp2: ssp@80014000 {
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi2_pins_a>;
+                                status = "okay";
+
+                                qca7000: ethernet@0 {
+                                        reg = <0>;
+                                        compatible = "qca,qca7000";
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&qca7000_pins>;
+                                        interrupt-parent = <&gpio3>;
+                                        interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+                                        spi-cpha;
+                                        spi-cpol;
+                                        spi-max-frequency = <8000000>;
+                                };
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_LCD_D17__GPIO_1_17    /* Revision detection */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                mac0_phy_reset_pin: mac0-phy-reset@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_GPMI_ALE__GPIO_0_26    /* PHY Reset */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                mac0_phy_int_pin: mac0-phy-int@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_GPMI_D07__GPIO_0_7    /* PHY Interrupt */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                led_pins: led@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_SAIF0_MCLK__GPIO_3_20
+                                                MX28_PAD_SAIF0_LRCLK__GPIO_3_21
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                qca7000_pins: qca7000@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_AUART0_RTS__GPIO_3_3    /* Interrupt */
+                                                MX28_PAD_LCD_D13__GPIO_1_13      /* QCA7K reset */
+                                                MX28_PAD_LCD_D14__GPIO_1_14      /* GPIO 0 */
+                                                MX28_PAD_LCD_D15__GPIO_1_15      /* GPIO 1 */
+                                                MX28_PAD_LCD_D18__GPIO_1_18      /* GPIO 2 */
+                                                MX28_PAD_LCD_D21__GPIO_1_21      /* GPIO 3 */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        status = "okay";
+                        dr_mode = "peripheral";
+                };
+
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
+                        phy-supply = <&reg_3p3v>;
+                        phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+                        phy-reset-duration = <25>;
+                        phy-handle = <&ethphy>;
+                        status = "okay";
+
+                        mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ethphy: ethernet-phy@0 {
+                                        compatible = "ethernet-phy-ieee802.3-c22";
+                                        reg = <0>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&mac0_phy_int_pin>;
+                                        interrupt-parent = <&gpio0>;
+                                        interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+                                        max-speed = <100>;
+                                };
+                        };
+                };
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+
+                status-red {
+                        label = "duckbill:red:status";
+                        gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                status-green {
+                        label = "duckbill:green:status";
+                        gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts
new file mode 100644
index 000000000000..7fa3d759505c
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill-2.dts
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2015-2017 I2SE GmbH <info@i2se.com>
+ * Copyright (C) 2016 Michael Heimpold <mhei@heimpold.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx28.dtsi"
+
+/ {
+        model = "I2SE Duckbill 2";
+        compatible = "i2se,duckbill-2", "fsl,imx28";
+
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_8bit_pins_a
+                                        &mmc0_cd_cfg &mmc0_sck_cfg>;
+                                bus-width = <8>;
+                                vmmc-supply = <&reg_3p3v>;
+                                status = "okay";
+                                non-removable;
+                        };
+
+                        ssp2: ssp@80014000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc2_4bit_pins_b
+                                        &mmc2_cd_cfg &mmc2_sck_cfg_b>;
+                                bus-width = <4>;
+                                vmmc-supply = <&reg_3p3v>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_LCD_D17__GPIO_1_17    /* Revision detection */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                mac0_phy_reset_pin: mac0-phy-reset@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_GPMI_ALE__GPIO_0_26    /* PHY Reset */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                mac0_phy_int_pin: mac0-phy-int@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_GPMI_D07__GPIO_0_7    /* PHY Interrupt */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                led_pins: leds@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_SAIF0_MCLK__GPIO_3_20
+                                                MX28_PAD_SAIF0_LRCLK__GPIO_3_21
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_2pins_a>;
+                                status = "okay";
+                        };
+
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        status = "okay";
+                        dr_mode = "peripheral";
+                };
+
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
+                        phy-supply = <&reg_3p3v>;
+                        phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+                        phy-reset-duration = <25>;
+                        phy-handle = <&ethphy>;
+                        status = "okay";
+
+                        mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ethphy: ethernet-phy@0 {
+                                        compatible = "ethernet-phy-ieee802.3-c22";
+                                        reg = <0>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&mac0_phy_int_pin>;
+                                        interrupt-parent = <&gpio0>;
+                                        interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+                                        max-speed = <100>;
+                                };
+                        };
+                };
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+
+                status-red {
+                        label = "duckbill:red:status";
+                        gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                status-green {
+                        label = "duckbill:green:status";
+                        gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
index ce1a7effba37..3e4385d4ed78 100644
--- a/arch/arm/boot/dts/imx28-duckbill.dts
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2013 Michael Heimpold <mhei@heimpold.de>
+ * Copyright (C) 2013-2014,2016 Michael Heimpold <mhei@heimpold.de>
+ * Copyright (C) 2015-2017 I2SE GmbH <info@i2se.com>
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -10,6 +11,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "imx28.dtsi"
 
 / {
@@ -32,6 +34,13 @@
                                 status = "okay";
                         };
 
+                        ssp2: ssp@80014000 {
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi2_pins_a>;
+                                status = "okay";
+                        };
+
                         pinctrl@80018000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
@@ -39,14 +48,24 @@
                                 hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
-                                                MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */
+                                                MX28_PAD_LCD_D17__GPIO_1_17    /* Revision detection */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
+                                mac0_phy_reset_pin: mac0-phy-reset@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_SSP0_DATA7__GPIO_2_7    /* PHY Reset */
                                         >;
                                         fsl,drive-strength = <MXS_DRIVE_4mA>;
                                         fsl,voltage = <MXS_VOLTAGE_HIGH>;
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
-                                led_pins_a: led_gpio@0 {
+                                led_pins: leds@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_AUART1_RX__GPIO_3_4
@@ -60,6 +79,22 @@
                 };
 
                 apbx@80040000 {
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_2pins_a>;
+                                status = "okay";
+                        };
+
                         duart: serial@80074000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&duart_pins_a>;
@@ -75,47 +110,43 @@
         ahb@80080000 {
                 usb0: usb@80080000 {
                         status = "okay";
+                        dr_mode = "peripheral";
                 };
 
                 mac0: ethernet@800f0000 {
                         phy-mode = "rmii";
                         pinctrl-names = "default";
-                        pinctrl-0 = <&mac0_pins_a>;
+                        pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>;
                         phy-supply = <&reg_3p3v>;
                         phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
-                        phy-reset-duration = <100>;
+                        phy-reset-duration = <25>;
                         status = "okay";
                 };
         };
 
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                reg_3p3v: regulator@0 {
-                        compatible = "regulator-fixed";
-                        reg = <0>;
-                        regulator-name = "3P3V";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        regulator-always-on;
-                };
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
         };
 
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
-                pinctrl-0 = <&led_pins_a>;
+                pinctrl-0 = <&led_pins>;
 
-                status {
-                        label = "duckbill:green:status";
-                        gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
-                };
-
-                failure {
+                status-red {
                         label = "duckbill:red:status";
                         gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                status-green {
+                        label = "duckbill:green:status";
+                        gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 2df63bee6f4e..bb5329479c62 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -57,7 +57,7 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc2_4bit_pins_a
                                              &mmc2_cd_cfg
-                                             &mmc2_sck_cfg>;
+                                             &mmc2_sck_cfg_a>;
                                 bus-width = <4>;
                                 vmmc-supply = <&reg_vddio_sd1>;
                                 status = "okay";
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 148fcf4d3b98..2f4ebe0318d3 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -590,6 +590,22 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
+                                mmc2_4bit_pins_b: mmc2-4bit@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_SSP2_SCK__SSP2_SCK
+                                                MX28_PAD_SSP2_MOSI__SSP2_CMD
+                                                MX28_PAD_SSP2_MISO__SSP2_D0
+                                                MX28_PAD_SSP2_SS0__SSP2_D3
+                                                MX28_PAD_SSP2_SS1__SSP2_D1
+                                                MX28_PAD_SSP2_SS2__SSP2_D2
+                                                MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_8mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_ENABLE>;
+                                };
+
                                 mmc2_cd_cfg: mmc2-cd-cfg {
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
@@ -597,7 +613,8 @@
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
-                                mmc2_sck_cfg: mmc2-sck-cfg {
+                                mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_SSP0_DATA7__SSP2_SCK
                                         >;
@@ -605,6 +622,15 @@
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
+                                mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_SSP2_SCK__SSP2_SCK
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_12mA>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
                                 i2c0_pins_a: i2c0@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index ceae909e2201..2a98afcd8a4e 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -109,7 +109,7 @@
                                 ranges;
 
                                 esdhc1: esdhc@50004000 {
-                                        compatible = "fsl,imx50-esdhc";
+                                        compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
                                         reg = <0x50004000 0x4000>;
                                         interrupts = <1>;
                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
@@ -121,7 +121,7 @@
                                 };
 
                                 esdhc2: esdhc@50008000 {
-                                        compatible = "fsl,imx50-esdhc";
+                                        compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
                                         reg = <0x50008000 0x4000>;
                                         interrupts = <2>;
                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
@@ -170,7 +170,7 @@
                                 };
 
                                 esdhc3: esdhc@50020000 {
-                                        compatible = "fsl,imx50-esdhc";
+                                        compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
                                         reg = <0x50020000 0x4000>;
                                         interrupts = <3>;
                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
@@ -182,7 +182,7 @@
                                 };
 
                                 esdhc4: esdhc@50024000 {
-                                        compatible = "fsl,imx50-esdhc";
+                                        compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
                                         reg = <0x50024000 0x4000>;
                                         interrupts = <4>;
                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index f4c158cce908..d3d662e37677 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -88,8 +88,8 @@
                         };
 
                         ldo7_reg: ldo7 {
-                                regulator-min-microvolt = <1200000>;
-                                regulator-max-microvolt = <3600000>;
+                                regulator-min-microvolt = <2750000>;
+                                regulator-max-microvolt = <2750000>;
                         };
 
                         ldo8_reg: ldo8 {
diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts
index 479ca4c9e384..de2215832372 100644
--- a/arch/arm/boot/dts/imx53-qsrb.dts
+++ b/arch/arm/boot/dts/imx53-qsrb.dts
@@ -128,8 +128,8 @@
 
                         vdac_reg: vdac {
                                 regulator-name = "VDAC";
-                                regulator-min-microvolt = <2500000>;
-                                regulator-max-microvolt = <2775000>;
+                                regulator-min-microvolt = <2750000>;
+                                regulator-max-microvolt = <2750000>;
                         };
 
                         vgen1_reg: vgen1 {
diff --git a/arch/arm/boot/dts/imx6dl-gw5903.dts b/arch/arm/boot/dts/imx6dl-gw5903.dts
new file mode 100644
index 000000000000..103261ea9334
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw5903.dts
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5903.dtsi"
+
+/ {
+        model = "Gateworks Ventana i.MX6 Duallite/Solo GW5903";
+        compatible = "gw,imx6dl-gw5903", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-gw5904.dts b/arch/arm/boot/dts/imx6dl-gw5904.dts
new file mode 100644
index 000000000000..9c6d3cd3d6a7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw5904.dts
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5904.dtsi"
+
+/ {
+        model = "Gateworks Ventana i.MX6 DualLite/Solo GW5904";
+        compatible = "gw,imx6dl-gw5904", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
index 116bebb5e435..404a93d9596b 100644
--- a/arch/arm/boot/dts/imx6q-b450v3.dts
+++ b/arch/arm/boot/dts/imx6q-b450v3.dts
@@ -104,4 +104,11 @@
                 output-low;
                 line-name = "PCA9539-P05";
         };
+
+        P07 {
+                gpio-hog;
+                gpios = <7 0>;
+                output-low;
+                line-name = "PCA9539-P07";
+        };
 };
diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts
index 33f5c436c09f..7f9f176901d4 100644
--- a/arch/arm/boot/dts/imx6q-b650v3.dts
+++ b/arch/arm/boot/dts/imx6q-b650v3.dts
@@ -97,6 +97,13 @@
                 output-low;
                 line-name = "PCA9539-P05";
         };
+
+        P07 {
+                gpio-hog;
+                gpios = <7 0>;
+                output-low;
+                line-name = "PCA9539-P07";
+        };
 };
 
 &usbphy1 {
diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
index d78514c92349..2c1e98e0cf7b 100644
--- a/arch/arm/boot/dts/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -72,6 +72,14 @@
                 fsl,data-mapping = "spwg";
                 fsl,data-width = <24>;
                 status = "okay";
+
+                port@4 {
+                        reg = <4>;
+
+                        lvds0_out: endpoint {
+                                remote-endpoint = <&stdp4028_in>;
+                        };
+                };
         };
 };
 
@@ -142,3 +150,65 @@
                 reg = <0x4a>;
         };
 };
+
+&mux2_i2c2 {
+        clock-frequency = <100000>;
+
+        stdp2690@72 {
+                compatible = "megachips,stdp2690-ge-b850v3-fw";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x72>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                stdp2690_in: endpoint {
+                                        remote-endpoint = <&stdp4028_out>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                stdp2690_out: endpoint {
+                                        /* Connector for external display */
+                                };
+                        };
+                };
+        };
+
+        stdp4028@73 {
+                compatible = "megachips,stdp4028-ge-b850v3-fw";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x73>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                stdp4028_in: endpoint {
+                                        remote-endpoint = <&lvds0_out>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                stdp4028_out: endpoint {
+                                        remote-endpoint = <&stdp2690_in>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index 36d6bb39593a..c90b26f00e24 100644
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -102,7 +102,7 @@
 
         m25_eeprom: m25p80@0 {
                 compatible = "atmel,at25";
-                spi-max-frequency = <20000000>;
+                spi-max-frequency = <10000000>;
                 size = <0x8000>;
                 pagesize = <64>;
                 reg = <0>;
@@ -183,20 +183,6 @@
                                 interrupt-parent = <&gpio2>;
                                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 
-                                P06 {
-                                        gpio-hog;
-                                        gpios = <6 0>;
-                                        output-low;
-                                        line-name = "PCA9539-P06";
-                                };
-
-                                P07 {
-                                        gpio-hog;
-                                        gpios = <7 0>;
-                                        output-low;
-                                        line-name = "PCA9539-P07";
-                                };
-
                                 P10 {
                                         gpio-hog;
                                         gpios = <8 0>;
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index d8a5789a4bc8..66cac5328b86 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -43,6 +43,7 @@
 
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
 #include "imx6q.dtsi"
 
 / {
@@ -90,6 +91,34 @@
                 enable-active-high;
         };
 
+        sound-analog {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "On-board analog audio";
+                simple-audio-card,widgets =
+                        "Headphone", "Headphone Jack",
+                        "Line", "Line Out",
+                        "Microphone", "Mic Jack",
+                        "Line", "Line In";
+                simple-audio-card,routing =
+                        "Headphone Jack", "RHPOUT",
+                        "Headphone Jack", "LHPOUT",
+                        "MICIN", "Mic Bias",
+                        "Mic Bias", "Mic Jack";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,bitclock-master = <&sound_master>;
+                simple-audio-card,frame-master = <&sound_master>;
+                simple-audio-card,bitclock-inversion;
+
+                sound_master: simple-audio-card,cpu {
+                        sound-dai = <&ssi2>;
+                        system-clock-frequency = <2822400>;
+                };
+
+                simple-audio-card,codec {
+                        sound-dai = <&wm8731>;
+                };
+        };
+
         sound-spdif {
                 compatible = "fsl,imx-audio-spdif";
                 model = "imx-spdif";
@@ -99,6 +128,36 @@
         };
 };
 
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+
+        ssi2 {
+                fsl,audmux-port = <1>;
+                fsl,port-config = <
+                        (IMX_AUDMUX_V2_PTCR_RCLKDIR |
+                        IMX_AUDMUX_V2_PTCR_RCSEL(3 | 0x8) |
+                        IMX_AUDMUX_V2_PTCR_TCLKDIR |
+                        IMX_AUDMUX_V2_PTCR_TCSEL(3))
+                        IMX_AUDMUX_V2_PDCR_RXDSEL(3)
+                >;
+        };
+
+        audmux4 {
+                fsl,audmux-port = <3>;
+                fsl,port-config = <
+                        (IMX_AUDMUX_V2_PTCR_TFSDIR |
+                        IMX_AUDMUX_V2_PTCR_TFSEL(1) |
+                        IMX_AUDMUX_V2_PTCR_RCLKDIR |
+                        IMX_AUDMUX_V2_PTCR_RCSEL(1 | 0x8) |
+                        IMX_AUDMUX_V2_PTCR_TCLKDIR |
+                        IMX_AUDMUX_V2_PTCR_TCSEL(1))
+                        IMX_AUDMUX_V2_PDCR_RXDSEL(1)
+                >;
+        };
+};
+
 &cpu0 {
         /*
          * Although the imx6q fuse indicates that 1.2GHz operation is possible,
@@ -160,9 +219,25 @@
                 reg = <0x50>;
                 pagesize = <16>;
         };
+
+        wm8731: codec@1a {
+                #sound-dai-cells = <0>;
+                compatible = "wlf,wm8731";
+                reg = <0x1a>;
+        };
 };
 
 &iomuxc {
+        pinctrl_audmux: audmuxgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD2_CMD__AUD4_RXC   0x17059
+                        MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x17059
+                        MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x17059
+                        MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x17059
+                        MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059
+                >;
+        };
+
         pinctrl_ecspi1: ecspi1grp {
                 fsl,pins = <
                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
@@ -279,6 +354,14 @@
         status = "okay";
 };
 
+&ssi2 {
+        assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>,
+                        <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
+        assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
+        assigned-clock-rates = <0>, <786432000>;
+        status = "okay";
+};
+
 &uart4 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart4>;
diff --git a/arch/arm/boot/dts/imx6q-gw5903.dts b/arch/arm/boot/dts/imx6q-gw5903.dts
new file mode 100644
index 000000000000..a182e4cb0e6e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5903.dts
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5903.dtsi"
+
+/ {
+        model = "Gateworks Ventana i.MX6 Dual/Quad GW5903";
+        compatible = "gw,imx6q-gw5903", "gw,ventana", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw5904.dts b/arch/arm/boot/dts/imx6q-gw5904.dts
new file mode 100644
index 000000000000..ca1e2ae3341e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5904.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5904.dtsi"
+
+/ {
+        model = "Gateworks Ventana i.MX6 Dual/Quad GW5904";
+        compatible = "gw,imx6q-gw5904", "gw,ventana", "fsl,imx6q";
+};
+
+&sata {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
new file mode 100644
index 000000000000..49b60ca20e6d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+        model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 10.1 Kit";
+        compatible = "engicam,imx6-icore", "fsl,imx6q";
+};
+
+&ldb {
+        status = "okay";
+
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <24>;
+                status = "okay";
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing0 {
+                                clock-frequency = <60000000>;
+                                hactive = <1280>;
+                                vactive = <800>;
+                                hback-porch = <40>;
+                                hfront-porch = <40>;
+                                vback-porch = <10>;
+                                vfront-porch = <3>;
+                                hsync-len = <80>;
+                                vsync-len = <10>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts b/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
new file mode 100644
index 000000000000..9e230f56c5fb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+        model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 12 Kit";
+        compatible = "engicam,imx6-icore", "fsl,imx6q";
+};
+
+&ldb {
+        status = "okay";
+
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing0 {
+                                clock-frequency = <46800000>;
+                                hactive = <1280>;
+                                vactive = <480>;
+                                hback-porch = <353>;
+                                hfront-porch = <47>;
+                                vback-porch = <39>;
+                                vfront-porch = <4>;
+                                hsync-len = <8>;
+                                vsync-len = <2>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/imx6q-icore.dts
index 59eb7adc2472..5613dd9dc469 100644
--- a/arch/arm/boot/dts/imx6q-icore.dts
+++ b/arch/arm/boot/dts/imx6q-icore.dts
@@ -57,3 +57,37 @@
 &can2 {
         status = "okay";
 };
+
+&i2c1 {
+        max11801: touchscreen@48 {
+                compatible = "maxim,max11801";
+                reg = <0x48>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+        };
+};
+
+&ldb {
+        status = "okay";
+
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing0 {
+                                clock-frequency = <60000000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <30>;
+                                hfront-porch = <30>;
+                                vback-porch = <5>;
+                                vfront-porch = <5>;
+                                hsync-len = <64>;
+                                vsync-len = <20>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts
index 69bdd82ce21f..d900ad6ec5f8 100644
--- a/arch/arm/boot/dts/imx6q-utilite-pro.dts
+++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts
@@ -101,9 +101,11 @@
 
         hdmi-connector {
                 compatible = "hdmi-connector";
-
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_hpd>;
                 type = "a";
                 ddc-i2c-bus = <&i2c_dvi_ddc>;
+                hpd-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 
                 port {
                         hdmi_connector_in: endpoint {
@@ -209,6 +211,12 @@
                 >;
         };
 
+        pinctrl_hpd: hpdgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+                >;
+        };
+
         pinctrl_i2c1: i2c1grp {
                 fsl,pins = <
                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/imx6q-zii-rdu2.dts
new file mode 100644
index 000000000000..b2d346640fd7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-zii-rdu2.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2016-2017 Zodiac Inflight Innovations
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <imx6q.dtsi>
+#include <imx6qdl-zii-rdu2.dtsi>
+
+/ {
+        model = "ZII RDU2 Board";
+        compatible = "zii,imx6q-zii-rdu2", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
new file mode 100644
index 000000000000..444425153fc7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
@@ -0,0 +1,654 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        chosen {
+                stdout-path = &uart2;
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 5000000>;
+                brightness-levels = <
+                        0  1  2  3  4  5  6  7  8  9
+                        10 11 12 13 14 15 16 17 18 19
+                        20 21 22 23 24 25 26 27 28 29
+                        30 31 32 33 34 35 36 37 38 39
+                        40 41 42 43 44 45 46 47 48 49
+                        50 51 52 53 54 55 56 57 58 59
+                        60 61 62 63 64 65 66 67 68 69
+                        70 71 72 73 74 75 76 77 78 79
+                        80 81 82 83 84 85 86 87 88 89
+                        90 91 92 93 94 95 96 97 98 99
+                        100
+                        >;
+                default-brightness-level = <100>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
+
+                led0: user1 {
+                        label = "user1";
+                        gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
+                        default-state = "off";
+                };
+        };
+
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+
+        reg_5p0v: regulator-5p0v {
+                compatible = "regulator-fixed";
+                regulator-name = "5P0V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        reg_2p5v: regulator-2p5v {
+                compatible = "regulator-fixed";
+                regulator-name = "2P5V";
+                regulator-min-microvolt = <2500000>;
+                regulator-max-microvolt = <2500000>;
+                regulator-always-on;
+        };
+
+        reg_usb_h1_vbus: regulator-usb-h1-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb_h1_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio3 30 0>;
+                enable-active-high;
+        };
+
+        reg_usb_otg_vbus: regulator-usb-otg-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb_otg_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_12p0: regulator-12p0v {
+                compatible = "regulator-fixed";
+                regulator-name = "12P0V";
+                regulator-min-microvolt = <12000000>;
+                regulator-max-microvolt = <12000000>;
+                gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        sound {
+                compatible = "fsl,imx-audio-tlv320";
+                model = "imx-tlv320";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&tlv320aic3105>;
+                /* routing of sink, source */
+                audio-routing =
+                        /* TLV320 LINE1L pin <-> Mic Jack connector */
+                        "LINE1L", "Mic Jack",
+                        /* board Headphone Jack <-> HPOUT */
+                        "Headphone Jack", "HPLOUT",
+                        "Headphone Jack", "HPROUT",
+                        "Mic Jack", "Mic Bias";
+                mux-int-port = <1>;
+                mux-ext-port = <6>;
+        };
+};
+
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+
+&clks {
+        assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                          <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+        assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+                                 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii-id";
+        status = "okay";
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+
+        pca9555: gpio@23 {
+                compatible = "nxp,pca9555";
+                reg = <0x23>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        eeprom1: eeprom@50 {
+                compatible = "atmel,24c02";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+
+        eeprom2: eeprom@51 {
+                compatible = "atmel,24c02";
+                reg = <0x51>;
+                pagesize = <16>;
+        };
+
+        eeprom3: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+                pagesize = <16>;
+        };
+
+        eeprom4: eeprom@53 {
+                compatible = "atmel,24c02";
+                reg = <0x53>;
+                pagesize = <16>;
+        };
+
+        dts1672: rtc@68 {
+                compatible = "dallas,ds1672";
+                reg = <0x68>;
+        };
+};
+
+&i2c2 {
+        clock-frequency = <400000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+
+        ltc3676: pmic@3c {
+                compatible = "lltc,ltc3676";
+                reg = <0x3c>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+
+                regulators {
+                        /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */
+                        reg_1p8v: sw1 {
+                                regulator-name = "vdd1p8";
+                                regulator-min-microvolt = <1033310>;
+                                regulator-max-microvolt = <2004000>;
+                                lltc,fb-voltage-divider = <301000 200000>;
+                                regulator-ramp-delay = <7000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        /* VDD_DDR (1+R1/R2 = 2.105) */
+                        reg_vdd_ddr: sw2 {
+                                regulator-name = "vddddr";
+                                regulator-min-microvolt = <868310>;
+                                regulator-max-microvolt = <1684000>;
+                                lltc,fb-voltage-divider = <221000 200000>;
+                                regulator-ramp-delay = <7000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        /* VDD_ARM (1+R1/R2 = 1.635) */
+                        reg_vdd_arm: sw3 {
+                                regulator-name = "vddarm";
+                                regulator-min-microvolt = <674400>;
+                                regulator-max-microvolt = <1308000>;
+                                lltc,fb-voltage-divider = <127000 200000>;
+                                regulator-ramp-delay = <7000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                linux,phandle = <&reg_vdd_arm>;
+                        };
+
+                        /* VDD_SOC (1+R1/R2 = 1.635) */
+                        reg_vdd_soc: sw4 {
+                                regulator-name = "vddsoc";
+                                regulator-min-microvolt = <674400>;
+                                regulator-max-microvolt = <1308000>;
+                                lltc,fb-voltage-divider = <127000 200000>;
+                                regulator-ramp-delay = <7000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                linux,phandle = <&reg_vdd_soc>;
+                        };
+
+                        /* VDD_1P0 (1+R1/R2 = 1.38): */
+                        reg_1p0v: ldo2 {
+                                regulator-name = "vdd1p0";
+                                regulator-min-microvolt = <1002777>;
+                                regulator-max-microvolt = <1002777>;
+                                lltc,fb-voltage-divider = <100000 261000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        /* VDD_HIGH (1+R1/R2 = 4.17) */
+                        reg_3p0v: ldo4 {
+                                regulator-name = "vdd3p0";
+                                regulator-min-microvolt = <3023250>;
+                                regulator-max-microvolt = <3023250>;
+                                lltc,fb-voltage-divider = <634000 200000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+
+&i2c3 {
+        clock-frequency = <400000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+
+        tlv320aic3105: codec@18 {
+                compatible = "ti,tlv320aic3x";
+                reg = <0x18>;
+                gpio-reset = <&gpio5 17 GPIO_ACTIVE_LOW>;
+                clocks = <&clks IMX6QDL_CLK_CKO>;
+                ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */
+                /* Regulators */
+                DRVDD-supply = <&reg_3p3v>;
+                AVDD-supply = <&reg_3p3v>;
+                IOVDD-supply = <&reg_3p3v>;
+                DVDD-supply = <&reg_1p8v>;
+        };
+
+        accelerometer@1d {
+                compatible = "fsl,mma8451";
+                reg = <0x1d>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <11 IRQ_TYPE_EDGE_RISING>;
+                interrupt-names = "INT2";
+        };
+
+        /* headphone detect */
+        ts3a227e@3b {
+                compatible = "ti,ts3a227e";
+                reg = <0x3b>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+                ti,micbias = <4>; /* 2.5V micbias */
+        };
+};
+
+&ldb {
+        status = "okay";
+
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: g101evn010 {
+                                clock-frequency = <68930000>;
+                                hactive = <1280>;
+                                vactive = <800>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
+        };
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+
+&ssi1 {
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        status = "okay";
+};
+
+&usdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc1_200mhz>;
+        vmmc-supply = <&reg_3p3v>;
+        non-removable;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+        cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+        vmmc-supply = <&reg_3p3v>;
+        max-frequency = <100000000>;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+        non-removable;
+        vmmc-supply = <&reg_3p3v>;
+        keep-power-in-suspend;
+        status = "okay";
+};
+
+&wdog1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_wdog>;
+        fsl,ext-reset-output;
+};
+
+&iomuxc {
+        pinctrl_audmux: audmuxgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_DI0_PIN2__AUD6_TXD           0x130b0
+                        MX6QDL_PAD_DI0_PIN3__AUD6_TXFS          0x130b0
+                        MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x130b0
+                        MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x130b0
+                        MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* MCK */
+                >;
+        };
+
+        pinctrl_enet: enetgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
+                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
+                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
+                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
+                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
+                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
+                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
+                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
+                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
+                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
+                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
+                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
+                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                        MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x4001b0b0 /* PHY_RST# */
+                        MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x4001b0b0 /* PHY_EN */
+                >;
+        };
+
+        pinctrl_gpio_leds: gpioledsgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x1b0b0
+                >;
+        };
+
+        pinctrl_i2c1: i2c1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                        MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0 /* GSC_IRQ# */
+                >;
+        };
+
+        pinctrl_i2c2: i2c2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                        MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
+                >;
+        };
+
+        pinctrl_i2c3: i2c3grp {
+                fsl,pins = <
+                        /* I2C3 */
+                        MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                        MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+
+                        /* Headphone Detect */
+                        MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x0001b0b0 /* HPDET_IRQ# */
+                        MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16      0x0001b0b0 /* HPDET_MIC# */
+
+                        /* Codec */
+                        MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x0001b0b0 /* CODEC_RST# */
+
+                        /* Touch Controller */
+                        MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x0001b0b0 /* TOUCH_IRQ# */
+                        MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x0001b0b0 /* TOUCH_RST */
+
+                        /* Stow Sensor */
+                        MX6QDL_PAD_GPIO_16__GPIO7_IO11          0x0001b0b0 /* ACCEL_IRQ2 */
+                        MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x0001b0b0 /* ACCEL_IRQ1 */
+                >;
+        };
+
+        pinctrl_pwm1: pwm1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
+                >;
+        };
+
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
+                        MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
+                        MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30       0x1b0b1 /* TXEN */
+                >;
+        };
+
+        pinctrl_uart2: uart2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                        MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+                >;
+        };
+
+        pinctrl_usbotg: usbotggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x13059
+                        MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x4001b0b0 /* PWR_EN */
+                        MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
+                >;
+        };
+
+        pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+                fsl,pins = <
+                        MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x4001b0b0 /* EMMY_EN */
+                        MX6QDL_PAD_NANDF_D4__GPIO2_IO04         0x4001b0b0 /* EMMY_CFG1# */
+                        MX6QDL_PAD_NANDF_D5__GPIO2_IO05         0x4001b0b0 /* EMMY_CFG2# */
+                        MX6QDL_PAD_NANDF_D6__GPIO2_IO06         0x0001b0b0 /* EMMY_BTWAKE# */
+                        MX6QDL_PAD_NANDF_D7__GPIO2_IO07         0x0001b0b0 /* EMMY_WFWAKE# */
+
+                        MX6QDL_PAD_SD1_CLK__SD1_CLK             0x100f9
+                        MX6QDL_PAD_SD1_CMD__SD1_CMD             0x100f9
+                        MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x170f9
+                        MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x170f9
+                        MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x170f9
+                        MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x170f9
+                >;
+        };
+
+        pinctrl_usdhc2: usdhc2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
+                        MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
+                        MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
+                        MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
+                        MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
+                        MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
+                        MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x17059 /* CD */
+                        MX6QDL_PAD_KEY_ROW1__SD2_VSELECT        0x17059
+                >;
+        };
+
+        pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+                fsl,pins = <
+                        MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170b9
+                        MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100b9
+                        MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170b9
+                        MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170b9
+                        MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170b9
+                        MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170b9
+                        MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x170b9 /* CD */
+                        MX6QDL_PAD_KEY_ROW1__SD2_VSELECT        0x170b9
+                >;
+        };
+
+        pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+                fsl,pins = <
+                        MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170f9
+                        MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100f9
+                        MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170f9
+                        MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170f9
+                        MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170f9
+                        MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170f9
+                        MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x170f9 /* CD */
+                        MX6QDL_PAD_KEY_ROW1__SD2_VSELECT        0x170f9
+                >;
+        };
+
+        pinctrl_usdhc3: usdhc3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                        MX6QDL_PAD_SD3_RST__SD3_RESET           0x10059
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
+                        MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
+                        MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
+                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
+                >;
+        };
+
+        pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
+                        MX6QDL_PAD_SD3_RST__SD3_RESET           0x100b9
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
+                        MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
+                        MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
+                        MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
+                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
+                >;
+        };
+
+        pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
+                        MX6QDL_PAD_SD3_RST__SD3_RESET           0x100f9
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
+                        MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
+                        MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
+                        MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
+                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
+                >;
+        };
+
+        pinctrl_wdog: wdoggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
new file mode 100644
index 000000000000..fd4b68be9fe9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
@@ -0,0 +1,641 @@
+/*
+ * Copyright 2017 Gateworks Corporation
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        /* these are used by bootloader for disabling nodes */
+        aliases {
+                led0 = &led0;
+                led1 = &led1;
+                led2 = &led2;
+                usb0 = &usbh1;
+                usb1 = &usbotg;
+        };
+
+        chosen {
+                stdout-path = &uart2;
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm4 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
+
+                led0: user1 {
+                        label = "user1";
+                        gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+
+                led1: user2 {
+                        label = "user2";
+                        gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+                        default-state = "off";
+                };
+
+                led2: user3 {
+                        label = "user3";
+                        gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
+                        default-state = "off";
+                };
+        };
+
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+
+        pps {
+                compatible = "pps-gpio";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pps>;
+                gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+        };
+
+        reg_1p0v: regulator-1p0v {
+                compatible = "regulator-fixed";
+                regulator-name = "1P0V";
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <1000000>;
+                regulator-always-on;
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        reg_usb_h1_vbus: regulator-usb-h1-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb_h1_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
+
+        reg_usb_otg_vbus: regulator-usb-otg-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb_otg_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+};
+
+&clks {
+        assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                          <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+        assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+                                 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii-id";
+        status = "okay";
+
+        fixed-link {
+                speed = <1000>;
+                full-duplex;
+        };
+
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                switch@0 {
+                        compatible = "marvell,mv88e6085";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        label = "lan4";
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        label = "lan3";
+                                };
+
+                                port@2 {
+                                        reg = <2>;
+                                        label = "lan2";
+                                };
+
+                                port@3 {
+                                        reg = <3>;
+                                        label = "lan1";
+                                };
+
+                                port@5 {
+                                        reg = <5>;
+                                        label = "cpu";
+                                        ethernet = <&fec>;
+                                };
+                        };
+                };
+        };
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+
+        pca9555: gpio@23 {
+                compatible = "nxp,pca9555";
+                reg = <0x23>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        eeprom1: eeprom@50 {
+                compatible = "atmel,24c02";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+
+        eeprom2: eeprom@51 {
+                compatible = "atmel,24c02";
+                reg = <0x51>;
+                pagesize = <16>;
+        };
+
+        eeprom3: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+                pagesize = <16>;
+        };
+
+        eeprom4: eeprom@53 {
+                compatible = "atmel,24c02";
+                reg = <0x53>;
+                pagesize = <16>;
+        };
+
+        dts1672: rtc@68 {
+                compatible = "dallas,ds1672";
+                reg = <0x68>;
+        };
+};
+
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+
+        ltc3676: pmic@3c {
+                compatible = "lltc,ltc3676";
+                reg = <0x3c>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+
+                regulators {
+                        /* VDD_SOC (1+R1/R2 = 1.635) */
+                        reg_vdd_soc: sw1 {
+                                regulator-name = "vddsoc";
+                                regulator-min-microvolt = <674400>;
+                                regulator-max-microvolt = <1308000>;
+                                lltc,fb-voltage-divider = <127000 200000>;
+                                regulator-ramp-delay = <7000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
+                        reg_1p8v: sw2 {
+                                regulator-name = "vdd1p8";
+                                regulator-min-microvolt = <1033310>;
+                                regulator-max-microvolt = <2004000>;
+                                lltc,fb-voltage-divider = <301000 200000>;
+                                regulator-ramp-delay = <7000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        /* VDD_ARM (1+R1/R2 = 1.635) */
+                        reg_vdd_arm: sw3 {
+                                regulator-name = "vddarm";
+                                regulator-min-microvolt = <674400>;
+                                regulator-max-microvolt = <1308000>;
+                                lltc,fb-voltage-divider = <127000 200000>;
+                                regulator-ramp-delay = <7000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        /* VDD_DDR (1+R1/R2 = 2.105) */
+                        reg_vdd_ddr: sw4 {
+                                regulator-name = "vddddr";
+                                regulator-min-microvolt = <868310>;
+                                regulator-max-microvolt = <1684000>;
+                                lltc,fb-voltage-divider = <221000 200000>;
+                                regulator-ramp-delay = <7000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
+                        reg_2p5v: ldo2 {
+                                regulator-name = "vdd2p5";
+                                regulator-min-microvolt = <2490375>;
+                                regulator-max-microvolt = <2490375>;
+                                lltc,fb-voltage-divider = <487000 200000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        /* VDD_HIGH (1+R1/R2 = 4.17) */
+                        reg_3p0v: ldo4 {
+                                regulator-name = "vdd3p0";
+                                regulator-min-microvolt = <3023250>;
+                                regulator-max-microvolt = <3023250>;
+                                lltc,fb-voltage-divider = <634000 200000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+
+        egalax_ts: touchscreen@4 {
+                compatible = "eeti,egalax_ts";
+                reg = <0x04>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+                wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+        };
+};
+
+&ldb {
+        status = "okay";
+
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
+        };
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+
+&pwm2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+        status = "disabled";
+};
+
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+        status = "disabled";
+};
+
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        uart-has-rtscts;
+        status = "okay";
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4>;
+        uart-has-rtscts;
+        status = "okay";
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+        non-removable;
+        vmmc-supply = <&reg_3p3v>;
+        keep-power-in-suspend;
+        status = "okay";
+};
+
+&wdog1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_wdog>;
+        fsl,ext-reset-output;
+};
+
+&iomuxc {
+        pinctrl_enet: enetgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
+                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
+                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
+                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
+                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
+                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
+                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
+                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
+                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
+                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
+                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
+                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
+                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                        MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x4001b0b0 /* PHY_RST# */
+                >;
+        };
+
+        pinctrl_gpio_leds: gpioledsgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
+                        MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
+                        MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
+                >;
+        };
+
+        pinctrl_i2c1: i2c1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                        MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                >;
+        };
+
+        pinctrl_i2c2: i2c2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                        MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                >;
+        };
+
+        pinctrl_i2c3: i2c3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                        MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                >;
+        };
+
+        pinctrl_pcie: pciegrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_0__GPIO1_IO00   0x1b0b0 /* PCIE RST */
+                >;
+        };
+
+        pinctrl_pmic: pmicgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x1b0b0 /* PMIC_IRQ# */
+                >;
+        };
+
+        pinctrl_pps: ppsgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
+                >;
+        };
+
+        pinctrl_pwm2: pwm2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
+                >;
+        };
+
+        pinctrl_pwm3: pwm3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
+                >;
+        };
+
+        pinctrl_pwm4: pwm4grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
+                >;
+        };
+
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
+                        MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
+                >;
+        };
+
+        pinctrl_uart2: uart2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                        MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+                >;
+        };
+
+        pinctrl_uart3: uart3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
+                        MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+                        MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+                        MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
+                >;
+        };
+
+        pinctrl_uart4: uart4grp {
+                fsl,pins = <
+                        MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
+                        MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
+                        MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
+                        MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
+                >;
+        };
+
+        pinctrl_uart5: uart5grp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
+                        MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
+                >;
+        };
+
+        pinctrl_usbotg: usbotggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                        MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
+                        MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
+                >;
+        };
+
+        pinctrl_usdhc3: usdhc3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                        MX6QDL_PAD_SD3_RST__SD3_RESET           0x10059
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
+                        MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
+                        MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
+                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
+                >;
+        };
+
+        pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
+                        MX6QDL_PAD_SD3_RST__SD3_RESET           0x100b9
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
+                        MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
+                        MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
+                        MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
+                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
+                >;
+        };
+
+        pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
+                        MX6QDL_PAD_SD3_RST__SD3_RESET           0x100f9
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
+                        MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
+                        MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
+                        MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
+                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
+                >;
+        };
+
+        pinctrl_wdog: wdoggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
index 55bebfc9ad94..56d0c5d21cd0 100644
--- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -48,6 +48,13 @@
                 reg = <0x10000000 0x80000000>;
         };
 
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm3 0 100000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+        };
+
         reg_3p3v: regulator-3p3v {
                 compatible = "regulator-fixed";
                 regulator-name = "3P3V";
@@ -136,6 +143,12 @@
         status = "okay";
 };
 
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+        status = "okay";
+};
+
 &uart4 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart4>;
@@ -246,6 +259,12 @@
                 >;
         };
 
+        pinctrl_pwm3: pwm3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+                >;
+        };
+
         pinctrl_usbotg: usbotggrp {
                 fsl,pins = <
                         MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 63bf95ed8c88..58055ceec6dc 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -548,6 +548,18 @@
         status = "okay";
 };
 
+&reg_arm {
+       vin-supply = <&sw1a_reg>;
+};
+
+&reg_pu {
+       vin-supply = <&sw1c_reg>;
+};
+
+&reg_soc {
+       vin-supply = <&sw1c_reg>;
+};
+
 &snvs_poweroff {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
new file mode 100644
index 000000000000..5d94b5ee6aa0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -0,0 +1,932 @@
+/*
+ * Copyright (C) 2016-2017 Zodiac Inflight Innovations
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
+
+/ {
+        chosen {
+                stdout-path = &uart1;
+        };
+
+        aliases {
+                mdio-gpio0 = &mdio1;
+        };
+
+        mdio1: mdio {
+                compatible = "virtual,mdio-gpio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_mdio1>;
+                gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
+                         &gpio6 4 GPIO_ACTIVE_HIGH>;
+        };
+
+        reg_28p0v: regulator-28p0v {
+                compatible = "regulator-fixed";
+                regulator-name = "28V_IN";
+                regulator-min-microvolt = <28000000>;
+                regulator-max-microvolt = <28000000>;
+                regulator-always-on;
+        };
+
+        reg_12p0v: regulator-12p0v {
+                compatible = "regulator-fixed";
+                vin-supply = <&reg_28p0v>;
+                regulator-name = "12V_MAIN";
+                regulator-min-microvolt = <12000000>;
+                regulator-max-microvolt = <12000000>;
+                regulator-always-on;
+        };
+
+        reg_5p0v_main: regulator-5p0v-main {
+                compatible = "regulator-fixed";
+                vin-supply = <&reg_12p0v>;
+                regulator-name = "5V_MAIN";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
+
+        reg_5p0v_user_usb: regulator-5p0v-user-usb {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_user_usb>;
+                vin-supply = <&reg_5p0v_main>;
+                regulator-name = "5V_USER_USB";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
+                startup-delay-us = <1000>;
+        };
+
+        reg_3p3v_pmic: regulator-3p3v-pmic {
+                compatible = "regulator-fixed";
+                vin-supply = <&reg_12p0v>;
+                regulator-name = "PMIC_3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                vin-supply = <&reg_3p3v_pmic>;
+                regulator-name = "GEN_3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        reg_3p3v_sd: regulator-3p3v-sd {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
+                vin-supply = <&reg_3p3v>;
+                regulator-name = "3V3_SD";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+                startup-delay-us = <1000>;
+                enable-active-high;
+                regulator-always-on;
+        };
+
+        reg_3p3v_display: regulator-3p3v-display {
+                compatible = "regulator-fixed";
+                vin-supply = <&reg_12p0v>;
+                regulator-name = "3V3_DISPLAY";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        reg_3p3v_ssd: regulator-3p3v-ssd {
+                compatible = "regulator-fixed";
+                vin-supply = <&reg_12p0v>;
+                regulator-name = "3V3_SSD";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        sound1 {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "Front";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,bitclock-master = <&sound1_codec>;
+                simple-audio-card,frame-master = <&sound1_codec>;
+                simple-audio-card,widgets =
+                        "Headphone", "Headphone Jack";
+                simple-audio-card,routing =
+                        "Headphone Jack", "HPLEFT",
+                        "Headphone Jack", "HPRIGHT",
+                        "LEFTIN", "HPL",
+                        "RIGHTIN", "HPR";
+                simple-audio-card,aux-devs = <&hpa1>;
+
+                sound1_cpu: simple-audio-card,cpu {
+                        sound-dai = <&ssi2>;
+                };
+
+                sound1_codec: simple-audio-card,codec {
+                        sound-dai = <&codec1>;
+                        clocks = <&cs2000>;
+                };
+        };
+
+        sound2 {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "Back";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,bitclock-master = <&sound2_codec>;
+                simple-audio-card,frame-master = <&sound2_codec>;
+                simple-audio-card,widgets =
+                        "Headphone", "Headphone Jack";
+                simple-audio-card,routing =
+                        "Headphone Jack", "HPLEFT",
+                        "Headphone Jack", "HPRIGHT",
+                        "LEFTIN", "HPL",
+                        "RIGHTIN", "HPR";
+                simple-audio-card,aux-devs = <&hpa2>;
+
+                sound2_cpu: simple-audio-card,cpu {
+                        sound-dai = <&ssi1>;
+                };
+
+                sound2_codec: simple-audio-card,codec {
+                        sound-dai = <&codec2>;
+                        clocks = <&cs2000>;
+                };
+        };
+
+        panel {
+                power-supply = <&reg_3p3v_display>;
+                status = "disabled";
+
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&lvds0_out>;
+                        };
+                };
+        };
+
+        disp0: disp0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,imx-parallel-display";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_disp0>;
+                status = "disabled";
+
+                port@0 {
+                        reg = <0>;
+
+                        disp0_in_0: endpoint {
+                                remote-endpoint = <&ipu1_di0_disp0>;
+                        };
+                };
+
+                port@1 {
+                        reg = <1>;
+
+                        disp0_out: endpoint {
+                                remote-endpoint = <&tc358767_in>;
+                        };
+                };
+        };
+
+        cs2000_ref: cs2000-ref {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24576000>;
+        };
+
+        cs2000_in_dummy: cs2000-in-dummy {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        edp_refclk: edp-refclk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <19200000>;
+        };
+};
+
+&reg_arm {
+        vin-supply = <&sw1a_reg>;
+};
+
+&reg_pu {
+        vin-supply = <&sw1c_reg>;
+};
+
+&reg_soc {
+        vin-supply = <&sw1c_reg>;
+};
+
+&ldb {
+        lvds-channel@0 {
+                port@4 {
+                        reg = <4>;
+
+                        lvds0_out: endpoint {
+                                remote-endpoint = <&panel_in>;
+                        };
+                };
+        };
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        uart-has-rtscts;
+        linux,rs485-enabled-at-boot-time;
+        status = "okay";
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4>;
+        status = "okay";
+};
+
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1>;
+        cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+
+        flash@0 {
+                compatible = "st,m25p128", "jedec,spi-nor";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        clock-frequency = <100000>;
+        status = "okay";
+
+        codec2: codec@18 {
+                compatible = "ti,tlv320dac3100";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_codec2>;
+                reg = <0x18>;
+                #sound-dai-cells = <0>;
+                HPVDD-supply = <&reg_3p3v>;
+                SPRVDD-supply = <&reg_3p3v>;
+                SPLVDD-supply = <&reg_3p3v>;
+                AVDD-supply = <&reg_3p3v>;
+                IOVDD-supply = <&reg_3p3v>;
+                DVDD-supply = <&vgen4_reg>;
+                gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+        };
+
+        accel@1c {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_accel>;
+                compatible = "fsl,mma8451";
+                reg = <0x1c>;
+                interrupt-parent = <&gpio1>;
+                interrupt-names = "int1", "int2";
+                interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>;
+        };
+
+        hpa2: amp@60 {
+                compatible = "ti,tpa6130a2";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_tpa2>;
+                reg = <0x60>;
+                power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+                Vdd-supply = <&reg_5p0v_main>;
+        };
+
+        edp-bridge@68 {
+                compatible = "toshiba,tc358767";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_tc358767>;
+                reg = <0x68>;
+                shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                clock-names = "ref";
+                clocks = <&edp_refclk>;
+                status = "disabled";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@1 {
+                                reg = <1>;
+
+                                tc358767_in: endpoint {
+                                        remote-endpoint = <&disp0_out>;
+                                };
+                        };
+                };
+        };
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        clock-frequency = <100000>;
+        status = "okay";
+
+        pmic@08 {
+                compatible = "fsl,pfuze100";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pfuze100_irq>;
+                reg = <0x08>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                        };
+
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-always-on;
+                        };
+
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+
+        temp-sense@48 {
+                compatible = "national,lm75";
+                reg = <0x48>;
+        };
+
+        cs2000: clkgen@4e {
+                compatible = "cirrus,cs2000-cp";
+                reg = <0x4e>;
+                #clock-cells = <0>;
+                clock-names = "clk_in", "ref_clk";
+                clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
+                assigned-clocks = <&cs2000>;
+                assigned-clock-rates = <24000000>;
+        };
+
+        eeprom@54 {
+                compatible = "at,24c128";
+                reg = <0x54>;
+        };
+
+        rtc@68 {
+                compatible = "dallas,ds1341";
+                reg = <0x68>;
+        };
+};
+
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        clock-frequency = <400000>;
+        status = "okay";
+
+        codec1: codec@18 {
+                compatible = "ti,tlv320dac3100";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_codec1>;
+                reg = <0x18>;
+                #sound-dai-cells = <0>;
+                HPVDD-supply = <&reg_3p3v>;
+                SPRVDD-supply = <&reg_3p3v>;
+                SPLVDD-supply = <&reg_3p3v>;
+                AVDD-supply = <&reg_3p3v>;
+                IOVDD-supply = <&reg_3p3v>;
+                DVDD-supply = <&vgen4_reg>;
+                gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+        };
+
+        touchscreen@20 {
+                compatible = "syna,rmi4-i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ts>;
+                reg = <0x20>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+                vdd-supply = <&reg_5p0v_main>;
+                vio-supply = <&reg_3p3v>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                rmi4-f01@1 {
+                        reg = <0x1>;
+                        syna,nosleep-mode = <1>;
+                };
+
+                rmi4-f11@11 {
+                        reg = <0x11>;
+                        touchscreen-inverted-y;
+                        touchscreen-swapped-x-y;
+                        syna,sensor-type = <1>;
+                };
+
+                rmi4-f12@12 {
+                        reg = <0x12>;
+                        touchscreen-inverted-y;
+                        touchscreen-swapped-x-y;
+                        syna,sensor-type = <1>;
+                };
+        };
+
+        hpa1: amp@60 {
+                compatible = "ti,tpa6130a2";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_tpa1>;
+                reg = <0x60>;
+                power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+                Vdd-supply = <&reg_5p0v_main>;
+        };
+};
+
+&ipu1_di0_disp0 {
+        remote-endpoint = <&disp0_in_0>;
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        bus-width = <4>;
+        cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+        wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+        vmmc-supply = <&reg_3p3v_sd>;
+        vqmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        bus-width = <4>;
+        cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+        wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+        vmmc-supply = <&reg_3p3v_sd>;
+        vqmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        bus-width = <8>;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_3p3v>;
+        non-removable;
+        status = "okay";
+};
+
+&sata {
+        target-supply = <&reg_3p3v_ssd>;
+        status = "okay";
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rmii";
+        phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+        phy-reset-duration = <100>;
+        phy-supply = <&reg_3p3v>;
+        status = "okay";
+
+        fixed-link {
+                speed = <100>;
+                full-duplex;
+        };
+};
+
+&usbh1 {
+        vbus-supply = <&reg_5p0v_main>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_5p0v_user_usb>;
+        disable-over-current;
+        dr_mode = "host";
+        status = "okay";
+};
+
+&ssi1 {
+        status = "okay";
+};
+
+&ssi2 {
+        status = "okay";
+};
+
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+
+        ssi1 {
+                fsl,audmux-port = <0>;
+                fsl,port-config = <
+                        (IMX_AUDMUX_V2_PTCR_SYN |
+                         IMX_AUDMUX_V2_PTCR_TFSEL(2) |
+                         IMX_AUDMUX_V2_PTCR_TCSEL(2) |
+                         IMX_AUDMUX_V2_PTCR_TFSDIR |
+                         IMX_AUDMUX_V2_PTCR_TCLKDIR)
+                        IMX_AUDMUX_V2_PDCR_RXDSEL(2)
+                >;
+        };
+
+        aud3 {
+                fsl,audmux-port = <2>;
+                fsl,port-config = <
+                        IMX_AUDMUX_V2_PTCR_SYN
+                        IMX_AUDMUX_V2_PDCR_RXDSEL(0)
+                >;
+        };
+
+        ssi2 {
+                fsl,audmux-port = <1>;
+                fsl,port-config = <
+                        (IMX_AUDMUX_V2_PTCR_SYN |
+                         IMX_AUDMUX_V2_PTCR_TFSEL(4) |
+                         IMX_AUDMUX_V2_PTCR_TCSEL(4) |
+                         IMX_AUDMUX_V2_PTCR_TFSDIR |
+                         IMX_AUDMUX_V2_PTCR_TCLKDIR)
+                        IMX_AUDMUX_V2_PDCR_RXDSEL(4)
+                >;
+        };
+
+        aud5 {
+                fsl,audmux-port = <4>;
+                fsl,port-config = <
+                        IMX_AUDMUX_V2_PTCR_SYN
+                        IMX_AUDMUX_V2_PDCR_RXDSEL(1)
+                >;
+        };
+};
+
+&iomuxc {
+        pinctrl_accel: accelgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x4001b000
+                        MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x4001b000
+                >;
+        };
+
+        pinctrl_audmux: audmuxgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0
+                        MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x130b0
+                        MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0
+                        MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
+                        MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x130b0
+                        MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
+                >;
+        };
+
+        pinctrl_codec1: dac1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x40000038
+                >;
+        };
+
+        pinctrl_codec2: dac2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x40000038
+                >;
+        };
+
+        pinctrl_disp0: disp0grp {
+                fsl,pins = <
+                        MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
+                        MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
+                        MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
+                        MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
+                        MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
+                        MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
+                        MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
+                        MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
+                        MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
+                        MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
+                        MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
+                        MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
+                        MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
+                        MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
+                        MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
+                        MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
+                        MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
+                        MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
+                        MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
+                        MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
+                        MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
+                        MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
+                        MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
+                        MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
+                        MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
+                        MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
+                        MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
+                        MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
+                >;
+        };
+
+        pinctrl_ecspi1: ecspi1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
+                        MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
+                        MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
+                        MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b1
+                >;
+        };
+
+        pinctrl_enet: enetgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x000b1
+                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b1
+                        MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x100f5
+                        MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x100f5
+                        MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x100c0
+                        MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x100c0
+                        MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x100f5
+                        MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x100f5
+                        MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x40010040
+                        MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x100b0
+                        MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
+                >;
+        };
+
+        pinctrl_i2c1: i2c1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
+                        MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
+                >;
+        };
+
+        pinctrl_i2c2: i2c2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                        MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                >;
+        };
+
+        pinctrl_i2c3: i2c3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                        MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                >;
+        };
+
+        pinctrl_mdio1: bitbangmdiogrp {
+                fsl,pins = <
+                        /* Bitbang MDIO for DEB Switch */
+                        MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x4001b030
+                        MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04       0x40018830
+                >;
+        };
+
+        pinctrl_pcie: pciegrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x10038
+                >;
+        };
+
+        pinctrl_pfuze100_irq: pfuze100grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x40010000
+                >;
+        };
+
+        pinctrl_reg_3p3v_sd: mmcsupply1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x858
+                >;
+        };
+
+        pinctrl_reg_user_usb: usbotggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x40000038
+                >;
+        };
+
+        pinctrl_rmii_phy_irq: phygrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x40010000
+                >;
+        };
+
+        pinctrl_tc358767: tc358767grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x10
+                >;
+        };
+
+        pinctrl_tpa1: tpa6130-1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x40000038
+                >;
+        };
+
+        pinctrl_tpa2: tpa6130-2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x40000038
+                >;
+        };
+
+        pinctrl_ts: tsgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x1b0b0
+                        MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
+                >;
+        };
+
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
+                        MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
+                >;
+        };
+
+        pinctrl_uart3: uart3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+                        MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+                        MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
+                >;
+        };
+
+        pinctrl_uart4: uart4grp {
+                fsl,pins = <
+                        MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
+                        MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
+                >;
+        };
+
+        pinctrl_usdhc2: usdhc2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD2_CMD__SD2_CMD             0x10059
+                        MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
+                        MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
+                        MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
+                        MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
+                        MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
+                        MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x40010040
+                        MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x40010040
+                >;
+        };
+
+        pinctrl_usdhc3: usdhc3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD             0x10059
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10069
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x40010040
+                        MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x40010040
+
+                >;
+        };
+
+        pinctrl_usdhc4: usdhc4grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                        MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                        MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                        MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                        MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                        MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                        MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
+                        MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
+                        MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
+                        MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
+                        MX6QDL_PAD_NANDF_ALE__SD4_RESET         0x1b0b1
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 6d7bf6496117..e426faa9c243 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -197,7 +197,7 @@
                         arm,shared-override;
                 };
 
-                pcie: pcie@0x01000000 {
+                pcie: pcie@1ffc000 {
                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
                         reg = <0x01ffc000 0x04000>,
                               <0x01f00000 0x80000>;
@@ -205,6 +205,7 @@
                         #address-cells = <3>;
                         #size-cells = <2>;
                         device_type = "pci";
+                        bus-range = <0x00 0xff>;
                         ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
                         num-lanes = <1>;
diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts
new file mode 100644
index 000000000000..011726c836cd
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2017 Boundary Devices, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6qp.dtsi"
+#include "imx6qdl-nitrogen6_som2.dtsi"
+
+/ {
+        model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_SOM2 Board";
+        compatible = "boundary,imx6qp-nitrogen6_som2", "fsl,imx6qp";
+};
+
+&sata {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts
index b23458062f5e..a8a5004dd9c8 100644
--- a/arch/arm/boot/dts/imx6qp-sabresd.dts
+++ b/arch/arm/boot/dts/imx6qp-sabresd.dts
@@ -50,8 +50,8 @@
         compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
 };
 
-&cpu0 {
-        arm-supply = <&sw2_reg>;
+&reg_arm {
+        vin-supply = <&sw2_reg>;
 };
 
 &iomuxc {
diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
new file mode 100644
index 000000000000..882b3bd97e07
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2016-2017 Zodiac Inflight Innovations
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <imx6qp.dtsi>
+#include <imx6qdl-zii-rdu2.dtsi>
+
+/ {
+        model = "ZII RDU2+ Board";
+        compatible = "zii,imx6qp-zii-rdu2", "fsl,imx6qp";
+};
diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi
index 24d071f5d9cd..59453f2ac4ba 100644
--- a/arch/arm/boot/dts/imx6qp.dtsi
+++ b/arch/arm/boot/dts/imx6qp.dtsi
@@ -56,40 +56,59 @@
                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
                 };
 
-                ipu1: ipu@02400000 {
-                        compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
-                        clocks = <&clks IMX6QDL_CLK_IPU1>,
-                                 <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
-                                 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
-                                 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>,
-                                 <&clks IMX6QDL_CLK_PRG0_APB>;
-                        clock-names = "bus",
-                                      "di0", "di1",
-                                      "di0_sel", "di1_sel",
-                                      "ldb_di0", "ldb_di1", "prg";
-                };
+                aips-bus@02100000 {
+                        pre1: pre@21c8000 {
+                                compatible = "fsl,imx6qp-pre";
+                                reg = <0x021c8000 0x1000>;
+                                interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clks IMX6QDL_CLK_PRE0>;
+                                clock-names = "axi";
+                                fsl,iram = <&ocram2>;
+                        };
 
-                ipu2: ipu@02800000 {
-                        compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
-                        clocks = <&clks IMX6QDL_CLK_IPU2>,
-                                 <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>,
-                                 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
-                                 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>,
-                                 <&clks IMX6QDL_CLK_PRG1_APB>;
-                        clock-names = "bus",
-                                      "di0", "di1",
-                                      "di0_sel", "di1_sel",
-                                      "ldb_di0", "ldb_di1", "prg";
-                };
+                        pre2: pre@21c9000 {
+                                compatible = "fsl,imx6qp-pre";
+                                reg = <0x021c9000 0x1000>;
+                                interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clks IMX6QDL_CLK_PRE1>;
+                                clock-names = "axi";
+                                fsl,iram = <&ocram2>;
+                        };
 
-                pcie: pcie@0x01000000 {
-                        compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
-                };
+                        pre3: pre@21ca000 {
+                                compatible = "fsl,imx6qp-pre";
+                                reg = <0x021ca000 0x1000>;
+                                interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clks IMX6QDL_CLK_PRE2>;
+                                clock-names = "axi";
+                                fsl,iram = <&ocram3>;
+                        };
 
-                aips-bus@02100000 {
-                        mmdc0: mmdc@021b0000 { /* MMDC0 */
-                                compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
-                                reg = <0x021b0000 0x4000>;
+                        pre4: pre@21cb000 {
+                                compatible = "fsl,imx6qp-pre";
+                                reg = <0x021cb000 0x1000>;
+                                interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clks IMX6QDL_CLK_PRE3>;
+                                clock-names = "axi";
+                                fsl,iram = <&ocram3>;
+                        };
+
+                        prg1: prg@21cc000 {
+                                compatible = "fsl,imx6qp-prg";
+                                reg = <0x021cc000 0x1000>;
+                                clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
+                                         <&clks IMX6QDL_CLK_PRG0_AXI>;
+                                clock-names = "ipg", "axi";
+                                fsl,pres = <&pre1>, <&pre2>, <&pre3>;
+                        };
+
+                        prg2: prg@21cd000 {
+                                compatible = "fsl,imx6qp-prg";
+                                reg = <0x021cd000 0x1000>;
+                                clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
+                                         <&clks IMX6QDL_CLK_PRG1_AXI>;
+                                clock-names = "ipg", "axi";
+                                fsl,pres = <&pre4>, <&pre2>, <&pre3>;
                         };
                 };
         };
@@ -101,6 +120,16 @@
                      <0 119 IRQ_TYPE_LEVEL_HIGH>;
 };
 
+&ipu1 {
+        compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+        fsl,prg = <&prg1>;
+};
+
+&ipu2 {
+        compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+        fsl,prg = <&prg2>;
+};
+
 &ldb {
         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -110,3 +139,11 @@
                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
                       "di0", "di1";
 };
+
+&mmdc0 {
+        compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
+};
+
+&pcie {
+        compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index dd4ec85ecbaa..3f1416be4c36 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -297,7 +297,8 @@
                                 };
 
                                 uart1: serial@02020000 {
-                                        compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+                                        compatible = "fsl,imx6sx-uart",
+                                                     "fsl,imx6q-uart", "fsl,imx21-uart";
                                         reg = <0x02020000 0x4000>;
                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
@@ -1053,7 +1054,8 @@
                         };
 
                         uart2: serial@021e8000 {
-                                compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+                                compatible = "fsl,imx6sx-uart",
+                                             "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021e8000 0x4000>;
                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
@@ -1065,7 +1067,8 @@
                         };
 
                         uart3: serial@021ec000 {
-                                compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+                                compatible = "fsl,imx6sx-uart",
+                                             "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021ec000 0x4000>;
                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
@@ -1077,7 +1080,8 @@
                         };
 
                         uart4: serial@021f0000 {
-                                compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+                                compatible = "fsl,imx6sx-uart",
+                                             "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021f0000 0x4000>;
                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
@@ -1089,7 +1093,8 @@
                         };
 
                         uart5: serial@021f4000 {
-                                compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+                                compatible = "fsl,imx6sx-uart",
+                                             "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021f4000 0x4000>;
                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
@@ -1229,7 +1234,8 @@
                         };
 
                         uart6: serial@022a0000 {
-                                compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+                                compatible = "fsl,imx6sx-uart",
+                                             "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x022a0000 0x4000>;
                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
@@ -1281,7 +1287,7 @@
                         };
                 };
 
-                pcie: pcie@0x08000000 {
+                pcie: pcie@8ffc000 {
                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
                         reg = <0x08ffc000 0x4000>; /* DBI */
                         #address-cells = <3>;
@@ -1293,6 +1299,7 @@
                                   0x81000000 0 0          0x08f80000 0 0x00010000
                                   /* non-prefetchable memory */
                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
+                        bus-range = <0x00 0xff>;
                         num-lanes = <1>;
                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
index 00f98e5bfcaf..f18e1f1d0ce2 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@@ -85,11 +85,6 @@
         assigned-clock-rates = <786432000>;
 };
 
-&cpu0 {
-        arm-supply = <&reg_arm>;
-        soc-supply = <&reg_soc>;
-};
-
 &i2c2 {
         clock_frequency = <100000>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6ul-geam.dtsi b/arch/arm/boot/dts/imx6ul-geam.dtsi
index 940aef67313b..eb94d956808b 100644
--- a/arch/arm/boot/dts/imx6ul-geam.dtsi
+++ b/arch/arm/boot/dts/imx6ul-geam.dtsi
@@ -49,6 +49,23 @@
                 reg = <0x80000000 0x08000000>;
         };
 
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm8 0 100000>;
+                brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+                                     10 11 12 13 14 15 16 17 18 19
+                                     20 21 22 23 24 25 26 27 28 29
+                                     30 31 32 33 34 35 36 37 38 39
+                                     40 41 42 43 44 45 46 47 48 49
+                                     50 51 52 53 54 55 56 57 58 59
+                                     60 61 62 63 64 65 66 67 68 69
+                                     70 71 72 73 74 75 76 77 78 79
+                                     80 81 82 83 84 85 86 87 88 89
+                                     90 91 92 93 94 95 96 97 98 99
+                                    100>;
+                default-brightness-level = <100>;
+        };
+
         chosen {
                 stdout-path = &uart1;
         };
@@ -143,12 +160,24 @@
         display = <&display0>;
 };
 
+&pwm8 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm8>;
+        status = "okay";
+};
+
 &tsc {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_tsc>;
         xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 };
 
+&sai2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_sai2>;
+        status = "okay";
+};
+
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
@@ -290,6 +319,12 @@
                 >;
         };
 
+        pinctrl_pwm8: pwm8grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_RX_ER__PWM8_OUT   0x110b0
+                >;
+        };
+
         pinctrl_tsc: tscgrp {
                 fsl,pin = <
                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0xb0
@@ -299,6 +334,16 @@
                 >;
         };
 
+        pinctrl_sai2: sai2grp {
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x130b0
+                        MX6UL_PAD_JTAG_TMS__CCM_CLKO1           0x4001b031
+                        MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
+                        MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
+                        MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x120b0
+                >;
+        };
+
         pinctrl_uart1: uart1grp {
                 fsl,pins = <
                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6ul-isiot-common.dtsi b/arch/arm/boot/dts/imx6ul-isiot-common.dtsi
new file mode 100644
index 000000000000..2beaab6e272e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-isiot-common.dtsi
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+&i2c1 {
+        stmpe811: gpio-expander@44 {
+                compatible = "st,stmpe811";
+                reg = <0x44>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_stmpe>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+
+                stmpe: touchscreen {
+                        compatible = "st,stmpe-ts";
+                        st,sample-time = <4>;
+                        st,mod-12b = <1>;
+                        st,ref-sel = <0>;
+                        st,adc-freq = <1>;
+                        st,ave-ctrl = <1>;
+                        st,touch-det-delay = <2>;
+                        st,settling = <2>;
+                        st,fraction-z = <7>;
+                        st,i-drive = <1>;
+                };
+        };
+};
+
+&lcdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcdif_dat
+                     &pinctrl_lcdif_ctrl>;
+        display = <&display0>;
+        status = "okay";
+
+        display0: display {
+                bits-per-pixel = <16>;
+                bus-width = <18>;
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing0 {
+                                clock-frequency = <28000000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hfront-porch = <30>;
+                                hback-porch = <30>;
+                                hsync-len = <64>;
+                                vback-porch = <5>;
+                                vfront-porch = <5>;
+                                vsync-len = <20>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+};
+
+&iomuxc {
+        pinctrl_lcdif_ctrl: lcdifctrlgrp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
+                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
+                        MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+                        MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+                >;
+        };
+
+        pinctrl_lcdif_dat: lcdifdatgrp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
+                        MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
+                        MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
+                        MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
+                        MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
+                        MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
+                        MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
+                        MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
+                        MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
+                        MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
+                        MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
+                        MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
+                        MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
+                        MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
+                        MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
+                        MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
+                        MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
+                        MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
+                >;
+        };
+
+        pinctrl_stmpe: stmpegrp  {
+                fsl,pins = <
+                        MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts b/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
index f5b422898e61..73a1d0f0b9d5 100644
--- a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
+++ b/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
@@ -43,6 +43,7 @@
 /dts-v1/;
 
 #include "imx6ul-isiot.dtsi"
+#include "imx6ul-isiot-common.dtsi"
 
 / {
         model = "Engicam Is.IoT MX6UL eMMC Starter kit";
diff --git a/arch/arm/boot/dts/imx6ul-isiot-nand.dts b/arch/arm/boot/dts/imx6ul-isiot-nand.dts
index de15e1c75dd1..da29a86eb6a8 100644
--- a/arch/arm/boot/dts/imx6ul-isiot-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-isiot-nand.dts
@@ -43,6 +43,7 @@
 /dts-v1/;
 
 #include "imx6ul-isiot.dtsi"
+#include "imx6ul-isiot-common.dtsi"
 
 / {
         model = "Engicam Is.IoT MX6UL NAND Starter kit";
diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi
index 0b43699af3e3..ea30380ad7a4 100644
--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
@@ -52,6 +52,49 @@
         chosen {
                 stdout-path = &uart1;
         };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm8 0 100000>;
+                brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+                                     10 11 12 13 14 15 16 17 18 19
+                                     20 21 22 23 24 25 26 27 28 29
+                                     30 31 32 33 34 35 36 37 38 39
+                                     40 41 42 43 44 45 46 47 48 49
+                                     50 51 52 53 54 55 56 57 58 59
+                                     60 61 62 63 64 65 66 67 68 69
+                                     70 71 72 73 74 75 76 77 78 79
+                                     80 81 82 83 84 85 86 87 88 89
+                                     90 91 92 93 94 95 96 97 98 99
+                                    100>;
+                default-brightness-level = <100>;
+        };
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+};
+
+&i2c2 {
+        clock_frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+};
+
+&pwm8 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm8>;
+        status = "okay";
+};
+
+&sai2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_sai2>;
+        status = "okay";
 };
 
 &uart1 {
@@ -72,6 +115,36 @@
 };
 
 &iomuxc {
+        pinctrl_i2c1: i2c1grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+                        MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+                >;
+        };
+
+        pinctrl_i2c2: i2c2grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
+                        MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
+                >;
+        };
+
+        pinctrl_pwm8: pwm8grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_RX_ER__PWM8_OUT   0x110b0
+                >;
+        };
+
+        pinctrl_sai2: sai2grp {
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x130b0
+                        MX6UL_PAD_JTAG_TMS__CCM_CLKO1           0x4001b031
+                        MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
+                        MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
+                        MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x120b0
+                >;
+        };
+
         pinctrl_uart1: uart1grp {
                 fsl,pins = <
                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
index 373ee19196a6..18bebd6d8d47 100644
--- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -44,11 +44,39 @@
         chosen {
                 stdout-path = "serial0:115200n8";
         };
+
+        panel: panel {
+                compatible = "edt,et057090dhu";
+                backlight = <&bl>;
+                power-supply = <&reg_3v3>;
+
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&lcdif_out>;
+                        };
+                };
+        };
+
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        reg_5v0: regulator-5v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "5V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
 };
 
 &bl {
         brightness-levels = <0 4 8 16 32 64 128 255>;
         default-brightness-level = <6>;
+        power-supply = <&reg_3v3>;
+
         status = "okay";
 };
 
@@ -75,32 +103,11 @@
 };
 
 &lcdif {
-        display = <&display0>;
         status = "okay";
 
-        display0: lcd-display {
-                bits-per-pixel = <16>;
-                bus-width = <18>;
-
-                display-timings {
-                        native-mode = <&timing_vga>;
-
-                        /* Standard VGA timing */
-                        timing_vga: 640x480 {
-                                clock-frequency = <25175000>;
-                                hactive = <640>;
-                                vactive = <480>;
-                                hback-porch = <40>;
-                                hfront-porch = <24>;
-                                vback-porch = <32>;
-                                vfront-porch = <11>;
-                                hsync-len = <96>;
-                                vsync-len = <2>;
-                                de-active = <1>;
-                                hsync-active = <0>;
-                                vsync-active = <0>;
-                                pixelclk-active = <0>;
-                        };
+        port {
+                lcdif_out: endpoint {
+                        remote-endpoint = <&panel_in>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index a171545478be..2d87489f9105 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -60,13 +60,6 @@
                 regulator-max-microvolt = <3300000>;
         };
 
-        reg_vref_1v8: regulator-vref-1v8 {
-                compatible = "regulator-fixed";
-                regulator-name = "vref-1v8";
-                regulator-min-microvolt = <1800000>;
-                regulator-max-microvolt = <1800000>;
-        };
-
         sound {
                 compatible = "simple-audio-card";
                 simple-audio-card,name = "imx7-sgtl5000";
@@ -85,11 +78,11 @@
 };
 
 &adc1 {
-        vref-supply = <&reg_vref_1v8>;
+        vref-supply = <&reg_DCDC3>;
 };
 
 &adc2 {
-        vref-supply = <&reg_vref_1v8>;
+        vref-supply = <&reg_DCDC3>;
 };
 
 &cpu0 {
@@ -151,29 +144,29 @@
 
                 regulators {
                         reg_DCDC1: DCDC1 {  /* V1.0_SOC */
-                                regulator-min-microvolt =  <975000>;
-                                regulator-max-microvolt = <1125000>;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1100000>;
                                 regulator-boot-on;
                                 regulator-always-on;
                         };
 
                         reg_DCDC2: DCDC2 { /* V1.1_ARM */
-                                regulator-min-microvolt =  <975000>;
-                                regulator-max-microvolt = <1125000>;
+                                regulator-min-microvolt = <975000>;
+                                regulator-max-microvolt = <1100000>;
                                 regulator-boot-on;
                                 regulator-always-on;
                         };
 
                         reg_DCDC3: DCDC3 { /* V1.8 */
-                                regulator-min-microvolt = <1775000>;
-                                regulator-max-microvolt = <1825000>;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
                                 regulator-boot-on;
                                 regulator-always-on;
                         };
 
                         reg_DCDC4: DCDC4 { /* V1.35_DRAM */
-                                regulator-min-microvolt = <1325000>;
-                                regulator-max-microvolt = <1375000>;
+                                regulator-min-microvolt = <1350000>;
+                                regulator-max-microvolt = <1350000>;
                                 regulator-boot-on;
                                 regulator-always-on;
                         };
@@ -181,33 +174,33 @@
                         reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <3300000>;
-                                regulator-always-on;
+                                regulator-boot-on;
                         };
 
                         reg_LDO2: LDO2 { /* +V1.8_SD */
-                                regulator-min-microvolt = <1775000>;
-                                regulator-max-microvolt = <3325000>;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
                                 regulator-boot-on;
                                 regulator-always-on;
                         };
 
                         reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
-                                regulator-min-microvolt = <3275000>;
-                                regulator-max-microvolt = <3325000>;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
                                 regulator-boot-on;
                                 regulator-always-on;
                         };
 
                         reg_LDO4: LDO4 { /* V1.8_LPSR */
-                                regulator-min-microvolt = <1775000>;
-                                regulator-max-microvolt = <1825000>;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
                                 regulator-boot-on;
                                 regulator-always-on;
                         };
 
                         reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
-                                regulator-min-microvolt = <1775000>;
-                                regulator-max-microvolt = <1825000>;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
                                 regulator-boot-on;
                                 regulator-always-on;
                         };
diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
index bd01d2cc642d..a608a14d8c85 100644
--- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
@@ -57,6 +57,7 @@
                 regulator-min-microvolt = <5000000>;
                 regulator-max-microvolt = <5000000>;
                 gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
+                vin-supply = <&reg_5v0>;
         };
 };
 
diff --git a/arch/arm/boot/dts/imx7d-sdb-sht11.dts b/arch/arm/boot/dts/imx7d-sdb-sht11.dts
new file mode 100644
index 000000000000..64a20ed1713a
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-sdb-sht11.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx7d-sdb.dts"
+
+/ {
+        sensor {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_sensor>;
+                compatible = "sensirion,sht15";
+                clk-gpios = <&gpio4 12 0>;
+                data-gpios = <&gpio4 13 0>;
+                vcc-supply = <&reg_sht15>;
+        };
+
+        reg_sht15: regulator-sht15 {
+                compatible = "regulator-fixed";
+                regulator-name = "reg_sht15";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+};
+
+&i2c3 {
+        status = "disabled";
+};
+
+&iomuxc {
+        pinctrl_sensor: sensorgrp {
+                fsl,pins = <
+                        MX7D_PAD_I2C3_SDA__GPIO4_IO13   0x4000007f
+                        MX7D_PAD_I2C3_SCL__GPIO4_IO12   0x4000007f
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 5d3a43b8de20..c4f12fd2e044 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -493,10 +493,9 @@
                         };
 
                         ocotp: ocotp-ctrl@30350000 {
-                                compatible = "syscon";
+                                compatible = "fsl,imx7d-ocotp", "syscon";
                                 reg = <0x30350000 0x10000>;
-                                clocks = <&clks IMX7D_CLK_DUMMY>;
-                                status = "disabled";
+                                clocks = <&clks IMX7D_OCOTP_CLK>;
                         };
 
                         anatop: anatop@30360000 {
@@ -559,7 +558,7 @@
                         };
 
                         src: src@30390000 {
-                                compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
+                                compatible = "fsl,imx7d-src", "syscon";
                                 reg = <0x30390000 0x10000>;
                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                                 #reset-cells = <1>;
diff --git a/arch/arm/boot/dts/include/arm b/arch/arm/boot/dts/include/arm
new file mode 120000
index 000000000000..a96aa0ea9d8c
--- /dev/null
+++ b/arch/arm/boot/dts/include/arm
@@ -0,0 +1 @@
+..
\ No newline at end of file
diff --git a/arch/arm/boot/dts/include/arm64 b/arch/arm/boot/dts/include/arm64
new file mode 120000
index 000000000000..074a835fca3e
--- /dev/null
+++ b/arch/arm/boot/dts/include/arm64
@@ -0,0 +1 @@
+../../../../arm64/boot/dts
\ No newline at end of file
diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
new file mode 100644
index 000000000000..f5aeb3959afd
--- /dev/null
+++ b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
@@ -0,0 +1,243 @@
+/*
+ * Common CPCAP configuration used on Motorola phones
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&mcspi1 {
+        cpcap: pmic@0 {
+                compatible = "motorola,cpcap", "st,6556002";
+                reg = <0>;      /* cs0 */
+                interrupt-parent = <&gpio1>;
+                interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                spi-max-frequency = <3000000>;
+                spi-cs-high;
+
+                cpcap_adc: adc {
+                        compatible = "motorola,mapphone-cpcap-adc";
+                        interrupts-extended = <&cpcap 8 0>;
+                        interrupt-names = "adcdone";
+                        #io-channel-cells = <1>;
+                };
+
+                cpcap_charger: charger {
+                        compatible = "motorola,mapphone-cpcap-charger";
+                        interrupts-extended = <
+                                &cpcap 13 0 &cpcap 12 0 &cpcap 29 0 &cpcap 28 0
+                                &cpcap 22 0 &cpcap 20 0 &cpcap 19 0 &cpcap 54 0
+                        >;
+                        interrupt-names =
+                                "chrg_det", "rvrs_chrg", "chrg_se1b", "se0conn",
+                                "rvrs_mode", "chrgcurr1", "vbusvld", "battdetb";
+                        mode-gpios = <&gpio3 29 GPIO_ACTIVE_LOW
+                                      &gpio3 23 GPIO_ACTIVE_LOW>;
+                        io-channels = <&cpcap_adc 0 &cpcap_adc 1
+                                       &cpcap_adc 2 &cpcap_adc 5
+                                       &cpcap_adc 6>;
+                        io-channel-names = "battdetb", "battp",
+                                           "vbus", "chg_isense",
+                                           "batti";
+                };
+
+                cpcap_regulator: regulator {
+                        compatible = "motorola,mapphone-cpcap-regulator";
+
+                        cpcap_regulators: regulators {
+                        };
+                };
+
+                cpcap_rtc: rtc {
+                        compatible = "motorola,cpcap-rtc";
+
+                        interrupt-parent = <&cpcap>;
+                        interrupts = <39 IRQ_TYPE_NONE>, <26 IRQ_TYPE_NONE>;
+                };
+
+                power_button: button {
+                        compatible = "motorola,cpcap-pwrbutton";
+
+                        interrupts = <23 IRQ_TYPE_NONE>;
+                };
+
+                cpcap_usb2_phy: phy {
+                        compatible = "motorola,mapphone-cpcap-usb-phy";
+                        pinctrl-0 = <&usb_gpio_mux_sel1 &usb_gpio_mux_sel2>;
+                        pinctrl-1 = <&usb_ulpi_pins>;
+                        pinctrl-2 = <&usb_utmi_pins>;
+                        pinctrl-3 = <&uart3_pins>;
+                        pinctrl-names = "default", "ulpi", "utmi", "uart";
+                        #phy-cells = <0>;
+                        interrupts-extended = <
+                                &cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0
+                                &cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0
+                                &cpcap 48 1
+                        >;
+                        interrupt-names =
+                                "id_ground", "id_float", "se0conn", "vbusvld",
+                                "sessvld", "sessend", "se1", "dm", "dp";
+                        mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH
+                                      &gpio1 0 GPIO_ACTIVE_HIGH>;
+                        io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>;
+                        io-channel-names = "vbus", "id";
+                        vusb-supply = <&vusb>;
+                };
+
+                led_red: led-red {
+                        compatible = "motorola,cpcap-led-red";
+                        vdd-supply = <&sw5>;
+                        label = "status-led:red";
+                };
+
+                led_green: led-green {
+                        compatible = "motorola,cpcap-led-green";
+                        vdd-supply = <&sw5>;
+                        label = "status-led:green";
+                };
+
+                led_blue: led-blue {
+                        compatible = "motorola,cpcap-led-blue";
+                        vdd-supply = <&sw5>;
+                        label = "status-led:blue";
+                };
+
+                led_adl: led-adl {
+                        compatible = "motorola,cpcap-led-adl";
+                        vdd-supply = <&sw5>;
+                        label = "button-backlight";
+                };
+
+                led_cp: led-cp {
+                        compatible = "motorola,cpcap-led-cp";
+                        vdd-supply = <&sw5>;
+                        label = "shift-key-light";
+                };
+        };
+};
+
+&cpcap_regulators {
+        sw5: SW5 {
+                regulator-min-microvolt = <5050000>;
+                regulator-max-microvolt = <5050000>;
+                regulator-enable-ramp-delay = <50000>;
+                regulator-boot-on;
+        };
+
+        vcam: VCAM {
+                regulator-min-microvolt = <2900000>;
+                regulator-max-microvolt = <2900000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        /* Used by DSS */
+        vcsi: VCSI {
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-enable-ramp-delay = <1000>;
+                regulator-boot-on;
+        };
+
+        vdac: VDAC {
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        vdig: VDIG {
+                regulator-min-microvolt = <1875000>;
+                regulator-max-microvolt = <1875000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        vfuse: VFUSE {
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <3150000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        vhvio: VHVIO {
+                regulator-min-microvolt = <2775000>;
+                regulator-max-microvolt = <2775000>;
+                regulator-enable-ramp-delay = <1000>;
+                regulator-always-on;
+        };
+
+        /* Used by eMMC at mmc2 */
+        vsdio: VSDIO {
+                regulator-min-microvolt = <2900000>;
+                regulator-max-microvolt = <2900000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        vpll: VPLL {
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-enable-ramp-delay = <100>;
+        };
+
+        vrf1: VRF1 {
+                regulator-min-microvolt = <2775000>;
+                regulator-max-microvolt = <2775000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        vrf2: VRF2 {
+                regulator-min-microvolt = <2775000>;
+                regulator-max-microvolt = <2775000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        vrfref: VRFREF {
+                regulator-min-microvolt = <2500000>;
+                regulator-max-microvolt = <2775000>;
+                regulator-enable-ramp-delay = <100>;
+        };
+
+        vwlan1: VWLAN1 {
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1900000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        /* Used by micro-SDIO at mmc1 */
+        vwlan2: VWLAN2 {
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        vsim: VSIM {
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <2900000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        vsimcard: VSIMCARD {
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <2900000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        vvib: VVIB {
+                regulator-min-microvolt = <1300000>;
+                regulator-max-microvolt = <3000000>;
+                regulator-enable-ramp-delay = <500>;
+        };
+
+        vusb: VUSB {
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+
+        vaudio: VAUDIO {
+                regulator-min-microvolt = <2775000>;
+                regulator-max-microvolt = <2775000>;
+                regulator-enable-ramp-delay = <1000>;
+        };
+};
diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts
index 10d088df0c35..4a962a26482d 100644
--- a/arch/arm/boot/dts/moxart-uc7112lx.dts
+++ b/arch/arm/boot/dts/moxart-uc7112lx.dts
@@ -6,7 +6,7 @@
  */
 
 /dts-v1/;
-/include/ "moxart.dtsi"
+#include "moxart.dtsi"
 
 / {
         model = "MOXA UC-7112-LX";
diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi
index 1fd27ed65a01..e86f8c905ac5 100644
--- a/arch/arm/boot/dts/moxart.dtsi
+++ b/arch/arm/boot/dts/moxart.dtsi
@@ -6,6 +6,7 @@
  */
 
 /include/ "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         compatible = "moxa,moxart";
@@ -36,8 +37,8 @@
                 ranges;
 
                 intc: interrupt-controller@98800000 {
-                        compatible = "moxa,moxart-ic";
-                        reg = <0x98800000 0x38>;
+                        compatible = "moxa,moxart-ic", "faraday,ftintc010";
+                        reg = <0x98800000 0x100>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         interrupt-mask = <0x00080000>;
@@ -59,15 +60,15 @@
                 timer: timer@98400000 {
                         compatible = "moxa,moxart-timer";
                         reg = <0x98400000 0x42>;
-                        interrupts = <19 1>;
+                        interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
                         clocks = <&clk_apb>;
                 };
 
                 gpio: gpio@98700000 {
                         gpio-controller;
                         #gpio-cells = <2>;
-                        compatible = "moxa,moxart-gpio";
-                        reg = <0x98700000 0xC>;
+                        compatible = "moxa,moxart-gpio", "faraday,ftgpio010";
+                        reg = <0x98700000 0x100>;
                 };
 
                 rtc: rtc {
@@ -80,7 +81,7 @@
                 dma: dma@90500000 {
                         compatible = "moxa,moxart-dma";
                         reg = <0x90500080 0x40>;
-                        interrupts = <24 0>;
+                        interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
                         #dma-cells = <1>;
                 };
 
@@ -93,7 +94,7 @@
                 sdhci: sdhci@98e00000 {
                         compatible = "moxa,moxart-sdhci";
                         reg = <0x98e00000 0x5C>;
-                        interrupts = <5 0>;
+                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&clk_apb>;
                         dmas =  <&dma 5>,
                                 <&dma 5>;
@@ -120,7 +121,7 @@
                 mac0: mac@90900000 {
                         compatible = "moxa,moxart-mac";
                         reg = <0x90900000 0x90>;
-                        interrupts = <25 0>;
+                        interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
                         phy-handle = <&ethphy0>;
                         phy-mode = "mii";
                         status = "disabled";
@@ -129,7 +130,7 @@
                 mac1: mac@92000000 {
                         compatible = "moxa,moxart-mac";
                         reg = <0x92000000 0x90>;
-                        interrupts = <27 0>;
+                        interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
                         phy-handle = <&ethphy1>;
                         phy-mode = "mii";
                         status = "disabled";
@@ -138,7 +139,7 @@
                 uart0: uart@98200000 {
                         compatible = "ns16550a";
                         reg = <0x98200000 0x20>;
-                        interrupts = <31 8>;
+                        interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clock-frequency = <14745600>;
diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
new file mode 100644
index 000000000000..235ecfd61e2d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Device Tree Source for OMAP3 SoC CPU thermal
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+cpu_thermal: cpu_thermal {
+        polling-delay-passive = <250>; /* milliseconds */
+        polling-delay = <1000>; /* milliseconds */
+        coefficients = <0 20000>;
+
+                        /* sensor       ID */
+        thermal-sensors = <&bandgap     0>;
+};
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index e268efde6c6d..4ad7d5565906 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -37,6 +37,13 @@
 };
 
 &omap3_pmx_core {
+        gpmc_pins: pinmux_gpmc_pins {
+                pinctrl-single,pins = <
+                        /* OneNAND seems to require PIN_INPUT on clock. */
+                        OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0)        /* gpmc_clk.gpmc_clk */
+                >;
+        };
+
         uart1_pins: pinmux_uart1_pins {
                 pinctrl-single,pins = <
                         OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0)        /* uart1_rx.uart1_rx */
@@ -98,6 +105,9 @@
 };
 
 &gpmc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpmc_pins>;
+
         nand@0,0 {
                 compatible = "ti,omap2-nand";
                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
@@ -126,6 +136,48 @@
 
                 #address-cells = <1>;
                 #size-cells = <1>;
+
+                status = "okay";
+        };
+
+        onenand@0,0 {
+                compatible = "ti,omap2-onenand";
+                reg = <0 0 0x20000>;    /* CS0, offset 0, IO size 128K */
+
+                gpmc,sync-read;
+                gpmc,sync-write;
+                gpmc,burst-length = <16>;
+                gpmc,burst-read;
+                gpmc,burst-wrap;
+                gpmc,burst-write;
+                gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
+                gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <87>;
+                gpmc,cs-wr-off-ns = <87>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <10>;
+                gpmc,adv-wr-off-ns = <10>;
+                gpmc,oe-on-ns = <15>;
+                gpmc,oe-off-ns = <87>;
+                gpmc,we-on-ns = <0>;
+                gpmc,we-off-ns = <87>;
+                gpmc,rd-cycle-ns = <112>;
+                gpmc,wr-cycle-ns = <112>;
+                gpmc,access-ns = <81>;
+                gpmc,page-burst-access-ns = <15>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <5>;
+                gpmc,wr-data-mux-bus-ns = <30>;
+                gpmc,wr-access-ns = <81>;
+                gpmc,sync-clk-ps = <15000>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                status = "disabled";
         };
 };
 
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index b64cfda8dbb7..49f37084e435 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -155,6 +155,13 @@
                 compatible = "nokia,n900-ir";
                 pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
         };
+
+        /* controlled (enabled/disabled) directly by bcm2048 and wl1251 */
+        vctcxo: vctcxo {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <38400000>;
+        };
 };
 
 &omap3_pmx_core {
@@ -162,8 +169,10 @@
 
         uart2_pins: pinmux_uart2_pins {
                 pinctrl-single,pins = <
-                        OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)                /* uart2_rx */
+                        OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0)         /* uart2_cts */
+                        OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)               /* uart2_rts */
                         OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)               /* uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)                /* uart2_rx */
                 >;
         };
 
@@ -920,6 +929,8 @@
 
                 interrupt-parent = <&gpio2>;
                 interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */
+
+                clocks = <&vctcxo>;
         };
 };
 
@@ -937,9 +948,17 @@
 };
 
 &uart2 {
-        interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
         pinctrl-names = "default";
         pinctrl-0 = <&uart2_pins>;
+
+        bcm2048: bluetooth {
+                compatible = "brcm,bcm2048-nokia", "nokia,h4p-bluetooth";
+                reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; /* 91 */
+                host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */
+                bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */
+                clocks = <&vctcxo>;
+                clock-names = "sysclk";
+        };
 };
 
 &uart3 {
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 5d8c4b4a4205..df3366fa5409 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -58,6 +58,13 @@
                         pinctrl-0 = <&debug_leds>;
                 };
         };
+
+        /* controlled (enabled/disabled) directly by wl1271 */
+        vctcxo: vctcxo {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <38400000>;
+        };
 };
 
 &omap3_pmx_core {
@@ -125,6 +132,15 @@
                         OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4)            /* gpio_93 (cmt_apeslpx) */
                 >;
         };
+
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0)         /* uart2_cts */
+                        OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)               /* uart2_rts */
+                        OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)               /* uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)                /* uart2_rx */
+                >;
+        };
 };
 
 &omap3_pmx_core2 {
@@ -435,3 +451,19 @@
 &ssi_port2 {
         status = "disabled";
 };
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+
+        bluetooth {
+                compatible = "ti,wl1271-bluetooth-nokia", "nokia,h4p-bluetooth";
+
+                reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; /* 26 */
+                host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */
+                bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */
+
+                clocks = <&vctcxo>;
+                clock-names = "sysclk";
+        };
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 834fdf13601f..ac4f8795b756 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -14,7 +14,7 @@
 
 / {
         cpus {
-                cpu@0 {
+                cpu: cpu@0 {
                         /* OMAP343x/OMAP35xx variants OPP1-5 */
                         operating-points = <
                                 /* kHz    uV */
@@ -56,12 +56,16 @@
                         };
                 };
 
-                bandgap@48002524 {
+                bandgap: bandgap@48002524 {
                         reg = <0x48002524 0x4>;
                         compatible = "ti,omap34xx-bandgap";
                         #thermal-sensor-cells = <0>;
                 };
         };
+
+        thermal_zones: thermal-zones {
+                #include "omap3-cpu-thermal.dtsi"
+        };
 };
 
 &ssi {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index d1a3e56b50ce..ade31d74c70c 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -19,7 +19,7 @@
 
         cpus {
                 /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
-                cpu@0 {
+                cpu: cpu@0 {
                         operating-points = <
                                 /* kHz    uV */
                                 300000  1012500
@@ -88,12 +88,16 @@
                         };
                 };
 
-                bandgap@48002524 {
+                bandgap: bandgap@48002524 {
                         reg = <0x48002524 0x4>;
                         compatible = "ti,omap36xx-bandgap";
                         #thermal-sensor-cells = <0>;
                 };
         };
+
+        thermal_zones: thermal-zones {
+                #include "omap3-cpu-thermal.dtsi"
+        };
 };
 
 /* OMAP3630 needs dss_96m_fck for VENC */
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
index f3ccb4ceed9e..89eb607f4a9e 100644
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -5,7 +5,9 @@
  */
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "omap443x.dtsi"
+#include "motorola-cpcap-mapphone.dtsi"
 
 / {
         model = "Motorola Droid 4 XT894";
@@ -15,35 +17,76 @@
                 stdout-path = &uart3;
         };
 
+        aliases {
+                display0 = &lcd0;
+                display1 = &hdmi0;
+        };
+
         /*
          * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
-         * then 1023 - 1024 seems to contain mbm. For SRAM, see the notes
-         * below about SRAM and L3_ICLK2 being unused by default,
+         * then 1023 - 1024 seems to contain mbm.
          */
         memory {
                 device_type = "memory";
                 reg = <0x80000000 0x3fd00000>;  /* 1021 MB */
         };
 
-        /* CPCAP really supports 1650000 to 3400000 range */
-        vmmc: regulator-mmc {
+        /* Poweroff GPIO probably connected to CPCAP */
+        gpio-poweroff {
+                compatible = "gpio-poweroff";
+                pinctrl-0 = <&poweroff_gpio>;
+                pinctrl-names = "default";
+                gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;    /* gpio50 */
+        };
+
+        hdmi0: connector {
+                compatible = "hdmi-connector";
+                pinctrl-0 = <&hdmi_hpd_gpio>;
+                pinctrl-names = "default";
+                label = "hdmi";
+                type = "d";
+
+                hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;       /* gpio63 */
+
+                port {
+                        hdmi_connector_in: endpoint {
+                                remote-endpoint = <&hdmi_out>;
+                        };
+                };
+        };
+
+        /*
+         * HDMI 5V regulator probably sourced from battery. Let's keep
+         * keep this as always enabled for HDMI to work until we've
+         * figured what the encoder chip is.
+         */
+        hdmi_regulator: regulator-hdmi {
                 compatible = "regulator-fixed";
-                regulator-name = "vmmc";
-                regulator-min-microvolt = <3000000>;
-                regulator-max-microvolt = <3000000>;
+                regulator-name = "hdmi";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>;    /* gpio59 */
+                enable-active-high;
                 regulator-always-on;
         };
 
-        /* CPCAP really supports 3000000 to 3100000 range */
-        vemmc: regulator-emmc {
+        /* HS USB Host PHY on PORT 1 */
+        hsusb1_phy: hsusb1_phy {
+                compatible = "usb-nop-xceiv";
+        };
+
+        /* LCD regulator from sw5 source */
+        lcd_regulator: regulator-lcd {
                 compatible = "regulator-fixed";
-                regulator-name = "vemmc";
-                regulator-min-microvolt = <3000000>;
-                regulator-max-microvolt = <3000000>;
-                regulator-always-on;
+                regulator-name = "lcd";
+                regulator-min-microvolt = <5050000>;
+                regulator-max-microvolt = <5050000>;
+                gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;     /* gpio96 */
+                enable-active-high;
+                vin-supply = <&sw5>;
         };
 
-        /* CPCAP really supports 1650000 to 1950000 range */
+        /* This is probably coming straight from the battery.. */
         wl12xx_vmmc: regulator-wl12xx {
                 compatible = "regulator-fixed";
                 regulator-name = "vwl1271";
@@ -53,21 +96,195 @@
                 startup-delay-us = <70000>;
                 enable-active-high;
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                volume_down {
+                        label = "Volume Down";
+                        gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */
+                        linux,code = <KEY_VOLUMEDOWN>;
+                        linux,can-disable;
+                };
+
+                slider {
+                        label = "Keypad Slide";
+                        gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */
+                        linux,input-type = <EV_SW>;
+                        linux,code = <SW_KEYPAD_SLIDE>;
+                        linux,can-disable;
+
+                };
+        };
+};
+
+&dss {
+        status = "okay";
+};
+
+&gpio6 {
+        touchscreen_reset {
+                gpio-hog;
+                gpios = <13 0>;
+                output-high;
+                line-name = "touchscreen-reset";
+        };
+};
+
+&dsi1 {
+        status = "okay";
+        vdd-supply = <&vcsi>;
+
+        port {
+                dsi1_out_ep: endpoint {
+                        remote-endpoint = <&lcd0_in>;
+                        lanes = <0 1 2 3 4 5>;
+                };
+        };
+
+        lcd0: display {
+                compatible = "panel-dsi-cm";
+                label = "lcd0";
+                vddi-supply = <&lcd_regulator>;
+                reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;      /* gpio101 */
+
+                panel-timing {
+                        clock-frequency = <0>;          /* Calculated by dsi */
+
+                        hback-porch = <2>;
+                        hactive = <540>;
+                        hfront-porch = <0>;
+                        hsync-len = <2>;
+
+                        vback-porch = <1>;
+                        vactive = <960>;
+                        vfront-porch = <0>;
+                        vsync-len = <1>;
+
+                        hsync-active = <0>;
+                        vsync-active = <0>;
+                        de-active = <1>;
+                        pixelclk-active = <1>;
+                };
+
+                port {
+                        lcd0_in: endpoint {
+                                remote-endpoint = <&dsi1_out_ep>;
+                        };
+                };
+        };
 };
 
-/* L3_2 interconnect is unused, SRAM, GPMC and L3_ICLK2 disabled */
-&gpmc {
-        status = "disabled";
+&hdmi {
+        status = "okay";
+        pinctrl-0 = <&dss_hdmi_pins>;
+        pinctrl-names = "default";
+        vdda-supply = <&vdac>;
+
+        port {
+                hdmi_out: endpoint {
+                        remote-endpoint = <&hdmi_connector_in>;
+                        lanes = <1 0 3 2 5 4 7 6>;
+                };
+        };
+};
+
+&i2c1 {
+        tmp105@48 {
+                compatible = "ti,tmp105";
+                reg = <0x48>;
+                pinctrl-0 = <&tmp105_irq>;
+                pinctrl-names = "default";
+                /* kpd_row0.gpio_178 */
+                interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING
+                                       &omap4_pmx_core 0x14e>;
+                interrupt-names = "irq", "wakeup";
+                wakeup-source;
+        };
+};
+
+&keypad {
+        keypad,num-rows = <8>;
+        keypad,num-columns = <8>;
+        linux,keymap = <
+
+        /* Row 1 */
+        MATRIX_KEY(0, 2, KEY_1)
+        MATRIX_KEY(0, 6, KEY_2)
+        MATRIX_KEY(2, 3, KEY_3)
+        MATRIX_KEY(0, 7, KEY_4)
+        MATRIX_KEY(0, 4, KEY_5)
+        MATRIX_KEY(5, 5, KEY_6)
+        MATRIX_KEY(0, 1, KEY_7)
+        MATRIX_KEY(0, 5, KEY_8)
+        MATRIX_KEY(0, 0, KEY_9)
+        MATRIX_KEY(1, 6, KEY_0)
+
+        /* Row 2 */
+        MATRIX_KEY(3, 4, KEY_APOSTROPHE)
+        MATRIX_KEY(7, 6, KEY_Q)
+        MATRIX_KEY(7, 7, KEY_W)
+        MATRIX_KEY(7, 2, KEY_E)
+        MATRIX_KEY(1, 0, KEY_R)
+        MATRIX_KEY(4, 4, KEY_T)
+        MATRIX_KEY(1, 2, KEY_Y)
+        MATRIX_KEY(6, 7, KEY_U)
+        MATRIX_KEY(2, 2, KEY_I)
+        MATRIX_KEY(5, 6, KEY_O)
+        MATRIX_KEY(3, 7, KEY_P)
+        MATRIX_KEY(6, 5, KEY_BACKSPACE)
+
+        /* Row 3 */
+        MATRIX_KEY(5, 4, KEY_TAB)
+        MATRIX_KEY(5, 7, KEY_A)
+        MATRIX_KEY(2, 7, KEY_S)
+        MATRIX_KEY(7, 0, KEY_D)
+        MATRIX_KEY(2, 6, KEY_F)
+        MATRIX_KEY(6, 2, KEY_G)
+        MATRIX_KEY(6, 6, KEY_H)
+        MATRIX_KEY(1, 4, KEY_J)
+        MATRIX_KEY(3, 1, KEY_K)
+        MATRIX_KEY(2, 1, KEY_L)
+        MATRIX_KEY(4, 6, KEY_ENTER)
+
+        /* Row 4 */
+        MATRIX_KEY(3, 6, KEY_LEFTSHIFT)         /* KEY_CAPSLOCK */
+        MATRIX_KEY(6, 1, KEY_Z)
+        MATRIX_KEY(7, 4, KEY_X)
+        MATRIX_KEY(5, 1, KEY_C)
+        MATRIX_KEY(1, 7, KEY_V)
+        MATRIX_KEY(2, 4, KEY_B)
+        MATRIX_KEY(4, 1, KEY_N)
+        MATRIX_KEY(1, 1, KEY_M)
+        MATRIX_KEY(3, 5, KEY_COMMA)
+        MATRIX_KEY(5, 2, KEY_DOT)
+        MATRIX_KEY(6, 3, KEY_UP)
+        MATRIX_KEY(7, 3, KEY_OK)
+
+        /* Row 5 */
+        MATRIX_KEY(2, 5, KEY_LEFTCTRL)          /* KEY_LEFTSHIFT */
+        MATRIX_KEY(4, 5, KEY_LEFTALT)           /* SYM */
+        MATRIX_KEY(6, 0, KEY_MINUS)
+        MATRIX_KEY(4, 7, KEY_EQUAL)
+        MATRIX_KEY(1, 5, KEY_SPACE)
+        MATRIX_KEY(3, 2, KEY_SLASH)
+        MATRIX_KEY(4, 3, KEY_LEFT)
+        MATRIX_KEY(5, 3, KEY_DOWN)
+        MATRIX_KEY(3, 3, KEY_RIGHT)
+
+        /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */
+        MATRIX_KEY(5, 0, KEY_VOLUMEUP)
+        >;
 };
 
 &mmc1 {
-        vmmc-supply = <&vmmc>;
+        vmmc-supply = <&vwlan2>;
         bus-width = <4>;
-        cd-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; /* gpio106 */
+        cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */
 };
 
 &mmc2 {
-        vmmc-supply = <&vemmc>;
+        vmmc-supply = <&vsdio>;
         bus-width = <8>;
         non-removable;
 };
@@ -93,12 +310,78 @@
         };
 };
 
-/* L3_2 interconnect is unused, SRAM, GPMC and L3_ICLK2 disabled */
-&ocmcram {
-        status = "disabled";
+&i2c1 {
+        lm3532@38 {
+                compatible = "ti,lm3532";
+                reg = <0x38>;
+
+                enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
+
+                backlight {
+                        compatible = "ti,lm3532-backlight";
+
+                        lcd {
+                                led-sources = <0 1 2>;
+                                ramp-up-msec = <1>;
+                                ramp-down-msec = <0>;
+                        };
+                };
+        };
+};
+
+/*
+ * REVISIT: Add gpio173 reset pin handling to the driver, see gpio-hog above.
+ * If the GPIO reset is used, we probably need to have /lib/firmware/maxtouch.fw
+ * available. See "mxt-app" and "droid4-touchscreen-firmware" tools for more
+ * information.
+ */
+&i2c2 {
+        tsp@4a {
+                compatible = "atmel,maxtouch";
+                reg = <0x4a>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&touchscreen_pins>;
+
+                /* gpio_183 with sys_nirq2 pad as wakeup */
+                interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING
+                                       &omap4_pmx_core 0x160>;
+                interrupt-names = "irq", "wakeup";
+                wakeup-source;
+        };
 };
 
 &omap4_pmx_core {
+
+        /* hdmi_hpd.gpio_63 */
+        hdmi_hpd_gpio: pinmux_hdmi_hpd_pins {
+                pinctrl-single,pins = <
+                OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3)
+                >;
+        };
+
+        /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */
+        dss_hdmi_pins: pinmux_dss_hdmi_pins {
+                pinctrl-single,pins = <
+                OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0)
+                OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0)
+                OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0)
+                >;
+        };
+
+        /* gpmc_ncs0.gpio_50 */
+        poweroff_gpio: pinmux_poweroff_pins {
+                pinctrl-single,pins = <
+                OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3)
+                >;
+        };
+
+        /* kpd_row0.gpio_178 */
+        tmp105_irq: pinmux_tmp105_irq {
+                pinctrl-single,pins = <
+                OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3)
+                >;
+        };
+
         usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins {
                 /* gpio_60 */
                 pinctrl-single,pins = <
@@ -106,6 +389,12 @@
                 >;
         };
 
+        touchscreen_pins: pinmux_touchscreen_pins {
+                pinctrl-single,pins = <
+                OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3)
+                >;
+        };
+
         usb_ulpi_pins: pinmux_usb_ulpi_pins {
                 pinctrl-single,pins = <
                 OMAP4_IOPAD(0x196, MUX_MODE7)
@@ -180,9 +469,49 @@
                                &omap4_pmx_core 0x17c>;
 };
 
+&usbhsehci {
+        phys = <&hsusb1_phy>;
+};
+
+&usbhshost {
+        port1-mode = "ohci-phy-4pin-dpdm";
+        port2-mode = "ehci-tll";
+};
+
 /* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */
 &usb_otg_hs {
         interface-type = <1>;
         mode = <3>;
         power = <50>;
 };
+
+&i2c4 {
+        ak8975: magnetometer@c {
+                compatible = "asahi-kasei,ak8975";
+                reg = <0x0c>;
+
+                vdd-supply = <&vhvio>;
+
+                interrupt-parent = <&gpio6>;
+                interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */
+
+                rotation-matrix = "-1", "0", "0",
+                                  "0", "1", "0",
+                                  "0", "0", "-1";
+
+        };
+
+        lis3dh: accelerometer@18 {
+                compatible = "st,lis3dh-accel";
+                reg = <0x18>;
+
+                vdd-supply = <&vhvio>;
+
+                interrupt-parent = <&gpio2>;
+                interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */
+
+                rotation-matrix = "0", "-1", "0",
+                                  "1", "0", "0",
+                                  "0", "0", "1";
+        };
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index fc6a8610c24c..03c8ad91ddac 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -71,4 +71,8 @@
 
 };
 
+&cpu_thermal {
+        coefficients = <0 20000>;
+};
+
 /include/ "omap443x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index ef66e12e0a67..c43f2a2d0a1e 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -90,4 +90,8 @@
 
 };
 
+&cpu_thermal {
+        coefficients = <348 (-9301)>;
+};
+
 /include/ "omap446x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 222155ca8ad7..eaff2a5751dd 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -1127,6 +1127,15 @@
 
 &cpu_thermal {
         polling-delay = <500>; /* milliseconds */
+        coefficients = <65 (-1791)>;
 };
 
 /include/ "omap54xx-clocks.dtsi"
+
+&gpu_thermal {
+        coefficients = <117 (-2992)>;
+};
+
+&core_thermal {
+        coefficients = <0 2000>;
+};
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
index 39d9e6ddefed..2da1413f5720 100644
--- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -95,17 +95,17 @@
                                              function = "sdc1";
                                 };
                                 clk {
-                                        pins = "gpio167"; /* SDC5 CLK */
+                                        pins = "gpio167"; /* SDC1 CLK */
                                         drive-strength = <16>;
                                         bias-disable;
                                 };
                                 cmd {
-                                        pins = "gpio168"; /* SDC5 CMD */
+                                        pins = "gpio168"; /* SDC1 CMD */
                                         drive-strength = <10>;
                                         bias-pull-up;
                                 };
                                 data {
-                                        /* SDC5 D0 to D7 */
+                                        /* SDC1 D0 to D7 */
                                         pins = "gpio159", "gpio160", "gpio161", "gpio162",
                                              "gpio163", "gpio164", "gpio165", "gpio166";
                                         drive-strength = <10>;
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 91c9a62ae725..747669a62aa8 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -392,6 +392,21 @@
                                 cap-mmc-highspeed;
                         };
 
+                        sdcc2: sdcc@12140000 {
+                                status          = "disabled";
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                reg             = <0x12140000 0x8000>;
+                                interrupts      = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <8>;
+                                max-frequency   = <48000000>;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                        };
+
                         sdcc3: sdcc@12180000 {
                                 compatible      = "arm,pl18x", "arm,primecell";
                                 arm,primecell-periphid = <0x00051180>;
@@ -408,6 +423,21 @@
                                 no-1-8-v;
                         };
 
+                        sdcc4: sdcc@121c0000 {
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                status          = "disabled";
+                                reg             = <0x121c0000 0x8000>;
+                                interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <4>;
+                                max-frequency   = <48000000>;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                        };
+
                         sdcc5: sdcc@12200000 {
                                 compatible      = "arm,pl18x", "arm,primecell";
                                 arm,primecell-periphid = <0x00051180>;
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
index 96c853bab8ba..e7c1577d56f4 100644
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
@@ -413,14 +413,6 @@
         dma-controller@f9944000 {
                 qcom,controlled-remotely;
         };
-
-        usb-phy@f9a55000 {
-                status = "ok";
-        };
-
-        usb@f9a55000 {
-                status = "ok";
-        };
 };
 
 &spmi_bus {
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index d3e1a61b8671..307bf6a647b3 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -2,8 +2,8 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/reset/qcom,gcc-msm8974.h>
 #include "skeleton.dtsi"
 
 / {
@@ -67,7 +67,7 @@
                 #size-cells = <0>;
                 interrupts = <1 9 0xf04>;
 
-                cpu@0 {
+                CPU0: cpu@0 {
                         compatible = "qcom,krait";
                         enable-method = "qcom,kpss-acc-v2";
                         device_type = "cpu";
@@ -78,7 +78,7 @@
                         cpu-idle-states = <&CPU_SPC>;
                 };
 
-                cpu@1 {
+                CPU1: cpu@1 {
                         compatible = "qcom,krait";
                         enable-method = "qcom,kpss-acc-v2";
                         device_type = "cpu";
@@ -89,7 +89,7 @@
                         cpu-idle-states = <&CPU_SPC>;
                 };
 
-                cpu@2 {
+                CPU2: cpu@2 {
                         compatible = "qcom,krait";
                         enable-method = "qcom,kpss-acc-v2";
                         device_type = "cpu";
@@ -100,7 +100,7 @@
                         cpu-idle-states = <&CPU_SPC>;
                 };
 
-                cpu@3 {
+                CPU3: cpu@3 {
                         compatible = "qcom,krait";
                         enable-method = "qcom,kpss-acc-v2";
                         device_type = "cpu";
@@ -250,6 +250,9 @@
 
                 cx-supply = <&pm8841_s2>;
 
+                clocks = <&xo_board>;
+                clock-names = "xo";
+
                 memory-region = <&adsp_region>;
 
                 qcom,smem-states = <&adsp_smp2p_out 0>;
@@ -695,42 +698,276 @@
                         qcom,ee = <0>;
                 };
 
-                usb1_phy: usb-phy@f9a55000 {
-                        compatible = "qcom,usb-otg-snps";
+                etr@fc322000 {
+                        compatible = "arm,coresight-tmc", "arm,primecell";
+                        reg = <0xfc322000 0x1000>;
 
-                        reg = <0xf9a55000 0x400>;
-                        interrupts-extended = <&intc 0 134 0>, <&intc 0 140 0>,
-                                <&spmi_bus 0 0x9 0 0>;
-                        interrupt-names = "core_irq", "async_irq", "pmic_id_irq";
+                        clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+                        clock-names = "apb_pclk", "atclk";
 
-                        vddcx-supply = <&pm8841_s2>;
-                        v3p3-supply = <&pm8941_l24>;
-                        v1p8-supply = <&pm8941_l6>;
+                        port {
+                                etr_in: endpoint {
+                                        slave-mode;
+                                        remote-endpoint = <&replicator_out0>;
+                                };
+                        };
+                };
 
-                        dr_mode = "otg";
-                        qcom,phy-init-sequence = <0x63 0x81 0xfffffff>;
-                        qcom,otg-control = <1>;
-                        qcom,phy-num = <0>;
+                tpiu@fc318000 {
+                        compatible = "arm,coresight-tpiu", "arm,primecell";
+                        reg = <0xfc318000 0x1000>;
 
-                        resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
-                        reset-names = "phy", "link";
+                        clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+                        clock-names = "apb_pclk", "atclk";
 
-                        clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
-                                <&gcc GCC_USB_HS_AHB_CLK>;
-                        clock-names = "phy", "core", "iface";
+                        port {
+                                tpiu_in: endpoint {
+                                         slave-mode;
+                                         remote-endpoint = <&replicator_out1>;
+                                 };
+                        };
+                };
 
-                        status = "disabled";
+                replicator@fc31c000 {
+                        compatible = "qcom,coresight-replicator1x", "arm,primecell";
+                        reg = <0xfc31c000 0x1000>;
+
+                        clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+                        clock-names = "apb_pclk", "atclk";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        replicator_out0: endpoint {
+                                                remote-endpoint = <&etr_in>;
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        replicator_out1: endpoint {
+                                                remote-endpoint = <&tpiu_in>;
+                                        };
+                                };
+                                port@2 {
+                                        reg = <0>;
+                                        replicator_in: endpoint {
+                                                slave-mode;
+                                                remote-endpoint = <&etf_out>;
+                                        };
+                                };
+                        };
                 };
 
-                usb@f9a55000 {
-                        compatible = "qcom,ci-hdrc";
-                        reg = <0xf9a55000 0x400>;
-                        dr_mode = "otg";
-                        interrupts = <0 134 0>, <0 140 0>;
-                        interrupt-names = "core_irq", "async_irq";
-                        usb-phy = <&usb1_phy>;
+                etf@fc307000 {
+                        compatible = "arm,coresight-tmc", "arm,primecell";
+                        reg = <0xfc307000 0x1000>;
 
-                        status = "disabled";
+                        clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+                        clock-names = "apb_pclk", "atclk";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        etf_out: endpoint {
+                                                remote-endpoint = <&replicator_in>;
+                                        };
+                                };
+                                port@1 {
+                                        reg = <0>;
+                                        etf_in: endpoint {
+                                                slave-mode;
+                                                remote-endpoint = <&merger_out>;
+                                        };
+                                };
+                        };
+                };
+
+                funnel@fc31b000 {
+                        compatible = "arm,coresight-funnel", "arm,primecell";
+                        reg = <0xfc31b000 0x1000>;
+
+                        clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+                        clock-names = "apb_pclk", "atclk";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                /*
+                                 * Not described input ports:
+                                 * 0 - connected trought funnel to Audio, Modem and
+                                 *     Resource and Power Manager CPU's
+                                 * 2...7 - not-connected
+                                 */
+                                port@1 {
+                                        reg = <1>;
+                                        merger_in1: endpoint {
+                                                slave-mode;
+                                                remote-endpoint = <&funnel1_out>;
+                                        };
+                                };
+                                port@8 {
+                                        reg = <0>;
+                                        merger_out: endpoint {
+                                                remote-endpoint = <&etf_in>;
+                                        };
+                                };
+                        };
+                };
+
+                funnel@fc31a000 {
+                        compatible = "arm,coresight-funnel", "arm,primecell";
+                        reg = <0xfc31a000 0x1000>;
+
+                        clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+                        clock-names = "apb_pclk", "atclk";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                /*
+                                 * Not described input ports:
+                                 * 0 - not-connected
+                                 * 1 - connected trought funnel to Multimedia CPU
+                                 * 2 - connected to Wireless CPU
+                                 * 3 - not-connected
+                                 * 4 - not-connected
+                                 * 6 - not-connected
+                                 * 7 - connected to STM
+                                 */
+                                port@5 {
+                                        reg = <5>;
+                                        funnel1_in5: endpoint {
+                                                slave-mode;
+                                                remote-endpoint = <&kpss_out>;
+                                        };
+                                };
+                                port@8 {
+                                        reg = <0>;
+                                        funnel1_out: endpoint {
+                                                remote-endpoint = <&merger_in1>;
+                                        };
+                                };
+                        };
+                };
+
+                funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
+                        compatible = "arm,coresight-funnel", "arm,primecell";
+                        reg = <0xfc345000 0x1000>;
+
+                        clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+                        clock-names = "apb_pclk", "atclk";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        kpss_in0: endpoint {
+                                                slave-mode;
+                                                remote-endpoint = <&etm0_out>;
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        kpss_in1: endpoint {
+                                                slave-mode;
+                                                remote-endpoint = <&etm1_out>;
+                                        };
+                                };
+                                port@2 {
+                                        reg = <2>;
+                                        kpss_in2: endpoint {
+                                                slave-mode;
+                                                remote-endpoint = <&etm2_out>;
+                                        };
+                                };
+                                port@3 {
+                                        reg = <3>;
+                                        kpss_in3: endpoint {
+                                                slave-mode;
+                                                remote-endpoint = <&etm3_out>;
+                                        };
+                                };
+                                port@8 {
+                                        reg = <0>;
+                                        kpss_out: endpoint {
+                                                remote-endpoint = <&funnel1_in5>;
+                                        };
+                                };
+                        };
+                };
+
+                etm@fc33c000 {
+                        compatible = "arm,coresight-etm4x", "arm,primecell";
+                        reg = <0xfc33c000 0x1000>;
+
+                        clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+                        clock-names = "apb_pclk", "atclk";
+
+                        cpu = <&CPU0>;
+
+                        port {
+                                etm0_out: endpoint {
+                                        remote-endpoint = <&kpss_in0>;
+                                };
+                        };
+                };
+
+                etm@fc33d000 {
+                        compatible = "arm,coresight-etm4x", "arm,primecell";
+                        reg = <0xfc33d000 0x1000>;
+
+                        clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+                        clock-names = "apb_pclk", "atclk";
+
+                        cpu = <&CPU1>;
+
+                        port {
+                                etm1_out: endpoint {
+                                        remote-endpoint = <&kpss_in1>;
+                                };
+                        };
+                };
+
+                etm@fc33e000 {
+                        compatible = "arm,coresight-etm4x", "arm,primecell";
+                        reg = <0xfc33e000 0x1000>;
+
+                        clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+                        clock-names = "apb_pclk", "atclk";
+
+                        cpu = <&CPU2>;
+
+                        port {
+                                etm2_out: endpoint {
+                                        remote-endpoint = <&kpss_in2>;
+                                };
+                        };
+                };
+
+                etm@fc33f000 {
+                        compatible = "arm,coresight-etm4x", "arm,primecell";
+                        reg = <0xfc33f000 0x1000>;
+
+                        clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+                        clock-names = "apb_pclk", "atclk";
+
+                        cpu = <&CPU3>;
+
+                        port {
+                                etm3_out: endpoint {
+                                        remote-endpoint = <&kpss_in3>;
+                                };
+                        };
                 };
         };
 
@@ -760,6 +997,11 @@
                                 compatible = "qcom,rpm-msm8974";
                                 qcom,smd-channels = "rpm_requests";
 
+                                rpmcc: clock-controller {
+                                        compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
+                                        #clock-cells = <1>;
+                                };
+
                                 pm8841-regulators {
                                         compatible = "qcom,rpm-pm8841-regulators";
 
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 118a8e2b86bd..52a7b586bac7 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -44,6 +44,10 @@
         clock-frequency = <48000000>;
 };
 
+&rtc_x1_clk {
+        clock-frequency = <32768>;
+};
+
 &mtu2 {
         status = "okay";
 };
@@ -59,6 +63,10 @@
         };
 };
 
+&rtc {
+        status = "okay";
+};
+
 &scif2 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index 02b59c5b3c53..72df20a04320 100644
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -43,6 +43,10 @@
         clock-frequency = <48000000>;
 };
 
+&rtc_x1_clk {
+        clock-frequency = <32768>;
+};
+
 &mtu2 {
         status = "okay";
 };
@@ -69,6 +73,10 @@
         status = "okay";
 };
 
+&rtc {
+        status = "okay";
+};
+
 &scif2 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 1cf2bd038090..0423996e4dcc 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -51,6 +51,20 @@
                         clock-frequency = <0>;
                 };
 
+                rtc_x1_clk: rtc_x1 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        /* If clk present, value must be set by board to 32678 */
+                        clock-frequency = <0>;
+                };
+
+                rtc_x3_clk: rtc_x3 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        /* If clk present, value must be set by board to 4000000 */
+                        clock-frequency = <0>;
+                };
+
                 /* Fixed factor clocks */
                 b_clk: b {
                         #clock-cells = <0>;
@@ -117,11 +131,20 @@
                         clock-output-names = "ostm0", "ostm1";
                 };
 
+                mstp6_clks: mstp6_clks@fcfe042c {
+                        #clock-cells = <1>;
+                        compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xfcfe042c 4>;
+                        clocks = <&p0_clk>;
+                        clock-indices = <R7S72100_CLK_RTC>;
+                        clock-output-names = "rtc";
+                };
+
                 mstp7_clks: mstp7_clks@fcfe0430 {
                         #clock-cells = <1>;
                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0xfcfe0430 4>;
-                        clocks = <&p0_clk>;
+                        clocks = <&b_clk>;
                         clock-indices = <R7S72100_CLK_ETHER>;
                         clock-output-names = "ether";
                 };
@@ -162,9 +185,12 @@
                         #clock-cells = <1>;
                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0xfcfe0444 4>;
-                        clocks = <&p1_clk>, <&p1_clk>;
-                        clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>;
-                        clock-output-names = "sdhi1", "sdhi0";
+                        clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
+                        clock-indices = <
+                                R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
+                                R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
+                        >;
+                        clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
                 };
         };
 
@@ -379,6 +405,13 @@
                 cache-level = <2>;
         };
 
+        wdt: watchdog@fcfe0000 {
+                compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
+                reg = <0xfcfe0000 0x6>;
+                interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
+                clocks = <&p0_clk>;
+        };
+
         i2c0: i2c@fcfee000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -499,7 +532,10 @@
                               GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
                               GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 
-                clocks = <&mstp12_clks R7S72100_CLK_SDHI0>;
+                clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
+                         <&mstp12_clks R7S72100_CLK_SDHI01>;
+                clock-names = "core", "cd";
+                power-domains = <&cpg_clocks>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -512,7 +548,10 @@
                               GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
                               GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
 
-                clocks = <&mstp12_clks R7S72100_CLK_SDHI1>;
+                clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
+                         <&mstp12_clks R7S72100_CLK_SDHI11>;
+                clock-names = "core", "cd";
+                power-domains = <&cpg_clocks>;
                 cap-sd-highspeed;
                 cap-sdio-irq;
                 status = "disabled";
@@ -535,4 +574,18 @@
                 power-domains = <&cpg_clocks>;
                 status = "disabled";
         };
+
+        rtc: rtc@fcff1000 {
+                compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
+                reg = <0xfcff1000 0x2e>;
+                interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
+                              GIC_SPI 277 IRQ_TYPE_EDGE_RISING
+                              GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
+                interrupt-names = "alarm", "period", "carry";
+                clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
+                         <&rtc_x3_clk>, <&extal_clk>;
+                clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
+                power-domains = <&cpg_clocks>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 00eb9a7114dc..1f5c9f6dddba 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -32,18 +32,16 @@
                         next-level-cache = <&L2_CA15>;
                 };
 
-                L2_CA15: cache-controller@0 {
+                L2_CA15: cache-controller-0 {
                         compatible = "cache";
-                        reg = <0>;
                         clocks = <&cpg_clocks R8A73A4_CLK_Z>;
                         power-domains = <&pd_a3sm>;
                         cache-unified;
                         cache-level = <2>;
                 };
 
-                L2_CA7: cache-controller@100 {
+                L2_CA7: cache-controller-1 {
                         compatible = "cache";
-                        reg = <0x100>;
                         clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
                         power-domains = <&pd_a3km>;
                         cache-unified;
@@ -469,6 +467,9 @@
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
+                clock-names = "clk";
+                power-domains = <&pd_c4>;
         };
 
         bsc: bus@fec10000 {
@@ -727,16 +728,18 @@
                 mstp4_clks: mstp4_clks@e6150140 {
                         compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
-                        clocks = <&main_div2_clk>, <&main_div2_clk>,
+                        clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
+                                 <&main_div2_clk>,
                                  <&cpg_clocks R8A73A4_CLK_HP>,
                                  <&cpg_clocks R8A73A4_CLK_HP>;
                         #clock-cells = <1>;
                         clock-indices = <
-                                R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5
-                                R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3
+                                R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
+                                R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
+                                R8A73A4_CLK_IIC3
                         >;
                         clock-output-names =
-                                "irqc", "iic5", "iic4", "iic3";
+                                "irqc", "intc-sys", "iic5", "iic4", "iic3";
                 };
                 mstp5_clks: mstp5_clks@e6150144 {
                         compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index d8393b97768b..0ddac81742e4 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -32,9 +32,8 @@
                         next-level-cache = <&L2_CA15>;
                 };
 
-                L2_CA15: cache-controller@0 {
+                L2_CA15: cache-controller-0 {
                         compatible = "cache";
-                        reg = <0>;
                         cache-unified;
                         cache-level = <2>;
                         power-domains = <&sysc R8A7743_PD_CA15_SCU>;
@@ -63,6 +62,7 @@
                         clocks = <&cpg CPG_MOD 408>;
                         clock-names = "clk";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 408>;
                 };
 
                 irqc: interrupt-controller@e61c0000 {
@@ -82,6 +82,7 @@
                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 407>;
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 407>;
                 };
 
                 timer {
@@ -103,6 +104,7 @@
                         clock-names = "extal", "usb_extal";
                         #clock-cells = <2>;
                         #power-domain-cells = <0>;
+                        #reset-cells = <1>;
                 };
 
                 prr: chipid@ff000044 {
@@ -149,6 +151,7 @@
                         clocks = <&cpg CPG_MOD 219>;
                         clock-names = "fck";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 219>;
                         #dma-cells = <1>;
                         dma-channels = <15>;
                 };
@@ -181,6 +184,7 @@
                         clocks = <&cpg CPG_MOD 218>;
                         clock-names = "fck";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 218>;
                         #dma-cells = <1>;
                         dma-channels = <15>;
                 };
@@ -196,6 +200,7 @@
                                <&dmac1 0x21>, <&dmac1 0x22>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 204>;
                         status = "disabled";
                 };
 
@@ -210,6 +215,7 @@
                                <&dmac1 0x25>, <&dmac1 0x26>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 203>;
                         status = "disabled";
                 };
 
@@ -224,6 +230,7 @@
                                <&dmac1 0x27>, <&dmac1 0x28>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 202>;
                         status = "disabled";
                 };
 
@@ -238,6 +245,7 @@
                                <&dmac1 0x1b>, <&dmac1 0x1c>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 1106>;
                         status = "disabled";
                 };
 
@@ -252,6 +260,7 @@
                                <&dmac1 0x1f>, <&dmac1 0x20>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 1107>;
                         status = "disabled";
                 };
 
@@ -266,6 +275,7 @@
                                <&dmac1 0x23>, <&dmac1 0x24>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 1108>;
                         status = "disabled";
                 };
 
@@ -277,9 +287,10 @@
                         clocks = <&cpg CPG_MOD 206>;
                         clock-names = "fck";
                         dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
-                       <&dmac1 0x3d>, <&dmac1 0x3e>;
+                               <&dmac1 0x3d>, <&dmac1 0x3e>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 206>;
                         status = "disabled";
                 };
 
@@ -294,6 +305,7 @@
                                <&dmac1 0x19>, <&dmac1 0x1a>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 207>;
                         status = "disabled";
                 };
 
@@ -308,6 +320,7 @@
                                <&dmac1 0x1d>, <&dmac1 0x1e>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 216>;
                         status = "disabled";
                 };
 
@@ -323,6 +336,7 @@
                                <&dmac1 0x29>, <&dmac1 0x2a>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 721>;
                         status = "disabled";
                 };
 
@@ -338,6 +352,7 @@
                                <&dmac1 0x2d>, <&dmac1 0x2e>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 720>;
                         status = "disabled";
                 };
 
@@ -353,6 +368,7 @@
                                <&dmac1 0x2b>, <&dmac1 0x2c>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 719>;
                         status = "disabled";
                 };
 
@@ -368,6 +384,7 @@
                                <&dmac1 0x2f>, <&dmac1 0x30>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 718>;
                         status = "disabled";
                 };
 
@@ -383,6 +400,7 @@
                                <&dmac1 0xfb>, <&dmac1 0xfc>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 715>;
                         status = "disabled";
                 };
 
@@ -398,6 +416,7 @@
                                <&dmac1 0xfd>, <&dmac1 0xfe>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 714>;
                         status = "disabled";
                 };
 
@@ -413,6 +432,7 @@
                                <&dmac1 0x39>, <&dmac1 0x3a>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 717>;
                         status = "disabled";
                 };
 
@@ -428,6 +448,7 @@
                                <&dmac1 0x4d>, <&dmac1 0x4e>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 716>;
                         status = "disabled";
                 };
 
@@ -443,6 +464,7 @@
                                <&dmac1 0x3b>, <&dmac1 0x3c>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 713>;
                         status = "disabled";
                 };
 
@@ -452,6 +474,7 @@
                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 813>;
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 813>;
                         phy-mode = "rmii";
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 1f65ff68a469..2feb0084bb3b 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -32,9 +32,8 @@
                         next-level-cache = <&L2_CA7>;
                 };
 
-                L2_CA7: cache-controller@0 {
+                L2_CA7: cache-controller-0 {
                         compatible = "cache";
-                        reg = <0>;
                         cache-unified;
                         cache-level = <2>;
                         power-domains = <&sysc R8A7745_PD_CA7_SCU>;
@@ -63,6 +62,7 @@
                         clocks = <&cpg CPG_MOD 408>;
                         clock-names = "clk";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 408>;
                 };
 
                 irqc: interrupt-controller@e61c0000 {
@@ -82,6 +82,7 @@
                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 407>;
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 407>;
                 };
 
                 timer {
@@ -103,6 +104,7 @@
                         clock-names = "extal", "usb_extal";
                         #clock-cells = <2>;
                         #power-domain-cells = <0>;
+                        #reset-cells = <1>;
                 };
 
                 prr: chipid@ff000044 {
@@ -149,6 +151,7 @@
                         clocks = <&cpg CPG_MOD 219>;
                         clock-names = "fck";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 219>;
                         #dma-cells = <1>;
                         dma-channels = <15>;
                 };
@@ -181,6 +184,7 @@
                         clocks = <&cpg CPG_MOD 218>;
                         clock-names = "fck";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 218>;
                         #dma-cells = <1>;
                         dma-channels = <15>;
                 };
@@ -196,6 +200,7 @@
                                <&dmac1 0x21>, <&dmac1 0x22>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 204>;
                         status = "disabled";
                 };
 
@@ -210,6 +215,7 @@
                                <&dmac1 0x25>, <&dmac1 0x26>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 203>;
                         status = "disabled";
                 };
 
@@ -224,6 +230,7 @@
                                <&dmac1 0x27>, <&dmac1 0x28>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 202>;
                         status = "disabled";
                 };
 
@@ -238,6 +245,7 @@
                                <&dmac1 0x1b>, <&dmac1 0x1c>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 1106>;
                         status = "disabled";
                 };
 
@@ -252,6 +260,7 @@
                                <&dmac1 0x1f>, <&dmac1 0x20>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 1107>;
                         status = "disabled";
                 };
 
@@ -266,6 +275,7 @@
                                <&dmac1 0x23>, <&dmac1 0x24>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 1108>;
                         status = "disabled";
                 };
 
@@ -277,9 +287,10 @@
                         clocks = <&cpg CPG_MOD 206>;
                         clock-names = "fck";
                         dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
-                       <&dmac1 0x3d>, <&dmac1 0x3e>;
+                               <&dmac1 0x3d>, <&dmac1 0x3e>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 206>;
                         status = "disabled";
                 };
 
@@ -294,6 +305,7 @@
                                <&dmac1 0x19>, <&dmac1 0x1a>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 207>;
                         status = "disabled";
                 };
 
@@ -308,6 +320,7 @@
                                <&dmac1 0x1d>, <&dmac1 0x1e>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 216>;
                         status = "disabled";
                 };
 
@@ -323,6 +336,7 @@
                                <&dmac1 0x29>, <&dmac1 0x2a>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 721>;
                         status = "disabled";
                 };
 
@@ -338,6 +352,7 @@
                                <&dmac1 0x2d>, <&dmac1 0x2e>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 720>;
                         status = "disabled";
                 };
 
@@ -353,6 +368,7 @@
                                <&dmac1 0x2b>, <&dmac1 0x2c>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 719>;
                         status = "disabled";
                 };
 
@@ -368,6 +384,7 @@
                                <&dmac1 0x2f>, <&dmac1 0x30>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 718>;
                         status = "disabled";
                 };
 
@@ -383,6 +400,7 @@
                                <&dmac1 0xfb>, <&dmac1 0xfc>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 715>;
                         status = "disabled";
                 };
 
@@ -398,6 +416,7 @@
                                <&dmac1 0xfd>, <&dmac1 0xfe>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 714>;
                         status = "disabled";
                 };
 
@@ -413,6 +432,7 @@
                                <&dmac1 0x39>, <&dmac1 0x3a>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 717>;
                         status = "disabled";
                 };
 
@@ -428,6 +448,7 @@
                                <&dmac1 0x4d>, <&dmac1 0x4e>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 716>;
                         status = "disabled";
                 };
 
@@ -443,6 +464,7 @@
                                <&dmac1 0x3b>, <&dmac1 0x3c>;
                         dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 713>;
                         status = "disabled";
                 };
 
@@ -452,6 +474,7 @@
                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 813>;
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 813>;
                         phy-mode = "rmii";
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 211d239d9041..c79d55eb43c5 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -229,5 +229,4 @@
 
 &scif_clk {
         clock-frequency = <14745600>;
-        status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index 89c5b24a3d03..9412a86f9b30 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -236,7 +236,6 @@
 
 &scif_clk {
         clock-frequency = <14745600>;
-        status = "okay";
 };
 
 &sdhi0 {
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index bd512c86e852..ba100a6f67ca 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -581,7 +581,6 @@
 
 &scif_clk {
         clock-frequency = <14745600>;
-        status = "okay";
 };
 
 &msiof1 {
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 6d10450de6d7..99269aaca6fc 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -129,17 +129,15 @@
                         next-level-cache = <&L2_CA7>;
                 };
 
-                L2_CA15: cache-controller@0 {
+                L2_CA15: cache-controller-0 {
                         compatible = "cache";
-                        reg = <0>;
                         power-domains = <&sysc R8A7790_PD_CA15_SCU>;
                         cache-unified;
                         cache-level = <2>;
                 };
 
-                L2_CA7: cache-controller@100 {
+                L2_CA7: cache-controller-1 {
                         compatible = "cache";
-                        reg = <0x100>;
                         power-domains = <&sysc R8A7790_PD_CA7_SCU>;
                         cache-unified;
                         cache-level = <2>;
@@ -187,6 +185,9 @@
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&mstp4_clks R8A7790_CLK_INTC_SYS>;
+                clock-names = "clk";
+                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
         };
 
         gpio0: gpio@e6050000 {
@@ -1100,7 +1101,7 @@
                 };
 
                 /* External CAN clock */
-                can_clk: can_clk {
+                can_clk: can {
                         compatible = "fixed-clock";
                         #clock-cells = <0>;
                         /* This value must be overridden by the board. */
@@ -1366,10 +1367,10 @@
                 mstp4_clks: mstp4_clks@e6150140 {
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
-                        clocks = <&cp_clk>;
+                        clocks = <&cp_clk>, <&zs_clk>;
                         #clock-cells = <1>;
-                        clock-indices = <R8A7790_CLK_IRQC>;
-                        clock-output-names = "irqc";
+                        clock-indices = <R8A7790_CLK_IRQC R8A7790_CLK_INTC_SYS>;
+                        clock-output-names = "irqc", "intc-sys";
                 };
                 mstp5_clks: mstp5_clks@e6150144 {
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1442,8 +1443,11 @@
                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
                         clocks = <&p_clk>,
-                                <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
-                                <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+                                <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>,
                                 <&p_clk>,
                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
@@ -1740,11 +1744,11 @@
 
                 rcar_sound,dvc {
                         dvc0: dvc-0 {
-                                dmas = <&audma0 0xbc>;
+                                dmas = <&audma1 0xbc>;
                                 dma-names = "tx";
                         };
                         dvc1: dvc-1 {
-                                dmas = <&audma0 0xbe>;
+                                dmas = <&audma1 0xbe>;
                                 dma-names = "tx";
                         };
                 };
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 5405d337d744..001e6116c47c 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -292,7 +292,7 @@
         x2_clk: x2-clock {
                 compatible = "fixed-clock";
                 #clock-cells = <0>;
-                clock-frequency = <148500000>;
+                clock-frequency = <74250000>;
         };
 
         x13_clk: x13-clock {
@@ -516,7 +516,6 @@
 
 &scif_clk {
         clock-frequency = <14745600>;
-        status = "okay";
 };
 
 &sdhi0 {
@@ -767,7 +766,6 @@
 
 &pcie_bus_clk {
         clock-frequency = <100000000>;
-        status = "okay";
 };
 
 &pciec {
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index 6761d11d3f9e..95da5cb9d37a 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -226,7 +226,7 @@
 
         phy-handle = <&phy1>;
         renesas,ether-link-active-low;
-        status = "ok";
+        status = "okay";
 
         phy1: ethernet-phy@1 {
                 reg = <1>;
@@ -359,7 +359,7 @@
 
 /* composite video input */
 &vin0 {
-        status = "ok";
+        status = "okay";
         pinctrl-0 = <&vin0_pins>;
         pinctrl-names = "default";
 
@@ -401,7 +401,6 @@
 
 &pcie_bus_clk {
         clock-frequency = <100000000>;
-        status = "okay";
 };
 
 &pciec {
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 9f9e48511836..4d0c2ce59900 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -74,9 +74,8 @@
                         next-level-cache = <&L2_CA15>;
                 };
 
-                L2_CA15: cache-controller@0 {
+                L2_CA15: cache-controller-0 {
                         compatible = "cache";
-                        reg = <0>;
                         power-domains = <&sysc R8A7791_PD_CA15_SCU>;
                         cache-unified;
                         cache-level = <2>;
@@ -118,6 +117,9 @@
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&mstp4_clks R8A7791_CLK_INTC_SYS>;
+                clock-names = "clk";
+                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
         };
 
         gpio0: gpio@e6050000 {
@@ -1124,7 +1126,7 @@
                 };
 
                 /* External CAN clock */
-                can_clk: can_clk {
+                can_clk: can {
                         compatible = "fixed-clock";
                         #clock-cells = <0>;
                         /* This value must be overridden by the board. */
@@ -1366,10 +1368,10 @@
                 mstp4_clks: mstp4_clks@e6150140 {
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
-                        clocks = <&cp_clk>;
+                        clocks = <&cp_clk>, <&zs_clk>;
                         #clock-cells = <1>;
-                        clock-indices = <R8A7791_CLK_IRQC>;
-                        clock-output-names = "irqc";
+                        clock-indices = <R8A7791_CLK_IRQC R8A7791_CLK_INTC_SYS>;
+                        clock-output-names = "irqc", "intc-sys";
                 };
                 mstp5_clks: mstp5_clks@e6150144 {
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1445,8 +1447,11 @@
                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
                         clocks = <&p_clk>,
-                                <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
-                                <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+                                <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>,
                                 <&p_clk>,
                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
@@ -1777,11 +1782,11 @@
 
                 rcar_sound,dvc {
                         dvc0: dvc-0 {
-                                dmas = <&audma0 0xbc>;
+                                dmas = <&audma1 0xbc>;
                                 dma-names = "tx";
                         };
                         dvc1: dvc-1 {
-                                dmas = <&audma0 0xbe>;
+                                dmas = <&audma1 0xbe>;
                                 dma-names = "tx";
                         };
                 };
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 8ecfda7a004e..0efecb232ee5 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -46,7 +46,7 @@
                         compatible = "arm,cortex-a15";
                         reg = <0>;
                         clock-frequency = <1000000000>;
-                        clocks = <&cpg_clocks R8A7792_CLK_Z>;
+                        clocks = <&z_clk>;
                         power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
                         next-level-cache = <&L2_CA15>;
                 };
@@ -60,9 +60,8 @@
                         next-level-cache = <&L2_CA15>;
                 };
 
-                L2_CA15: cache-controller@0 {
+                L2_CA15: cache-controller-0 {
                         compatible = "cache";
-                        reg = <0>;
                         cache-unified;
                         cache-level = <2>;
                         power-domains = <&sysc R8A7792_PD_CA15_SCU>;
@@ -93,6 +92,9 @@
                               <0 0xf1006000 0 0x2000>;
                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
                                       IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&mstp4_clks R8A7792_CLK_INTC_SYS>;
+                        clock-names = "clk";
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
                 };
 
                 irqc: interrupt-controller@e61c0000 {
@@ -764,7 +766,7 @@
                         clocks = <&extal_clk>;
                         #clock-cells = <1>;
                         clock-output-names = "main", "pll0", "pll1", "pll3",
-                                             "lb", "qspi", "z";
+                                             "lb", "qspi";
                         #power-domain-cells = <0>;
                 };
 
@@ -776,6 +778,13 @@
                         clock-div = <2>;
                         clock-mult = <1>;
                 };
+                z_clk: z {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7792_CLK_PLL0>;
+                        #clock-cells = <0>;
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                };
                 zx_clk: zx {
                         compatible = "fixed-factor-clock";
                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
@@ -896,10 +905,12 @@
                         compatible = "renesas,r8a7792-mstp-clocks",
                                      "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
-                        clocks = <&cp_clk>;
+                        clocks = <&cp_clk>, <&zs_clk>;
                         #clock-cells = <1>;
-                        clock-indices = <R8A7792_CLK_IRQC>;
-                        clock-output-names = "irqc";
+                        clock-indices = <
+                                R8A7792_CLK_IRQC R8A7792_CLK_INTC_SYS
+                        >;
+                        clock-output-names = "irqc", "intc-sys";
                 };
                 mstp7_clks: mstp7_clks@e615014c {
                         compatible = "renesas,r8a7792-mstp-clocks",
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 92fff07c5e2b..806c93f6ae8b 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -412,7 +412,6 @@
 
 &scif_clk {
         clock-frequency = <14745600>;
-        status = "okay";
 };
 
 &sdhi0 {
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 48ce21c5e8db..4de6041d61f9 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -65,9 +65,8 @@
                         power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
                 };
 
-                L2_CA15: cache-controller@0 {
+                L2_CA15: cache-controller-0 {
                         compatible = "cache";
-                        reg = <0>;
                         power-domains = <&sysc R8A7793_PD_CA15_SCU>;
                         cache-unified;
                         cache-level = <2>;
@@ -109,6 +108,9 @@
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&mstp4_clks R8A7793_CLK_INTC_SYS>;
+                clock-names = "clk";
+                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
         };
 
         gpio0: gpio@e6050000 {
@@ -1179,10 +1181,12 @@
                 mstp4_clks: mstp4_clks@e6150140 {
                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
-                        clocks = <&cp_clk>;
+                        clocks = <&cp_clk>, <&zs_clk>;
                         #clock-cells = <1>;
-                        clock-indices = <R8A7793_CLK_IRQC>;
-                        clock-output-names = "irqc";
+                        clock-indices = <
+                                R8A7793_CLK_IRQC R8A7793_CLK_INTC_SYS
+                        >;
+                        clock-output-names = "irqc", "intc-sys";
                 };
                 mstp5_clks: mstp5_clks@e6150144 {
                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1265,8 +1269,11 @@
                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
                         clocks = <&p_clk>,
-                                <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
-                                <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+                                <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+                                <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
                                 <&p_clk>,
                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
@@ -1426,11 +1433,11 @@
 
                 rcar_sound,dvc {
                         dvc0: dvc-0 {
-                                dmas = <&audma0 0xbc>;
+                                dmas = <&audma1 0xbc>;
                                 dma-names = "tx";
                         };
                         dvc1: dvc-1 {
-                                dmas = <&audma0 0xbe>;
+                                dmas = <&audma1 0xbe>;
                                 dma-names = "tx";
                         };
                 };
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 569e3f0e97a5..f1eea13cdf44 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -168,7 +168,7 @@
         status = "okay";
 
         clocks = <&mstp7_clks R8A7794_CLK_DU0>,
-                 <&mstp7_clks R8A7794_CLK_DU0>,
+                 <&mstp7_clks R8A7794_CLK_DU1>,
                  <&x13_clk>, <&x2_clk>;
         clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
 
@@ -375,7 +375,6 @@
 
 &scif_clk {
         clock-frequency = <14745600>;
-        status = "okay";
 };
 
 &qspi {
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index cf880ac06f4b..4cb5278d104d 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -248,7 +248,6 @@
 
 &scif_clk {
         clock-frequency = <14745600>;
-        status = "okay";
 };
 
 &ether {
@@ -425,7 +424,7 @@
         status = "okay";
 
         clocks = <&mstp7_clks R8A7794_CLK_DU0>,
-                 <&mstp7_clks R8A7794_CLK_DU0>,
+                 <&mstp7_clks R8A7794_CLK_DU1>,
                  <&x2_clk>, <&x3_clk>;
         clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
 
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 319c1069b7ee..a19b884fb258 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -43,6 +43,7 @@
                         compatible = "arm,cortex-a7";
                         reg = <0>;
                         clock-frequency = <1000000000>;
+                        clocks = <&z2_clk>;
                         power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
                         next-level-cache = <&L2_CA7>;
                 };
@@ -56,9 +57,8 @@
                         next-level-cache = <&L2_CA7>;
                 };
 
-                L2_CA7: cache-controller@0 {
+                L2_CA7: cache-controller-0 {
                         compatible = "cache";
-                        reg = <0>;
                         power-domains = <&sysc R8A7794_PD_CA7_SCU>;
                         cache-unified;
                         cache-level = <2>;
@@ -75,6 +75,9 @@
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>;
+                clock-names = "clk";
+                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
         };
 
         gpio0: gpio@e6050000 {
@@ -923,7 +926,7 @@
                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
-                         <&mstp7_clks R8A7794_CLK_DU0>;
+                         <&mstp7_clks R8A7794_CLK_DU1>;
                 clock-names = "du.0", "du.1";
                 status = "disabled";
 
@@ -1062,6 +1065,13 @@
                         clock-div = <2>;
                         clock-mult = <1>;
                 };
+                z2_clk: z2 {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7794_CLK_PLL0>;
+                        #clock-cells = <0>;
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                };
                 zg_clk: zg {
                         compatible = "fixed-factor-clock";
                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
@@ -1248,10 +1258,10 @@
                 mstp4_clks: mstp4_clks@e6150140 {
                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
-                        clocks = <&cp_clk>;
+                        clocks = <&cp_clk>, <&zs_clk>;
                         #clock-cells = <1>;
-                        clock-indices = <R8A7794_CLK_IRQC>;
-                        clock-output-names = "irqc";
+                        clock-indices = <R8A7794_CLK_IRQC R8A7794_CLK_INTC_SYS>;
+                        clock-output-names = "irqc", "intc-sys";
                 };
                 mstp5_clks: mstp5_clks@e6150144 {
                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1268,19 +1278,21 @@
                         clocks = <&mp_clk>, <&hp_clk>,
                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
-                                 <&zx_clk>;
+                                 <&zx_clk>, <&zx_clk>;
                         #clock-cells = <1>;
                         clock-indices = <
                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
-                                R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
+                                R8A7794_CLK_SCIF0
+                                R8A7794_CLK_DU1 R8A7794_CLK_DU0
                         >;
                         clock-output-names =
                                 "ehci", "hsusb",
                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
-                                "scif3", "scif2", "scif1", "scif0", "du0";
+                                "scif3", "scif2", "scif1", "scif0",
+                                "du1", "du0";
                 };
                 mstp8_clks: mstp8_clks@e6150990 {
                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index ff9b90bfaefd..ec91325d3b6e 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -250,6 +250,8 @@
                 clock-names = "biu", "ciu";
                 fifo-depth = <0x100>;
                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                resets = <&cru SRST_MMC0>;
+                reset-names = "reset";
                 status = "disabled";
         };
 
@@ -262,6 +264,8 @@
                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
                 fifo-depth = <0x100>;
                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                resets = <&cru SRST_SDIO>;
+                reset-names = "reset";
                 status = "disabled";
         };
 
@@ -286,6 +290,8 @@
                 num-slots = <1>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+                resets = <&cru SRST_EMMC>;
+                reset-names = "reset";
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 1aff4ad22fc4..1399bc04ea77 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -545,12 +545,12 @@
 };
 
 &global_timer {
-        interrupts = <GIC_PPI 11 0xf04>;
+        interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
         status = "disabled";
 };
 
 &local_timer {
-        interrupts = <GIC_PPI 13 0xf04>;
+        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 };
 
 &i2c0 {
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 641607d9ad29..48a0c1cf4301 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -414,6 +414,8 @@
                 fifo-depth = <0x100>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+                resets = <&cru SRST_EMMC>;
+                reset-names = "reset";
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 21326f3e8564..30e93f694ae8 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -68,11 +68,9 @@
                 compatible = "gpio-leds";
 
                 work {
-                        gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_LOW>;
+                        gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
                         label = "miqi:green:user";
-                        linux,default-trigger = "default-on";
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&led_ctl>;
+                        linux,default-trigger = "timer";
                 };
         };
 
@@ -363,12 +361,6 @@
                 };
         };
 
-        leds {
-                led_ctl: led-ctl {
-                        rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
-                };
-        };
-
         sdmmc {
                 /*
                  * Default drive strength isn't enough to achieve even
diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
new file mode 100644
index 000000000000..3dda79579b51
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
@@ -0,0 +1,298 @@
+/*
+ * Device tree file for Phytec PCM-947 carrier board
+ * Copyright (C) 2017 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/leds-pca9532.h>
+#include "rk3288-phycore-som.dtsi"
+
+/ {
+        model = "Phytec RK3288 PCM-947";
+        compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
+
+        user_buttons: user-buttons {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_button_pins>;
+
+                button@0 {
+                        label = "home";
+                        linux,code = <KEY_HOME>;
+                        gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
+                        wakeup-source;
+                };
+
+                button@1 {
+                        label = "menu";
+                        linux,code = <KEY_MENU>;
+                        gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>;
+                        wakeup-source;
+                };
+        };
+
+        vcc_host0_5v: usb-host0-regulator {
+                compatible = "regulator-fixed";
+                gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&host0_vbus_drv>;
+                regulator-name = "vcc_host0_5v";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                vin-supply = <&vdd_in_otg_out>;
+        };
+
+        vcc_host1_5v: usb-host1-regulator {
+                compatible = "regulator-fixed";
+                gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&host1_vbus_drv>;
+                regulator-name = "vcc_host1_5v";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                vin-supply = <&vdd_in_otg_out>;
+        };
+
+        vcc_otg_5v: usb-otg-regulator {
+                compatible = "regulator-fixed";
+                gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&otg_vbus_drv>;
+                regulator-name = "vcc_otg_5v";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                vin-supply = <&vdd_in_otg_out>;
+        };
+};
+
+&gmac {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+
+        touchscreen@44 {
+                compatible = "st,stmpe811";
+                reg = <0x44>;
+        };
+
+        adc@64 {
+                compatible = "maxim,max1037";
+                reg = <0x64>;
+        };
+
+        i2c_rtc: rtc@68 {
+                compatible = "rv4162";
+                reg = <0x68>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c_rtc_int>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <10 0>;
+        };
+};
+
+&i2c3 {
+        status = "okay";
+
+        i2c_eeprom_cb: eeprom@51 {
+                compatible = "atmel,24c32";
+                reg = <0x51>;
+                pagesize = <32>;
+        };
+};
+
+&i2c4 {
+        status = "okay";
+
+        /* PCA9533 - 4-bit LED dimmer */
+        leddim: leddimmer@62 {
+                compatible = "nxp,pca9533";
+                reg = <0x62>;
+
+                led1 {
+                        label = "red:user1";
+                        linux,default-trigger = "none";
+                        type = <PCA9532_TYPE_LED>;
+                };
+
+                led2 {
+                        label = "green:user2";
+                        linux,default-trigger = "none";
+                        type = <PCA9532_TYPE_LED>;
+                };
+
+                led3 {
+                        label = "blue:user3";
+                        linux,default-trigger = "none";
+                        type = <PCA9532_TYPE_LED>;
+                };
+
+                led4 {
+                        label = "red:user4";
+                        linux,default-trigger = "none";
+                        type = <PCA9532_TYPE_LED>;
+                };
+        };
+};
+
+&i2c5 {
+        status = "okay";
+};
+
+&pinctrl {
+        pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
+                bias-pull-up;
+                drive-strength = <12>;
+        };
+
+        buttons {
+                user_button_pins: user-button-pins {
+                        /* button 1 */
+                        rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_pull_up>,
+                        /* button 2 */
+                                        <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        rv4162 {
+                i2c_rtc_int: i2c-rtc-int {
+                        rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        sdmmc {
+                /*
+                 * Default drive strength isn't enough to achieve even
+                 * high-speed mode on pcm-947 board so bump up to 12 mA.
+                 */
+                sdmmc_bus4: sdmmc-bus4 {
+                        rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+                                        <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+                                        <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+                                        <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+                };
+
+                sdmmc_clk: sdmmc-clk {
+                        rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
+                };
+
+                sdmmc_cmd: sdmmc-cmd {
+                        rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+                };
+
+                sdmmc_pwr: sdmmc-pwr {
+                        rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        touchscreen {
+                ts_irq_pin: ts-irq-pin {
+                        rockchip,pins = <5 15 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        usb_host {
+                host0_vbus_drv: host0-vbus-drv {
+                        rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+
+                host1_vbus_drv: host1-vbus-drv {
+                        rockchip,pins = <2 0 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        usb_otg {
+                otg_vbus_drv: otg-vbus-drv {
+                        rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+};
+
+&sdmmc {
+        bus-width = <4>;
+        cap-mmc-highspeed;
+        cap-sd-highspeed;
+        card-detect-delay = <200>;
+        disable-wp;
+        num-slots = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+        vmmc-supply = <&vdd_io_sd>;
+        vqmmc-supply = <&vdd_io_sd>;
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&usbphy {
+        status = "okay";
+};
+
+&usb_host0_ehci {
+        status = "okay";
+};
+
+&usb_host1 {
+        status = "okay";
+};
+
+&usb_otg {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
new file mode 100644
index 000000000000..26cd3ad45160
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -0,0 +1,497 @@
+/*
+ * Device tree file for Phytec phyCORE-RK3288 SoM
+ * Copyright (C) 2017 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include "rk3288.dtsi"
+
+/ {
+        model = "Phytec RK3288 phyCORE";
+        compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
+
+        /*
+         * Set the minimum memory size here and
+         * let the bootloader set the real size.
+         */
+        memory {
+                device_type = "memory";
+                reg = <0 0x8000000>;
+        };
+
+        aliases {
+                rtc0 = &i2c_rtc;
+                rtc1 = &rk818;
+        };
+
+        ext_gmac: external-gmac-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <125000000>;
+                clock-output-names = "ext_gmac";
+        };
+
+        leds: user-leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_led>;
+
+                user {
+                        label = "green_led";
+                        gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                        default-state = "keep";
+                };
+        };
+
+        vdd_emmc_io: vdd-emmc-io {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd_emmc_io";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                vin-supply = <&vdd_3v3_io>;
+        };
+
+        vdd_in_otg_out: vdd-in-otg-out {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd_in_otg_out";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
+        vdd_misc_1v8: vdd-misc-1v8 {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd_misc_1v8";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+};
+
+&cpu0 {
+        cpu0-supply = <&vdd_cpu>;
+        operating-points = <
+                /* KHz    uV */
+                1800000 1400000
+                1608000 1350000
+                1512000 1300000
+                1416000 1200000
+                1200000 1100000
+                1008000 1050000
+                 816000 1000000
+                 696000  950000
+                 600000  900000
+                 408000  900000
+                 312000  900000
+                 216000  900000
+                 126000  900000
+        >;
+};
+
+&emmc {
+        status = "okay";
+        bus-width = <8>;
+        cap-mmc-highspeed;
+        disable-wp;
+        non-removable;
+        num-slots = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+        vmmc-supply = <&vdd_3v3_io>;
+        vqmmc-supply = <&vdd_emmc_io>;
+};
+
+&gmac {
+        assigned-clocks = <&cru SCLK_MAC>;
+        assigned-clock-parents = <&ext_gmac>;
+        clock_in_out = "input";
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>;
+        phy-handle = <&phy0>;
+        phy-supply = <&vdd_eth_2v5>;
+        phy-mode = "rgmii-id";
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 1000000>;
+        snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+        tx_delay = <0x0>;
+        rx_delay = <0x0>;
+
+        mdio0 {
+                compatible = "snps,dwmac-mdio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                phy0: ethernet-phy@0 {
+                        compatible = "ethernet-phy-ieee802.3-c22";
+                        reg = <0>;
+                        interrupt-parent = <&gpio4>;
+                        interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+                        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+                        ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+                        enet-phy-lane-no-swap;
+                };
+        };
+};
+
+&hdmi {
+        ddc-i2c-bus = <&i2c5>;
+};
+
+&io_domains {
+        status = "okay";
+        sdcard-supply = <&vdd_io_sd>;
+        flash0-supply = <&vdd_emmc_io>;
+        flash1-supply = <&vdd_misc_1v8>;
+        gpio1830-supply = <&vdd_3v3_io>;
+        gpio30-supply = <&vdd_3v3_io>;
+        bb-supply = <&vdd_3v3_io>;
+        dvp-supply = <&vdd_3v3_io>;
+        lcdc-supply = <&vdd_3v3_io>;
+        wifi-supply = <&vdd_3v3_io>;
+        audio-supply = <&vdd_3v3_io>;
+};
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        rk818: pmic@1c {
+                compatible = "rockchip,rk818";
+                reg = <0x1c>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pmic_int>;
+                rockchip,system-power-controller;
+                wakeup-source;
+                #clock-cells = <1>;
+
+                vcc1-supply = <&vdd_sys>;
+                vcc2-supply = <&vdd_sys>;
+                vcc3-supply = <&vdd_sys>;
+                vcc4-supply = <&vdd_sys>;
+                boost-supply = <&vdd_in_otg_out>;
+                vcc6-supply = <&vdd_sys>;
+                vcc7-supply = <&vdd_misc_1v8>;
+                vcc8-supply = <&vdd_misc_1v8>;
+                vcc9-supply = <&vdd_3v3_io>;
+                vddio-supply = <&vdd_3v3_io>;
+
+                regulators {
+                        vdd_log: DCDC_REG1 {
+                                regulator-name = "vdd_log";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vdd_gpu: DCDC_REG2 {
+                                regulator-name = "vdd_gpu";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1250000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        vcc_ddr: DCDC_REG3 {
+                                regulator-name = "vcc_ddr";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vdd_3v3_io: DCDC_REG4 {
+                                regulator-name = "vdd_3v3_io";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+
+                        vdd_sys: DCDC_BOOST {
+                                regulator-name = "vdd_sys";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <5000000>;
+                                };
+                        };
+
+                        /* vcc9 */
+                        vdd_sd: SWITCH_REG {
+                                regulator-name = "vdd_sd";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        /* vcc6 */
+                        vdd_eth_2v5: LDO_REG2 {
+                                regulator-name = "vdd_eth_2v5";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <2500000>;
+                                };
+                        };
+
+                        /* vcc7 */
+                        vdd_1v0: LDO_REG3 {
+                                regulator-name = "vdd_1v0";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        /* vcc8 */
+                        vdd_1v8_lcd_ldo: LDO_REG4 {
+                                regulator-name = "vdd_1v8_lcd_ldo";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        /* vcc8 */
+                        vdd_1v0_lcd: LDO_REG6 {
+                                regulator-name = "vdd_1v0_lcd";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        /* vcc7 */
+                        vdd_1v8_ldo: LDO_REG7 {
+                                regulator-name = "vdd_1v8_ldo";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        /* vcc9 */
+                        vdd_io_sd: LDO_REG9 {
+                                regulator-name = "vdd_io_sd";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+                };
+        };
+
+        /* M24C32-D */
+        i2c_eeprom: eeprom@50 {
+                compatible = "atmel,24c32";
+                reg = <0x50>;
+                pagesize = <32>;
+        };
+
+        vdd_cpu: regulator@60 {
+                compatible = "fcs,fan53555";
+                reg = <0x60>;
+                fcs,suspend-voltage-selector = <1>;
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-enable-ramp-delay = <300>;
+                regulator-name = "vdd_cpu";
+                regulator-min-microvolt = <800000>;
+                regulator-max-microvolt = <1430000>;
+                regulator-ramp-delay = <8000>;
+                vin-supply = <&vdd_sys>;
+        };
+};
+
+&pinctrl {
+        pcfg_output_high: pcfg-output-high {
+                output-high;
+        };
+
+        emmc {
+                /*
+                 * We run eMMC at max speed; bump up drive strength.
+                 * We also have external pulls, so disable the internal ones.
+                 */
+                emmc_clk: emmc-clk {
+                        rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>;
+                };
+
+                emmc_cmd: emmc-cmd {
+                        rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>;
+                };
+
+                emmc_bus8: emmc-bus8 {
+                        rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>,
+                                        <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
+                                        <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>,
+                                        <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>,
+                                        <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>,
+                                        <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>,
+                                        <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>,
+                                        <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>;
+                };
+        };
+
+        gmac {
+                phy_int: phy-int {
+                        rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+
+                phy_rst: phy-rst {
+                        rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+                };
+        };
+
+        leds {
+                user_led: user-led {
+                        rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>;
+                };
+        };
+
+        pmic {
+                pmic_int: pmic-int {
+                        rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+
+                /* Pin for switching state between sleep and non-sleep state */
+                pmic_sleep: pmic-sleep {
+                        rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+};
+
+&pwm1 {
+        status = "okay";
+};
+
+&saradc {
+        status = "okay";
+        vref-supply = <&vdd_1v8_ldo>;
+};
+
+&spi2 {
+        status = "okay";
+
+        serial_flash: flash@0 {
+                compatible = "micron,n25q128a13", "jedec,spi-nor";
+                reg = <0x0>;
+                spi-max-frequency = <50000000>;
+                m25p,fast-read;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                status = "okay";
+        };
+};
+
+&tsadc {
+        status = "okay";
+        rockchip,hw-tshut-mode = <0>;
+        rockchip,hw-tshut-polarity = <0>;
+};
+
+&vopb {
+        status = "okay";
+};
+
+&vopb_mmu {
+        status = "okay";
+};
+
+&vopl {
+        status = "okay";
+};
+
+&vopl_mmu {
+        status = "okay";
+};
+
+&wdt {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index 1c0bbc9b928b..f0778a46bca9 100644
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -136,7 +136,7 @@
                                 regulator-always-on;
                         };
 
-                        vcc_io: REG2 {
+                        vcc_io: vccio_codec: REG2 {
                                 regulator-name = "VCC_IO";
                                 regulator-min-microvolt = <3300000>;
                                 regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
index 96a2e745bb93..a23a94811be8 100644
--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
@@ -81,11 +81,35 @@
                 };
         };
 
+        sata_pwr: sata-prw-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sata_pwr_en>;
+                /* Always turn on the 5V sata power connector */
+                regulator-always-on;
+                regulator-name = "sata_pwr";
+        };
+
         spdif_out: spdif-out {
                 compatible = "linux,spdif-dit";
                 #sound-dai-cells = <0>;
         };
 
+        sound-i2s {
+                compatible = "rockchip,rk3288-hdmi-analog";
+                pinctrl-names = "default";
+                pinctrl-0 = <&phone_ctl>, <&hp_det>;
+                rockchip,audio-codec = <&es8388>;
+                rockchip,hp-det-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
+                rockchip,hp-en-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
+                rockchip,i2s-controller = <&i2s>;
+                rockchip,model = "I2S";
+                rockchip,routing = "Analog", "LOUT2",
+                                   "Analog", "ROUT2";
+        };
+
         sdio_pwrseq: sdio-pwrseq {
                 compatible = "mmc-pwrseq-simple";
                 clocks = <&hym8563>;
@@ -173,10 +197,28 @@
         };
 };
 
+&i2c2 {
+        status = "okay";
+
+        es8388: es8388@10 {
+                compatible = "everest,es8388", "everest,es8328";
+                reg = <0x10>;
+                AVDD-supply = <&vccio_codec>;
+                DVDD-supply = <&vccio_codec>;
+                HPVDD-supply = <&vccio_codec>;
+                PVDD-supply = <&vccio_codec>;
+                clocks = <&cru SCLK_I2S0_OUT>;
+        };
+};
+
 &i2c5 {
         status = "okay";
 };
 
+&i2s {
+        status = "okay";
+};
+
 &pinctrl {
         ir {
                 ir_int: ir-int {
@@ -190,12 +232,28 @@
                 };
         };
 
+        headphone {
+                hp_det: hp-det {
+                        rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+
+                phone_ctl: phone-ctl {
+                        rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
         usb {
                 host_vbus_drv: host-vbus-drv {
                         rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
                 };
         };
 
+        sata {
+                sata_pwr_en: sata-pwr-en {
+                        rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
         sdmmc {
                 sdmmc_pwr: sdmmc-pwr {
                         rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -224,3 +282,7 @@
 &usb_host0_ehci {
         status = "okay";
 };
+
+&usb_host1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
new file mode 100644
index 000000000000..f601c78386a9
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -0,0 +1,536 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3288.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Rockchip RK3288 Tinker Board";
+        compatible = "asus,rk3288-tinker", "rockchip,rk3288";
+
+        memory {
+                reg = <0x0 0x80000000>;
+                device_type = "memory";
+        };
+
+        ext_gmac: external-gmac-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <125000000>;
+                clock-output-names = "ext_gmac";
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwrbtn>;
+
+                button@0 {
+                        gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        label = "GPIO Key Power";
+                        linux,input-type = <1>;
+                        wakeup-source;
+                        debounce-interval = <100>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                act-led {
+                        gpios=<&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger="mmc0";
+                };
+
+                heartbeat-led {
+                        gpios=<&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger="heartbeat";
+                };
+
+                pwr-led {
+                        gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,name = "rockchip,tinker-codec";
+                simple-audio-card,mclk-fs = <512>;
+
+                simple-audio-card,codec {
+                        sound-dai = <&hdmi>;
+                };
+
+                simple-audio-card,cpu {
+                        sound-dai = <&i2s>;
+                };
+        };
+
+        vcc_sys: vsys-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_sys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        vcc_sd: sdmmc-regulator {
+                compatible = "regulator-fixed";
+                gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdmmc_pwr>;
+                regulator-name = "vcc_sd";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                startup-delay-us = <100000>;
+                vin-supply = <&vcc_io>;
+        };
+};
+
+&cpu0 {
+        cpu0-supply = <&vdd_cpu>;
+};
+
+&gmac {
+        assigned-clocks = <&cru SCLK_MAC>;
+        assigned-clock-parents = <&ext_gmac>;
+        clock_in_out = "input";
+        phy-mode = "rgmii";
+        phy-supply = <&vcc33_lan>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>;
+        snps,reset-gpio = <&gpio4 7 0>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 1000000>;
+        tx_delay = <0x30>;
+        rx_delay = <0x10>;
+        status = "ok";
+};
+
+&hdmi {
+        ddc-i2c-bus = <&i2c5>;
+        status = "okay";
+};
+
+&i2c0 {
+        clock-frequency = <400000>;
+        status = "okay";
+
+        rk808: pmic@1b {
+                compatible = "rockchip,rk808";
+                reg = <0x1b>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+                #clock-cells = <1>;
+                clock-output-names = "xin32k", "rk808-clkout2";
+                dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
+                                <&gpio0 12 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
+                rockchip,system-power-controller;
+                wakeup-source;
+
+                vcc1-supply = <&vcc_sys>;
+                vcc2-supply = <&vcc_sys>;
+                vcc3-supply = <&vcc_sys>;
+                vcc4-supply = <&vcc_sys>;
+                vcc6-supply = <&vcc_sys>;
+                vcc7-supply = <&vcc_sys>;
+                vcc8-supply = <&vcc_io>;
+                vcc9-supply = <&vcc_io>;
+                vcc10-supply = <&vcc_io>;
+                vcc11-supply = <&vcc_sys>;
+                vcc12-supply = <&vcc_io>;
+                vddio-supply = <&vcc_io>;
+
+                regulators {
+                        vdd_cpu: DCDC_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-name = "vdd_arm";
+                                regulator-ramp-delay = <6000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vdd_gpu: DCDC_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1250000>;
+                                regulator-name = "vdd_gpu";
+                                regulator-ramp-delay = <6000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        vcc_ddr: DCDC_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_ddr";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vcc_io: DCDC_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc_io";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+
+                        vcc18_ldo1: LDO_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc18_ldo1";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcc33_mipi: LDO_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc33_mipi";
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vdd_10: LDO_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd_10";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        vcc18_codec: LDO_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc18_codec";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vccio_sd: LDO_REG5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vccio_sd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+
+                        vdd10_lcd: LDO_REG6 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd10_lcd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        vcc_18: LDO_REG7 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc_18";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcc18_lcd: LDO_REG8 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc18_lcd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcc33_sd: SWITCH_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc33_sd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vcc33_lan: SWITCH_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc33_lan";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                };
+        };
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c5 {
+        status = "okay";
+};
+
+&i2s {
+        #sound-dai-cells = <0>;
+        status = "okay";
+};
+
+&io_domains {
+        status = "okay";
+
+        sdcard-supply = <&vccio_sd>;
+};
+
+&pinctrl {
+        pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+                drive-strength = <8>;
+        };
+
+        pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+                bias-pull-up;
+                drive-strength = <8>;
+        };
+
+        backlight {
+                bl_en: bl-en {
+                        rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        buttons {
+                pwrbtn: pwrbtn {
+                        rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        eth_phy {
+                eth_phy_pwr: eth-phy-pwr {
+                        rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        pmic {
+                pmic_int: pmic-int {
+                        rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO \
+                                        &pcfg_pull_up>;
+                };
+
+                dvs_1: dvs-1 {
+                        rockchip,pins = <RK_GPIO0 11 RK_FUNC_GPIO \
+                                        &pcfg_pull_down>;
+                };
+
+                dvs_2: dvs-2 {
+                        rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO \
+                                        &pcfg_pull_down>;
+                };
+        };
+
+        sdmmc {
+                sdmmc_bus4: sdmmc-bus4 {
+                        rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+                                        <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+                                        <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+                                        <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                };
+
+                sdmmc_clk: sdmmc-clk {
+                        rockchip,pins = <6 20 RK_FUNC_1 \
+                                        &pcfg_pull_none_drv_8ma>;
+                };
+
+                sdmmc_cmd: sdmmc-cmd {
+                        rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                };
+
+                sdmmc_pwr: sdmmc-pwr {
+                        rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        usb {
+                host_vbus_drv: host-vbus-drv {
+                        rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+
+                pwr_3g: pwr-3g {
+                        rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+};
+
+&pwm0 {
+        status = "okay";
+};
+
+&saradc {
+        vref-supply = <&vcc18_ldo1>;
+        status ="okay";
+};
+
+&sdmmc {
+        bus-width = <4>;
+        cap-mmc-highspeed;
+        cap-sd-highspeed;
+        card-detect-delay = <200>;
+        disable-wp;                     /* wp not hooked up */
+        num-slots = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+        status = "okay";
+        vmmc-supply = <&vcc33_sd>;
+        vqmmc-supply = <&vccio_sd>;
+};
+
+&tsadc {
+        rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
+        rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&uart4 {
+        status = "okay";
+};
+
+&usbphy {
+        status = "okay";
+};
+
+&usb_host0_ehci {
+        status = "okay";
+};
+
+&usb_host1 {
+        status = "okay";
+};
+
+&usb_otg {
+        status= "okay";
+};
+
+&vopb {
+        status = "okay";
+};
+
+&vopb_mmu {
+        status = "okay";
+};
+
+&vopl {
+        status = "okay";
+};
+
+&vopl_mmu {
+        status = "okay";
+};
+
+&wdt {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index df8a0dbe9d91..ad5d6022e95f 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -236,6 +236,8 @@
                 fifo-depth = <0x100>;
                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                 reg = <0xff0c0000 0x4000>;
+                resets = <&cru SRST_MMC0>;
+                reset-names = "reset";
                 status = "disabled";
         };
 
@@ -248,6 +250,8 @@
                 fifo-depth = <0x100>;
                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                 reg = <0xff0d0000 0x4000>;
+                resets = <&cru SRST_SDIO0>;
+                reset-names = "reset";
                 status = "disabled";
         };
 
@@ -260,6 +264,8 @@
                 fifo-depth = <0x100>;
                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                 reg = <0xff0e0000 0x4000>;
+                resets = <&cru SRST_SDIO1>;
+                reset-names = "reset";
                 status = "disabled";
         };
 
@@ -272,6 +278,8 @@
                 fifo-depth = <0x100>;
                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                 reg = <0xff0f0000 0x4000>;
+                resets = <&cru SRST_EMMC>;
+                reset-names = "reset";
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 0b45811cf28b..4aa6f60d6a22 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -132,14 +132,14 @@
         global_timer: global-timer@1013c200 {
                 compatible = "arm,cortex-a9-global-timer";
                 reg = <0x1013c200 0x20>;
-                interrupts = <GIC_PPI 11 0x304>;
+                interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
                 clocks = <&cru CORE_PERI>;
         };
 
         local_timer: local-timer@1013c600 {
                 compatible = "arm,cortex-a9-twd-timer";
                 reg = <0x1013c600 0x20>;
-                interrupts = <GIC_PPI 13 0x304>;
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
                 clocks = <&cru CORE_PERI>;
         };
 
@@ -223,7 +223,11 @@
                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
                 clock-names = "biu", "ciu";
+                dmas = <&dmac2 1>;
+                dma-names = "rx-tx";
                 fifo-depth = <256>;
+                resets = <&cru SRST_SDMMC>;
+                reset-names = "reset";
                 status = "disabled";
         };
 
@@ -233,7 +237,11 @@
                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
                 clock-names = "biu", "ciu";
+                dmas = <&dmac2 3>;
+                dma-names = "rx-tx";
                 fifo-depth = <256>;
+                resets = <&cru SRST_SDIO>;
+                reset-names = "reset";
                 status = "disabled";
         };
 
@@ -243,7 +251,11 @@
                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
                 clock-names = "biu", "ciu";
+                dmas = <&dmac2 4>;
+                dma-names = "rx-tx";
                 fifo-depth = <256>;
+                resets = <&cru SRST_EMMC>;
+                reset-names = "reset";
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi
index 0ccb414cd268..c55cbb3af2c0 100644
--- a/arch/arm/boot/dts/s3c64xx.dtsi
+++ b/arch/arm/boot/dts/s3c64xx.dtsi
@@ -94,13 +94,12 @@
                 };
 
                 watchdog: watchdog@7e004000 {
-                        compatible = "samsung,s3c2410-wdt";
+                        compatible = "samsung,s3c6410-wdt";
                         reg = <0x7e004000 0x1000>;
                         interrupt-parent = <&vic0>;
                         interrupts = <26>;
                         clock-names = "watchdog";
                         clocks = <&clocks PCLK_WDT>;
-                        status = "disabled";
                 };
 
                 i2c0: i2c@7f004000 {
diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
index a853918be43f..726c5d0dbd5b 100644
--- a/arch/arm/boot/dts/s5pv210.dtsi
+++ b/arch/arm/boot/dts/s5pv210.dtsi
@@ -310,7 +310,7 @@
                 };
 
                 watchdog: watchdog@e2700000 {
-                        compatible = "samsung,s3c2410-wdt";
+                        compatible = "samsung,s3c6410-wdt";
                         reg = <0xe2700000 0x1000>;
                         interrupt-parent = <&vic0>;
                         interrupts = <26>;
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 528b4e9c6d3d..8067c71c3a38 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -1305,6 +1305,11 @@
                                 status = "okay";
                         };
 
+                        sfrbu: sfr@fc05c000 {
+                                compatible = "atmel,sama5d2-sfrbu", "syscon";
+                                reg = <0xfc05c000 0x20>;
+                        };
+
                         chipid@fc069000 {
                                 compatible = "atmel,sama5d2-chipid";
                                 reg = <0xfc069000 0x8>;
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 2c43c4d85dee..b2674bdb8e6a 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -15,7 +15,6 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/reset/altr,rst-mgr.h>
 
 / {
@@ -38,13 +37,13 @@
                 #size-cells = <0>;
                 enable-method = "altr,socfpga-smp";
 
-                cpu@0 {
+                cpu0: cpu@0 {
                         compatible = "arm,cortex-a9";
                         device_type = "cpu";
                         reg = <0>;
                         next-level-cache = <&L2>;
                 };
-                cpu@1 {
+                cpu1: cpu@1 {
                         compatible = "arm,cortex-a9";
                         device_type = "cpu";
                         reg = <1>;
@@ -52,6 +51,15 @@
                 };
         };
 
+        pmu: pmu@ff111000 {
+                compatible = "arm,cortex-a9-pmu";
+                interrupt-parent = <&intc>;
+                interrupts = <0 176 4>, <0 177 4>;
+                interrupt-affinity = <&cpu0>, <&cpu1>;
+                reg = <0xff111000 0x1000>,
+                      <0xff113000 0x1000>;
+        };
+
         intc: intc@fffed000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -145,7 +153,7 @@
                                                 compatible = "fixed-clock";
                                         };
 
-                                        main_pll: main_pll {
+                                        main_pll: main_pll@40 {
                                                 #address-cells = <1>;
                                                 #size-cells = <0>;
                                                 #clock-cells = <0>;
@@ -153,7 +161,7 @@
                                                 clocks = <&osc1>;
                                                 reg = <0x40>;
 
-                                                mpuclk: mpuclk {
+                                                mpuclk: mpuclk@48 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&main_pll>;
@@ -161,7 +169,7 @@
                                                         reg = <0x48>;
                                                 };
 
-                                                mainclk: mainclk {
+                                                mainclk: mainclk@4c {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&main_pll>;
@@ -169,7 +177,7 @@
                                                         reg = <0x4C>;
                                                 };
 
-                                                dbg_base_clk: dbg_base_clk {
+                                                dbg_base_clk: dbg_base_clk@50 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&main_pll>, <&osc1>;
@@ -177,21 +185,21 @@
                                                         reg = <0x50>;
                                                 };
 
-                                                main_qspi_clk: main_qspi_clk {
+                                                main_qspi_clk: main_qspi_clk@54 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&main_pll>;
                                                         reg = <0x54>;
                                                 };
 
-                                                main_nand_sdmmc_clk: main_nand_sdmmc_clk {
+                                                main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&main_pll>;
                                                         reg = <0x58>;
                                                 };
 
-                                                cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
+                                                cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&main_pll>;
@@ -199,7 +207,7 @@
                                                 };
                                         };
 
-                                        periph_pll: periph_pll {
+                                        periph_pll: periph_pll@80 {
                                                 #address-cells = <1>;
                                                 #size-cells = <0>;
                                                 #clock-cells = <0>;
@@ -207,42 +215,42 @@
                                                 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
                                                 reg = <0x80>;
 
-                                                emac0_clk: emac0_clk {
+                                                emac0_clk: emac0_clk@88 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0x88>;
                                                 };
 
-                                                emac1_clk: emac1_clk {
+                                                emac1_clk: emac1_clk@8c {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0x8C>;
                                                 };
 
-                                                per_qspi_clk: per_qsi_clk {
+                                                per_qspi_clk: per_qsi_clk@90 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0x90>;
                                                 };
 
-                                                per_nand_mmc_clk: per_nand_mmc_clk {
+                                                per_nand_mmc_clk: per_nand_mmc_clk@94 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0x94>;
                                                 };
 
-                                                per_base_clk: per_base_clk {
+                                                per_base_clk: per_base_clk@98 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0x98>;
                                                 };
 
-                                                h2f_usr1_clk: h2f_usr1_clk {
+                                                h2f_usr1_clk: h2f_usr1_clk@9c {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&periph_pll>;
@@ -250,7 +258,7 @@
                                                 };
                                         };
 
-                                        sdram_pll: sdram_pll {
+                                        sdram_pll: sdram_pll@c0 {
                                                 #address-cells = <1>;
                                                 #size-cells = <0>;
                                                 #clock-cells = <0>;
@@ -258,28 +266,28 @@
                                                 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
                                                 reg = <0xC0>;
 
-                                                ddr_dqs_clk: ddr_dqs_clk {
+                                                ddr_dqs_clk: ddr_dqs_clk@c8 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&sdram_pll>;
                                                         reg = <0xC8>;
                                                 };
 
-                                                ddr_2x_dqs_clk: ddr_2x_dqs_clk {
+                                                ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&sdram_pll>;
                                                         reg = <0xCC>;
                                                 };
 
-                                                ddr_dq_clk: ddr_dq_clk {
+                                                ddr_dq_clk: ddr_dq_clk@d0 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&sdram_pll>;
                                                         reg = <0xD0>;
                                                 };
 
-                                                h2f_usr2_clk: h2f_usr2_clk {
+                                                h2f_usr2_clk: h2f_usr2_clk@d4 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&sdram_pll>;
@@ -678,7 +686,7 @@
                         status = "disabled";
                 };
 
-                eccmgr: eccmgr@ffd08140 {
+                eccmgr: eccmgr {
                         compatible = "altr,socfpga-ecc-manager";
                         #address-cells = <1>;
                         #size-cells = <1>;
@@ -879,7 +887,7 @@
                         dma-names = "tx", "rx";
                 };
 
-                usbphy0: usbphy@0 {
+                usbphy0: usbphy {
                         #phy-cells = <0>;
                         compatible = "usb-nop-xceiv";
                         status = "okay";
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 6b0b7463f36f..bead79e4b2aa 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -14,7 +14,6 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
 
@@ -119,7 +118,7 @@
                                                 compatible = "fixed-clock";
                                         };
 
-                                        main_pll: main_pll {
+                                        main_pll: main_pll@40 {
                                                 #address-cells = <1>;
                                                 #size-cells = <0>;
                                                 #clock-cells = <0>;
@@ -142,35 +141,35 @@
                                                         div-reg = <0x144 0 11>;
                                                 };
 
-                                                main_emaca_clk: main_emaca_clk {
+                                                main_emaca_clk: main_emaca_clk@68 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&main_pll>;
                                                         reg = <0x68>;
                                                 };
 
-                                                main_emacb_clk: main_emacb_clk {
+                                                main_emacb_clk: main_emacb_clk@6c {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&main_pll>;
                                                         reg = <0x6C>;
                                                 };
 
-                                                main_emac_ptp_clk: main_emac_ptp_clk {
+                                                main_emac_ptp_clk: main_emac_ptp_clk@70 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&main_pll>;
                                                         reg = <0x70>;
                                                 };
 
-                                                main_gpio_db_clk: main_gpio_db_clk {
+                                                main_gpio_db_clk: main_gpio_db_clk@74 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&main_pll>;
                                                         reg = <0x74>;
                                                 };
 
-                                                main_sdmmc_clk: main_sdmmc_clk {
+                                                main_sdmmc_clk: main_sdmmc_clk@78 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk"
 ;
@@ -178,28 +177,28 @@
                                                         reg = <0x78>;
                                                 };
 
-                                                main_s2f_usr0_clk: main_s2f_usr0_clk {
+                                                main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&main_pll>;
                                                         reg = <0x7C>;
                                                 };
 
-                                                main_s2f_usr1_clk: main_s2f_usr1_clk {
+                                                main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&main_pll>;
                                                         reg = <0x80>;
                                                 };
 
-                                                main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
+                                                main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&main_pll>;
                                                         reg = <0x84>;
                                                 };
 
-                                                main_periph_ref_clk: main_periph_ref_clk {
+                                                main_periph_ref_clk: main_periph_ref_clk@9c {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&main_pll>;
@@ -207,7 +206,7 @@
                                                 };
                                         };
 
-                                        periph_pll: periph_pll {
+                                        periph_pll: periph_pll@c0 {
                                                 #address-cells = <1>;
                                                 #size-cells = <0>;
                                                 #clock-cells = <0>;
@@ -230,56 +229,56 @@
                                                         div-reg = <0x144 16 11>;
                                                 };
 
-                                                peri_emaca_clk: peri_emaca_clk {
+                                                peri_emaca_clk: peri_emaca_clk@e8 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0xE8>;
                                                 };
 
-                                                peri_emacb_clk: peri_emacb_clk {
+                                                peri_emacb_clk: peri_emacb_clk@ec {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0xEC>;
                                                 };
 
-                                                peri_emac_ptp_clk: peri_emac_ptp_clk {
+                                                peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0xF0>;
                                                 };
 
-                                                peri_gpio_db_clk: peri_gpio_db_clk {
+                                                peri_gpio_db_clk: peri_gpio_db_clk@f4 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0xF4>;
                                                 };
 
-                                                peri_sdmmc_clk: peri_sdmmc_clk {
+                                                peri_sdmmc_clk: peri_sdmmc_clk@f8 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0xF8>;
                                                 };
 
-                                                peri_s2f_usr0_clk: peri_s2f_usr0_clk {
+                                                peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0xFC>;
                                                 };
 
-                                                peri_s2f_usr1_clk: peri_s2f_usr1_clk {
+                                                peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&periph_pll>;
                                                         reg = <0x100>;
                                                 };
 
-                                                peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
+                                                peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-a10-perip-clk";
                                                         clocks = <&periph_pll>;
@@ -287,7 +286,7 @@
                                                 };
                                         };
 
-                                        mpu_free_clk: mpu_free_clk {
+                                        mpu_free_clk: mpu_free_clk@60 {
                                                 #clock-cells = <0>;
                                                 compatible = "altr,socfpga-a10-perip-clk";
                                                 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
@@ -296,7 +295,7 @@
                                                 reg = <0x60>;
                                         };
 
-                                        noc_free_clk: noc_free_clk {
+                                        noc_free_clk: noc_free_clk@64 {
                                                 #clock-cells = <0>;
                                                 compatible = "altr,socfpga-a10-perip-clk";
                                                 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
@@ -305,7 +304,7 @@
                                                 reg = <0x64>;
                                         };
 
-                                        s2f_user1_free_clk: s2f_user1_free_clk {
+                                        s2f_user1_free_clk: s2f_user1_free_clk@104 {
                                                 #clock-cells = <0>;
                                                 compatible = "altr,socfpga-a10-perip-clk";
                                                 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
@@ -314,7 +313,7 @@
                                                 reg = <0x104>;
                                         };
 
-                                        sdmmc_free_clk: sdmmc_free_clk {
+                                        sdmmc_free_clk: sdmmc_free_clk@f8 {
                                                 #clock-cells = <0>;
                                                 compatible = "altr,socfpga-a10-perip-clk";
                                                 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
@@ -649,7 +648,7 @@
                         reg = <0xffe00000 0x40000>;
                 };
 
-                eccmgr: eccmgr@ffd06000 {
+                eccmgr: eccmgr {
                         compatible = "altr,socfpga-a10-ecc-manager";
                         altr,sysmgr-syscon = <&sysmgr>;
                         #address-cells = <1>;
@@ -806,7 +805,7 @@
                         status = "disabled";
                 };
 
-                usbphy0: usbphy@0 {
+                usbphy0: usbphy {
                         #phy-cells = <0>;
                         compatible = "usb-nop-xceiv";
                         status = "okay";
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index c57e6cea0d83..94e088473823 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -30,7 +30,7 @@
                 stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@0 {
                 name = "memory";
                 device_type = "memory";
                 reg = <0x0 0x40000000>; /* 1GB */
@@ -121,6 +121,11 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
+
+                a10sr_rst: reset-controller {
+                        compatible = "altr,a10sr-reset";
+                        #reset-cells = <1>;
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 8672edf9ba4e..aac4feea86f3 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -26,7 +26,7 @@
                 stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@0 {
                 name = "memory";
                 device_type = "memory";
                 reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
index 5ecd2ef405e3..7b49395452b6 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
@@ -25,7 +25,7 @@
                 stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@0 {
                 name = "memory";
                 device_type = "memory";
                 reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
index 6ad3b1eb9b86..3c03da6b8b1d 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
@@ -21,7 +21,7 @@
         model = "Aries/DENX MCV";
         compatible = "altr,socfpga-cyclone5", "altr,socfpga";
 
-        memory {
+        memory@0 {
                 name = "memory";
                 device_type = "memory";
                 reg = <0x0 0x40000000>; /* 1 GiB */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
index e5a98e5696ca..21e397287e29 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
@@ -71,7 +71,6 @@
 
                 stmpe_touchscreen {
                         compatible = "st,stmpe-ts";
-                        reg = <0>;
                         ts,sample-time = <4>;
                         ts,mod-12b = <1>;
                         ts,ref-sel = <0>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 7ea32c81e720..155829f9eba1 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -26,7 +26,7 @@
                 stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@0 {
                 name = "memory";
                 device_type = "memory";
                 reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index a0c90b3bdfd1..a4a555c19d94 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -26,7 +26,7 @@
                 stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@0 {
                 name = "memory";
                 device_type = "memory";
                 reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
index c3d52f27b21e..53bf99eef66d 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
@@ -25,7 +25,7 @@
                 bootargs = "console=ttyS0,115200";
         };
 
-        memory {
+        memory@0 {
                 name = "memory";
                 device_type = "memory";
                 reg = <0x0 0x40000000>; /* 1GB */
@@ -60,18 +60,18 @@
 &leds {
         compatible = "gpio-leds";
 
-        led@0 {
+        led0 {
                 label = "led:green:heartbeat";
                 gpios = <&porta 28 1>;
                 linux,default-trigger = "heartbeat";
         };
 
-        led@1 {
+        led1 {
                 label = "led:green:D7";
                 gpios = <&portb 19 1>;
         };
 
-        led@2 {
+        led2 {
                 label = "led:green:D8";
                 gpios = <&portb 25 1>;
         };
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
index 5b7e3c27e6e9..8860dd2e242c 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
@@ -28,7 +28,7 @@
                 stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@0 {
                 name = "memory";
                 device_type = "memory";
                 reg = <0x0 0x40000000>;
@@ -121,3 +121,24 @@
 &usb1 {
         status = "okay";
 };
+
+&qspi {
+        status = "okay";
+
+        flash0: n25q512a@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "n25q512a";
+                reg = <0>;
+                spi-max-frequency = <100000000>;
+
+                m25p,fast-read;
+                cdns,page-size = <256>;
+                cdns,block-size = <16>;
+                cdns,read-delay = <4>;
+                cdns,tshsl-ns = <50>;
+                cdns,tsd2d-ns = <50>;
+                cdns,tchsh-ns = <4>;
+                cdns,tslch-ns = <4>;
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index 363ee62457fe..893198049397 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -57,7 +57,7 @@
                 bootargs = "console=ttyS0,115200";
         };
 
-        memory {
+        memory@0 {
                 name = "memory";
                 device_type = "memory";
                 reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index f9345e02ca49..dfe2193cd4d5 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -26,7 +26,7 @@
                 bootargs = "console=ttyS0,57600";
         };
 
-        memory {
+        memory@0 {
                 name = "memory";
                 device_type = "memory";
                 reg = <0x0 0x40000000>; /* 1 GB */
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index d865a891776d..c67e76c8ba5d 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -22,95 +22,91 @@
                 device_type = "memory";
                 reg = <0 0x10000000>;
         };
+};
 
-        ahb {
-                clcd@fc200000 {
-                        status = "okay";
-                };
+&clcd {
+        status = "okay";
+};
 
-                dma@fc400000 {
-                        status = "okay";
-                };
+&dmac {
+        status = "okay";
+};
 
-                ehci@e1800000 {
-                        status = "okay";
-                };
+&ehci_usb0 {
+        status = "okay";
+};
 
-                ehci@e2000000 {
-                        status = "okay";
-                };
+&ehci_usb1 {
+        status = "okay";
+};
 
-                gmac: ethernet@e0800000 {
-                        phy-mode = "gmii";
-                        status = "okay";
-                };
+&gmac {
+        phy-mode = "gmii";
+        status = "okay";
+};
 
-                ohci@e1900000 {
-                        status = "okay";
-                };
+&ohci_usb0 {
+        status = "okay";
+};
 
-                ohci@e2100000 {
-                        status = "okay";
-                };
+&ohci_usb1 {
+        status = "okay";
+};
 
-                smi: flash@fc000000 {
-                        status = "okay";
-                        clock-rate=<50000000>;
-
-                        flash@f8000000 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = <0xf8000000 0x800000>;
-                                st,smi-fast-mode;
-
-                                partition@0 {
-                                        label = "xloader";
-                                        reg = <0x0 0x10000>;
-                                };
-                                partition@10000 {
-                                        label = "u-boot";
-                                        reg = <0x10000 0x50000>;
-                                };
-                                partition@60000 {
-                                        label = "environment";
-                                        reg = <0x60000 0x10000>;
-                                };
-                                partition@70000 {
-                                        label = "dtb";
-                                        reg = <0x70000 0x10000>;
-                                };
-                                partition@80000 {
-                                        label = "linux";
-                                        reg = <0x80000 0x310000>;
-                                };
-                                partition@390000 {
-                                        label = "rootfs";
-                                        reg = <0x390000 0x0>;
-                                };
-                        };
-                };
+&smi {
+        status = "okay";
+        clock-rate = <50000000>;
 
-                apb {
-                        serial@d0000000 {
-                                status = "okay";
-                                pinctrl-names = "default";
-                                pinctrl-0 = <>;
-                        };
+        flash@f8000000 {
+                reg = <0xf8000000 0x800000>;
+                st,smi-fast-mode;
 
-                        serial@d0080000 {
-                                status = "okay";
-                                pinctrl-names = "default";
-                                pinctrl-0 = <>;
-                        };
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
 
-                        rtc@fc900000 {
-                               status = "okay";
+                        partition@0 {
+                                label = "xloader";
+                                reg = <0x0 0x10000>;
                         };
-
-                        i2c@d0200000 {
-                                clock-frequency = <400000>;
-                                status = "okay";
+                        partition@10000 {
+                                label = "u-boot";
+                                reg = <0x10000 0x50000>;
+                        };
+                        partition@60000 {
+                                label = "environment";
+                                reg = <0x60000 0x10000>;
+                        };
+                        partition@70000 {
+                                label = "dtb";
+                                reg = <0x70000 0x10000>;
+                        };
+                        partition@80000 {
+                                label = "linux";
+                                reg = <0x80000 0x310000>;
+                        };
+                        partition@390000 {
+                                label = "rootfs";
+                                reg = <0x390000 0x0>;
                         };
                 };
         };
 };
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&rtc {
+        status = "okay";
+};
+
+&i2c {
+        clock-frequency = <400000>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 9f60a7b6a42b..6b32d20acc9f 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -49,7 +49,7 @@
                         #interrupt-cells = <1>;
                 };
 
-                clcd@fc200000 {
+                clcd: clcd@fc200000 {
                         compatible = "arm,pl110", "arm,primecell";
                         reg = <0xfc200000 0x1000>;
                         interrupt-parent = <&vic1>;
@@ -57,7 +57,7 @@
                         status = "disabled";
                 };
 
-                dma@fc400000 {
+                dmac: dma@fc400000 {
                         compatible = "arm,pl080", "arm,primecell";
                         reg = <0xfc400000 0x1000>;
                         interrupt-parent = <&vic1>;
@@ -97,7 +97,7 @@
                         status = "disabled";
                 };
 
-                ehci@e1800000 {
+                ehci_usb0: ehci@e1800000 {
                         compatible = "st,spear600-ehci", "usb-ehci";
                         reg = <0xe1800000 0x1000>;
                         interrupt-parent = <&vic1>;
@@ -105,7 +105,7 @@
                         status = "disabled";
                 };
 
-                ehci@e2000000 {
+                ehci_usb1: ehci@e2000000 {
                         compatible = "st,spear600-ehci", "usb-ehci";
                         reg = <0xe2000000 0x1000>;
                         interrupt-parent = <&vic1>;
@@ -113,7 +113,7 @@
                         status = "disabled";
                 };
 
-                ohci@e1900000 {
+                ohci_usb0: ohci@e1900000 {
                         compatible = "st,spear600-ohci", "usb-ohci";
                         reg = <0xe1900000 0x1000>;
                         interrupt-parent = <&vic1>;
@@ -121,7 +121,7 @@
                         status = "disabled";
                 };
 
-                ohci@e2100000 {
+                ohci_usb1: ohci@e2100000 {
                         compatible = "st,spear600-ohci", "usb-ohci";
                         reg = <0xe2100000 0x1000>;
                         interrupt-parent = <&vic1>;
@@ -135,7 +135,7 @@
                         compatible = "simple-bus";
                         ranges = <0xd0000000 0xd0000000 0x30000000>;
 
-                        serial@d0000000 {
+                        uart0: serial@d0000000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0xd0000000 0x1000>;
                                 interrupt-parent = <&vic0>;
@@ -143,7 +143,7 @@
                                 status = "disabled";
                         };
 
-                        serial@d0080000 {
+                        uart1: serial@d0080000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0xd0080000 0x1000>;
                                 interrupt-parent = <&vic0>;
@@ -181,7 +181,7 @@
                                 interrupts = <4>;
                         };
 
-                        i2c@d0200000 {
+                        i2c: i2c@d0200000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "snps,designware-i2c";
@@ -191,7 +191,7 @@
                                 status = "disabled";
                         };
 
-                        rtc@fc900000 {
+                        rtc: rtc@fc900000 {
                                 compatible = "st,spear600-rtc";
                                 reg = <0xfc900000 0x1000>;
                                 interrupts = <10>;
@@ -204,6 +204,14 @@
                                 interrupt-parent = <&vic0>;
                                 interrupts = <16>;
                         };
+
+                        adc: adc@d820b000 {
+                                compatible = "st,spear600-adc";
+                                reg = <0xd820b000 0x1000>;
+                                interrupt-parent = <&vic1>;
+                                interrupts = <6>;
+                                status = "disabled";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 044184580326..12c0757594d7 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -464,6 +464,8 @@
                         clock-names = "ssc";
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_spi1_default>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
 
                         status = "disabled";
                 };
@@ -476,6 +478,8 @@
                         clock-names = "ssc";
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_spi2_default>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
 
                         status = "disabled";
                 };
@@ -488,6 +492,8 @@
                         clock-names = "ssc";
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_spi3_default>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
 
                         status = "disabled";
                 };
@@ -500,6 +506,8 @@
                         clock-names = "ssc";
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_spi4_default>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
 
                         status = "disabled";
                 };
@@ -513,6 +521,8 @@
                         clock-names = "ssc";
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_spi10_default>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
 
                         status = "disabled";
                 };
@@ -525,6 +535,8 @@
                         clock-names = "ssc";
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_spi11_default>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
 
                         status = "disabled";
                 };
@@ -537,6 +549,8 @@
                         clock-names = "ssc";
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_spi12_default>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
 
                         status = "disabled";
                 };
@@ -789,7 +803,7 @@
                         status          = "okay";
                 };
 
-                st231_gp0: remote-processor {
+                st231_gp0: st231-gp0@0 {
                         compatible      = "st,st231-rproc";
                         memory-region   = <&gp0_reserved>;
                         resets          = <&softreset STIH407_ST231_GP0_SOFTRESET>;
@@ -802,7 +816,7 @@
                         mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
                 };
 
-                st231_delta: remote-processor {
+                st231_delta: st231-delta@0 {
                         compatible      = "st,st231-rproc";
                         memory-region   = <&delta_reserved>;
                         resets          = <&softreset STIH407_ST231_DMU_SOFTRESET>;
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 3c99466989b1..b6331146aa02 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -167,6 +167,34 @@
         status = "okay";
 };
 
+&timers1 {
+        status = "okay";
+
+        pwm {
+                pinctrl-0 = <&pwm1_pins>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        timer@0 {
+                status = "okay";
+        };
+};
+
+&timers3 {
+        status = "okay";
+
+        pwm {
+                pinctrl-0 = <&pwm3_pins>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        timer@2 {
+                status = "okay";
+        };
+};
+
 &usart1 {
         pinctrl-0 = <&usart1_pins_a>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts
index 0dc18a0f0940..69a957963fa8 100644
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -93,6 +93,10 @@
         status = "okay";
 };
 
+&rtc {
+        status = "okay";
+};
+
 &usart1 {
         pinctrl-0 = <&usart1_pins_a>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 9222b9f37bc0..191fa50e34eb 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -88,6 +88,14 @@
                         gpios = <&gpioa 0 0>;
                 };
         };
+
+        /* This turns on vbus for otg for host mode (dwc2) */
+        vcc5v_otg: vcc5v-otg-regulator {
+                compatible = "regulator-fixed";
+                gpio = <&gpioc 4 0>;
+                regulator-name = "vcc5_host1";
+                regulator-always-on;
+        };
 };
 
 &clk_hse {
@@ -105,3 +113,11 @@
         pinctrl-names = "default";
         status = "okay";
 };
+
+&usbotg_hs {
+        compatible = "st,stm32f4x9-fsotg";
+        dr_mode = "host";
+        pinctrl-0 = <&usbotg_fs_pins_b>;
+        pinctrl-names = "default";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index ee0da970e8ad..b2a2b5c38caa 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -450,6 +450,8 @@
                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
                                 interrupt-parent = <&adc>;
                                 interrupts = <0>;
+                                dmas = <&dma2 0 0 0x400 0x0>;
+                                dma-names = "rx";
                                 status = "disabled";
                         };
 
@@ -460,6 +462,8 @@
                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
                                 interrupt-parent = <&adc>;
                                 interrupts = <1>;
+                                dmas = <&dma2 3 1 0x400 0x0>;
+                                dma-names = "rx";
                                 status = "disabled";
                         };
 
@@ -470,6 +474,8 @@
                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
                                 interrupt-parent = <&adc>;
                                 interrupts = <2>;
+                                dmas = <&dma2 1 2 0x400 0x0>;
+                                dma-names = "rx";
                                 status = "disabled";
                         };
                 };
@@ -666,6 +672,28 @@
                                 };
                         };
 
+                        usbotg_fs_pins_a: usbotg_fs@0 {
+                                pins {
+                                        pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
+                                                 <STM32F429_PA11_FUNC_OTG_FS_DM>,
+                                                 <STM32F429_PA12_FUNC_OTG_FS_DP>;
+                                        bias-disable;
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+                        };
+
+                        usbotg_fs_pins_b: usbotg_fs@1 {
+                                pins {
+                                        pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
+                                                 <STM32F429_PB14_FUNC_OTG_HS_DM>,
+                                                 <STM32F429_PB15_FUNC_OTG_HS_DP>;
+                                        bias-disable;
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+                        };
+
                         usbotg_hs_pins_a: usbotg_hs@0 {
                                 pins {
                                         pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
@@ -805,6 +833,15 @@
                         status = "disabled";
                 };
 
+                usbotg_fs: usb@50000000 {
+                        compatible = "st,stm32f4x9-fsotg";
+                        reg = <0x50000000 0x40000>;
+                        interrupts = <67>;
+                        clocks = <&rcc 0 39>;
+                        clock-names = "otg";
+                        status = "disabled";
+                };
+
                 rng: rng@50060800 {
                         compatible = "st,stm32-rng";
                         reg = <0x50060800 0x400>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 0dd56ef574fa..75470c34b92c 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -68,6 +68,15 @@
         soc {
                 dma-ranges = <0xc0000000 0x0 0x10000000>;
         };
+
+        /* This turns on vbus for otg for host mode (dwc2) */
+        vcc5v_otg: vcc5v-otg-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpiob 2 0>;
+                regulator-name = "vcc5_host1";
+                regulator-always-on;
+        };
 };
 
 &rcc {
@@ -115,3 +124,10 @@
         pinctrl-names = "default";
         status = "okay";
 };
+
+&usbotg_fs {
+        dr_mode = "host";
+        pinctrl-0 = <&usbotg_fs_pins_a>;
+        pinctrl-names = "default";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 755fb923c07b..c2765ce12e2e 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -43,6 +43,8 @@
 #include "skeleton.dtsi"
 #include "armv7-m.dtsi"
 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
+#include <dt-bindings/clock/stm32fx-clock.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
 
 / {
         clocks {
@@ -51,6 +53,24 @@
                         compatible = "fixed-clock";
                         clock-frequency = <0>;
                 };
+
+                clk-lse {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                clk-lsi {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32000>;
+                };
+
+                clk_i2s_ckin: clk-i2s-ckin {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                };
         };
 
         soc {
@@ -58,7 +78,7 @@
                         compatible = "st,stm32-timer";
                         reg = <0x40000000 0x400>;
                         interrupts = <28>;
-                        clocks = <&rcc 0 128>;
+                        clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
                         status = "disabled";
                 };
 
@@ -66,7 +86,7 @@
                         compatible = "st,stm32-timer";
                         reg = <0x40000400 0x400>;
                         interrupts = <29>;
-                        clocks = <&rcc 0 129>;
+                        clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
                         status = "disabled";
                 };
 
@@ -74,7 +94,7 @@
                         compatible = "st,stm32-timer";
                         reg = <0x40000800 0x400>;
                         interrupts = <30>;
-                        clocks = <&rcc 0 130>;
+                        clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
                         status = "disabled";
                 };
 
@@ -82,14 +102,14 @@
                         compatible = "st,stm32-timer";
                         reg = <0x40000c00 0x400>;
                         interrupts = <50>;
-                        clocks = <&rcc 0 131>;
+                        clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
                 };
 
                 timer6: timer@40001000 {
                         compatible = "st,stm32-timer";
                         reg = <0x40001000 0x400>;
                         interrupts = <54>;
-                        clocks = <&rcc 0 132>;
+                        clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
                         status = "disabled";
                 };
 
@@ -97,7 +117,21 @@
                         compatible = "st,stm32-timer";
                         reg = <0x40001400 0x400>;
                         interrupts = <55>;
-                        clocks = <&rcc 0 133>;
+                        clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
+                        status = "disabled";
+                };
+
+                rtc: rtc@40002800 {
+                        compatible = "st,stm32-rtc";
+                        reg = <0x40002800 0x400>;
+                        clocks = <&rcc 1 CLK_RTC>;
+                        clock-names = "ck_rtc";
+                        assigned-clocks = <&rcc 1 CLK_RTC>;
+                        assigned-clock-parents = <&rcc 1 CLK_LSE>;
+                        interrupt-parent = <&exti>;
+                        interrupts = <17 1>;
+                        interrupt-names = "alarm";
+                        st,syscfg = <&pwrcfg>;
                         status = "disabled";
                 };
 
@@ -105,7 +139,7 @@
                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
                         reg = <0x40004400 0x400>;
                         interrupts = <38>;
-                        clocks =  <&rcc 0 145>;
+                        clocks = <&rcc 1 CLK_USART2>;
                         status = "disabled";
                 };
 
@@ -113,7 +147,7 @@
                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
                         reg = <0x40004800 0x400>;
                         interrupts = <39>;
-                        clocks = <&rcc 0 146>;
+                        clocks = <&rcc 1 CLK_USART3>;
                         status = "disabled";
                 };
 
@@ -121,7 +155,7 @@
                         compatible = "st,stm32f7-uart";
                         reg = <0x40004c00 0x400>;
                         interrupts = <52>;
-                        clocks = <&rcc 0 147>;
+                        clocks = <&rcc 1 CLK_UART4>;
                         status = "disabled";
                 };
 
@@ -129,7 +163,7 @@
                         compatible = "st,stm32f7-uart";
                         reg = <0x40005000 0x400>;
                         interrupts = <53>;
-                        clocks = <&rcc 0 148>;
+                        clocks = <&rcc 1 CLK_UART5>;
                         status = "disabled";
                 };
 
@@ -137,7 +171,7 @@
                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
                         reg = <0x40007800 0x400>;
                         interrupts = <82>;
-                        clocks = <&rcc 0 158>;
+                        clocks = <&rcc 1 CLK_UART7>;
                         status = "disabled";
                 };
 
@@ -145,7 +179,7 @@
                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
                         reg = <0x40007c00 0x400>;
                         interrupts = <83>;
-                        clocks = <&rcc 0 159>;
+                        clocks = <&rcc 1 CLK_UART8>;
                         status = "disabled";
                 };
 
@@ -153,7 +187,7 @@
                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
                         reg = <0x40011000 0x400>;
                         interrupts = <37>;
-                        clocks = <&rcc 0 164>;
+                        clocks = <&rcc 1 CLK_USART1>;
                         status = "disabled";
                 };
 
@@ -161,7 +195,7 @@
                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
                         reg = <0x40011400 0x400>;
                         interrupts = <71>;
-                        clocks = <&rcc 0 165>;
+                        clocks = <&rcc 1 CLK_USART6>;
                         status = "disabled";
                 };
 
@@ -178,6 +212,11 @@
                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
                 };
 
+                pwrcfg: power-config@40007000 {
+                        compatible = "syscon";
+                        reg = <0x40007000 0x400>;
+                };
+
                 pin-controller {
                         #address-cells = <1>;
                         #size-cells = <1>;
@@ -191,7 +230,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 reg = <0x0 0x400>;
-                                clocks = <&rcc 0 256>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
                                 st,bank-name = "GPIOA";
                         };
 
@@ -199,7 +238,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 reg = <0x400 0x400>;
-                                clocks = <&rcc 0 257>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
                                 st,bank-name = "GPIOB";
                         };
 
@@ -207,7 +246,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 reg = <0x800 0x400>;
-                                clocks = <&rcc 0 258>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
                                 st,bank-name = "GPIOC";
                         };
 
@@ -215,7 +254,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 reg = <0xc00 0x400>;
-                                clocks = <&rcc 0 259>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
                                 st,bank-name = "GPIOD";
                         };
 
@@ -223,7 +262,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 reg = <0x1000 0x400>;
-                                clocks = <&rcc 0 260>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
                                 st,bank-name = "GPIOE";
                         };
 
@@ -231,7 +270,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 reg = <0x1400 0x400>;
-                                clocks = <&rcc 0 261>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
                                 st,bank-name = "GPIOF";
                         };
 
@@ -239,7 +278,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 reg = <0x1800 0x400>;
-                                clocks = <&rcc 0 262>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
                                 st,bank-name = "GPIOG";
                         };
 
@@ -247,7 +286,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 reg = <0x1c00 0x400>;
-                                clocks = <&rcc 0 263>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
                                 st,bank-name = "GPIOH";
                         };
 
@@ -255,7 +294,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 reg = <0x2000 0x400>;
-                                clocks = <&rcc 0 264>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
                                 st,bank-name = "GPIOI";
                         };
 
@@ -263,7 +302,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 reg = <0x2400 0x400>;
-                                clocks = <&rcc 0 265>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
                                 st,bank-name = "GPIOJ";
                         };
 
@@ -271,7 +310,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 reg = <0x2800 0x400>;
-                                clocks = <&rcc 0 266>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
                                 st,bank-name = "GPIOK";
                         };
 
@@ -298,9 +337,12 @@
 
                 rcc: rcc@40023800 {
                         #clock-cells = <2>;
-                        compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+                        compatible = "st,stm32f746-rcc", "st,stm32-rcc";
                         reg = <0x40023800 0x400>;
-                        clocks = <&clk_hse>;
+                        clocks = <&clk_hse>, <&clk_i2s_ckin>;
+                        st,syscfg = <&pwrcfg>;
+                        assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
+                        assigned-clock-rates = <1000000>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
new file mode 100644
index 000000000000..fcc1e0640233
--- /dev/null
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
+
+/ {
+        soc {
+                pin-controller {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "st,stm32h743-pinctrl";
+                        ranges = <0 0x58020000 0x3000>;
+                        pins-are-numbered;
+
+                        gpioa: gpio@58020000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x0 0x400>;
+                                clocks = <&timer_clk>;
+                                st,bank-name = "GPIOA";
+                        };
+
+                        gpiob: gpio@58020400 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x400 0x400>;
+                                clocks = <&timer_clk>;
+                                st,bank-name = "GPIOB";
+                        };
+
+                        gpioc: gpio@58020800 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x800 0x400>;
+                                clocks = <&timer_clk>;
+                                st,bank-name = "GPIOC";
+                        };
+
+                        gpiod: gpio@58020c00 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0xc00 0x400>;
+                                clocks = <&timer_clk>;
+                                st,bank-name = "GPIOD";
+                        };
+
+                        gpioe: gpio@58021000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x1000 0x400>;
+                                clocks = <&timer_clk>;
+                                st,bank-name = "GPIOE";
+                        };
+
+                        gpiof: gpio@58021400 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x1400 0x400>;
+                                clocks = <&timer_clk>;
+                                st,bank-name = "GPIOF";
+                        };
+
+                        gpiog: gpio@58021800 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x1800 0x400>;
+                                clocks = <&timer_clk>;
+                                st,bank-name = "GPIOG";
+                        };
+
+                        gpioh: gpio@58021c00 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x1c00 0x400>;
+                                clocks = <&timer_clk>;
+                                st,bank-name = "GPIOH";
+                        };
+
+                        gpioi: gpio@58022000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x2000 0x400>;
+                                clocks = <&timer_clk>;
+                                st,bank-name = "GPIOI";
+                        };
+
+                        gpioj: gpio@58022400 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x2400 0x400>;
+                                clocks = <&timer_clk>;
+                                st,bank-name = "GPIOJ";
+                        };
+
+                        gpiok: gpio@58022800 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x2800 0x400>;
+                                clocks = <&timer_clk>;
+                                st,bank-name = "GPIOK";
+                        };
+
+                        usart1_pins: usart1@0 {
+                                pins1 {
+                                        pinmux = <STM32H7_PB14_FUNC_USART1_TX>;
+                                        bias-disable;
+                                        drive-push-pull;
+                                        slew-rate = <0>;
+                                };
+                                pins2 {
+                                        pinmux = <STM32H7_PB15_FUNC_USART1_RX>;
+                                        bias-disable;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
new file mode 100644
index 000000000000..46856298ee16
--- /dev/null
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+
+/ {
+        clocks {
+                clk_hse: clk-hse {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                timer_clk: timer-clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <125000000>;
+                };
+        };
+
+        soc {
+                usart1: serial@40011000 {
+                        compatible = "st,stm32f7-usart", "st,stm32f7-uart";
+                        reg = <0x40011000 0x400>;
+                        interrupts = <37>;
+                        status = "disabled";
+                        clocks = <&timer_clk>;
+
+                };
+
+                timer5: timer@40000c00 {
+                        compatible = "st,stm32-timer";
+                        reg = <0x40000c00 0x400>;
+                        interrupts = <50>;
+                        clocks = <&timer_clk>;
+                };
+        };
+};
+
+&systick {
+        clock-frequency = <250000000>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts
new file mode 100644
index 000000000000..c6effbb36e4a
--- /dev/null
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32h743.dtsi"
+#include "stm32h743-pinctrl.dtsi"
+
+/ {
+        model = "STMicroelectronics STM32H743i-EVAL board";
+        compatible = "st,stm32h743i-eval", "st,stm32h743";
+
+        chosen {
+                bootargs = "root=/dev/ram";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory {
+                reg = <0xd0000000 0x2000000>;
+        };
+
+        aliases {
+                serial0 = &usart1;
+        };
+};
+
+&clk_hse {
+        clock-frequency = <125000000>;
+};
+
+&usart1 {
+        pinctrl-0 = <&usart1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index f3fc27412a67..f2a01fe2bebc 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -47,7 +47,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Mele A1000";
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 04e040e6233d..d844938e2aa7 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -46,7 +46,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Cubietech Cubieboard";
diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
index 8317fbfeec4a..aad3bec1cb39 100644
--- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
+++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
@@ -46,7 +46,6 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <dt-bindings/pwm/pwm.h>
 
 / {
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index a48b46474417..a1a7282199d5 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -47,7 +47,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Miniand Hackberry";
diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts
index f3092703a1a6..b8923b92cb36 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet1.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts
@@ -46,7 +46,6 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <dt-bindings/pwm/pwm.h>
 
 / {
diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
index 4ef2a60a8cd4..4a27eb9102cd 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
@@ -46,7 +46,6 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "iNet-9F Rev 03";
diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
index fc4d4d49e2e2..308dc1513041 100644
--- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
+++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
@@ -47,7 +47,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Jesurun Q5";
diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
index a2885039d5f1..98a5f7258dca 100644
--- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
@@ -46,7 +46,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "HAOYU Electronics Marsboard A10";
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index af42ebb3a97b..484c57493bd2 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -47,7 +47,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "PineRiver Mini X-Plus";
diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/sun4i-a10-mk802.dts
index 9c1afd4277d7..2b75745cd246 100644
--- a/arch/arm/boot/dts/sun4i-a10-mk802.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mk802.dts
@@ -44,7 +44,6 @@
 #include "sun4i-a10.dtsi"
 #include "sunxi-common-regulators.dtsi"
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "MK802";
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index 214a5accfe93..3a2522a9419d 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Olimex A10-OLinuXino-LIME";
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index b0365d63ba70..83596fd2ccfc 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -47,7 +47,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "LinkSprite pcDuino";
diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
index bfa6bbdaab27..a68c7cc53b94 100644
--- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
@@ -46,7 +46,6 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <dt-bindings/pwm/pwm.h>
 
 / {
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index ba20b48c0702..b63668ece151 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -47,7 +47,6 @@
 
 #include <dt-bindings/clock/sun4i-a10-pll2.h>
 #include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         interrupt-parent = <&intc>;
@@ -974,6 +973,11 @@
                         #interrupt-cells = <3>;
                         #gpio-cells = <3>;
 
+                        can0_pins_a: can0@0 {
+                                pins = "PH20", "PH21";
+                                function = "can";
+                        };
+
                         emac_pins_a: emac0@0 {
                                 pins = "PA0", "PA1", "PA2",
                                        "PA3", "PA4", "PA5", "PA6",
@@ -1283,6 +1287,22 @@
                         status = "disabled";
                 };
 
+                ps20: ps2@01c2a000 {
+                        compatible = "allwinner,sun4i-a10-ps2";
+                        reg = <0x01c2a000 0x400>;
+                        interrupts = <62>;
+                        clocks = <&apb1_gates 6>;
+                        status = "disabled";
+                };
+
+                ps21: ps2@01c2a400 {
+                        compatible = "allwinner,sun4i-a10-ps2";
+                        reg = <0x01c2a400 0x400>;
+                        interrupts = <63>;
+                        clocks = <&apb1_gates 7>;
+                        status = "disabled";
+                };
+
                 i2c0: i2c@01c2ac00 {
                         compatible = "allwinner,sun4i-a10-i2c";
                         reg = <0x01c2ac00 0x400>;
@@ -1313,19 +1333,11 @@
                         #size-cells = <0>;
                 };
 
-                ps20: ps2@01c2a000 {
-                        compatible = "allwinner,sun4i-a10-ps2";
-                        reg = <0x01c2a000 0x400>;
-                        interrupts = <62>;
-                        clocks = <&apb1_gates 6>;
-                        status = "disabled";
-                };
-
-                ps21: ps2@01c2a400 {
-                        compatible = "allwinner,sun4i-a10-ps2";
-                        reg = <0x01c2a400 0x400>;
-                        interrupts = <63>;
-                        clocks = <&apb1_gates 7>;
+                can0: can@01c2bc00 {
+                        compatible = "allwinner,sun4i-a10-can";
+                        reg = <0x01c2bc00 0x400>;
+                        interrupts = <26>;
+                        clocks = <&apb1_gates 4>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
index a539b72ce093..c6f742a7e69f 100644
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
@@ -44,7 +44,6 @@
 #include "sun5i-a10s.dtsi"
 #include "sunxi-common-regulators.dtsi"
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Auxtek t003 A10s hdmi tv-stick";
diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
index e1b5e8a446fe..a27c3fa58736 100644
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
@@ -44,7 +44,6 @@
 #include "sun5i-a10s.dtsi"
 #include "sunxi-common-regulators.dtsi"
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Auxtek t004 A10s hdmi tv-stick";
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index d8245c6314a7..894f874a5beb 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Olimex A10s-Olinuxino Micro";
@@ -83,7 +82,7 @@
 
 &emac {
         pinctrl-names = "default";
-        pinctrl-0 = <&emac_pins_a>;
+        pinctrl-0 = <&emac_pins_b>;
         phy = <&phy1>;
         status = "okay";
 };
@@ -257,7 +256,7 @@
 
 &uart2 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart2_pins_a>;
+        pinctrl-0 = <&uart2_pins_b>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
index 51371f9b1cf0..262b3669f04d 100644
--- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "R7 A10s hdmi tv-stick";
diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
index 2b8adda0deda..ea3e5655a61b 100644
--- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "A10s-Wobo i5";
@@ -95,7 +94,7 @@
 
 &emac {
         pinctrl-names = "default";
-        pinctrl-0 = <&emac_pins_b>;
+        pinctrl-0 = <&emac_pins_a>;
         phy = <&phy1>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 24b0f5f556f8..1e38ff80366c 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -47,7 +47,6 @@
 #include "sun5i.dtsi"
 
 #include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         interrupt-parent = <&intc>;
@@ -61,7 +60,7 @@
                 #size-cells = <1>;
                 ranges;
 
-                framebuffer@0 {
+                framebuffer@2 {
                         compatible = "allwinner,simple-framebuffer",
                                      "simple-framebuffer";
                         allwinner,pipeline = "de_be0-lcd0-hdmi";
@@ -70,45 +69,9 @@
                                  <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
                         status = "disabled";
                 };
-
-                framebuffer@1 {
-                        compatible = "allwinner,simple-framebuffer",
-                                     "simple-framebuffer";
-                        allwinner,pipeline = "de_be0-lcd0";
-                        clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
-                                 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
-                        status = "disabled";
-                };
-
-                framebuffer@2 {
-                        compatible = "allwinner,simple-framebuffer",
-                                     "simple-framebuffer";
-                        allwinner,pipeline = "de_be0-lcd0-tve0";
-                        clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
-                                 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
-                                 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
-                        status = "disabled";
-                };
         };
 
         soc@01c00000 {
-                emac: ethernet@01c0b000 {
-                        compatible = "allwinner,sun4i-a10-emac";
-                        reg = <0x01c0b000 0x1000>;
-                        interrupts = <55>;
-                        clocks = <&ccu CLK_AHB_EMAC>;
-                        allwinner,sram = <&emac_sram 1>;
-                        status = "disabled";
-                };
-
-                mdio: mdio@01c0b080 {
-                        compatible = "allwinner,sun4i-a10-mdio";
-                        reg = <0x01c0b080 0x14>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
                 pwm: pwm@01c20e00 {
                         compatible = "allwinner,sun5i-a10s-pwm";
                         reg = <0x01c20e00 0xc>;
@@ -116,26 +79,6 @@
                         #pwm-cells = <3>;
                         status = "disabled";
                 };
-
-                uart0: serial@01c28000 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28000 0x400>;
-                        interrupts = <1>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clocks = <&ccu CLK_APB1_UART0>;
-                        status = "disabled";
-                };
-
-                uart2: serial@01c28800 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28800 0x400>;
-                        interrupts = <3>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clocks = <&ccu CLK_APB1_UART2>;
-                        status = "disabled";
-                };
         };
 };
 
@@ -151,12 +94,12 @@
                 function = "uart0";
         };
 
-        uart2_pins_a: uart2@0 {
+        uart2_pins_b: uart2@1 {
                 pins = "PC18", "PC19";
                 function = "uart2";
         };
 
-        emac_pins_a: emac0@0 {
+        emac_pins_b: emac0@1 {
                 pins = "PA0", "PA1", "PA2",
                                 "PA3", "PA4", "PA5", "PA6",
                                 "PA7", "PA8", "PA9", "PA10",
@@ -165,15 +108,6 @@
                 function = "emac";
         };
 
-        emac_pins_b: emac0@1 {
-                pins = "PD6", "PD7", "PD10",
-                                "PD11", "PD12", "PD13", "PD14",
-                                "PD15", "PD18", "PD19", "PD20",
-                                "PD21", "PD22", "PD23", "PD24",
-                                "PD25", "PD26", "PD27";
-                function = "emac";
-        };
-
         mmc1_pins_a: mmc1@0 {
                 pins = "PG3", "PG4", "PG5",
                                  "PG6", "PG7", "PG8";
@@ -193,9 +127,4 @@
 };
 
 &sram_a {
-        emac_sram: sram-section@8000 {
-                compatible = "allwinner,sun4i-a10-sram-a3-a4";
-                reg = <0x8000 0x4000>;
-                status = "disabled";
-        };
 };
diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
index 42435454acef..34411d27aadf 100644
--- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
+++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
@@ -46,7 +46,6 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <dt-bindings/pwm/pwm.h>
 
 / {
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
index 5879a75cf97a..2489c16f7efa 100644
--- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "HSG H702";
diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
index 566cda91a66b..bc883893f4a4 100644
--- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
+++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts
@@ -50,7 +50,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Lichee Pi One";
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index 60e393e28783..3a831eaf1dfc 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -46,7 +46,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Olimex A13-Olinuxino Micro";
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 940d47e88056..95f591bb8ced 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Olimex A13-Olinuxino";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index fb2ddb9a04c9..6436bad94404 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -46,27 +46,11 @@
 
 #include "sun5i.dtsi"
 
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
         interrupt-parent = <&intc>;
 
-        chosen {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                framebuffer@0 {
-                        compatible = "allwinner,simple-framebuffer",
-                                     "simple-framebuffer";
-                        allwinner,pipeline = "de_be0-lcd0";
-                        clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
-                                 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
-                        status = "disabled";
-                };
-        };
-
         thermal-zones {
                 cpu_thermal {
                         /* milliseconds */
@@ -105,44 +89,6 @@
         };
 
         soc@01c00000 {
-                tcon0: lcd-controller@01c0c000 {
-                        compatible = "allwinner,sun5i-a13-tcon";
-                        reg = <0x01c0c000 0x1000>;
-                        interrupts = <44>;
-                        resets = <&ccu RST_LCD>;
-                        reset-names = "lcd";
-                        clocks = <&ccu CLK_AHB_LCD>,
-                                 <&ccu CLK_TCON_CH0>,
-                                 <&ccu CLK_TCON_CH1>;
-                        clock-names = "ahb",
-                                      "tcon-ch0",
-                                      "tcon-ch1";
-                        clock-output-names = "tcon-pixel-clock";
-                        status = "disabled";
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                tcon0_in: port@0 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <0>;
-
-                                        tcon0_in_be0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&be0_out_tcon0>;
-                                        };
-                                };
-
-                                tcon0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-                                };
-                        };
-                };
-
                 pwm: pwm@01c20e00 {
                         compatible = "allwinner,sun5i-a13-pwm";
                         reg = <0x01c20e00 0xc>;
@@ -151,74 +97,6 @@
                         status = "disabled";
                 };
 
-                fe0: display-frontend@01e00000 {
-                        compatible = "allwinner,sun5i-a13-display-frontend";
-                        reg = <0x01e00000 0x20000>;
-                        interrupts = <47>;
-                        clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
-                                 <&ccu CLK_DRAM_DE_FE>;
-                        clock-names = "ahb", "mod",
-                                      "ram";
-                        resets = <&ccu RST_DE_FE>;
-                        status = "disabled";
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                fe0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        fe0_out_be0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&be0_in_fe0>;
-                                        };
-                                };
-                        };
-                };
-
-                be0: display-backend@01e60000 {
-                        compatible = "allwinner,sun5i-a13-display-backend";
-                        reg = <0x01e60000 0x10000>;
-                        clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
-                                 <&ccu CLK_DRAM_DE_BE>;
-                        clock-names = "ahb", "mod",
-                                      "ram";
-                        resets = <&ccu RST_DE_BE>;
-                        status = "disabled";
-
-                        assigned-clocks = <&ccu CLK_DE_BE>;
-                        assigned-clock-rates = <300000000>;
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                be0_in: port@0 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <0>;
-
-                                        be0_in_fe0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&fe0_out_be0>;
-                                        };
-                                };
-
-                                be0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        be0_out_tcon0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&tcon0_in_be0>;
-                                        };
-                                };
-                        };
-                };
         };
 };
 
@@ -244,22 +122,4 @@
 
 &pio {
         compatible = "allwinner,sun5i-a13-pinctrl";
-
-        lcd_rgb666_pins: lcd_rgb666@0 {
-                pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
-                       "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
-                       "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
-                       "PD24", "PD25", "PD26", "PD27";
-                function = "lcd0";
-        };
-
-        uart1_pins_a: uart1@0 {
-                pins = "PE10", "PE11";
-                function = "uart1";
-        };
-
-        uart1_pins_b: uart1@1 {
-                pins = "PG3", "PG4";
-                function = "uart1";
-        };
 };
diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
index 0cf0813d363a..c55b11a4d3c7 100644
--- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
@@ -171,7 +171,7 @@
 
 &pwm {
         pinctrl-names = "default";
-        pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins>;
+        pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
         status = "disabled";
 };
 
@@ -220,7 +220,7 @@
 
 &uart1 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
+        pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts
index 1a845af4d4db..558c16a30543 100644
--- a/arch/arm/boot/dts/sun5i-gr8-evb.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts
@@ -281,7 +281,7 @@
 
 &pwm {
         pinctrl-names = "default";
-        pinctrl-0 = <&pwm0_pins_a>;
+        pinctrl-0 = <&pwm0_pins>;
         status = "okay";
 };
 
@@ -332,7 +332,7 @@
 
 &uart1 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
+        pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index cb9b2aaf7297..3eb56cad0cea 100644
--- a/arch/arm/boot/dts/sun5i-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -42,429 +42,19 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include "sun5i.dtsi"
+
 #include <dt-bindings/clock/sun5i-ccu.h>
 #include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <dt-bindings/reset/sun5i-ccu.h>
 
 / {
-        interrupt-parent = <&intc>;
-        #address-cells = <1>;
-        #size-cells = <1>;
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                cpu0: cpu@0 {
-                        device_type = "cpu";
-                        compatible = "arm,cortex-a8";
-                        reg = <0x0>;
-                        clocks = <&ccu CLK_CPU>;
-                };
-        };
-
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                osc24M: clk@01c20050 {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <24000000>;
-                        clock-output-names = "osc24M";
-                };
-
-                osc32k: clk@0 {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <32768>;
-                        clock-output-names = "osc32k";
-                };
-        };
-
         display-engine {
                 compatible = "allwinner,sun5i-a13-display-engine";
                 allwinner,pipelines = <&fe0>;
         };
 
         soc@01c00000 {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                sram-controller@01c00000 {
-                        compatible = "allwinner,sun4i-a10-sram-controller";
-                        reg = <0x01c00000 0x30>;
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges;
-
-                        sram_a: sram@00000000 {
-                                compatible = "mmio-sram";
-                                reg = <0x00000000 0xc000>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                ranges = <0 0x00000000 0xc000>;
-                        };
-
-                        sram_d: sram@00010000 {
-                                compatible = "mmio-sram";
-                                reg = <0x00010000 0x1000>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                ranges = <0 0x00010000 0x1000>;
-
-                                otg_sram: sram-section@0000 {
-                                        compatible = "allwinner,sun4i-a10-sram-d";
-                                        reg = <0x0000 0x1000>;
-                                        status = "disabled";
-                                };
-                        };
-                };
-
-                dma: dma-controller@01c02000 {
-                        compatible = "allwinner,sun4i-a10-dma";
-                        reg = <0x01c02000 0x1000>;
-                        interrupts = <27>;
-                        clocks = <&ccu CLK_AHB_DMA>;
-                        #dma-cells = <2>;
-                };
-
-                nfc: nand@01c03000 {
-                        compatible = "allwinner,sun4i-a10-nand";
-                        reg = <0x01c03000 0x1000>;
-                        interrupts = <37>;
-                        clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
-                        clock-names = "ahb", "mod";
-                        dmas = <&dma SUN4I_DMA_DEDICATED 3>;
-                        dma-names = "rxtx";
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                spi0: spi@01c05000 {
-                        compatible = "allwinner,sun4i-a10-spi";
-                        reg = <0x01c05000 0x1000>;
-                        interrupts = <10>;
-                        clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
-                        clock-names = "ahb", "mod";
-                        dmas = <&dma SUN4I_DMA_DEDICATED 27>,
-                               <&dma SUN4I_DMA_DEDICATED 26>;
-                        dma-names = "rx", "tx";
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                spi1: spi@01c06000 {
-                        compatible = "allwinner,sun4i-a10-spi";
-                        reg = <0x01c06000 0x1000>;
-                        interrupts = <11>;
-                        clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
-                        clock-names = "ahb", "mod";
-                        dmas = <&dma SUN4I_DMA_DEDICATED 9>,
-                               <&dma SUN4I_DMA_DEDICATED 8>;
-                        dma-names = "rx", "tx";
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                tve0: tv-encoder@01c0a000 {
-                        compatible = "allwinner,sun4i-a10-tv-encoder";
-                        reg = <0x01c0a000 0x1000>;
-                        clocks = <&ccu CLK_AHB_TVE>;
-                        resets = <&ccu RST_TVE>;
-                        status = "disabled";
-
-                        port {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                tve0_in_tcon0: endpoint@0 {
-                                        reg = <0>;
-                                        remote-endpoint = <&tcon0_out_tve0>;
-                                };
-                        };
-                };
-
-                tcon0: lcd-controller@01c0c000 {
-                        compatible = "allwinner,sun5i-a13-tcon";
-                        reg = <0x01c0c000 0x1000>;
-                        interrupts = <44>;
-                        resets = <&ccu RST_LCD>;
-                        reset-names = "lcd";
-                        clocks = <&ccu CLK_AHB_LCD>,
-                                 <&ccu CLK_TCON_CH0>,
-                                 <&ccu CLK_TCON_CH1>;
-                        clock-names = "ahb",
-                                      "tcon-ch0",
-                                      "tcon-ch1";
-                        clock-output-names = "tcon-pixel-clock";
-                        status = "disabled";
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                tcon0_in: port@0 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <0>;
-
-                                        tcon0_in_be0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&be0_out_tcon0>;
-                                        };
-                                };
-
-                                tcon0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        tcon0_out_tve0: endpoint@1 {
-                                                reg = <1>;
-                                                remote-endpoint = <&tve0_in_tcon0>;
-                                        };
-                                };
-                        };
-                };
-
-                mmc0: mmc@01c0f000 {
-                        compatible = "allwinner,sun5i-a13-mmc";
-                        reg = <0x01c0f000 0x1000>;
-                        clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
-                        clock-names = "ahb", "mmc";
-                        interrupts = <32>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                mmc1: mmc@01c10000 {
-                        compatible = "allwinner,sun5i-a13-mmc";
-                        reg = <0x01c10000 0x1000>;
-                        clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
-                        clock-names = "ahb", "mmc";
-                        interrupts = <33>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                mmc2: mmc@01c11000 {
-                        compatible = "allwinner,sun5i-a13-mmc";
-                        reg = <0x01c11000 0x1000>;
-                        clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
-                        clock-names = "ahb", "mmc";
-                        interrupts = <34>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                usb_otg: usb@01c13000 {
-                        compatible = "allwinner,sun4i-a10-musb";
-                        reg = <0x01c13000 0x0400>;
-                        clocks = <&ccu CLK_AHB_OTG>;
-                        interrupts = <38>;
-                        interrupt-names = "mc";
-                        phys = <&usbphy 0>;
-                        phy-names = "usb";
-                        extcon = <&usbphy 0>;
-                        allwinner,sram = <&otg_sram 1>;
-                        status = "disabled";
-
-                        dr_mode = "otg";
-                };
-
-                usbphy: phy@01c13400 {
-                        #phy-cells = <1>;
-                        compatible = "allwinner,sun5i-a13-usb-phy";
-                        reg = <0x01c13400 0x10 0x01c14800 0x4>;
-                        reg-names = "phy_ctrl", "pmu1";
-                        clocks = <&ccu CLK_USB_PHY0>;
-                        clock-names = "usb_phy";
-                        resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
-                        reset-names = "usb0_reset", "usb1_reset";
-                        status = "disabled";
-                };
-
-                ehci0: usb@01c14000 {
-                        compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
-                        reg = <0x01c14000 0x100>;
-                        interrupts = <39>;
-                        clocks = <&ccu CLK_AHB_EHCI>;
-                        phys = <&usbphy 1>;
-                        phy-names = "usb";
-                        status = "disabled";
-                };
-
-                ohci0: usb@01c14400 {
-                        compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
-                        reg = <0x01c14400 0x100>;
-                        interrupts = <40>;
-                        clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
-                        phys = <&usbphy 1>;
-                        phy-names = "usb";
-                        status = "disabled";
-                };
-
-                spi2: spi@01c17000 {
-                        compatible = "allwinner,sun4i-a10-spi";
-                        reg = <0x01c17000 0x1000>;
-                        interrupts = <12>;
-                        clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
-                        clock-names = "ahb", "mod";
-                        dmas = <&dma SUN4I_DMA_DEDICATED 29>,
-                               <&dma SUN4I_DMA_DEDICATED 28>;
-                        dma-names = "rx", "tx";
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                ccu: clock@01c20000 {
-                        compatible = "nextthing,gr8-ccu";
-                        reg = <0x01c20000 0x400>;
-                        clocks = <&osc24M>, <&osc32k>;
-                        clock-names = "hosc", "losc";
-                        #clock-cells = <1>;
-                        #reset-cells = <1>;
-                };
-
-                intc: interrupt-controller@01c20400 {
-                        compatible = "allwinner,sun4i-a10-ic";
-                        reg = <0x01c20400 0x400>;
-                        interrupt-controller;
-                        #interrupt-cells = <1>;
-                };
-
-                pio: pinctrl@01c20800 {
-                        compatible = "nextthing,gr8-pinctrl";
-                        reg = <0x01c20800 0x400>;
-                        interrupts = <28>;
-                        clocks = <&ccu CLK_APB0_PIO>;
-                        gpio-controller;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        #gpio-cells = <3>;
-
-                        i2c0_pins_a: i2c0@0 {
-                                pins = "PB0", "PB1";
-                                function = "i2c0";
-                        };
-
-                        i2c1_pins_a: i2c1@0 {
-                                pins = "PB15", "PB16";
-                                function = "i2c1";
-                        };
-
-                        i2c2_pins_a: i2c2@0 {
-                                pins = "PB17", "PB18";
-                                function = "i2c2";
-                        };
-
-                        i2s0_data_pins_a: i2s0-data@0 {
-                                pins = "PB6", "PB7", "PB8", "PB9";
-                                function = "i2s0";
-                        };
-
-                        i2s0_mclk_pins_a: i2s0-mclk@0 {
-                                pins = "PB5";
-                                function = "i2s0";
-                        };
-
-                        ir0_rx_pins_a: ir0@0 {
-                                pins = "PB4";
-                                function = "ir0";
-                        };
-
-                        lcd_rgb666_pins: lcd-rgb666@0 {
-                                pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
-                                                 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
-                                                 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
-                                                 "PD24", "PD25", "PD26", "PD27";
-                                function = "lcd0";
-                        };
-
-                        mmc0_pins_a: mmc0@0 {
-                                pins = "PF0", "PF1", "PF2", "PF3",
-                                                 "PF4", "PF5";
-                                function = "mmc0";
-                                drive-strength = <30>;
-                        };
-
-                        nand_pins_a: nand-base0@0 {
-                                pins = "PC0", "PC1", "PC2",
-                                                "PC5", "PC8", "PC9", "PC10",
-                                                "PC11", "PC12", "PC13", "PC14",
-                                                "PC15";
-                                function = "nand0";
-                        };
-
-                        nand_cs0_pins_a: nand-cs@0 {
-                                pins = "PC4";
-                                function = "nand0";
-                        };
-
-                        nand_rb0_pins_a: nand-rb@0 {
-                                pins = "PC6";
-                                function = "nand0";
-                        };
-
-                        pwm0_pins_a: pwm0@0 {
-                                pins = "PB2";
-                                function = "pwm0";
-                        };
-
-                        pwm1_pins: pwm1 {
-                                pins = "PG13";
-                                function = "pwm1";
-                        };
-
-                        spdif_tx_pins_a: spdif@0 {
-                                pins = "PB10";
-                                function = "spdif";
-                                bias-pull-up;
-                        };
-
-                        uart1_pins_a: uart1@1 {
-                                pins = "PG3", "PG4";
-                                function = "uart1";
-                        };
-
-                        uart1_cts_rts_pins_a: uart1-cts-rts@0 {
-                                pins = "PG5", "PG6";
-                                function = "uart1";
-                        };
-
-                        uart2_pins_a: uart2@1 {
-                                pins = "PD2", "PD3";
-                                function = "uart2";
-                        };
-
-                        uart2_cts_rts_pins_a: uart2-cts-rts@0 {
-                                pins = "PD4", "PD5";
-                                function = "uart2";
-                        };
-
-                        uart3_pins_a: uart3@1 {
-                                pins = "PG9", "PG10";
-                                function = "uart3";
-                        };
-
-                        uart3_cts_rts_pins_a: uart3-cts-rts@0 {
-                                pins = "PG11", "PG12";
-                                function = "uart3";
-                        };
-                };
-
                 pwm: pwm@01c20e00 {
                         compatible = "allwinner,sun5i-a10s-pwm";
                         reg = <0x01c20e00 0xc>;
@@ -473,18 +63,6 @@
                         status = "disabled";
                 };
 
-                timer@01c20c00 {
-                        compatible = "allwinner,sun4i-a10-timer";
-                        reg = <0x01c20c00 0x90>;
-                        interrupts = <22>;
-                        clocks = <&ccu CLK_HOSC>;
-                };
-
-                wdt: watchdog@01c20c90 {
-                        compatible = "allwinner,sun4i-a10-wdt";
-                        reg = <0x01c20c90 0x10>;
-                };
-
                 spdif: spdif@01c21000 {
                         #sound-dai-cells = <0>;
                         compatible = "allwinner,sun4i-a10-spdif";
@@ -498,15 +76,6 @@
                         status = "disabled";
                 };
 
-                ir0: ir@01c21800 {
-                        compatible = "allwinner,sun4i-a10-ir";
-                        clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
-                        clock-names = "apb", "ir";
-                        interrupts = <5>;
-                        reg = <0x01c21800 0x40>;
-                        status = "disabled";
-                };
-
                 i2s0: i2s@01c22400 {
                         #sound-dai-cells = <0>;
                         compatible = "allwinner,sun4i-a10-i2s";
@@ -519,168 +88,39 @@
                         dma-names = "rx", "tx";
                         status = "disabled";
                 };
+        };
+};
 
-                lradc: lradc@01c22800 {
-                        compatible = "allwinner,sun4i-a10-lradc-keys";
-                        reg = <0x01c22800 0x100>;
-                        interrupts = <31>;
-                        status = "disabled";
-                };
-
-                codec: codec@01c22c00 {
-                        #sound-dai-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-codec";
-                        reg = <0x01c22c00 0x40>;
-                        interrupts = <30>;
-                        clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
-                        clock-names = "apb", "codec";
-                        dmas = <&dma SUN4I_DMA_NORMAL 19>,
-                               <&dma SUN4I_DMA_NORMAL 19>;
-                        dma-names = "rx", "tx";
-                        status = "disabled";
-                };
-
-                rtp: rtp@01c25000 {
-                        compatible = "allwinner,sun5i-a13-ts";
-                        reg = <0x01c25000 0x100>;
-                        interrupts = <29>;
-                        #thermal-sensor-cells = <0>;
-                };
-
-                uart1: serial@01c28400 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28400 0x400>;
-                        interrupts = <2>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clocks = <&ccu CLK_APB1_UART1>;
-                        status = "disabled";
-                };
-
-                uart2: serial@01c28800 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28800 0x400>;
-                        interrupts = <3>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clocks = <&ccu CLK_APB1_UART2>;
-                        status = "disabled";
-                };
-
-                uart3: serial@01c28c00 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28c00 0x400>;
-                        interrupts = <4>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clocks = <&ccu CLK_APB1_UART3>;
-                        status = "disabled";
-                };
-
-                i2c0: i2c@01c2ac00 {
-                        compatible = "allwinner,sun4i-a10-i2c";
-                        reg = <0x01c2ac00 0x400>;
-                        interrupts = <7>;
-                        clocks = <&ccu CLK_APB1_I2C0>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                i2c1: i2c@01c2b000 {
-                        compatible = "allwinner,sun4i-a10-i2c";
-                        reg = <0x01c2b000 0x400>;
-                        interrupts = <8>;
-                        clocks = <&ccu CLK_APB1_I2C1>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                i2c2: i2c@01c2b400 {
-                        compatible = "allwinner,sun4i-a10-i2c";
-                        reg = <0x01c2b400 0x400>;
-                        interrupts = <9>;
-                        clocks = <&ccu CLK_APB1_I2C2>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                timer@01c60000 {
-                        compatible = "allwinner,sun5i-a13-hstimer";
-                        reg = <0x01c60000 0x1000>;
-                        interrupts = <82>, <83>;
-                        clocks = <&ccu CLK_AHB_HSTIMER>;
-                };
-
-                fe0: display-frontend@01e00000 {
-                        compatible = "allwinner,sun5i-a13-display-frontend";
-                        reg = <0x01e00000 0x20000>;
-                        interrupts = <47>;
-                        clocks = <&ccu CLK_AHB_DE_FE>, <&ccu CLK_DE_FE>,
-                                 <&ccu CLK_DRAM_DE_FE>;
-                        clock-names = "ahb", "mod",
-                                      "ram";
-                        resets = <&ccu RST_DE_FE>;
-                        status = "disabled";
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                fe0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        fe0_out_be0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&be0_in_fe0>;
-                                        };
-                                };
-                        };
-                };
-
-                be0: display-backend@01e60000 {
-                        compatible = "allwinner,sun5i-a13-display-backend";
-                        reg = <0x01e60000 0x10000>;
-                        clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
-                                 <&ccu CLK_DRAM_DE_BE>;
-                        clock-names = "ahb", "mod",
-                                      "ram";
-                        resets = <&ccu RST_DE_BE>;
-                        status = "disabled";
+&ccu {
+        compatible = "nextthing,gr8-ccu";
+};
 
-                        assigned-clocks = <&ccu CLK_DE_BE>;
-                        assigned-clock-rates = <300000000>;
+&pio {
+        compatible = "nextthing,gr8-pinctrl";
 
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
+        i2s0_data_pins_a: i2s0-data@0 {
+                pins = "PB6", "PB7", "PB8", "PB9";
+                function = "i2s0";
+        };
 
-                                be0_in: port@0 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <0>;
+        i2s0_mclk_pins_a: i2s0-mclk@0 {
+                pins = "PB5";
+                function = "i2s0";
+        };
 
-                                        be0_in_fe0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&fe0_out_be0>;
-                                        };
-                                };
+        pwm1_pins: pwm1 {
+                pins = "PG13";
+                function = "pwm1";
+        };
 
-                                be0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
+        spdif_tx_pins_a: spdif@0 {
+                pins = "PB10";
+                function = "spdif";
+                bias-pull-up;
+        };
 
-                                        be0_out_tcon0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&tcon0_in_be0>;
-                                        };
-                                };
-                        };
-                };
+        uart1_cts_rts_pins_a: uart1-cts-rts@0 {
+                pins = "PG5", "PG6";
+                function = "uart1";
         };
 };
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index e86fa46fdd45..d0785602663b 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -128,6 +128,10 @@
 
 #include "axp209.dtsi"
 
+&ac_power_supply {
+        status = "okay";
+};
+
 &i2c1 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c1_pins_a>;
@@ -281,7 +285,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart3_pins_a>,
-                    <&uart3_pins_cts_rts_a>;
+                    <&uart3_cts_rts_pins_a>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index 4c1141396c99..de35dbcd1191 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -45,43 +45,3 @@
 
 #include "sun5i-a13.dtsi"
 
-/ {
-        chosen {
-                framebuffer@1 {
-                        compatible = "allwinner,simple-framebuffer",
-                                     "simple-framebuffer";
-                        allwinner,pipeline = "de_be0-lcd0-tve0";
-                        clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
-                                 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
-                                 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
-                        status = "disabled";
-                };
-        };
-
-        soc@01c00000 {
-                tve0: tv-encoder@01c0a000 {
-                        compatible = "allwinner,sun4i-a10-tv-encoder";
-                        reg = <0x01c0a000 0x1000>;
-                        clocks = <&ccu CLK_AHB_TVE>;
-                        resets = <&ccu RST_TVE>;
-                        status = "disabled";
-
-                        port {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                tve0_in_tcon0: endpoint@0 {
-                                        reg = <0>;
-                                        remote-endpoint = <&tcon0_out_tve0>;
-                                };
-                        };
-                };
-        };
-};
-
-&tcon0_out {
-        tcon0_out_tve0: endpoint@1 {
-                reg = <1>;
-                remote-endpoint = <&tve0_in_tcon0>;
-        };
-};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index a9574a6cd95c..5175f9cc9bed 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/clock/sun5i-ccu.h>
 #include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <dt-bindings/reset/sun5i-ccu.h>
 
 / {
@@ -64,6 +63,31 @@
                 };
         };
 
+        chosen {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                framebuffer@0 {
+                        compatible = "allwinner,simple-framebuffer",
+                                     "simple-framebuffer";
+                        allwinner,pipeline = "de_be0-lcd0";
+                        clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+                                 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
+                        status = "disabled";
+                };
+
+                framebuffer@1 {
+                        compatible = "allwinner,simple-framebuffer",
+                                     "simple-framebuffer";
+                        allwinner,pipeline = "de_be0-lcd0-tve0";
+                        clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
+                                 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+                                 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
+                        status = "disabled";
+                };
+        };
+
         clocks {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -105,6 +129,12 @@
                                 ranges = <0 0x00000000 0xc000>;
                         };
 
+                        emac_sram: sram-section@8000 {
+                                compatible = "allwinner,sun4i-a10-sram-a3-a4";
+                                reg = <0x8000 0x4000>;
+                                status = "disabled";
+                        };
+
                         sram_d: sram@00010000 {
                                 compatible = "mmio-sram";
                                 reg = <0x00010000 0x1000>;
@@ -128,6 +158,19 @@
                         #dma-cells = <2>;
                 };
 
+                nfc: nand@01c03000 {
+                        compatible = "allwinner,sun4i-a10-nand";
+                        reg = <0x01c03000 0x1000>;
+                        interrupts = <37>;
+                        clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
+                        clock-names = "ahb", "mod";
+                        dmas = <&dma SUN4I_DMA_DEDICATED 3>;
+                        dma-names = "rxtx";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
                 spi0: spi@01c05000 {
                         compatible = "allwinner,sun4i-a10-spi";
                         reg = <0x01c05000 0x1000>;
@@ -156,6 +199,84 @@
                         #size-cells = <0>;
                 };
 
+                tve0: tv-encoder@01c0a000 {
+                        compatible = "allwinner,sun4i-a10-tv-encoder";
+                        reg = <0x01c0a000 0x1000>;
+                        clocks = <&ccu CLK_AHB_TVE>;
+                        resets = <&ccu RST_TVE>;
+                        status = "disabled";
+
+                        port {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tve0_in_tcon0: endpoint@0 {
+                                        reg = <0>;
+                                        remote-endpoint = <&tcon0_out_tve0>;
+                                };
+                        };
+                };
+
+                emac: ethernet@01c0b000 {
+                        compatible = "allwinner,sun4i-a10-emac";
+                        reg = <0x01c0b000 0x1000>;
+                        interrupts = <55>;
+                        clocks = <&ccu CLK_AHB_EMAC>;
+                        allwinner,sram = <&emac_sram 1>;
+                        status = "disabled";
+                };
+
+                mdio: mdio@01c0b080 {
+                        compatible = "allwinner,sun4i-a10-mdio";
+                        reg = <0x01c0b080 0x14>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                tcon0: lcd-controller@01c0c000 {
+                        compatible = "allwinner,sun5i-a13-tcon";
+                        reg = <0x01c0c000 0x1000>;
+                        interrupts = <44>;
+                        resets = <&ccu RST_LCD>;
+                        reset-names = "lcd";
+                        clocks = <&ccu CLK_AHB_LCD>,
+                                 <&ccu CLK_TCON_CH0>,
+                                 <&ccu CLK_TCON_CH1>;
+                        clock-names = "ahb",
+                                      "tcon-ch0",
+                                      "tcon-ch1";
+                        clock-output-names = "tcon-pixel-clock";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tcon0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        tcon0_in_be0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be0_out_tcon0>;
+                                        };
+                                };
+
+                                tcon0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        tcon0_out_tve0: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&tve0_in_tcon0>;
+                                        };
+                                };
+                        };
+                };
+
                 mmc0: mmc@01c0f000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c0f000 0x1000>;
@@ -273,6 +394,15 @@
                         #interrupt-cells = <3>;
                         #gpio-cells = <3>;
 
+                        emac_pins_a: emac0@0 {
+                                pins = "PD6", "PD7", "PD10",
+                                       "PD11", "PD12", "PD13", "PD14",
+                                       "PD15", "PD18", "PD19", "PD20",
+                                       "PD21", "PD22", "PD23", "PD24",
+                                       "PD25", "PD26", "PD27";
+                                function = "emac";
+                        };
+
                         i2c0_pins_a: i2c0@0 {
                                 pins = "PB0", "PB1";
                                 function = "i2c0";
@@ -288,6 +418,11 @@
                                 function = "i2c2";
                         };
 
+                        ir0_rx_pins_a: ir0@0 {
+                                pins = "PB4";
+                                function = "ir0";
+                        };
+
                         lcd_rgb565_pins: lcd_rgb565@0 {
                                 pins = "PD3", "PD4", "PD5", "PD6", "PD7",
                                                  "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
@@ -296,6 +431,14 @@
                                 function = "lcd0";
                         };
 
+                        lcd_rgb666_pins: lcd_rgb666@0 {
+                                pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+                                       "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
+                                       "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
+                                       "PD24", "PD25", "PD26", "PD27";
+                                function = "lcd0";
+                        };
+
                         mmc0_pins_a: mmc0@0 {
                                 pins = "PF0", "PF1", "PF2", "PF3",
                                        "PF4", "PF5";
@@ -321,6 +464,24 @@
                                 bias-pull-up;
                         };
 
+                        nand_pins_a: nand-base0@0 {
+                                pins = "PC0", "PC1", "PC2",
+                                       "PC5", "PC8", "PC9", "PC10",
+                                       "PC11", "PC12", "PC13", "PC14",
+                                       "PC15";
+                                function = "nand0";
+                        };
+
+                        nand_cs0_pins_a: nand-cs@0 {
+                                pins = "PC4";
+                                function = "nand0";
+                        };
+
+                        nand_rb0_pins_a: nand-rb@0 {
+                                pins = "PC6";
+                                function = "nand0";
+                        };
+
                         spi2_pins_a: spi2@0 {
                                 pins = "PE1", "PE2", "PE3";
                                 function = "spi2";
@@ -331,12 +492,32 @@
                                 function = "spi2";
                         };
 
+                        uart1_pins_a: uart1@0 {
+                                pins = "PE10", "PE11";
+                                function = "uart1";
+                        };
+
+                        uart1_pins_b: uart1@1 {
+                                pins = "PG3", "PG4";
+                                function = "uart1";
+                        };
+
+                        uart2_pins_a: uart2@0 {
+                                pins = "PD2", "PD3";
+                                function = "uart2";
+                        };
+
+                        uart2_cts_rts_pins_a: uart2-cts-rts@0 {
+                                pins = "PD4", "PD5";
+                                function = "uart2";
+                        };
+
                         uart3_pins_a: uart3@0 {
                                 pins = "PG9", "PG10";
                                 function = "uart3";
                         };
 
-                        uart3_pins_cts_rts_a: uart3-cts-rts@0 {
+                        uart3_cts_rts_pins_a: uart3-cts-rts@0 {
                                 pins = "PG11", "PG12";
                                 function = "uart3";
                         };
@@ -359,6 +540,15 @@
                         reg = <0x01c20c90 0x10>;
                 };
 
+                ir0: ir@01c21800 {
+                        compatible = "allwinner,sun4i-a10-ir";
+                        clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
+                        clock-names = "apb", "ir";
+                        interrupts = <5>;
+                        reg = <0x01c21800 0x40>;
+                        status = "disabled";
+                };
+
                 lradc: lradc@01c22800 {
                         compatible = "allwinner,sun4i-a10-lradc-keys";
                         reg = <0x01c22800 0x100>;
@@ -391,6 +581,16 @@
                         #thermal-sensor-cells = <0>;
                 };
 
+                uart0: serial@01c28000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28000 0x400>;
+                        interrupts = <1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu CLK_APB1_UART0>;
+                        status = "disabled";
+                };
+
                 uart1: serial@01c28400 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28400 0x400>;
@@ -401,6 +601,16 @@
                         status = "disabled";
                 };
 
+                uart2: serial@01c28800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28800 0x400>;
+                        interrupts = <3>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu CLK_APB1_UART2>;
+                        status = "disabled";
+                };
+
                 uart3: serial@01c28c00 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28c00 0x400>;
@@ -447,5 +657,75 @@
                         interrupts = <82>, <83>;
                         clocks = <&ccu CLK_AHB_HSTIMER>;
                 };
+
+                fe0: display-frontend@01e00000 {
+                        compatible = "allwinner,sun5i-a13-display-frontend";
+                        reg = <0x01e00000 0x20000>;
+                        interrupts = <47>;
+                        clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
+                                 <&ccu CLK_DRAM_DE_FE>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&ccu RST_DE_FE>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                fe0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        fe0_out_be0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be0_in_fe0>;
+                                        };
+                                };
+                        };
+                };
+
+                be0: display-backend@01e60000 {
+                        compatible = "allwinner,sun5i-a13-display-backend";
+                        reg = <0x01e60000 0x10000>;
+                        interrupts = <47>;
+                        clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+                                 <&ccu CLK_DRAM_DE_BE>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&ccu RST_DE_BE>;
+                        status = "disabled";
+
+                        assigned-clocks = <&ccu CLK_DE_BE>;
+                        assigned-clock-rates = <300000000>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                be0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        be0_in_fe0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&fe0_out_be0>;
+                                        };
+                                };
+
+                                be0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        be0_out_tcon0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&tcon0_in_be0>;
+                                        };
+                                };
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
index effbdc766938..7f34323a668c 100644
--- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
+++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
@@ -47,7 +47,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Allwinner A31 APP4 EVB1 Evaluation Board";
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index f5ececd45bc0..85eff0307ca4 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -47,7 +47,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "WITS A31 Colombus Evaluation Board";
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index f094eeb6c499..d4f74f476f25 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -47,7 +47,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Merrii A31 Hummingbird";
diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts
index 2bc57d2dcd80..010a84c7c012 100644
--- a/arch/arm/boot/dts/sun6i-a31-i7.dts
+++ b/arch/arm/boot/dts/sun6i-a31-i7.dts
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Mele I7 Quad top set box";
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
index 8af5b667a46d..50605fd4449e 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Mele M9 top set box";
diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
index bf0f5831126f..5219556e9f73 100644
--- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
+++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Mele A1000G Quad top set box";
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index a4b96184cac1..9c999d3788f6 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -48,7 +48,6 @@
 #include <dt-bindings/thermal/thermal.h>
 
 #include <dt-bindings/clock/sun6i-a31-ccu.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <dt-bindings/reset/sun6i-a31-ccu.h>
 
 / {
diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
index 5e8f8c4f2b30..75e578159c3a 100644
--- a/arch/arm/boot/dts/sun6i-a31s-cs908.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts
@@ -43,8 +43,6 @@
 /dts-v1/;
 #include "sun6i-a31s.dtsi"
 
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
 / {
         model = "CSQ CS908 top set box";
         compatible = "csq,cs908", "allwinner,sun6i-a31s";
diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
index 2238eda318f6..f3712753fa42 100644
--- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "MSI Primo81 tablet";
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
index 4ec0c8679b2e..d7325bc4eeb4 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Sinlinx SinA31s Core Board";
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
index 7ff68bdd7109..b3d98222bd81 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
@@ -63,6 +63,23 @@
                         gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
                 };
         };
+
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "On-board SPDIF";
+                simple-audio-card,cpu {
+                        sound-dai = <&spdif>;
+                };
+
+                simple-audio-card,codec {
+                        sound-dai = <&spdif_out>;
+                };
+        };
+
+        spdif_out: spdif-out {
+                #sound-dai-cells = <0>;
+                compatible = "linux,spdif-dit";
+        };
 };
 
 &codec {
@@ -153,6 +170,12 @@
         regulator-name = "vcc-gmac-phy";
 };
 
+&spdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spdif_pins_a>;
+        status = "okay";
+};
+
 &usb_otg {
         dr_mode = "peripheral";
         status = "okay";
diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index 3bd862bf82a9..bdfdce8ca6ba 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -86,6 +86,10 @@
         };
 };
 
+&cpu0 {
+        cpu-supply = <&reg_dcdc3>;
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -151,6 +155,17 @@
         status = "okay";
 };
 
+&p2wi {
+        status = "okay";
+
+        axp22x: pmic@68 {
+                compatible = "x-powers,axp221";
+                reg = <0x68>;
+                interrupt-parent = <&nmi_intc>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+
 &pio {
         gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin@0 {
                 pins = "PA21";
@@ -176,6 +191,48 @@
         };
 };
 
+#include "axp22x.dtsi"
+
+&reg_dc5ldo {
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+        regulator-always-on;
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-name = "vdd-3v0";
+};
+
+&reg_dcdc2 {
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-gpu";
+};
+
+&reg_dcdc3 {
+        regulator-always-on;
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc4 {
+        regulator-always-on;
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-sys-dll";
+};
+
+&reg_dcdc5 {
+        regulator-always-on;
+        regulator-min-microvolt = <1500000>;
+        regulator-max-microvolt = <1500000>;
+        regulator-name = "vcc-dram";
+};
+
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
index 154ebf5082ed..f3edf9ca435c 100644
--- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
@@ -45,7 +45,6 @@
 #include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Yones TopTech BS1078 v2 Tablet";
diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
index edaba5f904fd..3cc4046b904a 100644
--- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
@@ -44,7 +44,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         aliases {
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
index 91f2e5f9efcb..ed2f35adf542 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "LeMaker Banana Pi";
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 4dc1e10f88c4..a2eab7aa80e0 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Cubietech Cubieboard2";
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index f019aa3fe96d..102903e83bd2 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Cubietech Cubietruck";
@@ -268,6 +267,10 @@
 
 #include "axp209.dtsi"
 
+&ac_power_supply {
+        status = "okay";
+};
+
 &reg_dcdc2 {
         regulator-always-on;
         regulator-min-microvolt = <1000000>;
@@ -324,6 +327,10 @@
         status = "okay";
 };
 
+&usb_power_supply {
+        status = "okay";
+};
+
 &usbphy {
         pinctrl-names = "default";
         pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
index e921ba42f170..99c00b9a1546 100644
--- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
+++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Merrii A20 Hummingbird";
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
index 385fd8232ae0..4da49717da21 100644
--- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "I12 / Q5 / QT840A A20 tvbox";
diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
index f5b5325a70e2..28d3abbdc2d4 100644
--- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
+++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "ICnova-A20 SWAC";
diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
index bbf1c8cbaac6..96bb0bc198ba 100644
--- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Lamobo R1";
diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts
index 0e074bd0e8c9..86f69813683e 100644
--- a/arch/arm/boot/dts/sun7i-a20-m3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-m3.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Mele M3";
diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
index 97d7a8b65a03..c4ee30709f3a 100644
--- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts
+++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
@@ -53,7 +53,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "mk808c";
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
index a1450c10b08e..1af5b46862cb 100644
--- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
@@ -48,7 +48,6 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Olimex A20-Olimex-SOM-EVB";
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index 1297432c2802..dcd0f7a0dffa 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -49,7 +49,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Olimex A20-OLinuXino-LIME";
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
index 71cca5360728..e7d45425758c 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Olimex A20-OLinuXino-LIME2";
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index 223fbd9f7c62..def0ad8395bb 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -49,7 +49,6 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Olimex A20-Olinuxino Micro";
@@ -85,6 +84,14 @@
         status = "okay";
 };
 
+&codec {
+        status = "okay";
+};
+
+&cpu0 {
+        cpu-supply = <&reg_dcdc2>;
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -111,13 +118,9 @@
         status = "okay";
 
         axp209: pmic@34 {
-                compatible = "x-powers,axp209";
                 reg = <0x34>;
                 interrupt-parent = <&nmi_intc>;
                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
-                interrupt-controller;
-                #interrupt-cells = <1>;
         };
 };
 
@@ -251,6 +254,29 @@
         };
 };
 
+#include "axp209.dtsi"
+
+&reg_dcdc2 {
+        regulator-always-on;
+        regulator-min-microvolt = <1000000>;
+        regulator-max-microvolt = <1400000>;
+        regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+        regulator-always-on;
+        regulator-min-microvolt = <1000000>;
+        regulator-max-microvolt = <1400000>;
+        regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo2 {
+        regulator-always-on;
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-name = "avcc";
+};
+
 &reg_ahci_5v {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
index a74265749227..7af4c8fc1865 100644
--- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
+++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Orange Pi Mini";
diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts
index 3de980c8f8ff..0a8d4a05e8a0 100644
--- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Orange Pi";
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 4599f98a3aee..7c96b53b76bf 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -48,7 +48,6 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "LinkSprite pcDuino3";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 2db97fc820dd..93aa55970bd7 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -49,7 +49,6 @@
 
 #include <dt-bindings/clock/sun4i-a10-pll2.h>
 #include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         interrupt-parent = <&gic>;
@@ -1096,6 +1095,11 @@
                         #interrupt-cells = <3>;
                         #gpio-cells = <3>;
 
+                        can0_pins_a: can0@0 {
+                                pins = "PH20", "PH21";
+                                function = "can";
+                        };
+
                         clk_out_a_pins_a: clk_out_a@0 {
                                 pins = "PI12";
                                 function = "clk_out_a";
@@ -1538,6 +1542,22 @@
                         status = "disabled";
                 };
 
+                ps20: ps2@01c2a000 {
+                        compatible = "allwinner,sun4i-a10-ps2";
+                        reg = <0x01c2a000 0x400>;
+                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&apb1_gates 6>;
+                        status = "disabled";
+                };
+
+                ps21: ps2@01c2a400 {
+                        compatible = "allwinner,sun4i-a10-ps2";
+                        reg = <0x01c2a400 0x400>;
+                        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&apb1_gates 7>;
+                        status = "disabled";
+                };
+
                 i2c0: i2c@01c2ac00 {
                         compatible = "allwinner,sun7i-a20-i2c",
                                      "allwinner,sun4i-a10-i2c";
@@ -1582,6 +1602,15 @@
                         #size-cells = <0>;
                 };
 
+                can0: can@01c2bc00 {
+                        compatible = "allwinner,sun7i-a20-can",
+                                     "allwinner,sun4i-a10-can";
+                        reg = <0x01c2bc00 0x400>;
+                        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&apb1_gates 4>;
+                        status = "disabled";
+                };
+
                 i2c4: i2c@01c2c000 {
                         compatible = "allwinner,sun7i-a20-i2c",
                                      "allwinner,sun4i-a10-i2c";
@@ -1629,20 +1658,5 @@
                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                 };
 
-                ps20: ps2@01c2a000 {
-                        compatible = "allwinner,sun4i-a10-ps2";
-                        reg = <0x01c2a000 0x400>;
-                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&apb1_gates 6>;
-                        status = "disabled";
-                };
-
-                ps21: ps2@01c2a400 {
-                        compatible = "allwinner,sun4i-a10-ps2";
-                        reg = <0x01c2a400 0x400>;
-                        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&apb1_gates 7>;
-                        status = "disabled";
-                };
         };
 };
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 8a3ed21cb7bc..a8b978d0f35b 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -47,7 +47,6 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
 
 / {
@@ -493,6 +492,7 @@
                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
                         clock-names = "bus", "core";
                         resets = <&ccu RST_BUS_GPU>;
+                        #cooling-cells = <2>;
 
                         assigned-clocks = <&ccu CLK_GPU>;
                         assigned-clock-rates = <384000000>;
diff --git a/arch/arm/boot/dts/sun8i-a23-evb.dts b/arch/arm/boot/dts/sun8i-a23-evb.dts
index c21f5b1b255e..87289a60c520 100644
--- a/arch/arm/boot/dts/sun8i-a23-evb.dts
+++ b/arch/arm/boot/dts/sun8i-a23-evb.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Allwinner A23 Evaluation Board";
diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
index 3ab5c0c09d93..b6958e8f2f01 100644
--- a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
+++ b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
@@ -50,7 +50,6 @@
 };
 
 &codec {
-        pinctrl-0 = <&codec_pa_pin>;
         allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
         allwinner,audio-routing =
                 "Headphone", "HP",
@@ -62,12 +61,3 @@
                 "Headset Mic", "HBIAS";
         status = "okay";
 };
-
-&pio {
-        codec_pa_pin: codec_pa_pin@0 {
-                allwinner,pins = "PH9";
-                allwinner,function = "gpio_out";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-        };
-};
diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 03b89bdd55ba..9b620cc1d5f1 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -48,7 +48,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Sinlinx SinA33";
@@ -84,6 +83,24 @@
         status = "okay";
 };
 
+&cpu0 {
+        cpu-supply = <&reg_dcdc3>;
+};
+
+&cpu0_opp_table {
+        opp@1104000000 {
+                opp-hz = /bits/ 64 <1104000000>;
+                opp-microvolt = <1320000>;
+                clock-latency-ns = <244144>; /* 8 32k periods */
+        };
+
+        opp@1200000000 {
+                opp-hz = /bits/ 64 <1200000000>;
+                opp-microvolt = <1320000>;
+                clock-latency-ns = <244144>; /* 8 32k periods */
+        };
+};
+
 &de {
         status = "okay";
 };
@@ -175,6 +192,10 @@
 
 #include "axp223.dtsi"
 
+&ac_power_supply {
+        status = "okay";
+};
+
 &reg_aldo1 {
         regulator-always-on;
         regulator-min-microvolt = <3000000>;
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 306af6cadf26..013978259372 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -43,24 +43,79 @@
  */
 
 #include "sun8i-a23-a33.dtsi"
+#include <dt-bindings/thermal/thermal.h>
 
 / {
         cpu0_opp_table: opp_table0 {
                 compatible = "operating-points-v2";
                 opp-shared;
 
+                opp@120000000 {
+                        opp-hz = /bits/ 64 <120000000>;
+                        opp-microvolt = <1040000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp@240000000 {
+                        opp-hz = /bits/ 64 <240000000>;
+                        opp-microvolt = <1040000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp@312000000 {
+                        opp-hz = /bits/ 64 <312000000>;
+                        opp-microvolt = <1040000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp@408000000 {
+                        opp-hz = /bits/ 64 <408000000>;
+                        opp-microvolt = <1040000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp@480000000 {
+                        opp-hz = /bits/ 64 <480000000>;
+                        opp-microvolt = <1040000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp@504000000 {
+                        opp-hz = /bits/ 64 <504000000>;
+                        opp-microvolt = <1040000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp@600000000 {
+                        opp-hz = /bits/ 64 <600000000>;
+                        opp-microvolt = <1040000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
                 opp@648000000 {
                         opp-hz = /bits/ 64 <648000000>;
                         opp-microvolt = <1040000>;
                         clock-latency-ns = <244144>; /* 8 32k periods */
                 };
 
+                opp@720000000 {
+                        opp-hz = /bits/ 64 <720000000>;
+                        opp-microvolt = <1100000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
                 opp@816000000 {
                         opp-hz = /bits/ 64 <816000000>;
                         opp-microvolt = <1100000>;
                         clock-latency-ns = <244144>; /* 8 32k periods */
                 };
 
+                opp@912000000 {
+                        opp-hz = /bits/ 64 <912000000>;
+                        opp-microvolt = <1200000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
                 opp@1008000000 {
                         opp-hz = /bits/ 64 <1008000000>;
                         opp-microvolt = <1200000>;
@@ -73,6 +128,7 @@
                         clocks = <&ccu CLK_CPUX>;
                         clock-names = "cpu";
                         operating-points-v2 = <&cpu0_opp_table>;
+                        #cooling-cells = <2>;
                 };
 
                 cpu@1 {
@@ -100,6 +156,27 @@
                 status = "disabled";
         };
 
+        iio-hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&ths>;
+        };
+
+        mali_opp_table: gpu-opp-table {
+                compatible = "operating-points-v2";
+
+                opp@144000000 {
+                        opp-hz = /bits/ 64 <144000000>;
+                };
+
+                opp@240000000 {
+                        opp-hz = /bits/ 64 <240000000>;
+                };
+
+                opp@384000000 {
+                        opp-hz = /bits/ 64 <384000000>;
+                };
+        };
+
         memory {
                 reg = <0x40000000 0x80000000>;
         };
@@ -196,6 +273,13 @@
                         status = "disabled";
                 };
 
+                ths: ths@01c25000 {
+                        compatible = "allwinner,sun8i-a33-ths";
+                        reg = <0x01c25000 0x100>;
+                        #thermal-sensor-cells = <0>;
+                        #io-channel-cells = <0>;
+                };
+
                 fe0: display-frontend@01e00000 {
                         compatible = "allwinner,sun8i-a33-display-frontend";
                         reg = <0x01e00000 0x20000>;
@@ -306,12 +390,83 @@
                         };
                 };
         };
+
+        thermal-zones {
+                cpu_thermal {
+                        /* milliseconds */
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+                        thermal-sensors = <&ths>;
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&cpu_alert0>;
+                                        cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                };
+                                map1 {
+                                        trip = <&cpu_alert1>;
+                                        cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                };
+
+                                map2 {
+                                        trip = <&gpu_alert0>;
+                                        cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
+                                };
+
+                                map3 {
+                                        trip = <&gpu_alert1>;
+                                        cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
+                                };
+                        };
+
+                        trips {
+                                cpu_alert0: cpu_alert0 {
+                                        /* milliCelsius */
+                                        temperature = <75000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                gpu_alert0: gpu_alert0 {
+                                        /* milliCelsius */
+                                        temperature = <85000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_alert1: cpu_alert1 {
+                                        /* milliCelsius */
+                                        temperature = <90000>;
+                                        hysteresis = <2000>;
+                                        type = "hot";
+                                };
+
+                                gpu_alert1: gpu_alert1 {
+                                        /* milliCelsius */
+                                        temperature = <95000>;
+                                        hysteresis = <2000>;
+                                        type = "hot";
+                                };
+
+                                cpu_crit: cpu_crit {
+                                        /* milliCelsius */
+                                        temperature = <110000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+        };
 };
 
 &ccu {
         compatible = "allwinner,sun8i-a33-ccu";
 };
 
+&mali {
+        operating-points-v2 = <&mali_opp_table>;
+};
+
 &pio {
         compatible = "allwinner,sun8i-a33-pinctrl";
         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a789a7caf217..0ec143773ee9 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -47,8 +47,6 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
 / {
         interrupt-parent = <&gic>;
 
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index b7ca916d871d..9e8b082c134f 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -49,7 +49,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Xunlong Orange Pi Zero";
@@ -96,6 +95,10 @@
         };
 };
 
+&ehci0 {
+        status = "okay";
+};
+
 &ehci1 {
         status = "okay";
 };
@@ -132,6 +135,10 @@
         bias-pull-up;
 };
 
+&ohci0 {
+        status = "okay";
+};
+
 &ohci1 {
         status = "okay";
 };
@@ -154,7 +161,17 @@
         status = "disabled";
 };
 
+&usb_otg {
+        dr_mode = "peripheral";
+        status = "okay";
+};
+
 &usbphy {
-        /* USB VBUS is always on */
+        /*
+         * USB Type-A port VBUS is always on. However, MicroUSB VBUS can only
+         * power up the board; when it's used as OTG port, this VBUS is
+         * always off even if the board is powered via GPIO pins.
+         */
         status = "okay";
+        usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
 };
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index c0c49dd4d3b2..52acbe111cad 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Banana Pi BPI-M2-Plus";
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index 25b225b7dfd6..e7fae65eb5d3 100644
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Beelink X2";
@@ -138,6 +137,16 @@
         };
 };
 
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_8bit_pins>;
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <8>;
+        non-removable;
+        cap-mmc-hw-reset;
+        status = "okay";
+};
+
 &ohci1 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
new file mode 100644
index 000000000000..03ff6f8b93ff
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2017 Jelle van der Waa <jelle@vdwaa.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "FriendlyARM NanoPi NEO Air";
+        compatible = "friendlyarm,nanopi-neo-air", "allwinner,sun8i-h3";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                pwr {
+                        label = "nanopi:green:pwr";
+                        gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+                        default-state = "on";
+                };
+
+                status {
+                        label = "nanopi:blue:status";
+                        gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+                };
+        };
+};
+
+&mmc0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <4>;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+        cd-inverted;
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins_a>;
+        status = "okay";
+};
+
+&usbphy {
+        /* USB VBUS is always on */
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
index 2216e68d1838..c6decee41a27 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
@@ -47,7 +47,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         aliases {
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 047e9e1c6093..5b6d14555b7c 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Xunlong Orange Pi 2";
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
index 22b99b407019..9b47a0def740 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Xunlong Orange Pi Lite";
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 34da853ee037..5fea430e0eb1 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Xunlong Orange Pi One";
@@ -90,6 +89,10 @@
         };
 };
 
+&ehci0 {
+        status = "okay";
+};
+
 &ehci1 {
         status = "okay";
 };
@@ -104,6 +107,10 @@
         status = "okay";
 };
 
+&ohci0 {
+        status = "okay";
+};
+
 &ohci1 {
         status = "okay";
 };
@@ -127,6 +134,11 @@
         };
 };
 
+&reg_usb0_vbus {
+        gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+        status = "okay";
+};
+
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_pins_a>;
@@ -151,7 +163,14 @@
         status = "disabled";
 };
 
+&usb_otg {
+        dr_mode = "otg";
+        status = "okay";
+};
+
 &usbphy {
-        /* USB VBUS is always on */
+        /* USB Type-A port's VBUS is always on */
+        usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+        usb0_vbus-supply = <&reg_usb0_vbus>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index d43978d3294e..f148111c326d 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -46,7 +46,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Xunlong Orange Pi PC";
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 27780b97c863..b36f9f423c39 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -40,16 +40,9 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
-
-#include <dt-bindings/clock/sun8i-h3-ccu.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-#include <dt-bindings/reset/sun8i-h3-ccu.h>
+#include "sunxi-h3-h5.dtsi"
 
 / {
-        interrupt-parent = <&gic>;
-
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -86,563 +79,48 @@
                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
+};
 
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                osc24M: osc24M_clk {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <24000000>;
-                        clock-output-names = "osc24M";
-                };
-
-                osc32k: osc32k_clk {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <32768>;
-                        clock-output-names = "osc32k";
-                };
-
-                apb0: apb0_clk {
-                        compatible = "fixed-factor-clock";
-                        #clock-cells = <0>;
-                        clock-div = <1>;
-                        clock-mult = <1>;
-                        clocks = <&osc24M>;
-                        clock-output-names = "apb0";
-                };
-
-                apb0_gates: clk@01f01428 {
-                        compatible = "allwinner,sun8i-h3-apb0-gates-clk",
-                                     "allwinner,sun4i-a10-gates-clk";
-                        reg = <0x01f01428 0x4>;
-                        #clock-cells = <1>;
-                        clocks = <&apb0>;
-                        clock-indices = <0>, <1>;
-                        clock-output-names = "apb0_pio", "apb0_ir";
-                };
-
-                ir_clk: ir_clk@01f01454 {
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
-                        reg = <0x01f01454 0x4>;
-                        #clock-cells = <0>;
-                        clocks = <&osc32k>, <&osc24M>;
-                        clock-output-names = "ir";
-                };
-        };
-
-        soc {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                dma: dma-controller@01c02000 {
-                        compatible = "allwinner,sun8i-h3-dma";
-                        reg = <0x01c02000 0x1000>;
-                        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_DMA>;
-                        resets = <&ccu RST_BUS_DMA>;
-                        #dma-cells = <1>;
-                };
-
-                mmc0: mmc@01c0f000 {
-                        compatible = "allwinner,sun7i-a20-mmc";
-                        reg = <0x01c0f000 0x1000>;
-                        clocks = <&ccu CLK_BUS_MMC0>,
-                                 <&ccu CLK_MMC0>,
-                                 <&ccu CLK_MMC0_OUTPUT>,
-                                 <&ccu CLK_MMC0_SAMPLE>;
-                        clock-names = "ahb",
-                                      "mmc",
-                                      "output",
-                                      "sample";
-                        resets = <&ccu RST_BUS_MMC0>;
-                        reset-names = "ahb";
-                        interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                mmc1: mmc@01c10000 {
-                        compatible = "allwinner,sun7i-a20-mmc";
-                        reg = <0x01c10000 0x1000>;
-                        clocks = <&ccu CLK_BUS_MMC1>,
-                                 <&ccu CLK_MMC1>,
-                                 <&ccu CLK_MMC1_OUTPUT>,
-                                 <&ccu CLK_MMC1_SAMPLE>;
-                        clock-names = "ahb",
-                                      "mmc",
-                                      "output",
-                                      "sample";
-                        resets = <&ccu RST_BUS_MMC1>;
-                        reset-names = "ahb";
-                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                mmc2: mmc@01c11000 {
-                        compatible = "allwinner,sun7i-a20-mmc";
-                        reg = <0x01c11000 0x1000>;
-                        clocks = <&ccu CLK_BUS_MMC2>,
-                                 <&ccu CLK_MMC2>,
-                                 <&ccu CLK_MMC2_OUTPUT>,
-                                 <&ccu CLK_MMC2_SAMPLE>;
-                        clock-names = "ahb",
-                                      "mmc",
-                                      "output",
-                                      "sample";
-                        resets = <&ccu RST_BUS_MMC2>;
-                        reset-names = "ahb";
-                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                usbphy: phy@01c19400 {
-                        compatible = "allwinner,sun8i-h3-usb-phy";
-                        reg = <0x01c19400 0x2c>,
-                              <0x01c1a800 0x4>,
-                              <0x01c1b800 0x4>,
-                              <0x01c1c800 0x4>,
-                              <0x01c1d800 0x4>;
-                        reg-names = "phy_ctrl",
-                                    "pmu0",
-                                    "pmu1",
-                                    "pmu2",
-                                    "pmu3";
-                        clocks = <&ccu CLK_USB_PHY0>,
-                                 <&ccu CLK_USB_PHY1>,
-                                 <&ccu CLK_USB_PHY2>,
-                                 <&ccu CLK_USB_PHY3>;
-                        clock-names = "usb0_phy",
-                                      "usb1_phy",
-                                      "usb2_phy",
-                                      "usb3_phy";
-                        resets = <&ccu RST_USB_PHY0>,
-                                 <&ccu RST_USB_PHY1>,
-                                 <&ccu RST_USB_PHY2>,
-                                 <&ccu RST_USB_PHY3>;
-                        reset-names = "usb0_reset",
-                                      "usb1_reset",
-                                      "usb2_reset",
-                                      "usb3_reset";
-                        status = "disabled";
-                        #phy-cells = <1>;
-                };
-
-                ehci1: usb@01c1b000 {
-                        compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
-                        reg = <0x01c1b000 0x100>;
-                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
-                        resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
-                        phys = <&usbphy 1>;
-                        phy-names = "usb";
-                        status = "disabled";
-                };
-
-                ohci1: usb@01c1b400 {
-                        compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
-                        reg = <0x01c1b400 0x100>;
-                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
-                                 <&ccu CLK_USB_OHCI1>;
-                        resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
-                        phys = <&usbphy 1>;
-                        phy-names = "usb";
-                        status = "disabled";
-                };
-
-                ehci2: usb@01c1c000 {
-                        compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
-                        reg = <0x01c1c000 0x100>;
-                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
-                        resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
-                        phys = <&usbphy 2>;
-                        phy-names = "usb";
-                        status = "disabled";
-                };
-
-                ohci2: usb@01c1c400 {
-                        compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
-                        reg = <0x01c1c400 0x100>;
-                        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
-                                 <&ccu CLK_USB_OHCI2>;
-                        resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
-                        phys = <&usbphy 2>;
-                        phy-names = "usb";
-                        status = "disabled";
-                };
-
-                ehci3: usb@01c1d000 {
-                        compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
-                        reg = <0x01c1d000 0x100>;
-                        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
-                        resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
-                        phys = <&usbphy 3>;
-                        phy-names = "usb";
-                        status = "disabled";
-                };
-
-                ohci3: usb@01c1d400 {
-                        compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
-                        reg = <0x01c1d400 0x100>;
-                        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
-                                 <&ccu CLK_USB_OHCI3>;
-                        resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
-                        phys = <&usbphy 3>;
-                        phy-names = "usb";
-                        status = "disabled";
-                };
-
-                ccu: clock@01c20000 {
-                        compatible = "allwinner,sun8i-h3-ccu";
-                        reg = <0x01c20000 0x400>;
-                        clocks = <&osc24M>, <&osc32k>;
-                        clock-names = "hosc", "losc";
-                        #clock-cells = <1>;
-                        #reset-cells = <1>;
-                };
-
-                pio: pinctrl@01c20800 {
-                        compatible = "allwinner,sun8i-h3-pinctrl";
-                        reg = <0x01c20800 0x400>;
-                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
-                        clock-names = "apb", "hosc", "losc";
-                        gpio-controller;
-                        #gpio-cells = <3>;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-
-                        i2c0_pins: i2c0 {
-                                pins = "PA11", "PA12";
-                                function = "i2c0";
-                        };
-
-                        i2c1_pins: i2c1 {
-                                pins = "PA18", "PA19";
-                                function = "i2c1";
-                        };
-
-                        i2c2_pins: i2c2 {
-                                pins = "PE12", "PE13";
-                                function = "i2c2";
-                        };
-
-                        mmc0_pins_a: mmc0@0 {
-                                pins = "PF0", "PF1", "PF2", "PF3",
-                                       "PF4", "PF5";
-                                function = "mmc0";
-                                drive-strength = <30>;
-                                bias-pull-up;
-                        };
-
-                        mmc0_cd_pin: mmc0_cd_pin@0 {
-                                pins = "PF6";
-                                function = "gpio_in";
-                                bias-pull-up;
-                        };
-
-                        mmc1_pins_a: mmc1@0 {
-                                pins = "PG0", "PG1", "PG2", "PG3",
-                                       "PG4", "PG5";
-                                function = "mmc1";
-                                drive-strength = <30>;
-                                bias-pull-up;
-                        };
-
-                        mmc2_8bit_pins: mmc2_8bit {
-                                pins = "PC5", "PC6", "PC8",
-                                       "PC9", "PC10", "PC11",
-                                       "PC12", "PC13", "PC14",
-                                       "PC15", "PC16";
-                                function = "mmc2";
-                                drive-strength = <30>;
-                                bias-pull-up;
-                        };
-
-                        spdif_tx_pins_a: spdif@0 {
-                                pins = "PA17";
-                                function = "spdif";
-                        };
-
-                        spi0_pins: spi0 {
-                                pins = "PC0", "PC1", "PC2", "PC3";
-                                function = "spi0";
-                        };
-
-                        spi1_pins: spi1 {
-                                pins = "PA15", "PA16", "PA14", "PA13";
-                                function = "spi1";
-                        };
-
-                        uart0_pins_a: uart0@0 {
-                                pins = "PA4", "PA5";
-                                function = "uart0";
-                        };
-
-                        uart1_pins: uart1 {
-                                pins = "PG6", "PG7";
-                                function = "uart1";
-                        };
-
-                        uart1_rts_cts_pins: uart1_rts_cts {
-                                pins = "PG8", "PG9";
-                                function = "uart1";
-                        };
-
-                        uart2_pins: uart2 {
-                                pins = "PA0", "PA1";
-                                function = "uart2";
-                        };
-
-                        uart3_pins: uart3 {
-                                pins = "PA13", "PA14";
-                                function = "uart3";
-                        };
-                };
-
-                timer@01c20c00 {
-                        compatible = "allwinner,sun4i-a10-timer";
-                        reg = <0x01c20c00 0xa0>;
-                        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&osc24M>;
-                };
-
-                spi0: spi@01c68000 {
-                        compatible = "allwinner,sun8i-h3-spi";
-                        reg = <0x01c68000 0x1000>;
-                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
-                        clock-names = "ahb", "mod";
-                        dmas = <&dma 23>, <&dma 23>;
-                        dma-names = "rx", "tx";
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&spi0_pins>;
-                        resets = <&ccu RST_BUS_SPI0>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                spi1: spi@01c69000 {
-                        compatible = "allwinner,sun8i-h3-spi";
-                        reg = <0x01c69000 0x1000>;
-                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
-                        clock-names = "ahb", "mod";
-                        dmas = <&dma 24>, <&dma 24>;
-                        dma-names = "rx", "tx";
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&spi1_pins>;
-                        resets = <&ccu RST_BUS_SPI1>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                wdt0: watchdog@01c20ca0 {
-                        compatible = "allwinner,sun6i-a31-wdt";
-                        reg = <0x01c20ca0 0x20>;
-                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-                };
-
-                spdif: spdif@01c21000 {
-                        #sound-dai-cells = <0>;
-                        compatible = "allwinner,sun8i-h3-spdif";
-                        reg = <0x01c21000 0x400>;
-                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
-                        resets = <&ccu RST_BUS_SPDIF>;
-                        clock-names = "apb", "spdif";
-                        dmas = <&dma 2>;
-                        dma-names = "tx";
-                        status = "disabled";
-                };
-
-                pwm: pwm@01c21400 {
-                        compatible = "allwinner,sun8i-h3-pwm";
-                        reg = <0x01c21400 0x8>;
-                        clocks = <&osc24M>;
-                        #pwm-cells = <3>;
-                        status = "disabled";
-                };
-
-                codec: codec@01c22c00 {
-                        #sound-dai-cells = <0>;
-                        compatible = "allwinner,sun8i-h3-codec";
-                        reg = <0x01c22c00 0x400>;
-                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
-                        clock-names = "apb", "codec";
-                        resets = <&ccu RST_BUS_CODEC>;
-                        dmas = <&dma 15>, <&dma 15>;
-                        dma-names = "rx", "tx";
-                        allwinner,codec-analog-controls = <&codec_analog>;
-                        status = "disabled";
-                };
-
-                uart0: serial@01c28000 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28000 0x400>;
-                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clocks = <&ccu CLK_BUS_UART0>;
-                        resets = <&ccu RST_BUS_UART0>;
-                        dmas = <&dma 6>, <&dma 6>;
-                        dma-names = "rx", "tx";
-                        status = "disabled";
-                };
-
-                uart1: serial@01c28400 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28400 0x400>;
-                        interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clocks = <&ccu CLK_BUS_UART1>;
-                        resets = <&ccu RST_BUS_UART1>;
-                        dmas = <&dma 7>, <&dma 7>;
-                        dma-names = "rx", "tx";
-                        status = "disabled";
-                };
-
-                uart2: serial@01c28800 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28800 0x400>;
-                        interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clocks = <&ccu CLK_BUS_UART2>;
-                        resets = <&ccu RST_BUS_UART2>;
-                        dmas = <&dma 8>, <&dma 8>;
-                        dma-names = "rx", "tx";
-                        status = "disabled";
-                };
-
-                uart3: serial@01c28c00 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28c00 0x400>;
-                        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clocks = <&ccu CLK_BUS_UART3>;
-                        resets = <&ccu RST_BUS_UART3>;
-                        dmas = <&dma 9>, <&dma 9>;
-                        dma-names = "rx", "tx";
-                        status = "disabled";
-                };
-
-                i2c0: i2c@01c2ac00 {
-                        compatible = "allwinner,sun6i-a31-i2c";
-                        reg = <0x01c2ac00 0x400>;
-                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_I2C0>;
-                        resets = <&ccu RST_BUS_I2C0>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&i2c0_pins>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                i2c1: i2c@01c2b000 {
-                        compatible = "allwinner,sun6i-a31-i2c";
-                        reg = <0x01c2b000 0x400>;
-                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_I2C1>;
-                        resets = <&ccu RST_BUS_I2C1>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&i2c1_pins>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                i2c2: i2c@01c2b400 {
-                        compatible = "allwinner,sun6i-a31-i2c";
-                        reg = <0x01c2b000 0x400>;
-                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_I2C2>;
-                        resets = <&ccu RST_BUS_I2C2>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&i2c2_pins>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
-                gic: interrupt-controller@01c81000 {
-                        compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
-                        reg = <0x01c81000 0x1000>,
-                              <0x01c82000 0x2000>,
-                              <0x01c84000 0x2000>,
-                              <0x01c86000 0x2000>;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-                };
-
-                rtc: rtc@01f00000 {
-                        compatible = "allwinner,sun6i-a31-rtc";
-                        reg = <0x01f00000 0x54>;
-                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-                };
-
-                apb0_reset: reset@01f014b0 {
-                        reg = <0x01f014b0 0x4>;
-                        compatible = "allwinner,sun6i-a31-clock-reset";
-                        #reset-cells = <1>;
-                };
+&ccu {
+        compatible = "allwinner,sun8i-h3-ccu";
+};
 
-                codec_analog: codec-analog@01f015c0 {
-                        compatible = "allwinner,sun8i-h3-codec-analog";
-                        reg = <0x01f015c0 0x4>;
-                };
+&mmc0 {
+        compatible = "allwinner,sun7i-a20-mmc";
+        clocks = <&ccu CLK_BUS_MMC0>,
+                 <&ccu CLK_MMC0>,
+                 <&ccu CLK_MMC0_OUTPUT>,
+                 <&ccu CLK_MMC0_SAMPLE>;
+        clock-names = "ahb",
+                      "mmc",
+                      "output",
+                      "sample";
+};
 
-                ir: ir@01f02000 {
-                        compatible = "allwinner,sun5i-a13-ir";
-                        clocks = <&apb0_gates 1>, <&ir_clk>;
-                        clock-names = "apb", "ir";
-                        resets = <&apb0_reset 1>;
-                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-                        reg = <0x01f02000 0x40>;
-                        status = "disabled";
-                };
+&mmc1 {
+        compatible = "allwinner,sun7i-a20-mmc";
+        clocks = <&ccu CLK_BUS_MMC1>,
+                 <&ccu CLK_MMC1>,
+                 <&ccu CLK_MMC1_OUTPUT>,
+                 <&ccu CLK_MMC1_SAMPLE>;
+        clock-names = "ahb",
+                      "mmc",
+                      "output",
+                      "sample";
+};
 
-                r_pio: pinctrl@01f02c00 {
-                        compatible = "allwinner,sun8i-h3-r-pinctrl";
-                        reg = <0x01f02c00 0x400>;
-                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
-                        clock-names = "apb", "hosc", "losc";
-                        resets = <&apb0_reset 0>;
-                        gpio-controller;
-                        #gpio-cells = <3>;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
+&mmc2 {
+        compatible = "allwinner,sun7i-a20-mmc";
+        clocks = <&ccu CLK_BUS_MMC2>,
+                 <&ccu CLK_MMC2>,
+                 <&ccu CLK_MMC2_OUTPUT>,
+                 <&ccu CLK_MMC2_SAMPLE>;
+        clock-names = "ahb",
+                      "mmc",
+                      "output",
+                      "sample";
+};
 
-                        ir_pins_a: ir@0 {
-                                pins = "PL11";
-                                function = "s_cir_rx";
-                        };
-                };
-        };
+&pio {
+        compatible = "allwinner,sun8i-h3-pinctrl";
 };
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 9112a200fd5e..3741ac71c3d6 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -47,7 +47,6 @@
 #include "sun9i-a80.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Cubietech Cubieboard4";
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 0fc3a87f5576..85f1ad670310 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -46,7 +46,6 @@
 #include "sun9i-a80.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
         model = "Merrii A80 Optimus Board";
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 15b6d122f878..759a72317eb8 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -46,8 +46,6 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
 #include <dt-bindings/clock/sun9i-a80-ccu.h>
 #include <dt-bindings/clock/sun9i-a80-de.h>
 #include <dt-bindings/clock/sun9i-a80-usb.h>
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index 17c09fed9e84..ce5c53e4452f 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -43,7 +43,6 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 &pio {
         ahci_pwr_pin_a: ahci_pwr_pin@0 {
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
new file mode 100644
index 000000000000..6640ebfa6419
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -0,0 +1,618 @@
+/*
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/sun8i-h3-ccu.h>
+
+/ {
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                osc24M: osc24M_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                        clock-output-names = "osc24M";
+                };
+
+                osc32k: osc32k_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                        clock-output-names = "osc32k";
+                };
+
+                apb0: apb0_clk {
+                        compatible = "fixed-factor-clock";
+                        #clock-cells = <0>;
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "apb0";
+                };
+
+                apb0_gates: clk@01f01428 {
+                        compatible = "allwinner,sun8i-h3-apb0-gates-clk",
+                                     "allwinner,sun4i-a10-gates-clk";
+                        reg = <0x01f01428 0x4>;
+                        #clock-cells = <1>;
+                        clocks = <&apb0>;
+                        clock-indices = <0>, <1>;
+                        clock-output-names = "apb0_pio", "apb0_ir";
+                };
+
+                ir_clk: ir_clk@01f01454 {
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01f01454 0x4>;
+                        #clock-cells = <0>;
+                        clocks = <&osc32k>, <&osc24M>;
+                        clock-output-names = "ir";
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                dma: dma-controller@01c02000 {
+                        compatible = "allwinner,sun8i-h3-dma";
+                        reg = <0x01c02000 0x1000>;
+                        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_DMA>;
+                        resets = <&ccu RST_BUS_DMA>;
+                        #dma-cells = <1>;
+                };
+
+                mmc0: mmc@01c0f000 {
+                        /* compatible and clocks are in per SoC .dtsi file */
+                        reg = <0x01c0f000 0x1000>;
+                        resets = <&ccu RST_BUS_MMC0>;
+                        reset-names = "ahb";
+                        interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                mmc1: mmc@01c10000 {
+                        /* compatible and clocks are in per SoC .dtsi file */
+                        reg = <0x01c10000 0x1000>;
+                        resets = <&ccu RST_BUS_MMC1>;
+                        reset-names = "ahb";
+                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                mmc2: mmc@01c11000 {
+                        /* compatible and clocks are in per SoC .dtsi file */
+                        reg = <0x01c11000 0x1000>;
+                        resets = <&ccu RST_BUS_MMC2>;
+                        reset-names = "ahb";
+                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                usb_otg: usb@01c19000 {
+                        compatible = "allwinner,sun8i-h3-musb";
+                        reg = <0x01c19000 0x400>;
+                        clocks = <&ccu CLK_BUS_OTG>;
+                        resets = <&ccu RST_BUS_OTG>;
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "mc";
+                        phys = <&usbphy 0>;
+                        phy-names = "usb";
+                        extcon = <&usbphy 0>;
+                        status = "disabled";
+                };
+
+                usbphy: phy@01c19400 {
+                        compatible = "allwinner,sun8i-h3-usb-phy";
+                        reg = <0x01c19400 0x2c>,
+                              <0x01c1a800 0x4>,
+                              <0x01c1b800 0x4>,
+                              <0x01c1c800 0x4>,
+                              <0x01c1d800 0x4>;
+                        reg-names = "phy_ctrl",
+                                    "pmu0",
+                                    "pmu1",
+                                    "pmu2",
+                                    "pmu3";
+                        clocks = <&ccu CLK_USB_PHY0>,
+                                 <&ccu CLK_USB_PHY1>,
+                                 <&ccu CLK_USB_PHY2>,
+                                 <&ccu CLK_USB_PHY3>;
+                        clock-names = "usb0_phy",
+                                      "usb1_phy",
+                                      "usb2_phy",
+                                      "usb3_phy";
+                        resets = <&ccu RST_USB_PHY0>,
+                                 <&ccu RST_USB_PHY1>,
+                                 <&ccu RST_USB_PHY2>,
+                                 <&ccu RST_USB_PHY3>;
+                        reset-names = "usb0_reset",
+                                      "usb1_reset",
+                                      "usb2_reset",
+                                      "usb3_reset";
+                        status = "disabled";
+                        #phy-cells = <1>;
+                };
+
+                ehci0: usb@01c1a000 {
+                        compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+                        reg = <0x01c1a000 0x100>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+                        resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@01c1a400 {
+                        compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+                        reg = <0x01c1a400 0x100>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
+                                 <&ccu CLK_USB_OHCI0>;
+                        resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+                        status = "disabled";
+                };
+
+                ehci1: usb@01c1b000 {
+                        compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+                        reg = <0x01c1b000 0x100>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
+                        resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+
+                ohci1: usb@01c1b400 {
+                        compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+                        reg = <0x01c1b400 0x100>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
+                                 <&ccu CLK_USB_OHCI1>;
+                        resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+
+                ehci2: usb@01c1c000 {
+                        compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+                        reg = <0x01c1c000 0x100>;
+                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
+                        resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
+                        phys = <&usbphy 2>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+
+                ohci2: usb@01c1c400 {
+                        compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+                        reg = <0x01c1c400 0x100>;
+                        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
+                                 <&ccu CLK_USB_OHCI2>;
+                        resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
+                        phys = <&usbphy 2>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+
+                ehci3: usb@01c1d000 {
+                        compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+                        reg = <0x01c1d000 0x100>;
+                        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
+                        resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
+                        phys = <&usbphy 3>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+
+                ohci3: usb@01c1d400 {
+                        compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+                        reg = <0x01c1d400 0x100>;
+                        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
+                                 <&ccu CLK_USB_OHCI3>;
+                        resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
+                        phys = <&usbphy 3>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+
+                ccu: clock@01c20000 {
+                        /* compatible is in per SoC .dtsi file */
+                        reg = <0x01c20000 0x400>;
+                        clocks = <&osc24M>, <&osc32k>;
+                        clock-names = "hosc", "losc";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
+
+                pio: pinctrl@01c20800 {
+                        /* compatible is in per SoC .dtsi file */
+                        reg = <0x01c20800 0x400>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+                        clock-names = "apb", "hosc", "losc";
+                        gpio-controller;
+                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+
+                        i2c0_pins: i2c0 {
+                                pins = "PA11", "PA12";
+                                function = "i2c0";
+                        };
+
+                        i2c1_pins: i2c1 {
+                                pins = "PA18", "PA19";
+                                function = "i2c1";
+                        };
+
+                        i2c2_pins: i2c2 {
+                                pins = "PE12", "PE13";
+                                function = "i2c2";
+                        };
+
+                        mmc0_pins_a: mmc0@0 {
+                                pins = "PF0", "PF1", "PF2", "PF3",
+                                       "PF4", "PF5";
+                                function = "mmc0";
+                                drive-strength = <30>;
+                                bias-pull-up;
+                        };
+
+                        mmc0_cd_pin: mmc0_cd_pin@0 {
+                                pins = "PF6";
+                                function = "gpio_in";
+                                bias-pull-up;
+                        };
+
+                        mmc1_pins_a: mmc1@0 {
+                                pins = "PG0", "PG1", "PG2", "PG3",
+                                       "PG4", "PG5";
+                                function = "mmc1";
+                                drive-strength = <30>;
+                                bias-pull-up;
+                        };
+
+                        mmc2_8bit_pins: mmc2_8bit {
+                                pins = "PC5", "PC6", "PC8",
+                                       "PC9", "PC10", "PC11",
+                                       "PC12", "PC13", "PC14",
+                                       "PC15", "PC16";
+                                function = "mmc2";
+                                drive-strength = <30>;
+                                bias-pull-up;
+                        };
+
+                        spdif_tx_pins_a: spdif@0 {
+                                pins = "PA17";
+                                function = "spdif";
+                        };
+
+                        spi0_pins: spi0 {
+                                pins = "PC0", "PC1", "PC2", "PC3";
+                                function = "spi0";
+                        };
+
+                        spi1_pins: spi1 {
+                                pins = "PA15", "PA16", "PA14", "PA13";
+                                function = "spi1";
+                        };
+
+                        uart0_pins_a: uart0@0 {
+                                pins = "PA4", "PA5";
+                                function = "uart0";
+                        };
+
+                        uart1_pins: uart1 {
+                                pins = "PG6", "PG7";
+                                function = "uart1";
+                        };
+
+                        uart1_rts_cts_pins: uart1_rts_cts {
+                                pins = "PG8", "PG9";
+                                function = "uart1";
+                        };
+
+                        uart2_pins: uart2 {
+                                pins = "PA0", "PA1";
+                                function = "uart2";
+                        };
+
+                        uart3_pins: uart3 {
+                                pins = "PA13", "PA14";
+                                function = "uart3";
+                        };
+                };
+
+                timer@01c20c00 {
+                        compatible = "allwinner,sun4i-a10-timer";
+                        reg = <0x01c20c00 0xa0>;
+                        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&osc24M>;
+                };
+
+                spi0: spi@01c68000 {
+                        compatible = "allwinner,sun8i-h3-spi";
+                        reg = <0x01c68000 0x1000>;
+                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+                        clock-names = "ahb", "mod";
+                        dmas = <&dma 23>, <&dma 23>;
+                        dma-names = "rx", "tx";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi0_pins>;
+                        resets = <&ccu RST_BUS_SPI0>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                spi1: spi@01c69000 {
+                        compatible = "allwinner,sun8i-h3-spi";
+                        reg = <0x01c69000 0x1000>;
+                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+                        clock-names = "ahb", "mod";
+                        dmas = <&dma 24>, <&dma 24>;
+                        dma-names = "rx", "tx";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi1_pins>;
+                        resets = <&ccu RST_BUS_SPI1>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                wdt0: watchdog@01c20ca0 {
+                        compatible = "allwinner,sun6i-a31-wdt";
+                        reg = <0x01c20ca0 0x20>;
+                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                spdif: spdif@01c21000 {
+                        #sound-dai-cells = <0>;
+                        compatible = "allwinner,sun8i-h3-spdif";
+                        reg = <0x01c21000 0x400>;
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
+                        resets = <&ccu RST_BUS_SPDIF>;
+                        clock-names = "apb", "spdif";
+                        dmas = <&dma 2>;
+                        dma-names = "tx";
+                        status = "disabled";
+                };
+
+                pwm: pwm@01c21400 {
+                        compatible = "allwinner,sun8i-h3-pwm";
+                        reg = <0x01c21400 0x8>;
+                        clocks = <&osc24M>;
+                        #pwm-cells = <3>;
+                        status = "disabled";
+                };
+
+                codec: codec@01c22c00 {
+                        #sound-dai-cells = <0>;
+                        compatible = "allwinner,sun8i-h3-codec";
+                        reg = <0x01c22c00 0x400>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
+                        clock-names = "apb", "codec";
+                        resets = <&ccu RST_BUS_CODEC>;
+                        dmas = <&dma 15>, <&dma 15>;
+                        dma-names = "rx", "tx";
+                        allwinner,codec-analog-controls = <&codec_analog>;
+                        status = "disabled";
+                };
+
+                uart0: serial@01c28000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28000 0x400>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu CLK_BUS_UART0>;
+                        resets = <&ccu RST_BUS_UART0>;
+                        dmas = <&dma 6>, <&dma 6>;
+                        dma-names = "rx", "tx";
+                        status = "disabled";
+                };
+
+                uart1: serial@01c28400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu CLK_BUS_UART1>;
+                        resets = <&ccu RST_BUS_UART1>;
+                        dmas = <&dma 7>, <&dma 7>;
+                        dma-names = "rx", "tx";
+                        status = "disabled";
+                };
+
+                uart2: serial@01c28800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28800 0x400>;
+                        interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu CLK_BUS_UART2>;
+                        resets = <&ccu RST_BUS_UART2>;
+                        dmas = <&dma 8>, <&dma 8>;
+                        dma-names = "rx", "tx";
+                        status = "disabled";
+                };
+
+                uart3: serial@01c28c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28c00 0x400>;
+                        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu CLK_BUS_UART3>;
+                        resets = <&ccu RST_BUS_UART3>;
+                        dmas = <&dma 9>, <&dma 9>;
+                        dma-names = "rx", "tx";
+                        status = "disabled";
+                };
+
+                i2c0: i2c@01c2ac00 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x01c2ac00 0x400>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_I2C0>;
+                        resets = <&ccu RST_BUS_I2C0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c1: i2c@01c2b000 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x01c2b000 0x400>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_I2C1>;
+                        resets = <&ccu RST_BUS_I2C1>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c2: i2c@01c2b400 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x01c2b000 0x400>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_I2C2>;
+                        resets = <&ccu RST_BUS_I2C2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                gic: interrupt-controller@01c81000 {
+                        compatible = "arm,gic-400";
+                        reg = <0x01c81000 0x1000>,
+                              <0x01c82000 0x2000>,
+                              <0x01c84000 0x2000>,
+                              <0x01c86000 0x2000>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                };
+
+                rtc: rtc@01f00000 {
+                        compatible = "allwinner,sun6i-a31-rtc";
+                        reg = <0x01f00000 0x54>;
+                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                apb0_reset: reset@01f014b0 {
+                        reg = <0x01f014b0 0x4>;
+                        compatible = "allwinner,sun6i-a31-clock-reset";
+                        #reset-cells = <1>;
+                };
+
+                codec_analog: codec-analog@01f015c0 {
+                        compatible = "allwinner,sun8i-h3-codec-analog";
+                        reg = <0x01f015c0 0x4>;
+                };
+
+                ir: ir@01f02000 {
+                        compatible = "allwinner,sun5i-a13-ir";
+                        clocks = <&apb0_gates 1>, <&ir_clk>;
+                        clock-names = "apb", "ir";
+                        resets = <&apb0_reset 1>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0x01f02000 0x40>;
+                        status = "disabled";
+                };
+
+                r_pio: pinctrl@01f02c00 {
+                        compatible = "allwinner,sun8i-h3-r-pinctrl";
+                        reg = <0x01f02c00 0x400>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+                        clock-names = "apb", "hosc", "losc";
+                        resets = <&apb0_reset 0>;
+                        gpio-controller;
+                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+
+                        ir_pins_a: ir@0 {
+                                pins = "PL11";
+                                function = "s_cir_rx";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
index b8241462fcea..245d0bcde441 100644
--- a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
@@ -42,7 +42,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include "sunxi-common-regulators.dtsi"
 
 &i2c0 {
diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts
index 110031bc0e7e..e0da4ee21c21 100644
--- a/arch/arm/boot/dts/uniphier-ld4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts
@@ -52,11 +52,6 @@
         model = "UniPhier LD4 Reference Board";
         compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4";
 
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x20000000>;
-        };
-
         chosen {
                 stdout-path = "serial0:115200n8";
         };
@@ -71,6 +66,11 @@
                 i2c2 = &i2c2;
                 i2c3 = &i2c3;
         };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>;
+        };
 };
 
 &ethsc {
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index a7c494d7c43a..4f5fe15eaee2 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -43,10 +43,10 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/include/ "skeleton.dtsi"
-
 / {
         compatible = "socionext,uniphier-ld4";
+        #address-cells = <1>;
+        #size-cells = <1>;
 
         cpus {
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
index c05d631dcf02..a397a8811c78 100644
--- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
@@ -52,11 +52,6 @@
         model = "UniPhier LD6b Reference Board";
         compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";
 
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x80000000>;
-        };
-
         chosen {
                 stdout-path = "serial0:115200n8";
         };
@@ -73,6 +68,11 @@
                 i2c5 = &i2c5;
                 i2c6 = &i2c6;
         };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x80000000>;
+        };
 };
 
 &ethsc {
diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
index 8ee79da9af7c..246f35ffb638 100644
--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
@@ -45,7 +45,7 @@
 
 &pinctrl {
         pinctrl_emmc: emmc_grp {
-                groups = "emmc";
+                groups = "emmc", "emmc_dat8";
                 function = "emmc";
         };
 
diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts
index 0ab0a40c041e..fefc89149234 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts
@@ -50,11 +50,6 @@
         model = "UniPhier Pro4 Ace Board";
         compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4";
 
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x40000000>;
-        };
-
         chosen {
                 stdout-path = "serial0:115200n8";
         };
@@ -70,6 +65,11 @@
                 i2c5 = &i2c5;
                 i2c6 = &i2c6;
         };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>;
+        };
 };
 
 &serial0 {
@@ -90,6 +90,7 @@
         eeprom@54 {
                 compatible = "st,24c64";
                 reg = <0x54>;
+                pagesize = <32>;
         };
 };
 
diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts
index 9e92e60d25ce..6077e634d14a 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts
@@ -52,11 +52,6 @@
         model = "UniPhier Pro4 Reference Board";
         compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";
 
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x40000000>;
-        };
-
         chosen {
                 stdout-path = "serial0:115200n8";
         };
@@ -73,6 +68,11 @@
                 i2c5 = &i2c5;
                 i2c6 = &i2c6;
         };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>;
+        };
 };
 
 &ethsc {
diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
index dc4ea8832ce2..6c63c8bad825 100644
--- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
@@ -50,11 +50,6 @@
         model = "UniPhier Pro4 Sanji Board";
         compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4";
 
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x80000000>;
-        };
-
         chosen {
                 stdout-path = "serial0:115200n8";
         };
@@ -69,6 +64,11 @@
                 i2c5 = &i2c5;
                 i2c6 = &i2c6;
         };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x80000000>;
+        };
 };
 
 &serial0 {
@@ -85,6 +85,7 @@
         eeprom@54 {
                 compatible = "st,24c64";
                 reg = <0x54>;
+                pagesize = <32>;
         };
 };
 
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index e960b09ff01c..794a85a7068b 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -43,10 +43,10 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/include/ "skeleton.dtsi"
-
 / {
         compatible = "socionext,uniphier-pro4";
+        #address-cells = <1>;
+        #size-cells = <1>;
 
         cpus {
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index dbc5e5333163..df07b555cbed 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -43,10 +43,10 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/include/ "skeleton.dtsi"
-
 / {
         compatible = "socionext,uniphier-pro5";
+        #address-cells = <1>;
+        #size-cells = <1>;
 
         cpus {
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
index 373818ace086..cccc86658d20 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
@@ -51,11 +51,6 @@
         compatible = "socionext,uniphier-pxs2-gentil",
                      "socionext,uniphier-pxs2";
 
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x80000000>;
-        };
-
         chosen {
                 stdout-path = "serial0:115200n8";
         };
@@ -70,6 +65,11 @@
                 i2c5 = &i2c5;
                 i2c6 = &i2c6;
         };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x80000000>;
+        };
 };
 
 &serial2 {
@@ -82,6 +82,7 @@
         eeprom@54 {
                 compatible = "st,24c64";
                 reg = <0x54>;
+                pagesize = <32>;
         };
 };
 
diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
index 51a3eacddfc6..803a39aa39d0 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
@@ -50,11 +50,6 @@
         model = "UniPhier PXs2 Vodka Board";
         compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2";
 
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x80000000>;
-        };
-
         chosen {
                 stdout-path = "serial0:115200n8";
         };
@@ -68,6 +63,11 @@
                 i2c5 = &i2c5;
                 i2c6 = &i2c6;
         };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x80000000>;
+        };
 };
 
 &serial2 {
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index e9e031d63c1a..58c3e2f35706 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -43,10 +43,10 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/include/ "skeleton.dtsi"
-
 / {
         compatible = "socionext,uniphier-pxs2";
+        #address-cells = <1>;
+        #size-cells = <1>;
 
         cpus {
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
index f7df0881c5e0..c62ae1a81f47 100644
--- a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
+++ b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
@@ -1,7 +1,8 @@
 /*
  * Device Tree Source for UniPhier Reference Daughter Board
  *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -46,5 +47,6 @@
         eeprom@50 {
                 compatible = "microchip,24lc128";
                 reg = <0x50>;
+                pagesize = <64>;
         };
 };
diff --git a/arch/arm/boot/dts/uniphier-sld3-ref.dts b/arch/arm/boot/dts/uniphier-sld3-ref.dts
index ac792ae07ae0..eb63dcca92b5 100644
--- a/arch/arm/boot/dts/uniphier-sld3-ref.dts
+++ b/arch/arm/boot/dts/uniphier-sld3-ref.dts
@@ -52,12 +52,6 @@
         model = "UniPhier sLD3 Reference Board";
         compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
 
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x20000000
-                       0xc0000000 0x20000000>;
-        };
-
         chosen {
                 stdout-path = "serial0:115200n8";
         };
@@ -72,6 +66,12 @@
                 i2c3 = &i2c3;
                 i2c4 = &i2c4;
         };
+
+        memory@8000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000
+                       0xc0000000 0x20000000>;
+        };
 };
 
 &ethsc {
diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi
index 9fad6bd2db8a..01d77edac01f 100644
--- a/arch/arm/boot/dts/uniphier-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld3.dtsi
@@ -43,10 +43,10 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/include/ "skeleton.dtsi"
-
 / {
         compatible = "socionext,uniphier-sld3";
+        #address-cells = <1>;
+        #size-cells = <1>;
 
         cpus {
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts
index a8291f988066..737d276349fd 100644
--- a/arch/arm/boot/dts/uniphier-sld8-ref.dts
+++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts
@@ -52,11 +52,6 @@
         model = "UniPhier sLD8 Reference Board";
         compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8";
 
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x20000000>;
-        };
-
         chosen {
                 stdout-path = "serial0:115200n8";
         };
@@ -71,6 +66,11 @@
                 i2c2 = &i2c2;
                 i2c3 = &i2c3;
         };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>;
+        };
 };
 
 &ethsc {
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index b2c980ead7f0..eb06fdc04b02 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -43,10 +43,10 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/include/ "skeleton.dtsi"
-
 / {
         compatible = "socionext,uniphier-sld8";
+        #address-cells = <1>;
+        #size-cells = <1>;
 
         cpus {
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi
index 51ecc9b9c0ce..f61dfec2807f 100644
--- a/arch/arm/boot/dts/uniphier-support-card.dtsi
+++ b/arch/arm/boot/dts/uniphier-support-card.dtsi
@@ -1,7 +1,8 @@
 /*
  * Device Tree Source for UniPhier Support Card (Expansion Board)
  *
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -46,7 +47,7 @@
         status = "okay";
         ranges = <1 0x00000000 0x42000000 0x02000000>;
 
-        support_card: support_card {
+        support_card: support_card@1,1f00000 {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index 3086efacd00e..35714ff6f467 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -71,7 +71,7 @@
                         #size-cells = <1>;
                         ranges = <0 3 0 0x200000>;
 
-                        v2m_sysreg: sysreg@010000 {
+                        v2m_sysreg: sysreg@10000 {
                                 compatible = "arm,vexpress-sysreg";
                                 reg = <0x010000 0x1000>;
 
@@ -94,7 +94,7 @@
                                 };
                         };
 
-                        v2m_sysctl: sysctl@020000 {
+                        v2m_sysctl: sysctl@20000 {
                                 compatible = "arm,sp810", "arm,primecell";
                                 reg = <0x020000 0x1000>;
                                 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
@@ -106,7 +106,7 @@
                         };
 
                         /* PCI-E I2C bus */
-                        v2m_i2c_pcie: i2c@030000 {
+                        v2m_i2c_pcie: i2c@30000 {
                                 compatible = "arm,versatile-i2c";
                                 reg = <0x030000 0x1000>;
 
@@ -119,7 +119,7 @@
                                 };
                         };
 
-                        aaci@040000 {
+                        aaci@40000 {
                                 compatible = "arm,pl041", "arm,primecell";
                                 reg = <0x040000 0x1000>;
                                 interrupts = <11>;
@@ -127,7 +127,7 @@
                                 clock-names = "apb_pclk";
                         };
 
-                        mmci@050000 {
+                        mmci@50000 {
                                 compatible = "arm,pl180", "arm,primecell";
                                 reg = <0x050000 0x1000>;
                                 interrupts = <9 10>;
@@ -139,7 +139,7 @@
                                 clock-names = "mclk", "apb_pclk";
                         };
 
-                        kmi@060000 {
+                        kmi@60000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x060000 0x1000>;
                                 interrupts = <12>;
@@ -147,7 +147,7 @@
                                 clock-names = "KMIREFCLK", "apb_pclk";
                         };
 
-                        kmi@070000 {
+                        kmi@70000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x070000 0x1000>;
                                 interrupts = <13>;
@@ -155,7 +155,7 @@
                                 clock-names = "KMIREFCLK", "apb_pclk";
                         };
 
-                        v2m_serial0: uart@090000 {
+                        v2m_serial0: uart@90000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x090000 0x1000>;
                                 interrupts = <5>;
@@ -163,7 +163,7 @@
                                 clock-names = "uartclk", "apb_pclk";
                         };
 
-                        v2m_serial1: uart@0a0000 {
+                        v2m_serial1: uart@a0000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0a0000 0x1000>;
                                 interrupts = <6>;
@@ -171,7 +171,7 @@
                                 clock-names = "uartclk", "apb_pclk";
                         };
 
-                        v2m_serial2: uart@0b0000 {
+                        v2m_serial2: uart@b0000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0b0000 0x1000>;
                                 interrupts = <7>;
@@ -179,7 +179,7 @@
                                 clock-names = "uartclk", "apb_pclk";
                         };
 
-                        v2m_serial3: uart@0c0000 {
+                        v2m_serial3: uart@c0000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0c0000 0x1000>;
                                 interrupts = <8>;
@@ -187,7 +187,7 @@
                                 clock-names = "uartclk", "apb_pclk";
                         };
 
-                        wdt@0f0000 {
+                        wdt@f0000 {
                                 compatible = "arm,sp805", "arm,primecell";
                                 reg = <0x0f0000 0x1000>;
                                 interrupts = <0>;
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index c6393d3f1719..1b6f6393be93 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -70,7 +70,7 @@
                         #size-cells = <1>;
                         ranges = <0 7 0 0x20000>;
 
-                        v2m_sysreg: sysreg@00000 {
+                        v2m_sysreg: sysreg@0 {
                                 compatible = "arm,vexpress-sysreg";
                                 reg = <0x00000 0x1000>;
 
@@ -93,7 +93,7 @@
                                 };
                         };
 
-                        v2m_sysctl: sysctl@01000 {
+                        v2m_sysctl: sysctl@1000 {
                                 compatible = "arm,sp810", "arm,primecell";
                                 reg = <0x01000 0x1000>;
                                 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
@@ -105,7 +105,7 @@
                         };
 
                         /* PCI-E I2C bus */
-                        v2m_i2c_pcie: i2c@02000 {
+                        v2m_i2c_pcie: i2c@2000 {
                                 compatible = "arm,versatile-i2c";
                                 reg = <0x02000 0x1000>;
 
@@ -118,7 +118,7 @@
                                 };
                         };
 
-                        aaci@04000 {
+                        aaci@4000 {
                                 compatible = "arm,pl041", "arm,primecell";
                                 reg = <0x04000 0x1000>;
                                 interrupts = <11>;
@@ -126,7 +126,7 @@
                                 clock-names = "apb_pclk";
                         };
 
-                        mmci@05000 {
+                        mmci@5000 {
                                 compatible = "arm,pl180", "arm,primecell";
                                 reg = <0x05000 0x1000>;
                                 interrupts = <9 10>;
@@ -138,7 +138,7 @@
                                 clock-names = "mclk", "apb_pclk";
                         };
 
-                        kmi@06000 {
+                        kmi@6000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x06000 0x1000>;
                                 interrupts = <12>;
@@ -146,7 +146,7 @@
                                 clock-names = "KMIREFCLK", "apb_pclk";
                         };
 
-                        kmi@07000 {
+                        kmi@7000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x07000 0x1000>;
                                 interrupts = <13>;
@@ -154,7 +154,7 @@
                                 clock-names = "KMIREFCLK", "apb_pclk";
                         };
 
-                        v2m_serial0: uart@09000 {
+                        v2m_serial0: uart@9000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x09000 0x1000>;
                                 interrupts = <5>;
@@ -162,7 +162,7 @@
                                 clock-names = "uartclk", "apb_pclk";
                         };
 
-                        v2m_serial1: uart@0a000 {
+                        v2m_serial1: uart@a000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0a000 0x1000>;
                                 interrupts = <6>;
@@ -170,7 +170,7 @@
                                 clock-names = "uartclk", "apb_pclk";
                         };
 
-                        v2m_serial2: uart@0b000 {
+                        v2m_serial2: uart@b000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0b000 0x1000>;
                                 interrupts = <7>;
@@ -178,7 +178,7 @@
                                 clock-names = "uartclk", "apb_pclk";
                         };
 
-                        v2m_serial3: uart@0c000 {
+                        v2m_serial3: uart@c000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0c000 0x1000>;
                                 interrupts = <8>;
@@ -186,7 +186,7 @@
                                 clock-names = "uartclk", "apb_pclk";
                         };
 
-                        wdt@0f000 {
+                        wdt@f000 {
                                 compatible = "arm,sp805", "arm,primecell";
                                 reg = <0x0f000 0x1000>;
                                 interrupts = <0>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 15f4fd3f4695..0c8de0ca73ee 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -220,7 +220,7 @@
                 };
         };
 
-        smb@08000000 {
+        smb@8000000 {
                 compatible = "simple-bus";
 
                 #address-cells = <2>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index bd107c5a0226..65ecf206388c 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -385,7 +385,7 @@
                 };
         };
 
-        etb@0,20010000 {
+        etb@20010000 {
                 compatible = "arm,coresight-etb10", "arm,primecell";
                 reg = <0 0x20010000 0 0x1000>;
 
@@ -399,7 +399,7 @@
                 };
         };
 
-        tpiu@0,20030000 {
+        tpiu@20030000 {
                 compatible = "arm,coresight-tpiu", "arm,primecell";
                 reg = <0 0x20030000 0 0x1000>;
 
@@ -449,7 +449,7 @@
                 };
         };
 
-        funnel@0,20040000 {
+        funnel@20040000 {
                 compatible = "arm,coresight-funnel", "arm,primecell";
                 reg = <0 0x20040000 0 0x1000>;
 
@@ -513,7 +513,7 @@
                 };
         };
 
-        ptm@0,2201c000 {
+        ptm@2201c000 {
                 compatible = "arm,coresight-etm3x", "arm,primecell";
                 reg = <0 0x2201c000 0 0x1000>;
 
@@ -527,7 +527,7 @@
                 };
         };
 
-        ptm@0,2201d000 {
+        ptm@2201d000 {
                 compatible = "arm,coresight-etm3x", "arm,primecell";
                 reg = <0 0x2201d000 0 0x1000>;
 
@@ -541,7 +541,7 @@
                 };
         };
 
-        etm@0,2203c000 {
+        etm@2203c000 {
                 compatible = "arm,coresight-etm3x", "arm,primecell";
                 reg = <0 0x2203c000 0 0x1000>;
 
@@ -555,7 +555,7 @@
                 };
         };
 
-        etm@0,2203d000 {
+        etm@2203d000 {
                 compatible = "arm,coresight-etm3x", "arm,primecell";
                 reg = <0 0x2203d000 0 0x1000>;
 
@@ -569,7 +569,7 @@
                 };
         };
 
-        etm@0,2203e000 {
+        etm@2203e000 {
                 compatible = "arm,coresight-etm3x", "arm,primecell";
                 reg = <0 0x2203e000 0 0x1000>;
 
@@ -583,7 +583,7 @@
                 };
         };
 
-        smb@08000000 {
+        smb@8000000 {
                 compatible = "simple-bus";
 
                 #address-cells = <2>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 1acecaf4b13d..6e69b8e6c1a7 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -190,7 +190,7 @@
                 };
         };
 
-        smb@08000000 {
+        smb@8000000 {
                 compatible = "simple-bus";
 
                 #address-cells = <2>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index b608a03ee02f..c9305b58afc2 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -300,7 +300,7 @@
                 };
         };
 
-        smb@04000000 {
+        smb@4000000 {
                 compatible = "simple-bus";
 
                 #address-cells = <2>;
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
index 7940408838df..37f95427616f 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
@@ -239,7 +239,7 @@
                         #size-cells = <0>;
                         reg = <4>;
 
-                        switch2: switch2@0 {
+                        switch2: switch@0 {
                                 compatible = "marvell,mv88e6085";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -459,18 +459,6 @@
                 >;
         };
 
-        pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
-                fsl,pins = <
-                        VF610_PAD_PTB5__GPIO_27         0x219d
-                >;
-        };
-
-        pinctrl_gpio_switch1: pinctrl-gpio-switch1 {
-                fsl,pins = <
-                        VF610_PAD_PTB4__GPIO_26         0x219d
-                >;
-        };
-
         pinctrl_mdio_mux: pinctrl-mdio-mux {
                 fsl,pins = <
                         VF610_PAD_PTA18__GPIO_8         0x31c2
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
index 6a45bd24ffe6..db3b408ea55a 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
@@ -67,11 +67,17 @@
 
                         switch0: switch@0 {
                                 compatible = "marvell,mv88e6190";
+                                pinctrl-0 = <&pinctrl_gpio_switch0>;
+                                pinctrl-names = "default";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 reg = <0>;
                                 dsa,member = <0 0>;
                                 eeprom-length = <512>;
+                                interrupt-parent = <&gpio0>;
+                                interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
 
                                 ports {
                                         #address-cells = <1>;
@@ -91,21 +97,25 @@
                                         port@1 {
                                                 reg = <1>;
                                                 label = "lan1";
+                                                phy-handle = <&switch0phy1>;
                                         };
 
                                         port@2 {
                                                 reg = <2>;
                                                 label = "lan2";
+                                                phy-handle = <&switch0phy2>;
                                         };
 
                                         port@3 {
                                                 reg = <3>;
                                                 label = "lan3";
+                                                phy-handle = <&switch0phy3>;
                                         };
 
                                         port@4 {
                                                 reg = <4>;
                                                 label = "lan4";
+                                                phy-handle = <&switch0phy4>;
                                         };
 
                                         switch0port10: port@10 {
@@ -115,6 +125,35 @@
                                                 link = <&switch1port10>;
                                         };
                                 };
+
+                                mdio {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        switch0phy1: switch0phy@1 {
+                                                reg = <1>;
+                                                interrupt-parent = <&switch0>;
+                                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+                                        };
+
+                                        switch0phy2: switch0phy@2 {
+                                                reg = <2>;
+                                                interrupt-parent = <&switch0>;
+                                                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+                                        };
+
+                                        switch0phy3: switch0phy@3 {
+                                                reg = <3>;
+                                                interrupt-parent = <&switch0>;
+                                                interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+                                        };
+
+                                        switch0phy4: switch0phy@4 {
+                                                reg = <4>;
+                                                interrupt-parent = <&switch0>;
+                                                interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+                                        };
+                                };
                         };
                 };
 
@@ -125,11 +164,17 @@
 
                         switch1: switch@0 {
                                 compatible = "marvell,mv88e6190";
+                                pinctrl-0 = <&pinctrl_gpio_switch1>;
+                                pinctrl-names = "default";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 reg = <0>;
                                 dsa,member = <0 1>;
                                 eeprom-length = <512>;
+                                interrupt-parent = <&gpio0>;
+                                interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
 
                                 ports {
                                         #address-cells = <1>;
@@ -138,21 +183,25 @@
                                         port@1 {
                                                 reg = <1>;
                                                 label = "lan5";
+                                                phy-handle = <&switch1phy1>;
                                         };
 
                                         port@2 {
                                                 reg = <2>;
                                                 label = "lan6";
+                                                phy-handle = <&switch1phy2>;
                                         };
 
                                         port@3 {
                                                 reg = <3>;
                                                 label = "lan7";
+                                                phy-handle = <&switch1phy3>;
                                         };
 
                                         port@4 {
                                                 reg = <4>;
                                                 label = "lan8";
+                                                phy-handle = <&switch1phy4>;
                                         };
 
 
@@ -163,6 +212,34 @@
                                                 link = <&switch0port10>;
                                         };
                                 };
+                                mdio {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        switch1phy1: switch1phy@1 {
+                                                reg = <1>;
+                                                interrupt-parent = <&switch1>;
+                                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+                                        };
+
+                                        switch1phy2: switch1phy@2 {
+                                                reg = <2>;
+                                                interrupt-parent = <&switch1>;
+                                                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+                                        };
+
+                                        switch1phy3: switch1phy@3 {
+                                                reg = <3>;
+                                                interrupt-parent = <&switch1>;
+                                                interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+                                        };
+
+                                        switch1phy4: switch1phy@4 {
+                                                reg = <4>;
+                                                interrupt-parent = <&switch1>;
+                                                interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+                                        };
+                                };
                         };
                 };
 
diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi
index ca9e1bc35e45..6b58d3a97992 100644
--- a/arch/arm/boot/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi
@@ -296,6 +296,18 @@
                 >;
         };
 
+        pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
+                fsl,pins = <
+                        VF610_PAD_PTB5__GPIO_27         0x219d
+                >;
+        };
+
+        pinctrl_gpio_switch1: pinctrl-gpio-switch1 {
+                fsl,pins = <
+                        VF610_PAD_PTB4__GPIO_26         0x219d
+                >;
+        };
+
         pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
                 fsl,pins = <
                          VF610_PAD_PTE14__GPIO_119      0x31c2
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 098ad557fee3..e2b0da2c0bc7 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -106,6 +106,13 @@
                 };
         };
 
+        irda_regulator: irda-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>;
+                regulator-name = "irda_regulator";
+        };
+
         sound {
                 compatible = "samsung,tm2-audio";
                 audio-codec = <&wm5110>;
@@ -298,6 +305,8 @@
         status = "okay";
         vddcore-supply = <&ldo6_reg>;
         vddio-supply = <&ldo7_reg>;
+        samsung,burst-clock-frequency = <512000000>;
+        samsung,esc-clock-frequency = <16000000>;
         samsung,pll-clock-frequency = <24000000>;
         pinctrl-names = "default";
         pinctrl-0 = <&te_irq>;
@@ -749,6 +758,19 @@
         };
 };
 
+&hsi2c_5 {
+        status = "okay";
+
+        stmfts: touchscreen@49 {
+                compatible = "st,stmfts";
+                reg = <0x49>;
+                interrupt-parent = <&gpa1>;
+                interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+                avdd-supply = <&ldo30_reg>;
+                vdd-supply = <&ldo31_reg>;
+        };
+};
+
 &hsi2c_7 {
         status = "okay";
 
@@ -894,7 +916,7 @@
                 PIN(INPUT, gpa0-7, NONE, FAST_SR1);
 
                 PIN(INPUT, gpa1-0, UP, FAST_SR1);
-                PIN(INPUT, gpa1-1, NONE, FAST_SR1);
+                PIN(INPUT, gpa1-1, UP, FAST_SR1);
                 PIN(INPUT, gpa1-2, NONE, FAST_SR1);
                 PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
                 PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
@@ -1074,7 +1096,6 @@
                 PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
                 PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
                 PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
-                PIN(INPUT, gpg3-7, DOWN, FAST_SR1);
         };
 };
 
@@ -1152,6 +1173,24 @@
         };
 };
 
+&spi_3 {
+        status = "okay";
+        no-cs-readback;
+
+        irled@0 {
+                compatible = "ir-spi-led";
+                reg = <0x0>;
+                spi-max-frequency = <5000000>;
+                power-supply = <&irda_regulator>;
+                duty-cycle = <60>;
+                led-active-low;
+
+                controller-data {
+                        samsung,spi-feedback-delay = <0>;
+                };
+        };
+};
+
 &timer {
         clock-frequency = <24000000>;
 };
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index dea0a6f5bc18..3ff95277a8ec 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -52,6 +52,18 @@
         assigned-clock-rates = <250000000>, <400000000>;
 };
 
+&dsi {
+        panel@0 {
+                compatible = "samsung,s6e3ha2";
+                reg = <0>;
+                vdd3-supply = <&ldo27_reg>;
+                vci-supply = <&ldo28_reg>;
+                reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
+                enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
+                te-gpios = <&gpf1 3 GPIO_ACTIVE_HIGH>;
+        };
+};
+
 &hsi2c_9 {
         status = "okay";
 
@@ -76,3 +88,8 @@
         regulator-min-microvolt = <3000000>;
         regulator-max-microvolt = <3000000>;
 };
+
+&stmfts {
+        touchscreen-size-x = <1439>;
+        touchscreen-size-y = <2559>;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index 7891a31adc17..b73e1231a86f 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -52,6 +52,17 @@
         assigned-clock-rates = <278000000>, <400000000>;
 };
 
+&dsi {
+        panel@0 {
+                compatible = "samsung,s6e3hf2";
+                reg = <0>;
+                vdd3-supply = <&ldo27_reg>;
+                vci-supply = <&ldo28_reg>;
+                reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
+                enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
+        };
+};
+
 &ldo31_reg {
         regulator-name = "TSP_VDD_1.8V_AP";
         regulator-min-microvolt = <1800000>;
@@ -63,3 +74,10 @@
         regulator-min-microvolt = <3300000>;
         regulator-max-microvolt = <3300000>;
 };
+
+&stmfts {
+        touchscreen-size-x = <1599>;
+        touchscreen-size-y = <2559>;
+        touch-key-connected;
+        ledvdd-supply = <&ldo33_reg>;
+};
diff --git a/arch/arm64/boot/dts/include/arm b/arch/arm64/boot/dts/include/arm
new file mode 120000
index 000000000000..cf63d80e2b93
--- /dev/null
+++ b/arch/arm64/boot/dts/include/arm
@@ -0,0 +1 @@
+../../../../arm/boot/dts
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/include/arm64 b/arch/arm64/boot/dts/include/arm64
new file mode 120000
index 000000000000..a96aa0ea9d8c
--- /dev/null
+++ b/arch/arm64/boot/dts/include/arm64
@@ -0,0 +1 @@
+..
\ No newline at end of file
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
index ce09915c298f..bc256d31099a 100644
--- a/include/dt-bindings/clock/r7s72100-clock.h
+++ b/include/dt-bindings/clock/r7s72100-clock.h
@@ -29,6 +29,9 @@
 #define R7S72100_CLK_OSTM0      1
 #define R7S72100_CLK_OSTM1      0
 
+/* MSTP6 */
+#define R7S72100_CLK_RTC        0
+
 /* MSTP7 */
 #define R7S72100_CLK_ETHER      4
 
@@ -49,7 +52,9 @@
 #define R7S72100_CLK_SPI4       3
 
 /* MSTP12 */
-#define R7S72100_CLK_SDHI0      3
-#define R7S72100_CLK_SDHI1      2
+#define R7S72100_CLK_SDHI00     3
+#define R7S72100_CLK_SDHI01     2
+#define R7S72100_CLK_SDHI10     1
+#define R7S72100_CLK_SDHI11     0
 
 #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h
index dd11ecdf837e..4b3668157257 100644
--- a/include/dt-bindings/clock/r8a73a4-clock.h
+++ b/include/dt-bindings/clock/r8a73a4-clock.h
@@ -54,6 +54,7 @@
 #define R8A73A4_CLK_IIC3        11
 #define R8A73A4_CLK_IIC4        10
 #define R8A73A4_CLK_IIC5        9
+#define R8A73A4_CLK_INTC_SYS    8
 #define R8A73A4_CLK_IRQC        7
 
 /* MSTP5 */
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index fa5e8da809f2..20641fa68e73 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -82,6 +82,7 @@
 
 /* MSTP4 */
 #define R8A7790_CLK_IRQC                7
+#define R8A7790_CLK_INTC_SYS            8
 
 /* MSTP5 */
 #define R8A7790_CLK_AUDIO_DMAC1         1
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index ffa11379b3f0..adc50dc31ab3 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -72,6 +72,7 @@
 
 /* MSTP4 */
 #define R8A7791_CLK_IRQC                7
+#define R8A7791_CLK_INTC_SYS            8
 
 /* MSTP5 */
 #define R8A7791_CLK_AUDIO_DMAC1         1
diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h
index 9a8b392ceb00..5be90bc23bd7 100644
--- a/include/dt-bindings/clock/r8a7792-clock.h
+++ b/include/dt-bindings/clock/r8a7792-clock.h
@@ -17,7 +17,6 @@
 #define R8A7792_CLK_PLL3                3
 #define R8A7792_CLK_LB                  4
 #define R8A7792_CLK_QSPI                5
-#define R8A7792_CLK_Z                   6
 
 /* MSTP0 */
 #define R8A7792_CLK_MSIOF0              0
@@ -45,6 +44,7 @@
 
 /* MSTP4 */
 #define R8A7792_CLK_IRQC                7
+#define R8A7792_CLK_INTC_SYS            8
 
 /* MSTP5 */
 #define R8A7792_CLK_AUDIO_DMAC0         2
diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h
index efcbc594fe82..7318d45d4e7e 100644
--- a/include/dt-bindings/clock/r8a7793-clock.h
+++ b/include/dt-bindings/clock/r8a7793-clock.h
@@ -77,10 +77,11 @@
 
 /* MSTP4 */
 #define R8A7793_CLK_IRQC                7
+#define R8A7793_CLK_INTC_SYS            8
 
 /* MSTP5 */
-#define R8A7793_CLK_AUDIO_DMAC1         1
-#define R8A7793_CLK_AUDIO_DMAC0         2
+#define R8A7793_CLK_AUDIO_DMAC1         1
+#define R8A7793_CLK_AUDIO_DMAC0         2
 #define R8A7793_CLK_ADSP_MOD            6
 #define R8A7793_CLK_THERMAL             22
 #define R8A7793_CLK_PWM                 23
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
index 88e64846cf37..93e99c3ffc8d 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -64,6 +64,7 @@
 
 /* MSTP4 */
 #define R8A7794_CLK_IRQC                7
+#define R8A7794_CLK_INTC_SYS            8
 
 /* MSTP5 */
 #define R8A7794_CLK_AUDIO_DMAC0         2
@@ -81,6 +82,7 @@
 #define R8A7794_CLK_SCIF2               19
 #define R8A7794_CLK_SCIF1               20
 #define R8A7794_CLK_SCIF0               21
+#define R8A7794_CLK_DU1                 23
 #define R8A7794_CLK_DU0                 24
 
 /* MSTP8 */
diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
new file mode 100644
index 000000000000..e36cc69959c7
--- /dev/null
+++ b/include/dt-bindings/mfd/stm32f7-rcc.h
@@ -0,0 +1,112 @@
+/*
+ * This header provides constants for the STM32F7 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
+#define _DT_BINDINGS_MFD_STM32F7_RCC_H
+
+/* AHB1 */
+#define STM32F7_RCC_AHB1_GPIOA          0
+#define STM32F7_RCC_AHB1_GPIOB          1
+#define STM32F7_RCC_AHB1_GPIOC          2
+#define STM32F7_RCC_AHB1_GPIOD          3
+#define STM32F7_RCC_AHB1_GPIOE          4
+#define STM32F7_RCC_AHB1_GPIOF          5
+#define STM32F7_RCC_AHB1_GPIOG          6
+#define STM32F7_RCC_AHB1_GPIOH          7
+#define STM32F7_RCC_AHB1_GPIOI          8
+#define STM32F7_RCC_AHB1_GPIOJ          9
+#define STM32F7_RCC_AHB1_GPIOK          10
+#define STM32F7_RCC_AHB1_CRC            12
+#define STM32F7_RCC_AHB1_BKPSRAM        18
+#define STM32F7_RCC_AHB1_DTCMRAM        20
+#define STM32F7_RCC_AHB1_DMA1           21
+#define STM32F7_RCC_AHB1_DMA2           22
+#define STM32F7_RCC_AHB1_DMA2D          23
+#define STM32F7_RCC_AHB1_ETHMAC         25
+#define STM32F7_RCC_AHB1_ETHMACTX       26
+#define STM32F7_RCC_AHB1_ETHMACRX       27
+#define STM32FF_RCC_AHB1_ETHMACPTP      28
+#define STM32F7_RCC_AHB1_OTGHS          29
+#define STM32F7_RCC_AHB1_OTGHSULPI      30
+
+#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
+#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
+
+
+/* AHB2 */
+#define STM32F7_RCC_AHB2_DCMI           0
+#define STM32F7_RCC_AHB2_CRYP           4
+#define STM32F7_RCC_AHB2_HASH           5
+#define STM32F7_RCC_AHB2_RNG            6
+#define STM32F7_RCC_AHB2_OTGFS          7
+
+#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
+#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
+
+/* AHB3 */
+#define STM32F7_RCC_AHB3_FMC            0
+#define STM32F7_RCC_AHB3_QSPI           1
+
+#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8))
+#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40)
+
+/* APB1 */
+#define STM32F7_RCC_APB1_TIM2           0
+#define STM32F7_RCC_APB1_TIM3           1
+#define STM32F7_RCC_APB1_TIM4           2
+#define STM32F7_RCC_APB1_TIM5           3
+#define STM32F7_RCC_APB1_TIM6           4
+#define STM32F7_RCC_APB1_TIM7           5
+#define STM32F7_RCC_APB1_TIM12          6
+#define STM32F7_RCC_APB1_TIM13          7
+#define STM32F7_RCC_APB1_TIM14          8
+#define STM32F7_RCC_APB1_LPTIM1         9
+#define STM32F7_RCC_APB1_WWDG           11
+#define STM32F7_RCC_APB1_SPI2           14
+#define STM32F7_RCC_APB1_SPI3           15
+#define STM32F7_RCC_APB1_SPDIFRX        16
+#define STM32F7_RCC_APB1_UART2          17
+#define STM32F7_RCC_APB1_UART3          18
+#define STM32F7_RCC_APB1_UART4          19
+#define STM32F7_RCC_APB1_UART5          20
+#define STM32F7_RCC_APB1_I2C1           21
+#define STM32F7_RCC_APB1_I2C2           22
+#define STM32F7_RCC_APB1_I2C3           23
+#define STM32F7_RCC_APB1_I2C4           24
+#define STM32F7_RCC_APB1_CAN1           25
+#define STM32F7_RCC_APB1_CAN2           26
+#define STM32F7_RCC_APB1_CEC            27
+#define STM32F7_RCC_APB1_PWR            28
+#define STM32F7_RCC_APB1_DAC            29
+#define STM32F7_RCC_APB1_UART7          30
+#define STM32F7_RCC_APB1_UART8          31
+
+#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8))
+#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80)
+
+/* APB2 */
+#define STM32F7_RCC_APB2_TIM1           0
+#define STM32F7_RCC_APB2_TIM8           1
+#define STM32F7_RCC_APB2_USART1         4
+#define STM32F7_RCC_APB2_USART6         5
+#define STM32F7_RCC_APB2_ADC1           8
+#define STM32F7_RCC_APB2_ADC2           9
+#define STM32F7_RCC_APB2_ADC3           10
+#define STM32F7_RCC_APB2_SDMMC1         11
+#define STM32F7_RCC_APB2_SPI1           12
+#define STM32F7_RCC_APB2_SPI4           13
+#define STM32F7_RCC_APB2_SYSCFG         14
+#define STM32F7_RCC_APB2_TIM9           16
+#define STM32F7_RCC_APB2_TIM10          17
+#define STM32F7_RCC_APB2_TIM11          18
+#define STM32F7_RCC_APB2_SPI5           20
+#define STM32F7_RCC_APB2_SPI6           21
+#define STM32F7_RCC_APB2_SAI1           22
+#define STM32F7_RCC_APB2_SAI2           23
+#define STM32F7_RCC_APB2_LTDC           26
+
+#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
+#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
+
+#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */