fpga: dfl: afu: add afu sub feature support

User Accelerated Function Unit sub feature exposes the MMIO region of
the AFU. After valid PR bitstream is programmed and the port is enabled,
then this MMIO region could be accessed.

This patch adds support to enumerate the AFU MMIO region and expose it
to userspace via mmap file operation. Below interfaces are exposed to user:

Sysfs interface:
* /sys/class/fpga_region/<regionX>/<dfl-port.x>/afu_id
  Read-only. Indicate which PR bitstream is programmed to this AFU.

Ioctl interfaces:
* DFL_FPGA_PORT_GET_INFO
  Provide info to userspace on the number of supported region.
  Only UAFU region is supported now.

* DFL_FPGA_PORT_GET_REGION_INFO
  Provide region information, including access permission, region size,
  offset from the start of device fd.

Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

6 files changed, 508 insertions, 7 deletions

diff --git a/Documentation/ABI/testing/sysfs-platform-dfl-port b/Documentation/ABI/testing/sysfs-platform-dfl-port
index cb91165f5397..6a92dda517b0 100644
--- a/Documentation/ABI/testing/sysfs-platform-dfl-port
+++ b/Documentation/ABI/testing/sysfs-platform-dfl-port
@@ -5,3 +5,12 @@ Contact:	Wu Hao <hao.wu@intel.com>
 Description:    Read-only. It returns id of this port. One DFL FPGA device
                 may have more than one port. Userspace could use this id to
                 distinguish different ports under same FPGA device.
+
+What:           /sys/bus/platform/devices/dfl-port.0/afu_id
+Date:           June 2018
+KernelVersion:  4.19
+Contact:        Wu Hao <hao.wu@intel.com>
+Description:    Read-only. User can program different PR bitstreams to FPGA
+                Accelerator Function Unit (AFU) for different functions. It
+                returns uuid which could be used to identify which PR bitstream
+                is programmed in this AFU.
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 1ac7749b2542..a44d50dd0b70 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -38,7 +38,7 @@ obj-$(CONFIG_FPGA_DFL_FME_REGION)	+= dfl-fme-region.o
 obj-$(CONFIG_FPGA_DFL_AFU)              += dfl-afu.o
 
 dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
-dfl-afu-objs := dfl-afu-main.o
+dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
 
 # Drivers for FPGAs which implement DFL
 obj-$(CONFIG_FPGA_DFL_PCI)              += dfl-pci.o
diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
index 4074b97122e2..f67a78d7e9ad 100644
--- a/drivers/fpga/dfl-afu-main.c
+++ b/drivers/fpga/dfl-afu-main.c
@@ -16,18 +16,18 @@
 
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/uaccess.h>
 #include <linux/fpga-dfl.h>
 
-#include "dfl.h"
+#include "dfl-afu.h"
 
 /**
  * port_enable - enable a port
  * @pdev: port platform device.
  *
  * Enable Port by clear the port soft reset bit, which is set by default.
- * The User AFU is unable to respond to any MMIO access while in reset.
- * port_enable function should only be used after port_disable
- * function.
+ * The AFU is unable to respond to any MMIO access while in reset.
+ * port_enable function should only be used after port_disable function.
  */
 static void port_enable(struct platform_device *pdev)
 {
@@ -191,12 +191,75 @@ static const struct dfl_feature_ops port_hdr_ops = {
         .ioctl = port_hdr_ioctl,
 };
 
+static ssize_t
+afu_id_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+        struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
+        void __iomem *base;
+        u64 guidl, guidh;
+
+        base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_AFU);
+
+        mutex_lock(&pdata->lock);
+        if (pdata->disable_count) {
+                mutex_unlock(&pdata->lock);
+                return -EBUSY;
+        }
+
+        guidl = readq(base + GUID_L);
+        guidh = readq(base + GUID_H);
+        mutex_unlock(&pdata->lock);
+
+        return scnprintf(buf, PAGE_SIZE, "%016llx%016llx\n", guidh, guidl);
+}
+static DEVICE_ATTR_RO(afu_id);
+
+static const struct attribute *port_afu_attrs[] = {
+        &dev_attr_afu_id.attr,
+        NULL
+};
+
+static int port_afu_init(struct platform_device *pdev,
+                         struct dfl_feature *feature)
+{
+        struct resource *res = &pdev->resource[feature->resource_index];
+        int ret;
+
+        dev_dbg(&pdev->dev, "PORT AFU Init.\n");
+
+        ret = afu_mmio_region_add(dev_get_platdata(&pdev->dev),
+                                  DFL_PORT_REGION_INDEX_AFU, resource_size(res),
+                                  res->start, DFL_PORT_REGION_READ |
+                                  DFL_PORT_REGION_WRITE | DFL_PORT_REGION_MMAP);
+        if (ret)
+                return ret;
+
+        return sysfs_create_files(&pdev->dev.kobj, port_afu_attrs);
+}
+
+static void port_afu_uinit(struct platform_device *pdev,
+                           struct dfl_feature *feature)
+{
+        dev_dbg(&pdev->dev, "PORT AFU UInit.\n");
+
+        sysfs_remove_files(&pdev->dev.kobj, port_afu_attrs);
+}
+
+static const struct dfl_feature_ops port_afu_ops = {
+        .init = port_afu_init,
+        .uinit = port_afu_uinit,
+};
+
 static struct dfl_feature_driver port_feature_drvs[] = {
         {
                 .id = PORT_FEATURE_ID_HEADER,
                 .ops = &port_hdr_ops,
         },
         {
+                .id = PORT_FEATURE_ID_AFU,
+                .ops = &port_afu_ops,
+        },
+        {
                 .ops = NULL,
         }
 };
@@ -243,6 +306,64 @@ static long afu_ioctl_check_extension(struct dfl_feature_platform_data *pdata,
         return 0;
 }
 
+static long
+afu_ioctl_get_info(struct dfl_feature_platform_data *pdata, void __user *arg)
+{
+        struct dfl_fpga_port_info info;
+        struct dfl_afu *afu;
+        unsigned long minsz;
+
+        minsz = offsetofend(struct dfl_fpga_port_info, num_umsgs);
+
+        if (copy_from_user(&info, arg, minsz))
+                return -EFAULT;
+
+        if (info.argsz < minsz)
+                return -EINVAL;
+
+        mutex_lock(&pdata->lock);
+        afu = dfl_fpga_pdata_get_private(pdata);
+        info.flags = 0;
+        info.num_regions = afu->num_regions;
+        info.num_umsgs = afu->num_umsgs;
+        mutex_unlock(&pdata->lock);
+
+        if (copy_to_user(arg, &info, sizeof(info)))
+                return -EFAULT;
+
+        return 0;
+}
+
+static long afu_ioctl_get_region_info(struct dfl_feature_platform_data *pdata,
+                                      void __user *arg)
+{
+        struct dfl_fpga_port_region_info rinfo;
+        struct dfl_afu_mmio_region region;
+        unsigned long minsz;
+        long ret;
+
+        minsz = offsetofend(struct dfl_fpga_port_region_info, offset);
+
+        if (copy_from_user(&rinfo, arg, minsz))
+                return -EFAULT;
+
+        if (rinfo.argsz < minsz || rinfo.padding)
+                return -EINVAL;
+
+        ret = afu_mmio_region_get_by_index(pdata, rinfo.index, &region);
+        if (ret)
+                return ret;
+
+        rinfo.flags = region.flags;
+        rinfo.size = region.size;
+        rinfo.offset = region.offset;
+
+        if (copy_to_user(arg, &rinfo, sizeof(rinfo)))