aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJoonas Kylmälä <joonas.kylmala@iki.fi>2018-02-08 07:01:41 -0500
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-02-15 03:27:38 -0500
commit8566df712b5bb7b35d292f3b6b9216f511607e1f (patch)
treed59d33080dffe03e5462f59e3689085e582080e6
parente607b605be46a44f50e3b48597188477e52eeff8 (diff)
ARM: dts: sunxi: h3-h5: rename mmc0_pins_a and mmc1_pins_a
There is only one pinctrl configuration for mmc0 and mmc1 so let's drop the _a suffix from both of them. Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
-rw-r--r--arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts2
-rw-r--r--arch/arm/boot/dts/sunxi-h3-h5.dtsi8
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index 73978853bb4c..f868cf197c8e 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -134,7 +134,7 @@
134 }; 134 };
135}; 135};
136 136
137&mmc1_pins_a { 137&mmc1_pins {
138 bias-pull-up; 138 bias-pull-up;
139}; 139};
140 140
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index b4a4b3cb6c4e..7741166d34d8 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -142,7 +142,7 @@
142 /* compatible and clocks are in per SoC .dtsi file */ 142 /* compatible and clocks are in per SoC .dtsi file */
143 reg = <0x01c0f000 0x1000>; 143 reg = <0x01c0f000 0x1000>;
144 pinctrl-names = "default"; 144 pinctrl-names = "default";
145 pinctrl-0 = <&mmc0_pins_a>; 145 pinctrl-0 = <&mmc0_pins>;
146 resets = <&ccu RST_BUS_MMC0>; 146 resets = <&ccu RST_BUS_MMC0>;
147 reset-names = "ahb"; 147 reset-names = "ahb";
148 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 148 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -155,7 +155,7 @@
155 /* compatible and clocks are in per SoC .dtsi file */ 155 /* compatible and clocks are in per SoC .dtsi file */
156 reg = <0x01c10000 0x1000>; 156 reg = <0x01c10000 0x1000>;
157 pinctrl-names = "default"; 157 pinctrl-names = "default";
158 pinctrl-0 = <&mmc1_pins_a>; 158 pinctrl-0 = <&mmc1_pins>;
159 resets = <&ccu RST_BUS_MMC1>; 159 resets = <&ccu RST_BUS_MMC1>;
160 reset-names = "ahb"; 160 reset-names = "ahb";
161 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 161 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -352,7 +352,7 @@
352 function = "i2c2"; 352 function = "i2c2";
353 }; 353 };
354 354
355 mmc0_pins_a: mmc0 { 355 mmc0_pins: mmc0 {
356 pins = "PF0", "PF1", "PF2", "PF3", 356 pins = "PF0", "PF1", "PF2", "PF3",
357 "PF4", "PF5"; 357 "PF4", "PF5";
358 function = "mmc0"; 358 function = "mmc0";
@@ -360,7 +360,7 @@
360 bias-pull-up; 360 bias-pull-up;
361 }; 361 };
362 362
363 mmc1_pins_a: mmc1 { 363 mmc1_pins: mmc1 {
364 pins = "PG0", "PG1", "PG2", "PG3", 364 pins = "PG0", "PG1", "PG2", "PG3",
365 "PG4", "PG5"; 365 "PG4", "PG5";
366 function = "mmc1"; 366 function = "mmc1";