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authorThierry Reding <treding@nvidia.com>2017-06-26 11:38:43 -0400
committerThierry Reding <treding@nvidia.com>2017-12-13 07:15:43 -0500
commit85593b75ee715490f0207d95de4978fc465fda89 (patch)
treee8c520fa7ecb30699f37a7f5bbd66805de76cc78
parent94e25dc3a2b55eb9732f6da41bd25b9dccd60b5a (diff)
arm64: tegra: Add FUSE block on Tegra186
The FUSE register block found on Tegra186 SoCs encodes various settings, such as calibration data for other blocks. Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186.dtsi7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 11795dbd30f0..c9f4a6dc162c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -265,6 +265,13 @@
265 status = "disabled"; 265 status = "disabled";
266 }; 266 };
267 267
268 fuse@3820000 {
269 compatible = "nvidia,tegra186-efuse";
270 reg = <0x0 0x03820000 0x0 0x10000>;
271 clocks = <&bpmp TEGRA186_CLK_FUSE>;
272 clock-names = "fuse";
273 };
274
268 gic: interrupt-controller@3881000 { 275 gic: interrupt-controller@3881000 {
269 compatible = "arm,gic-400"; 276 compatible = "arm,gic-400";
270 #interrupt-cells = <3>; 277 #interrupt-cells = <3>;