Merge branch 'amd-xgbe-updates'

Tom Lendacky says:

====================
amd-xgbe: AMD XGBE driver updates 2016-11-10

This patch series is targeted at adding support for a new PCI version
of the hardware. As part of the new PCI device, there is a new PCS/PHY
interaction, ECC support, I2C sideband communication, SFP+ support and
more.

The following updates and fixes are included in this driver update series:

- Hardware workaround for possible incorrectly generated interrupts
  during software reset
- Hardware workaround for Tx timestamp register access order
- Add support for a PCI version of the device
- Increase the Rx queue limit to take advantage of the increased number
  of DMA channels that might be available
- Add support for a new DMA channel interrupt mode
- Add ECC support for the device memory
- Add support for using the integrated I2C controller for sideband
  communication
- Expose the phylib phy_aneg_done() function so it can be called by the
  driver
- Add support for SFP+ modules
- Add support for MDIO attached PHYs
- Add support for KR re-driver between the PCS/SerDes and an external
  PHY

This patch series is based on net-next.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

17 files changed, 5487 insertions, 90 deletions

diff --git a/drivers/net/ethernet/aeroflex/greth.c b/drivers/net/ethernet/aeroflex/greth.c
index f8df8248035e..93def92f9997 100644
--- a/drivers/net/ethernet/aeroflex/greth.c
+++ b/drivers/net/ethernet/aeroflex/greth.c
@@ -1290,15 +1290,6 @@ static int greth_mdio_probe(struct net_device *dev)
         return 0;
 }
 
-static inline int phy_aneg_done(struct phy_device *phydev)
-{
-        int retval;
-
-        retval = phy_read(phydev, MII_BMSR);
-
-        return (retval < 0) ? retval : (retval & BMSR_ANEGCOMPLETE);
-}
-
 static int greth_mdio_init(struct greth_private *greth)
 {
         int ret;
diff --git a/drivers/net/ethernet/amd/Kconfig b/drivers/net/ethernet/amd/Kconfig
index 0038709fd317..7ab6efbe4189 100644
--- a/drivers/net/ethernet/amd/Kconfig
+++ b/drivers/net/ethernet/amd/Kconfig
@@ -173,11 +173,13 @@ config SUNLANCE
 
 config AMD_XGBE
         tristate "AMD 10GbE Ethernet driver"
-        depends on ((OF_NET && OF_ADDRESS) || ACPI) && HAS_IOMEM && HAS_DMA
-        depends on ARM64 || COMPILE_TEST
+        depends on ((OF_NET && OF_ADDRESS) || ACPI || PCI) && HAS_IOMEM && HAS_DMA
+        depends on X86 || ARM64 || COMPILE_TEST
         select BITREVERSE
         select CRC32
         select PTP_1588_CLOCK
+        select PHYLIB
+        select AMD_XGBE_HAVE_ECC if X86
         ---help---
           This driver supports the AMD 10GbE Ethernet device found on an
           AMD SoC.
@@ -195,4 +197,8 @@ config AMD_XGBE_DCB
 
           If unsure, say N.
 
+config AMD_XGBE_HAVE_ECC
+        bool
+        default n
+
 endif # NET_VENDOR_AMD
diff --git a/drivers/net/ethernet/amd/xgbe/Makefile b/drivers/net/ethernet/amd/xgbe/Makefile
index 217d59ea1c52..0dea8f5da899 100644
--- a/drivers/net/ethernet/amd/xgbe/Makefile
+++ b/drivers/net/ethernet/amd/xgbe/Makefile
@@ -3,8 +3,9 @@ obj-$(CONFIG_AMD_XGBE) += amd-xgbe.o
 amd-xgbe-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \
                  xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \
                  xgbe-ptp.o \
-                 xgbe-phy-v1.o \
+                 xgbe-i2c.o xgbe-phy-v1.o xgbe-phy-v2.o \
                  xgbe-platform.o
 
+amd-xgbe-$(CONFIG_PCI) += xgbe-pci.o
 amd-xgbe-$(CONFIG_AMD_XGBE_DCB) += xgbe-dcb.o
 amd-xgbe-$(CONFIG_DEBUG_FS) += xgbe-debugfs.o
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
index 8036ee52add6..5b7ba25e0065 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
@@ -159,6 +159,8 @@
 #define DMA_ISR_MACIS_WIDTH             1
 #define DMA_ISR_MTLIS_INDEX             16
 #define DMA_ISR_MTLIS_WIDTH             1
+#define DMA_MR_INTM_INDEX               12
+#define DMA_MR_INTM_WIDTH               2
 #define DMA_MR_SWR_INDEX                0
 #define DMA_MR_SWR_WIDTH                1
 #define DMA_SBMR_EAME_INDEX             11
@@ -309,6 +311,11 @@
 #define MAC_HWF0R                       0x011c
 #define MAC_HWF1R                       0x0120
 #define MAC_HWF2R                       0x0124
+#define MAC_MDIOSCAR                    0x0200
+#define MAC_MDIOSCCDR                   0x0204
+#define MAC_MDIOISR                     0x0214
+#define MAC_MDIOIER                     0x0218
+#define MAC_MDIOCL22R                   0x0220
 #define MAC_GPIOCR                      0x0278
 #define MAC_GPIOSR                      0x027c
 #define MAC_MACA0HR                     0x0300
@@ -409,10 +416,34 @@
 #define MAC_ISR_MMCTXIS_WIDTH           1
 #define MAC_ISR_PMTIS_INDEX             4
 #define MAC_ISR_PMTIS_WIDTH             1
+#define MAC_ISR_SMI_INDEX               1
+#define MAC_ISR_SMI_WIDTH               1
 #define MAC_ISR_TSIS_INDEX              12
 #define MAC_ISR_TSIS_WIDTH              1
 #define MAC_MACA1HR_AE_INDEX            31
 #define MAC_MACA1HR_AE_WIDTH            1
+#define MAC_MDIOIER_SNGLCOMPIE_INDEX    12
+#define MAC_MDIOIER_SNGLCOMPIE_WIDTH    1
+#define MAC_MDIOISR_SNGLCOMPINT_INDEX   12
+#define MAC_MDIOISR_SNGLCOMPINT_WIDTH   1
+#define MAC_MDIOSCAR_DA_INDEX           21
+#define MAC_MDIOSCAR_DA_WIDTH           5
+#define MAC_MDIOSCAR_PA_INDEX           16
+#define MAC_MDIOSCAR_PA_WIDTH           5
+#define MAC_MDIOSCAR_RA_INDEX           0
+#define MAC_MDIOSCAR_RA_WIDTH           16
+#define MAC_MDIOSCAR_REG_INDEX          0
+#define MAC_MDIOSCAR_REG_WIDTH          21
+#define MAC_MDIOSCCDR_BUSY_INDEX        22
+#define MAC_MDIOSCCDR_BUSY_WIDTH        1
+#define MAC_MDIOSCCDR_CMD_INDEX         16
+#define MAC_MDIOSCCDR_CMD_WIDTH         2
+#define MAC_MDIOSCCDR_CR_INDEX          19
+#define MAC_MDIOSCCDR_CR_WIDTH          3
+#define MAC_MDIOSCCDR_DATA_INDEX        0
+#define MAC_MDIOSCCDR_DATA_WIDTH        16
+#define MAC_MDIOSCCDR_SADDR_INDEX       18
+#define MAC_MDIOSCCDR_SADDR_WIDTH       1
 #define MAC_PFR_HMC_INDEX               2
 #define MAC_PFR_HMC_WIDTH               1
 #define MAC_PFR_HPF_INDEX               10
@@ -858,8 +889,15 @@
 
 /* PCS register offsets */
 #define PCS_V1_WINDOW_SELECT            0x03fc
+#define PCS_V2_WINDOW_DEF               0x9060
 #define PCS_V2_WINDOW_SELECT            0x9064
 
+/* PCS register entry bit positions and sizes */
+#define PCS_V2_WINDOW_DEF_OFFSET_INDEX  6
+#define PCS_V2_WINDOW_DEF_OFFSET_WIDTH  14
+#define PCS_V2_WINDOW_DEF_SIZE_INDEX    2
+#define PCS_V2_WINDOW_DEF_SIZE_WIDTH    4
+
 /* SerDes integration register offsets */
 #define SIR0_KR_RT_1                    0x002c
 #define SIR0_STATUS                     0x0040
@@ -902,6 +940,198 @@
 #define RXTX_REG129_RXDFE_CONFIG_INDEX  14
 #define RXTX_REG129_RXDFE_CONFIG_WIDTH  2
 
+/* MAC Control register offsets */
+#define XP_PROP_0                       0x0000
+#define XP_PROP_1                       0x0004
+#define XP_PROP_2                       0x0008
+#define XP_PROP_3                       0x000c
+#define XP_PROP_4                       0x0010
+#define XP_PROP_5                       0x0014
+#define XP_MAC_ADDR_LO                  0x0020
+#define XP_MAC_ADDR_HI                  0x0024
+#define XP_ECC_ISR                      0x0030
+#define XP_ECC_IER                      0x0034
+#define XP_ECC_CNT0                     0x003c
+#define XP_ECC_CNT1                     0x0040
+#define XP_DRIVER_INT_REQ               0x0060
+#define XP_DRIVER_INT_RO                0x0064
+#define XP_DRIVER_SCRATCH_0             0x0068
+#define XP_DRIVER_SCRATCH_1             0x006c
+#define XP_INT_EN                       0x0078
+#define XP_I2C_MUTEX                    0x0080
+#define XP_MDIO_MUTEX                   0x0084
+
+/* MAC Control register entry bit positions and sizes */
+#define XP_DRIVER_INT_REQ_REQUEST_INDEX         0
+#define XP_DRIVER_INT_REQ_REQUEST_WIDTH         1
+#define XP_DRIVER_INT_RO_STATUS_INDEX           0
+#define XP_DRIVER_INT_RO_STATUS_WIDTH           1
+#define XP_DRIVER_SCRATCH_0_COMMAND_INDEX       0
+#define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH       8
+#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX   8
+#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH   8
+#define XP_ECC_CNT0_RX_DED_INDEX                24
+#define XP_ECC_CNT0_RX_DED_WIDTH                8
+#define XP_ECC_CNT0_RX_SEC_INDEX                16
+#define XP_ECC_CNT0_RX_SEC_WIDTH                8
+#define XP_ECC_CNT0_TX_DED_INDEX                8
+#define XP_ECC_CNT0_TX_DED_WIDTH                8
+#define XP_ECC_CNT0_TX_SEC_INDEX                0
+#define XP_ECC_CNT0_TX_SEC_WIDTH                8
+#define XP_ECC_CNT1_DESC_DED_INDEX              8
+#define XP_ECC_CNT1_DESC_DED_WIDTH              8
+#define XP_ECC_CNT1_DESC_SEC_INDEX              0
+#define XP_ECC_CNT1_DESC_SEC_WIDTH              8
+#define XP_ECC_IER_DESC_DED_INDEX               0
+#define XP_ECC_IER_DESC_DED_WIDTH               1
+#define XP_ECC_IER_DESC_SEC_INDEX               1
+#define XP_ECC_IER_DESC_SEC_WIDTH               1
+#define XP_ECC_IER_RX_DED_INDEX                 2
+#define XP_ECC_IER_RX_DED_WIDTH                 1
+#define XP_ECC_IER_RX_SEC_INDEX                 3
+#define XP_ECC_IER_RX_SEC_WIDTH                 1
+#define XP_ECC_IER_TX_DED_INDEX                 4
+#define XP_ECC_IER_TX_DED_WIDTH                 1
+#define XP_ECC_IER_TX_SEC_INDEX                 5
+#define XP_ECC_IER_TX_SEC_WIDTH                 1
+#define XP_ECC_ISR_DESC_DED_INDEX               0
+#define XP_ECC_ISR_DESC_DED_WIDTH               1
+#define XP_ECC_ISR_DESC_SEC_INDEX               1
+#define XP_ECC_ISR_DESC_SEC_WIDTH               1
+#define XP_ECC_ISR_RX_DED_INDEX                 2
+#define XP_ECC_ISR_RX_DED_WIDTH                 1
+#define XP_ECC_ISR_RX_SEC_INDEX                 3
+#define XP_ECC_ISR_RX_SEC_WIDTH                 1
+#define XP_ECC_ISR_TX_DED_INDEX                 4
+#define XP_ECC_ISR_TX_DED_WIDTH                 1
+#define XP_ECC_ISR_TX_SEC_INDEX                 5
+#define XP_ECC_ISR_TX_SEC_WIDTH                 1
+#define XP_I2C_MUTEX_BUSY_INDEX                 31
+#define XP_I2C_MUTEX_BUSY_WIDTH                 1
+#define XP_I2C_MUTEX_ID_INDEX                   29
+#define XP_I2C_MUTEX_ID_WIDTH                   2
+#define XP_I2C_MUTEX_ACTIVE_INDEX               0
+#define XP_I2C_MUTEX_ACTIVE_WIDTH               1
+#define XP_MAC_ADDR_HI_VALID_INDEX              31
+#define XP_MAC_ADDR_HI_VALID_WIDTH              1
+#define XP_PROP_0_CONN_TYPE_INDEX               28
+#define XP_PROP_0_CONN_TYPE_WIDTH               3
+#define XP_PROP_0_MDIO_ADDR_INDEX               16
+#define XP_PROP_0_MDIO_ADDR_WIDTH               5
+#define XP_PROP_0_PORT_ID_INDEX                 0
+#define XP_PROP_0_PORT_ID_WIDTH                 8
+#define XP_PROP_0_PORT_MODE_INDEX               8
+#define XP_PROP_0_PORT_MODE_WIDTH               4
+#define XP_PROP_0_PORT_SPEEDS_INDEX             23
+#define XP_PROP_0_PORT_SPEEDS_WIDTH             4
+#define XP_PROP_1_MAX_RX_DMA_INDEX              24
+#define XP_PROP_1_MAX_RX_DMA_WIDTH              5
+#define XP_PROP_1_MAX_RX_QUEUES_INDEX           8
+#define XP_PROP_1_MAX_RX_QUEUES_WIDTH           5
+#define XP_PROP_1_MAX_TX_DMA_INDEX              16
+#define XP_PROP_1_MAX_TX_DMA_WIDTH              5
+#define XP_PROP_1_MAX_TX_QUEUES_INDEX           0
+#define XP_PROP_1_MAX_TX_QUEUES_WIDTH           5
+#define XP_PROP_2_RX_FIFO_SIZE_INDEX            16
+#define XP_PROP_2_RX_FIFO_SIZE_WIDTH            16
+#define XP_PROP_2_TX_FIFO_SIZE_INDEX            0
+#define XP_PROP_2_TX_FIFO_SIZE_WIDTH            16
+#define XP_PROP_3_GPIO_MASK_INDEX               28
+#define XP_PROP_3_GPIO_MASK_WIDTH               4
+#define XP_PROP_3_GPIO_MOD_ABS_INDEX            20
+#define XP_PROP_3_GPIO_MOD_ABS_WIDTH            4
+#define XP_PROP_3_GPIO_RATE_SELECT_INDEX        16
+#define XP_PROP_3_GPIO_RATE_SELECT_WIDTH        4
+#define XP_PROP_3_GPIO_RX_LOS_INDEX             24
+#define XP_PROP_3_GPIO_RX_LOS_WIDTH             4
+#define XP_PROP_3_GPIO_TX_FAULT_INDEX           12
+#define XP_PROP_3_GPIO_TX_FAULT_WIDTH           4
+#define XP_PROP_3_GPIO_ADDR_INDEX               8
+#define XP_PROP_3_GPIO_ADDR_WIDTH               3
+#define XP_PROP_3_MDIO_RESET_INDEX              0
+#define XP_PROP_3_MDIO_RESET_WIDTH              2
+#define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX     8
+#define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH     3
+#define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX     12
+#define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH     4
+#define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX     4
+#define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH     2
+#define XP_PROP_4_MUX_ADDR_HI_INDEX             8
+#define XP_PROP_4_MUX_ADDR_HI_WIDTH             5
+#define XP_PROP_4_MUX_ADDR_LO_INDEX             0
+#define XP_PROP_4_MUX_ADDR_LO_WIDTH             3
+#define XP_PROP_4_MUX_CHAN_INDEX                4
+#define XP_PROP_4_MUX_CHAN_WIDTH                3
+#define XP_PROP_4_REDRV_ADDR_INDEX              16
+#define XP_PROP_4_REDRV_ADDR_WIDTH              7
+#define XP_PROP_4_REDRV_IF_INDEX                23
+#define XP_PROP_4_REDRV_IF_WIDTH                1
+#define XP_PROP_4_REDRV_LANE_INDEX              24
+#define XP_PROP_4_REDRV_LANE_WIDTH              3
+#define XP_PROP_4_REDRV_MODEL_INDEX             28
+#define XP_PROP_4_REDRV_MODEL_WIDTH             3
+#define XP_PROP_4_REDRV_PRESENT_INDEX           31
+#define XP_PROP_4_REDRV_PRESENT_WIDTH           1
+
+/* I2C Control register offsets */
+#define IC_CON                                  0x0000
+#define IC_TAR                                  0x0004
+#define IC_DATA_CMD                             0x0010
+#define IC_INTR_STAT                            0x002c
+#define IC_INTR_MASK                            0x0030
+#define IC_RAW_INTR_STAT                        0x0034
+#define IC_CLR_INTR                             0x0040
+#define IC_CLR_TX_ABRT                          0x0054
+#define IC_CLR_STOP_DET                         0x0060
+#define IC_ENABLE                               0x006c
+#define IC_TXFLR                                0x0074
+#define IC_RXFLR                                0x0078
+#define IC_TX_ABRT_SOURCE                       0x0080
+#define IC_ENABLE_STATUS                        0x009c
+#define IC_COMP_PARAM_1                         0x00f4
+
+/* I2C Control register entry bit positions and sizes */
+#define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX    2
+#define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH    2
+#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX   8
+#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH   8
+#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX   16
+#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH   8
+#define IC_CON_MASTER_MODE_INDEX                0
+#define IC_CON_MASTER_MODE_WIDTH                1
+#define IC_CON_RESTART_EN_INDEX                 5
+#define IC_CON_RESTART_EN_WIDTH                 1
+#define IC_CON_RX_FIFO_FULL_HOLD_INDEX          9
+#define IC_CON_RX_FIFO_FULL_HOLD_WIDTH          1
+#define IC_CON_SLAVE_DISABLE_INDEX              6
+#define IC_CON_SLAVE_DISABLE_WIDTH              1
+#define IC_CON_SPEED_INDEX                      1
+#define IC_CON_SPEED_WIDTH                      2
+#define IC_DATA_CMD_CMD_INDEX                   8
+#define IC_DATA_CMD_CMD_WIDTH                   1
+#define IC_DATA_CMD_STOP_INDEX                  9
+#define IC_DATA_CMD_STOP_WIDTH                  1
+#define IC_ENABLE_ABORT_INDEX                   1
+#define IC_ENABLE_ABORT_WIDTH                   1
+#define IC_ENABLE_EN_INDEX                      0
+#define IC_ENABLE_EN_WIDTH                      1
+#define IC_ENABLE_STATUS_EN_INDEX               0
+#define IC_ENABLE_STATUS_EN_WIDTH               1
+#define IC_INTR_MASK_TX_EMPTY_INDEX             4
+#define IC_INTR_MASK_TX_EMPTY_WIDTH             1
+#define IC_RAW_INTR_STAT_RX_FULL_INDEX          2
+#define IC_RAW_INTR_STAT_RX_FULL_WIDTH          1
+#define IC_RAW_INTR_STAT_STOP_DET_INDEX         9
+#define IC_RAW_INTR_STAT_STOP_DET_WIDTH         1
+#define IC_RAW_INTR_STAT_TX_ABRT_INDEX          6
+#define IC_RAW_INTR_STAT_TX_ABRT_WIDTH          1
+#define IC_RAW_INTR_STAT_TX_EMPTY_INDEX         4
+#define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH         1
+
+/* I2C Control register value */
+#define IC_TX_ABRT_7B_ADDR_NOACK                0x0001
+#define IC_TX_ABRT_ARB_LOST                     0x1000
+
 /* Descriptor/Packet entry bit positions and sizes */
 #define RX_PACKET_ERRORS_CRC_INDEX              2
 #define RX_PACKET_ERRORS_CRC_WIDTH              1
@@ -1078,6 +1308,14 @@
 #define MDIO_VEND2_CTRL1_AN_RESTART     BIT(9)
 #endif
 
+#ifndef MDIO_VEND2_CTRL1_SS6
+#define MDIO_VEND2_CTRL1_SS6            BIT(6)
+#endif
+
+#ifndef MDIO_VEND2_CTRL1_SS13
+#define MDIO_VEND2_CTRL1_SS13           BIT(13)
+#endif
+
 /* MDIO mask values */
 #define XGBE_AN_CL73_INT_CMPLT          BIT(0)
 #define XGBE_AN_CL73_INC_LINK           BIT(1)
@@ -1240,6 +1478,16 @@ do {									\
 /* Macros for building, reading or writing register values or bits
  * within the register values of XPCS registers.
  */
+#define XPCS_GET_BITS(_var, _prefix, _field)                            \
+        GET_BITS((_var),                                                \
+                 _prefix##_##_field##_INDEX,                            \
+                 _prefix##_##_field##_WIDTH)
+
+#define XPCS_SET_BITS(_var, _prefix, _field, _val)                      \
+        SET_BITS((_var),                                                \
+                 _prefix##_##_field##_INDEX,                            \
+                 _prefix##_##_field##_WIDTH, (_val))
+
 #define XPCS32_IOWRITE(_pdata, _off, _val)                              \
         iowrite32(_val, (_pdata)->xpcs_regs + (_off))
 
@@ -1329,6 +1577,72 @@ do {									\
 } while (0)
 
 /* Macros for building, reading or writing register values or bits
+ * within the register values of MAC Control registers.
+ */
+#define XP_GET_BITS(_var, _prefix, _field)                              \
+        GET_BITS((_var),                                                \
+                 _prefix##_##_field##_INDEX,                            \
+                 _prefix##_##_field##_WIDTH)
+
+#define XP_SET_BITS(_var, _prefix, _field, _val)                        \
+        SET_BITS((_var),                                                \
+                 _prefix##_##_field##_INDEX,                            \
+                 _prefix##_##_field##_WIDTH, (_val))
+
+#define XP_IOREAD(_pdata, _reg)                                         \
+        ioread32((_pdata)->xprop_regs + (_reg))
+
+#define XP_IOREAD_BITS(_pdata, _reg, _field)                            \
+        GET_BITS(XP_IOREAD((_pdata), (_reg)),                           \
+                 _reg##_##_field##_INDEX,                               \
+                 _reg##_##_field##_WIDTH)
+
+#define XP_IOWRITE(_pdata, _reg, _val)                                  \
+        iowrite32((_val), (_pdata)->xprop_regs + (_reg))
+
+#define XP_IOWRITE_BITS(_pdata, _reg, _field, _val)                     \
+do {                                                                    \
+        u32 reg_val = XP_IOREAD((_pdata), (_reg));                      \
+        SET_BITS(reg_val,                                               \
+                 _reg##_##_field##_INDEX,                               \
+                 _reg##_##_field##_WIDTH, (_val));                      \
+        XP_IOWRITE((_pdata), (_reg), reg_val);                          \
+} while (0)
+
+/* Macros for building, reading or writing register values or bits
+ * within the register values of I2C Control registers.
+ */
+#define XI2C_GET_BITS(_var, _prefix, _field)                            \
+        GET_BITS((_var),                                                \
+                 _prefix##_##_field##_INDEX,                            \
+                 _prefix##_##_field##_WIDTH)
+
+#define XI2C_SET_BITS(_var, _prefix, _field, _val)                      \
+        SET_BITS((_var),                                                \
+                 _prefix##_##_field##_INDEX,                            \
+                 _prefix##_##_field##_WIDTH, (_val))
+
+#define XI2C_IOREAD(_pdata, _reg)                                       \
+        ioread32((_pdata)->xi2c_regs + (_reg))
+
+#define XI2C_IOREAD_BITS(_pdata, _reg, _field)                          \
+        GET_BITS(XI2C_IOREAD((_pdata), (_reg)),                         \
+                 _reg##_##_field##_INDEX,                               \
+                 _reg##_##_field##_WIDTH)
+
+#define XI2C_IOWRITE(_pdata, _reg, _val)                                \
+        iowrite32((_val), (_pdata)->xi2c_regs + (_reg))
+
+#define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val)                   \
+do {                                                                    \
+        u32 reg_val = XI2C_IOREAD((_pdata), (_reg));                    \
+        SET_BITS(reg_val,                                               \
+                 _reg##_##_field##_INDEX,                               \
+                 _reg##_##_field##_WIDTH, (_val));                      \
+        XI2C_IOWRITE((_pdata), (_reg), reg_val);                        \
+} while (0)
+
+/* Macros for building, reading or writing register values or bits
  * using MDIO.  Different from above because of the use of standardized
  * Linux include values.  No shifting is performed with the bit
  * operations, everything works on mask values.
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c b/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c
index 96f485ab612e..0c0140decbc2 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c
@@ -316,6 +316,126 @@ static const struct file_operations xpcs_reg_value_fops = {
         .write = xpcs_reg_value_write,
 };
 
+static ssize_t xprop_reg_addr_read(struct file *filp, char __user *buffer,
+                                   size_t count, loff_t *ppos)
+{
+        struct xgbe_prv_data *pdata = filp->private_data;
+
+        return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xprop_reg);
+}
+
+static ssize_t xprop_reg_addr_write(struct file *filp,
+                                    const char __user *buffer,
+                                    size_t count, loff_t *ppos)
+{
+        struct xgbe_prv_data *pdata = filp->private_data;
+
+        return xgbe_common_write(buffer, count, ppos,
+                                 &pdata->debugfs_xprop_reg);
+}
+
+static ssize_t xprop_reg_value_read(struct file *filp, char __user *buffer,
+                                    size_t count, loff_t *ppos)
+{
+        struct xgbe_prv_data *pdata = filp->private_data;
+        unsigned int value;
+
+        value = XP_IOREAD(pdata, pdata->debugfs_xprop_reg);
+
+        return xgbe_common_read(buffer, count, ppos, value);
+}
+
+static ssize_t xprop_reg_value_write(struct file *filp,
+                                     const char __user *buffer,
+                                     size_t count, loff_t *ppos)
+{
+        struct xgbe_prv_data *pdata = filp->private_data;
+        unsigned int value;
+        ssize_t len;
+
+        len = xgbe_common_write(buffer, count, ppos, &value);
+        if (len < 0)
+                return len;
+
+        XP_IOWRITE(pdata, pdata->debugfs_xprop_reg, value);
+
+        return len;
+}
+
+static const struct file_operations xprop_reg_addr_fops = {
+        .owner = THIS_MODULE,
+        .open = simple_open,
+        .read =  xprop_reg_addr_read,
+        .write = xprop_reg_addr_write,
+};
+
+static const struct file_operations xprop_reg_value_fops = {
+        .owner = THIS_MODULE,
+        .open = simple_open,
+        .read =  xprop_reg_value_read,
+        .write = xprop_reg_value_write,
+};
+
+static ssize_t xi2c_reg_addr_read(struct file *filp, char __user *buffer,
+                                  size_t count, loff_t *ppos)
+{
+        struct xgbe_prv_data *pdata = filp->private_data;
+
+        return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xi2c_reg);
+}
+
+static ssize_t xi2c_reg_addr_write(struct file *filp,
+                                   const char __user *buffer,
+                                   size_t count, loff_t *ppos)
+{
+        struct xgbe_prv_data *pdata = filp->private_data;
+
+        return xgbe_common_write(buffer, count, ppos,
+                                 &pdata->debugfs_xi2c_reg);
+}
+
+static ssize_t xi2c_reg_value_read(struct file *filp, char __user *buffer,
+                                   size_t count, loff_t *ppos)
+{
+        struct xgbe_prv_data *pdata = filp->private_data;
+        unsigned int value;
+
+        value = XI2C_IOREAD(pdata, pdata->debugfs_xi2c_reg);
+
+        return xgbe_common_read(buffer, count, ppos, value);
+}
+
+static ssize_t xi2c_reg_value_write(struct file *filp,
+                                    const char __user *buffer,
+                                    size_t count, loff_t *ppos)
+{
+        struct xgbe_prv_data *pdata = filp->private_data;
+        unsigned int value;
+        ssize_t len;
+
+        len = xgbe_common_write(buffer, count, ppos, &value);
+        if (len < 0)
+                return len;
+
+        XI2C_IOWRITE(pdata, pdata->debugfs_xi2c_reg, value);
+
+        return len;
+}
+
+static const struct file_operations xi2c_reg_addr_fops = {
+        .owner = THIS_MODULE,
+        .open = simple_open,
+        .read =  xi2c_reg_addr_read,
+        .write = xi2c_reg_addr_write,
+};
+
+static const struct file_operations xi2c_reg_value_fops = {
+        .owner = THIS_MODULE,
+        .open = simple_open,
+        .read =  xi2c_reg_value_read,
+        .write = xi2c_reg_value_write,
+};
+
 void xgbe_debugfs_init(struct xgbe_prv_data *pdata)
 {
         struct dentry *pfile;
@@ -367,6 +487,38 @@ void xgbe_debugfs_init(struct xgbe_prv_data *pdata)
         if (!pfile)
                 netdev_err(pdata->netdev, "debugfs_create_file failed\n");
 
+        if (pdata->xprop_regs) {
+                pfile = debugfs_create_file("xprop_register", 0600,
+                                            pdata->xgbe_debugfs, pdata,
+                                            &xprop_reg_addr_fops);
+                if (!pfile)
+                        netdev_err(pdata->netdev,
+                                   "debugfs_create_file failed\n");
+
+                pfile = debugfs_create_file("xprop_register_value", 0600,
+                                            pdata->xgbe_debugfs, pdata,
+                                            &xprop_reg_value_fops);
+                if (!pfile)
+                        netdev_err(pdata->netdev,
+                                   "debugfs_create_file failed\n");
+        }
+
+        if (pdata->xi2c_regs) {
+                pfile = debugfs_create_file("xi2c_register", 0600,
+                                            pdata->xgbe_debugfs, pdata,
+                                            &xi2c_reg_addr_fops);
+                if (!pfile)
+                        netdev_err(pdata->netdev,
+                                   "debugfs_create_file failed\n");
+
+                pfile = debugfs_create_file("xi2c_register_value", 0600,
+                                            pdata->xgbe_debugfs, pdata,
+                                            &xi2c_reg_value_fops);
+                if (!pfile)
+                        netdev_err(pdata->netdev,
+                                   "debugfs_create_file failed\n");
+        }
+
         kfree(buf);
 }
 
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
index 903731902153..30056e24e1fc 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
@@ -646,6 +646,11 @@ static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
         unsigned int dma_ch_isr, dma_ch_ier;
         unsigned int i;
 
+        /* Set the interrupt mode if supported */
+        if (pdata->channel_irq_mode)
+                XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM,
+                                   pdata->channel_irq_mode);
+
         channel = pdata->channel;
         for (i = 0; i < pdata->channel_count; i++, channel++) {
                 /* Clear all the interrupts which are set */
@@ -667,19 +672,21 @@ static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
                 if (channel->tx_ring) {
                         /* Enable the following Tx interrupts
                          *   TIE  - Transmit Interrupt Enable (unless using
-                         *          per channel interrupts)
+                         *          per channel interrupts in edge triggered
+                         *          mode)
                          */
-                        if (!pdata->per_channel_irq)
+                        if (!pdata->per_channel_irq || pdata->channel_irq_mode)
                                 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
                 }
                 if (channel->rx_ring) {
                         /* Enable following Rx interrupts
                          *   RBUE - Receive Buffer Unavailable Enable
                          *   RIE  - Receive Interrupt Enable (unless using
-                         *          per channel interrupts)
+                         *          per channel interrupts in edge triggered
+                         *          mode)
                          */
                         XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
-                        if (!pdata->per_channel_irq)
+                        if (!pdata->per_channel_irq || pdata->channel_irq_mode)
                                 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
                 }
 
@@ -715,6 +722,68 @@ static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
         /* Enable all counter interrupts */
         XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
         XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
+
+        /* Enable MDIO single command completion interrupt */
+        XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1);
+}
+
+static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata)
+{
+        unsigned int ecc_isr, ecc_ier = 0;
+
+        if (!pdata->vdata->ecc_support)
+                return;
+
+        /* Clear all the interrupts which are set */
+        ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
+        XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
+
+        /* Enable ECC interrupts */
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 1);
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 1);
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 1);
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 1);
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 1);
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 1);
+
+        XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
+}
+
+static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata)
+{
+        unsigned int ecc_ier;
+
+        ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
+
+        /* Disable ECC DED interrupts */
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 0);
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 0);
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 0);
+
+        XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
+}
+
+static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata,
+                                 enum xgbe_ecc_sec sec)
+{
+        unsigned int ecc_ier;
+
+        ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
+
+        /* Disable ECC SEC interrupt */
+        switch (sec) {
+        case XGBE_ECC_SEC_TX:
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 0);
+                break;
+        case XGBE_ECC_SEC_RX:
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 0);
+                break;
+        case XGBE_ECC_SEC_DESC:
+        XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 0);
+                break;
+        }
+
+        XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
 }
 
 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed)
@@ -1026,6 +1095,36 @@ static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata)
         return 0;
 }
 
+static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
+{
+        unsigned int reg;
+
+        if (gpio > 16)
+                return -EINVAL;
+
+        reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
+
+        reg &= ~(1 << (gpio + 16));
+        XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
+
+        return 0;
+}
+
+static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
+{
+        unsigned int reg;
+
+        if (gpio > 16)
+                return -EINVAL;
+
+        reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
+
+        reg |= (1 << (gpio + 16));
+        XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
+
+        return 0;
+}
+
 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
                                  int mmd_reg)
 {
@@ -1170,6 +1269,79 @@ static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
         }
 }
 
+static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr,
+                                   int reg, u16 val)
+{
+        unsigned int mdio_sca, mdio_sccd;
+
+        reinit_completion(&pdata->mdio_complete);
+
+        mdio_sca = 0;
+        XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg);
+        XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr);
+        XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
+
+        mdio_sccd = 0;
+        XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val);
+        XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1);
+        XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
+        XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
+
+        if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) {
+                netdev_err(pdata->netdev, "mdio write operation timed out\n");
+                return -ETIMEDOUT;
+        }
+
+        return 0;
+}
+
+static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr,
+                                  int reg)
+{
+        unsigned int mdio_sca, mdio_sccd;
+
+        reinit_completion(&pdata->mdio_complete);
+
+        mdio_sca = 0;
+        XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg);
+        XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr);
+        XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
+
+        mdio_sccd = 0;
+        XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3);
+        XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
+        XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
+
+        if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) {
+                netdev_err(pdata->netdev, "mdio read operation timed out\n");
+                return -ETIMEDOUT;
+        }
+
+        return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA);
+}
+
+static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port,
+                                 enum xgbe_mdio_mode mode)
+{
+        unsigned int reg_val = 0;
+
+        switch (mode) {
+        case XGBE_MDIO_MODE_CL22:
+                if (port > XGMAC_MAX_C22_PORT)
+                        return -EINVAL;
+                reg_val |= (1 << port);
+                break;
+        case XGBE_MDIO_MODE_CL45:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val);
+
+        return 0;
+}
+
 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
 {
         return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
@@ -1360,14 +1532,21 @@ static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
 
 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
 {
-        unsigned int tx_snr;
+        unsigned int tx_snr, tx_ssr;
         u64 nsec;
 
-        tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
+        if (pdata->vdata->tx_tstamp_workaround) {
+                tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
+                tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
+        } else {
+                tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
+                tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
+        }
+
         if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
                 return 0;
 
-        nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
+        nsec = tx_ssr;
         nsec *= NSEC_PER_SEC;
         nsec += tx_snr;
 
@@ -1897,7 +2076,7 @@ static int xgbe_disable_int(struct xgbe_channel *channel,
         return 0;
 }
 
-static int xgbe_exit(struct xgbe_prv_data *pdata)
+static int __xgbe_exit(struct xgbe_prv_data *pdata)
 {
         unsigned int count = 2000;
 
@@ -1919,6 +2098,20 @@ static int xgbe_exit(struct xgbe_prv_data *pdata)
         return 0;
 }
 
+static int xgbe_exit(struct xgbe_prv_data *pdata)
+{
+        int ret;
+
+        /* To guard against possible incorrectly generated interrupts,
+         * issue the software reset twice.
+         */
+        ret = __xgbe_exit(pdata);
+        if (ret)
+                return ret;
+
+        return __xgbe_exit(pdata);
+}
+
 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
 {
         unsigned int i, count;
@@ -3266,6 +3459,11 @@ static int xgbe_init(struct xgbe_prv_data *pdata)
         xgbe_config_mmc(pdata);
         xgbe_enable_mac_interrupts(pdata);
 
+        /*
+         * Initialize ECC related features
+         */
+        xgbe_enable_ecc_interrupts(pdata);
+
         DBGPR("<--xgbe_init\n");
 
         return 0;
@@ -3294,6 +3492,13 @@ void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
 
         hw_if->set_speed = xgbe_set_speed;
 
+        hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode;
+        hw_if->read_ext_mii_regs = xgbe_read_ext_mii_regs;
+        hw_if->write_ext_mii_regs = xgbe_write_ext_mii_regs;
+
+        hw_if->set_gpio = xgbe_set_gpio;
+        hw_if->clr_gpio = xgbe_clr_gpio;
+
         hw_if->enable_tx = xgbe_enable_tx;
         hw_if->disable_tx = xgbe_disable_tx;
         hw_if->enable_rx = xgbe_enable_rx;
@@ -3371,5 +3576,9 @@ void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
         hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
         hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
 
+        /* For ECC */
+        hw_if->disable_ecc_ded = xgbe_disable_ecc_ded;
+        hw_if->disable_ecc_sec = xgbe_disable_ecc_sec;
+
         DBGPR("<--xgbe_init_function_ptrs\n");
 }
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
index a43e9303be90..155190db682d 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
@@ -114,6 +114,7 @@
  *     THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/tcp.h>
 #include <linux/if_vlan.h>
@@ -126,8 +127,35 @@
 #include "xgbe.h"
 #include "xgbe-common.h"
 
+static unsigned int ecc_sec_info_threshold = 10;
+static unsigned int ecc_sec_warn_threshold = 10000;
+static unsigned int ecc_sec_period = 600;
+static unsigned int ecc_ded_threshold = 2;
+static unsigned int ecc_ded_period = 600;
+
+#ifdef CONFIG_AMD_XGBE_HAVE_ECC
+/* Only expose the ECC parameters if supported */
+module_param(ecc_sec_info_threshold, uint, S_IWUSR | S_IRUGO);
+MODULE_PARM_DESC(ecc_sec_info_threshold,
+                 " ECC corrected error informational threshold setting");
+
+module_param(ecc_sec_warn_threshold, uint, S_IWUSR | S_IRUGO);
+MODULE_PARM_DESC(ecc_sec_warn_threshold,
+                 " ECC corrected error warning threshold setting");
+
+module_param(ecc_sec_period, uint, S_IWUSR | S_IRUGO);
+MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
+
+module_param(ecc_ded_threshold, uint, S_IWUSR | S_IRUGO);
+MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
+
+module_param(ecc_ded_period, uint, S_IWUSR | S_IRUGO);
+MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
+#endif
+
 static int xgbe_one_poll(struct napi_struct *, int);
 static int xgbe_all_poll(struct napi_struct *, int);
+static void xgbe_stop(struct xgbe_prv_data *);
 
 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
 {
@@ -252,48 +280,161 @@ static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
         return rx_buf_size;
 }
 
-static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
+static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
+                                  struct xgbe_channel *channel)
 {
         struct xgbe_hw_if *hw_if = &pdata->hw_if;
-        struct xgbe_channel *channel;
         enum xgbe_int int_id;
+
+        if (channel->tx_ring && channel->rx_ring)
+                int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
+        else if (channel->tx_ring)
+                int_id = XGMAC_INT_DMA_CH_SR_TI;
+        else if (channel->rx_ring)
+                int_id = XGMAC_INT_DMA_CH_SR_RI;
+        else
+                return;
+
+        hw_if->enable_int(channel, int_id);
+}
+
+static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_channel *channel;
         unsigned int i;
 
         channel = pdata->channel;
-        for (i = 0; i < pdata->channel_count; i++, channel++) {
-                if (channel->tx_ring && channel->rx_ring)
-                        int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
-                else if (channel->tx_ring)
-                        int_id = XGMAC_INT_DMA_CH_SR_TI;
-                else if (channel->rx_ring)
-                        int_id = XGMAC_INT_DMA_CH_SR_RI;
-                else
-                        continue;
+        for (i = 0; i < pdata->channel_count; i++, channel++)
+                xgbe_enable_rx_tx_int(pdata, channel);
+}
 
-                hw_if->enable_int(channel, int_id);
-        }
+static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
+                                   struct xgbe_channel *channel)
+{
+        struct xgbe_hw_if *hw_if = &pdata->hw_if;
+        enum xgbe_int int_id;
+
+        if (channel->tx_ring && channel->rx_ring)
+                int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
+        else if (channel->tx_ring)
+                int_id = XGMAC_INT_DMA_CH_SR_TI;
+        else if (channel->rx_ring)
+                int_id = XGMAC_INT_DMA_CH_SR_RI;
+        else
+                return;
+
+        hw_if->disable_int(channel, int_id);
 }
 
 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
 {
-        struct xgbe_hw_if *hw_if = &pdata->hw_if;
         struct xgbe_channel *channel;
-        enum xgbe_int int_id;
         unsigned int i;
 
         channel = pdata->channel;
-        for (i = 0; i < pdata->channel_count; i++, channel++) {
-                if (channel->tx_ring && channel->rx_ring)
-                        int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
-                else if (channel->tx_ring)
-                        int_id = XGMAC_INT_DMA_CH_SR_TI;
-                else if (channel->rx_ring)
-                        int_id = XGMAC_INT_DMA_CH_SR_RI;
-                else
-                        continue;
+        for (i = 0; i < pdata->channel_count; i++, channel++)
+                xgbe_disable_rx_tx_int(pdata, channel);
+}
+
+static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
+                         unsigned int *count, const char *area)
+{
+        if (time_before(jiffies, *period)) {
+                (*count)++;
+        } else {
+                *period = jiffies + (ecc_sec_period * HZ);
+                *count = 1;
+        }
+
+        if (*count > ecc_sec_info_threshold)
+                dev_warn_once(pdata->dev,
+                              "%s ECC corrected errors exceed informational threshold\n",
+                              area);
+
+        if (*count > ecc_sec_warn_threshold) {
+                dev_warn_once(pdata->dev,
+                              "%s ECC corrected errors exceed warning threshold\n",
+                              area);
+                return true;
+        }
+
+        return false;
+}
+
+static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
+                         unsigned int *count, const char *area)
+{
+        if (time_before(jiffies, *period)) {
+                (*count)++;
+        } else {
+                *period = jiffies + (ecc_ded_period * HZ);
+                *count = 1;
+        }
+
+        if (*count > ecc_ded_threshold) {
+                netdev_alert(pdata->netdev,
+                             "%s ECC detected errors exceed threshold\n",
+                             area);
+                return true;
+        }
+
+        return false;
+}
+
+static irqreturn_t xgbe_ecc_isr(int irq, void *data)
+{
+        struct xgbe_prv_data *pdata = data;
+        unsigned int ecc_isr;
+        bool stop = false;
+
+        /* Mask status with only the interrupts we care about */
+        ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
+        ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
+        netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
+
+        if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
+                stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
+                                     &pdata->tx_ded_count, "TX fifo");
+        }
+
+        if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
+                stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
+                                     &pdata->rx_ded_count, "RX fifo");
+        }
 
-                hw_if->disable_int(channel, int_id);
+        if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
+                stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
+                                     &pdata->desc_ded_count,
+                                     "descriptor cache");
         }
+
+        if (stop) {
+                pdata->hw_if.disable_ecc_ded(pdata);
+                schedule_work(&pdata->stopdev_work);
+                goto out;
+        }
+
+        if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
+                if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
+                                 &pdata->tx_sec_count, "TX fifo"))
+                        pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
+        }
+
+        if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
+                if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
+                                 &pdata->rx_sec_count, "RX fifo"))
+                        pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
+
+        if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
+                if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
+                                 &pdata->desc_sec_count, "descriptor cache"))
+                        pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
+
+out:
+        /* Clear all ECC interrupts */
+        XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
+
+        return IRQ_HANDLED;
 }
 
 static irqreturn_t xgbe_isr(int irq, void *data)
@@ -302,7 +443,7 @@ static irqreturn_t xgbe_isr(int irq, void *data)
         struct xgbe_hw_if *hw_if = &pdata->hw_if;
         struct xgbe_channel *channel;
         unsigned int dma_isr, dma_ch_isr;
-        unsigned int mac_isr, mac_tssr;
+        unsigned int mac_isr, mac_tssr, mac_mdioisr;
         unsigned int i;
 
         /* The DMA interrupt status register also reports MAC and MTL
@@ -339,6 +480,13 @@ static irqreturn_t xgbe_isr(int irq, void *data)
                                 /* Turn on polling */
                                 __napi_schedule_irqoff(&pdata->napi);
                         }
+                } else {
+                        /* Don't clear Rx/Tx status if doing per channel DMA
+                         * interrupts, these will be cleared by the ISR for
+                         * per channel DMA interrupts.
+                         */
+                        XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
+                        XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
                 }
 
                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
@@ -348,13 +496,16 @@ static irqreturn_t xgbe_isr(int irq, void *data)
                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
                         schedule_work(&pdata->restart_work);
 
-                /* Clear all interrupt signals */
+                /* Clear interrupt signals */
                 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
         }
 
         if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
                 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
 
+                netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
+                          mac_isr);
+
                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
                         hw_if->tx_mmc_int(pdata);
 
@@ -364,6 +515,9 @@ static irqreturn_t xgbe_isr(int irq, void *data)
                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
                         mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
 
+                        netif_dbg(pdata, intr, pdata->netdev,
+                                  "MAC_TSSR=%#010x\n", mac_tssr);
+
                         if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
                                 /* Read Tx Timestamp to clear interrupt */
                                 pdata->tx_tstamp =
@@ -372,8 +526,31 @@ static irqreturn_t xgbe_isr(int irq, void *data)
                                            &pdata->tx_tstamp_work);
                         }
                 }
+
+                if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
+                        mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
+
+                        netif_dbg(pdata, intr, pdata->netdev,
+                                  "MAC_MDIOISR=%#010x\n", mac_mdioisr);
+
+                        if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
+                                           SNGLCOMPINT))
+                                complete(&pdata->mdio_complete);
+                }
         }
 
+        /* If there is not a separate AN irq, handle it here */
+        if (pdata->dev_irq == pdata->an_irq)
+                pdata->phy_if.an_isr(irq, pdata);
+
+        /* If there is not a separate ECC irq, handle it here */
+        if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
+                xgbe_ecc_isr(irq, pdata);
+
+        /* If there is not a separate I2C irq, handle it here */
+        if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
+                pdata->i2c_if.i2c_isr(irq, pdata);
+
 isr_done:
         return IRQ_HANDLED;
 }
@@ -381,18 +558,29 @@ isr_done:
 static irqreturn_t xgbe_dma_isr(int irq, void *data)
 {
         struct xgbe_channel *channel = data;
+        struct xgbe_prv_data *pdata = channel->pdata;
+        unsigned int dma_status;
 
         /* Per channel DMA interrupts are enabled, so we use the per
          * channel napi structure and not the private data napi structure
          */
         if (napi_schedule_prep(&channel->napi)) {
                 /* Disable Tx and Rx interrupts */
-                disable_irq_nosync(channel->dma_irq);
+                if (pdata->channel_irq_mode)
+                        xgbe_disable_rx_tx_int(pdata, channel);
+                else
+                        disable_irq_nosync(channel->dma_irq);
 
                 /* Turn on polling */
                 __napi_schedule_irqoff(&channel->napi);
         }
 
+        /* Clear Tx/Rx signals */
+        dma_status = 0;
+        XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
+        XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
+        XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
+
         return IRQ_HANDLED;
 }
 
@@ -409,7 +597,10 @@ static void xgbe_tx_timer(unsigned long data)
         if (napi_schedule_prep(napi)) {
                 /* Disable Tx and Rx interrupts */
                 if (pdata->per_channel_irq)
-                        disable_irq_nosync(channel->dma_irq);
+                        if (pdata->channel_irq_mode)
+                                xgbe_disable_rx_tx_int(pdata, channel);
+                        else
+                                disable_irq_nosync(channel->dma_irq);
                 else
                         xgbe_disable_rx_tx_ints(pdata);
 
@@ -642,6 +833,16 @@ static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
                 return ret;
         }
 
+        if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
+                ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
+                                       0, pdata->ecc_name, pdata);
+                if (ret) {
+                        netdev_alert(netdev, "error requesting ecc irq %d\n",
+                                     pdata->ecc_irq);
+                        goto err_dev_irq;
+                }
+        }
+
         if (!pdata->per_channel_irq)
                 return 0;
 
@@ -658,17 +859,21 @@ static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
                 if (ret) {
                         netdev_alert(netdev, "error requesting irq %d\n",
                                      channel->dma_irq);
-                        goto err_irq;
+                        goto err_dma_irq;
                 }
         }
 
         return 0;
 
-err_irq:
+err_dma_irq:
         /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
         for (i--, channel--; i < pdata->channel_count; i--, channel--)
                 devm_free_irq(pdata->dev, channel->dma_irq, channel);
 
+        if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
+                devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
+
+err_dev_irq:
         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
 
         return ret;
@@ -681,6 +886,9 @@ static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
 
         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
 
+        if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
+                devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
+
         if (!pdata->per_channel_irq)
                 return;
 
@@ -864,16 +1072,16 @@ static int xgbe_start(struct xgbe_prv_data *pdata)
 
         hw_if->init(pdata);
 
-        ret = phy_if->phy_start(pdata);
-        if (ret)
-                goto err_phy;
-
         xgbe_napi_enable(pdata, 1);
 
         ret = xgbe_request_irqs(pdata);
         if (ret)
                 goto err_napi;
 
+        ret = phy_if->phy_start(pdata);
+        if (ret)
+                goto err_irqs;
+
         hw_if->enable_tx(pdata);
         hw_if->enable_rx(pdata);
 
@@ -882,16 +1090,18 @@ static int xgbe_start(struct xgbe_prv_data *pdata)
         xgbe_start_timers(pdata);
         queue_work(pdata->dev_workqueue, &pdata->service_work);
 
+        clear_bit(XGBE_STOPPED, &pdata->dev_state);
+
         DBGPR("<--xgbe_start\n");
 
         return 0;
 
+err_irqs:
+        xgbe_free_irqs(pdata);
+
 err_napi:
         xgbe_napi_disable(pdata, 1);
 
-        phy_if->phy_stop(pdata);
-
-err_phy:
         hw_if->exit(pdata);
 
         return ret;
@@ -908,6 +1118,9 @@ static void xgbe_stop(struct xgbe_prv_data *pdata)
 
         DBGPR("-->xgbe_stop\n");
 
+        if (test_bit(XGBE_STOPPED, &pdata->dev_state))
+                return;
+
         netif_tx_stop_all_queues(netdev);
 
         xgbe_stop_timers(pdata);
@@ -933,9 +1146,29 @@ static void xgbe_stop(struct xgbe_prv_data *pdata)
                 netdev_tx_reset_queue(txq);
         }
 
+        set_bit(XGBE_STOPPED, &pdata->dev_state);
+
         DBGPR("<--xgbe_stop\n");
 }
 
+static void xgbe_stopdev(struct work_struct *work)
+{
+        struct xgbe_prv_data *pdata = container_of(work,
+                                                   struct xgbe_prv_data,
+                                                   stopdev_work);
+
+        rtnl_lock();
+
+        xgbe_stop(pdata);
+
+        xgbe_free_tx_data(pdata);
+        xgbe_free_rx_data(pdata);
+
+        rtnl_unlock();
+
+        netdev_alert(pdata->netdev, "device stopped\n");
+}
+
 static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
 {
         DBGPR("-->xgbe_restart_dev\n");
@@ -1318,6 +1551,7 @@ static int xgbe_open(struct net_device *netdev)
 
         INIT_WORK(&pdata->service_work, xgbe_service);
         INIT_WORK(&pdata->restart_work, xgbe_restart);
+        INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
         INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
         xgbe_init_timers(pdata);
 
@@ -2026,6 +2260,7 @@ static int xgbe_one_poll(struct napi_struct *napi, int budget)
 {
         struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
                                                     napi);
+        struct xgbe_prv_data *pdata = channel->pdata;
         int processed = 0;
 
         DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
@@ -2042,7 +2277,10 @@ static int xgbe_one_poll(struct napi_struct *napi, int budget)
                 napi_complete_done(napi, processed);
 
                 /* Enable Tx and Rx interrupts */
-                enable_irq(channel->dma_irq);
+                if (pdata->channel_irq_mode)
+                        xgbe_enable_rx_tx_int(pdata, channel);
+                else
+                        enable_irq(channel->dma_irq);
         }
 
         DBGPR("<--xgbe_one_poll: received = %d\n", processed);
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-i2c.c b/drivers/net/ethernet/amd/xgbe/xgbe-i2c.c
new file mode 100644
index 000000000000..0c7088a426e9
--- /dev/null
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-i2c.c
@@ -0,0 +1,492 @@
+/*
+ * AMD 10Gb Ethernet driver
+ *
+ * This file is available to you under your choice of the following two
+ * licenses:
+ *
+ * License 1: GPLv2
+ *
+ * Copyright (c) 2016 Advanced Micro Devices, Inc.
+ *
+ * This file is free software; you may copy, redistribute and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * License 2: Modified BSD
+ *
+ * Copyright (c) 2016 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/module.h>
+#include <linux/kmod.h>
+#include <linux/delay.h>
+#include <linux/completion.h>
+#include <linux/mutex.h>
+
+#include "xgbe.h"
+#include "xgbe-common.h"
+
+#define XGBE_ABORT_COUNT        500
+#define XGBE_DISABLE_COUNT      1000
+
+#define XGBE_STD_SPEED          1
+
+#define XGBE_INTR_RX_FULL       BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX)
+#define XGBE_INTR_TX_EMPTY      BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX)
+#define XGBE_INTR_TX_ABRT       BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX)
+#define XGBE_INTR_STOP_DET      BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX)
+#define XGBE_DEFAULT_INT_MASK   (XGBE_INTR_RX_FULL  |   \
+                                 XGBE_INTR_TX_EMPTY |   \
+                                 XGBE_INTR_TX_ABRT  |   \
+                                 XGBE_INTR_STOP_DET)
+
+#define XGBE_I2C_READ           BIT(8)
+#define XGBE_I2C_STOP           BIT(9)
+
+static int xgbe_i2c_abort(struct xgbe_prv_data *pdata)
+{
+        unsigned int wait = XGBE_ABORT_COUNT;
+
+        /* Must be enabled to recognize the abort request */
+        XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1);
+
+        /* Issue the abort */
+        XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1);
+
+        while (wait--) {
+                if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT))
+                        return 0;
+
+                usleep_range(500, 600);
+        }
+
+        return -EBUSY;
+}
+
+static int xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable)
+{
+        unsigned int wait = XGBE_DISABLE_COUNT;
+        unsigned int mode = enable ? 1 : 0;
+
+        while (wait--) {
+                XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode);
+                if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode)
+                        return 0;
+
+                usleep_range(100, 110);
+        }
+
+        return -EBUSY;
+}
+
+static int xgbe_i2c_disable(struct xgbe_prv_data *pdata)
+{
+        unsigned int ret;
+
+        ret = xgbe_i2c_set_enable(pdata, false);
+        if (ret) {
+                /* Disable failed, try an abort */
+                ret = xgbe_i2c_abort(pdata);
+                if (ret)
+                        return ret;
+
+                /* Abort succeeded, try to disable again */
+                ret = xgbe_i2c_set_enable(pdata, false);
+        }
+
+        return ret;
+}
+
+static int xgbe_i2c_enable(struct xgbe_prv_data *pdata)
+{
+        return xgbe_i2c_set_enable(pdata, true);
+}
+
+static void xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata)
+{
+        XI2C_IOREAD(pdata, IC_CLR_INTR);
+}
+
+static void xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata)
+{
+        XI2C_IOWRITE(pdata, IC_INTR_MASK, 0);
+}
+
+static void xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata)
+{
+        XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK);
+}
+
+static void xgbe_i2c_write(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
+        unsigned int tx_slots;
+        unsigned int cmd;
+
+        /* Configured to never receive Rx overflows, so fill up Tx fifo */
+        tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR);
+        while (tx_slots && state->tx_len) {
+                if (state->op->cmd == XGBE_I2C_CMD_READ)
+                        cmd = XGBE_I2C_READ;
+                else
+                        cmd = *state->tx_buf++;
+
+                if (state->tx_len == 1)
+                        XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1);
+
+                XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd);
+
+                tx_slots--;
+                state->tx_len--;
+        }
+
+        /* No more Tx operations, so ignore TX_EMPTY and return */
+        if (!state->tx_len)
+                XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0);
+}
+
+static void xgbe_i2c_read(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
+        unsigned int rx_slots;
+
+        /* Anything to be read? */
+        if (state->op->cmd != XGBE_I2C_CMD_READ)
+                return;
+
+        rx_slots = XI2C_IOREAD(pdata, IC_RXFLR);
+        while (rx_slots && state->rx_len) {
+                *state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD);
+                state->rx_len--;
+                rx_slots--;
+        }
+}
+
+static void xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata,
+                                          unsigned int isr)
+{
+        struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
+
+        if (isr & XGBE_INTR_TX_ABRT) {
+                state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE);
+                XI2C_IOREAD(pdata, IC_CLR_TX_ABRT);
+        }
+
+        if (isr & XGBE_INTR_STOP_DET)
+                XI2C_IOREAD(pdata, IC_CLR_STOP_DET);
+}
+
+static irqreturn_t xgbe_i2c_isr(int irq, void *data)
+{
+        struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
+        struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
+        unsigned int isr;
+
+        isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT);
+        netif_dbg(pdata, intr, pdata->netdev,
+                  "I2C interrupt received: status=%#010x\n", isr);
+
+        xgbe_i2c_clear_isr_interrupts(pdata, isr);
+
+        if (isr & XGBE_INTR_TX_ABRT) {
+                netif_dbg(pdata, link, pdata->netdev,
+                          "I2C TX_ABRT received (%#010x) for target %#04x\n",
+                          state->tx_abort_source, state->op->target);
+
+                xgbe_i2c_disable_interrupts(pdata);
+
+                state->ret = -EIO;
+                goto out;
+        }
+
+        /* Check for data in the Rx fifo */
+        xgbe_i2c_read(pdata);
+
+        /* Fill up the Tx fifo next */
+        xgbe_i2c_write(pdata);
+
+out:
+        /* Complete on an error or STOP condition */
+        if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET))
+                complete(&pdata->i2c_complete);
+
+        return IRQ_HANDLED;
+}
+
+static void xgbe_i2c_set_mode(struct xgbe_prv_data *pdata)
+{
+        unsigned int reg;
+
+        reg = XI2C_IOREAD(pdata, IC_CON);
+        XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1);
+        XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1);
+        XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1);
+        XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED);
+        XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1);
+        XI2C_IOWRITE(pdata, IC_CON, reg);
+}
+
+static void xgbe_i2c_get_features(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_i2c *i2c = &pdata->i2c;
+        unsigned int reg;
+
+        reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1);
+        i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
+                                            MAX_SPEED_MODE);
+        i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
+                                          RX_BUFFER_DEPTH);
+        i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
+                                          TX_BUFFER_DEPTH);
+
+        if (netif_msg_probe(pdata))
+                dev_dbg(pdata->dev, "I2C features: %s=%u, %s=%u, %s=%u\n",
+                        "MAX_SPEED_MODE", i2c->max_speed_mode,
+                        "RX_BUFFER_DEPTH", i2c->rx_fifo_size,
+                        "TX_BUFFER_DEPTH", i2c->tx_fifo_size);
+}
+
+static void xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr)
+{
+        XI2C_IOWRITE(pdata, IC_TAR, addr);
+}
+
+static irqreturn_t xgbe_i2c_combined_isr(int irq, struct xgbe_prv_data *pdata)
+{
+        if (!XI2C_IOREAD(pdata, IC_RAW_INTR_STAT))
+                return IRQ_HANDLED;
+
+        return xgbe_i2c_isr(irq, pdata);
+}
+
+static int xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op)
+{
+        struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
+        int ret;
+
+        mutex_lock(&pdata->i2c_mutex);
+
+        reinit_completion(&pdata->i2c_complete);
+
+        ret = xgbe_i2c_disable(pdata);
+        if (ret) {
+                netdev_err(pdata->netdev, "failed to disable i2c master\n");
+                goto unlock;
+        }
+
+        xgbe_i2c_set_target(pdata, op->target);
+
+        memset(state, 0, sizeof(*state));
+        state->op = op;
+        state->tx_len = op->len;
+        state->tx_buf = op->buf;
+        state->rx_len = op->len;
+        state->rx_buf = op->buf;
+
+        xgbe_i2c_clear_all_interrupts(pdata);
+        ret = xgbe_i2c_enable(pdata);
+        if (ret) {
+                netdev_err(pdata->netdev, "failed to enable i2c master\n");
+                goto unlock;
+        }
+
+        /* Enabling the interrupts will cause the TX FIFO empty interrupt to
+         * fire and begin to process the command via the ISR.
+         */
+        xgbe_i2c_enable_interrupts(pdata);
+
+        if (!wait_for_completion_timeout(&pdata->i2c_complete, HZ)) {
+                netdev_err(pdata->netdev, "i2c operation timed out\n");
+                ret = -ETIMEDOUT;
+                goto disable;
+        }
+
+        ret = state->ret;
+        if (ret) {
+                if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK)
+                        ret = -ENOTCONN;
+                else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST)
+                        ret = -EAGAIN;
+        }
+
+disable:
+        xgbe_i2c_disable_interrupts(pdata);
+        xgbe_i2c_disable(pdata);
+
+unlock:
+        mutex_unlock(&pdata->i2c_mutex);
+
+        return ret;
+}
+
+static void xgbe_i2c_stop(struct xgbe_prv_data *pdata)
+{
+        if (!pdata->i2c.started)
+                return;
+
+        netif_dbg(pdata, link, pdata->netdev, "stopping I2C\n");
+
+        pdata->i2c.started = 0;
+
+        xgbe_i2c_disable_interrupts(pdata);
+        xgbe_i2c_disable(pdata);
+        xgbe_i2c_clear_all_interrupts(pdata);
+
+        if (pdata->dev_irq != pdata->i2c_irq)
+                devm_free_irq(pdata->dev, pdata->i2c_irq, pdata);
+}
+
+static int xgbe_i2c_start(struct xgbe_prv_data *pdata)
+{
+        int ret;
+
+        if (pdata->i2c.started)
+                return 0;
+
+        netif_dbg(pdata, link, pdata->netdev, "starting I2C\n");
+
+        /* If we have a separate I2C irq, enable it */
+        if (pdata->dev_irq != pdata->i2c_irq) {
+                ret = devm_request_irq(pdata->dev, pdata->i2c_irq,
+                                       xgbe_i2c_isr, 0, pdata->i2c_name,
+                                       pdata);
+                if (ret) {
+                        netdev_err(pdata->netdev, "i2c irq request failed\n");
+                        return ret;
+                }
+        }
+
+        pdata->i2c.started = 1;
+
+        return 0;
+}
+
+static int xgbe_i2c_init(struct xgbe_prv_data *pdata)
+{
+        int ret;
+
+        xgbe_i2c_disable_interrupts(pdata);
+
+        ret = xgbe_i2c_disable(pdata);
+        if (ret) {
+                dev_err(pdata->dev, "failed to disable i2c master\n");
+                return ret;
+        }
+
+        xgbe_i2c_get_features(pdata);
+
+        xgbe_i2c_set_mode(pdata);
+
+        xgbe_i2c_clear_all_interrupts(pdata);
+
+        return 0;
+}
+
+void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if)
+{
+        i2c_if->i2c_init                = xgbe_i2c_init;
+
+        i2c_if->i2c_start               = xgbe_i2c_start;
+        i2c_if->i2c_stop                = xgbe_i2c_stop;
+
+        i2c_if->i2c_xfer                = xgbe_i2c_xfer;
+
+        i2c_if->i2c_isr                 = xgbe_i2c_combined_isr;
+}
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
index c7187fca5fb7..b87a89988ffd 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
@@ -161,6 +161,7 @@ static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
 {
         xgbe_init_function_ptrs_dev(&pdata->hw_if);
         xgbe_init_function_ptrs_phy(&pdata->phy_if);
+        xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
         xgbe_init_function_ptrs_desc(&pdata->desc_if);
 
         pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
@@ -186,10 +187,14 @@ struct xgbe_prv_data *xgbe_alloc_pdata(struct device *dev)
         spin_lock_init(&pdata->xpcs_lock);
         mutex_init(&pdata->rss_mutex);
         spin_lock_init(&pdata->tstamp_lock);
+        mutex_init(&pdata->i2c_mutex);
+        init_completion(&pdata->i2c_complete);
+        init_completion(&pdata->mdio_complete);
 
         pdata->msg_enable = netif_msg_init(debug, default_msg_level);
 
         set_bit(XGBE_DOWN, &pdata->dev_state);
+        set_bit(XGBE_STOPPED, &pdata->dev_state);
 
         return pdata;
 }
@@ -236,8 +241,7 @@ void xgbe_set_counts(struct xgbe_prv_data *pdata)
 
         pdata->tx_q_count = pdata->tx_ring_count;
 
-        pdata->rx_ring_count = min_t(unsigned int,
-                                     netif_get_num_default_rss_queues(),
+        pdata->rx_ring_count = min_t(unsigned int, num_online_cpus(),
                                      pdata->hw_feat.rx_ch_cnt);
         pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
                                      pdata->rx_max_channel_count);
@@ -264,6 +268,14 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata)
         netdev->base_addr = (unsigned long)pdata->xgmac_regs;
         memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
 
+        /* Initialize ECC timestamps */
+        pdata->tx_sec_period = jiffies;
+        pdata->tx_ded_period = jiffies;
+        pdata->rx_sec_period = jiffies;
+        pdata->rx_ded_period = jiffies;
+        pdata->desc_sec_period = jiffies;
+        pdata->desc_ded_period = jiffies;
+
         /* Issue software reset to device */
         pdata->hw_if.exit(pdata);
 
@@ -291,6 +303,19 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata)
         BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_RX_DESC_CNT);
         pdata->rx_desc_count = XGBE_RX_DESC_CNT;
 
+        /* Adjust the number of queues based on interrupts assigned */
+        if (pdata->channel_irq_count) {
+                pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
+                                             pdata->channel_irq_count);
+                pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
+                                             pdata->channel_irq_count);
+
+                if (netif_msg_probe(pdata))
+                        dev_dbg(pdata->dev,
+                                "adjusted TX/RX DMA channel count = %u/%u\n",
+                                pdata->tx_ring_count, pdata->rx_ring_count);
+        }
+
         /* Set the number of queues */
         ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
         if (ret) {
@@ -372,6 +397,14 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata)
         snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
                  netdev_name(netdev));
 
+        /* Create the ECC name based on netdev name */
+        snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
+                 netdev_name(netdev));
+
+        /* Create the I2C name based on netdev name */
+        snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
+                 netdev_name(netdev));
+
         /* Create workqueues */
         pdata->dev_workqueue =
                 create_singlethread_workqueue(netdev_name(netdev));
@@ -393,6 +426,11 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata)
 
         xgbe_debugfs_init(pdata);
 
+        netif_dbg(pdata, drv, pdata->netdev, "%u Tx software queues\n",
+                  pdata->tx_ring_count);
+        netif_dbg(pdata, drv, pdata->netdev, "%u Rx software queues\n",
+                  pdata->rx_ring_count);
+
         return 0;
 
 err_wq:
@@ -431,11 +469,17 @@ static int __init xgbe_mod_init(void)
         if (ret)
                 return ret;
 
+        ret = xgbe_pci_init();
+        if (ret)
+                return ret;
+
         return 0;
 }
 
 static void __exit xgbe_mod_exit(void)
 {
+        xgbe_pci_exit();
+
         xgbe_platform_exit();
 }
 
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
index 723eb908b262..0ecae7045044 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
@@ -179,6 +179,7 @@ static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
 {
         switch (pdata->an_mode) {
         case XGBE_AN_MODE_CL73:
+        case XGBE_AN_MODE_CL73_REDRV:
                 xgbe_an73_enable_interrupts(pdata);
                 break;
         case XGBE_AN_MODE_CL37:
@@ -252,6 +253,58 @@ static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
         pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
 }
 
+static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
+{
+        /* If a KR re-driver is present, change to KR mode instead */
+        if (pdata->kr_redrv)
+                return xgbe_kr_mode(pdata);
+
+        /* Disable KR training */
+        xgbe_an73_disable_kr_training(pdata);
+
+        /* Set MAC to 10G speed */
+        pdata->hw_if.set_speed(pdata, SPEED_10000);
+
+        /* Call PHY implementation support to complete rate change */
+        pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
+}
+
+static void xgbe_x_mode(struct xgbe_prv_data *pdata)
+{
+        /* Disable KR training */
+        xgbe_an73_disable_kr_training(pdata);
+
+        /* Set MAC to 1G speed */
+        pdata->hw_if.set_speed(pdata, SPEED_1000);
+
+        /* Call PHY implementation support to complete rate change */
+        pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
+}
+
+static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
+{
+        /* Disable KR training */
+        xgbe_an73_disable_kr_training(pdata);
+
+        /* Set MAC to 1G speed */
+        pdata->hw_if.set_speed(pdata, SPEED_1000);
+
+        /* Call PHY implementation support to complete rate change */
+        pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
+}
+
+static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
+{
+        /* Disable KR training */
+        xgbe_an73_disable_kr_training(pdata);
+
+        /* Set MAC to 1G speed */
+        pdata->hw_if.set_speed(pdata, SPEED_1000);
+
+        /* Call PHY implementation support to complete rate change */
+        pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
+}
+
 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
 {
         return pdata->phy_if.phy_impl.cur_mode(pdata);
@@ -275,6 +328,18 @@ static void xgbe_change_mode(struct xgbe_prv_data *pdata,
         case XGBE_MODE_KR:
                 xgbe_kr_mode(pdata);
                 break;
+        case XGBE_MODE_SGMII_100:
+                xgbe_sgmii_100_mode(pdata);
+                break;
+        case XGBE_MODE_SGMII_1000:
+                xgbe_sgmii_1000_mode(pdata);
+                break;
+        case XGBE_MODE_X:
+                xgbe_x_mode(pdata);
+                break;
+        case XGBE_MODE_SFI:
+                xgbe_sfi_mode(pdata);
+                break;
         case XGBE_MODE_UNKNOWN:
                 break;
         default:
@@ -373,6 +438,7 @@ static void xgbe_an_restart(struct xgbe_prv_data *pdata)
 {
         switch (pdata->an_mode) {
         case XGBE_AN_MODE_CL73:
+        case XGBE_AN_MODE_CL73_REDRV:
                 xgbe_an73_restart(pdata);
                 break;
         case XGBE_AN_MODE_CL37:
@@ -388,6 +454,7 @@ static void xgbe_an_disable(struct xgbe_prv_data *pdata)
 {
         switch (pdata->an_mode) {
         case XGBE_AN_MODE_CL73:
+        case XGBE_AN_MODE_CL73_REDRV:
                 xgbe_an73_disable(pdata);
                 break;
         case XGBE_AN_MODE_CL37:
@@ -627,6 +694,7 @@ static irqreturn_t xgbe_an_isr(int irq, void *data)
 
         switch (pdata->an_mode) {
         case XGBE_AN_MODE_CL73:
+        case XGBE_AN_MODE_CL73_REDRV:
                 xgbe_an73_isr(pdata);
                 break;
         case XGBE_AN_MODE_CL37:
@@ -640,6 +708,11 @@ static irqreturn_t xgbe_an_isr(int irq, void *data)
         return IRQ_HANDLED;
 }
 
+static irqreturn_t xgbe_an_combined_isr(int irq, struct xgbe_prv_data *pdata)
+{
+        return xgbe_an_isr(irq, pdata);
+}
+
 static void xgbe_an_irq_work(struct work_struct *work)
 {
         struct xgbe_prv_data *pdata = container_of(work,
@@ -830,6 +903,7 @@ static void xgbe_an_state_machine(struct work_struct *work)
 
         switch (pdata->an_mode) {
         case XGBE_AN_MODE_CL73:
+        case XGBE_AN_MODE_CL73_REDRV:
                 xgbe_an73_state_machine(pdata);
                 break;
         case XGBE_AN_MODE_CL37:
@@ -845,16 +919,18 @@ static void xgbe_an_state_machine(struct work_struct *work)
 
 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
 {
-        unsigned int reg;
+        unsigned int advertising, reg;
+
+        advertising = pdata->phy_if.phy_impl.an_advertising(pdata);
 
         /* Set up Advertisement register */
         reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
-        if (pdata->phy.advertising & ADVERTISED_Pause)
+        if (advertising & ADVERTISED_Pause)
                 reg |= 0x100;
         else
                 reg &= ~0x100;
 
-        if (pdata->phy.advertising & ADVERTISED_Asym_Pause)
+        if (advertising & ADVERTISED_Asym_Pause)
                 reg |= 0x80;
         else
                 reg &= ~0x80;
@@ -889,11 +965,13 @@ static void xgbe_an37_init(struct xgbe_prv_data *pdata)
 
 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
 {
-        unsigned int reg;
+        unsigned int advertising, reg;
+
+        advertising = pdata->phy_if.phy_impl.an_advertising(pdata);
 
         /* Set up Advertisement register 3 first */
         reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
-        if (pdata->phy.advertising & ADVERTISED_10000baseR_FEC)
+        if (advertising & ADVERTISED_10000baseR_FEC)
                 reg |= 0xc000;
         else
                 reg &= ~0xc000;
@@ -902,13 +980,13 @@ static void xgbe_an73_init(struct xgbe_prv_data *pdata)
 
         /* Set up Advertisement register 2 next */
         reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
-        if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full)
+        if (advertising & ADVERTISED_10000baseKR_Full)
                 reg |= 0x80;
         else
                 reg &= ~0x80;
 
-        if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) ||
-            (pdata->phy.advertising & ADVERTISED_2500baseX_Full))
+        if ((advertising & ADVERTISED_1000baseKX_Full) ||
+            (advertising & ADVERTISED_2500baseX_Full))
                 reg |= 0x20;
         else
                 reg &= ~0x20;
@@ -917,12 +995,12 @@ static void xgbe_an73_init(struct xgbe_prv_data *pdata)
 
         /* Set up Advertisement register 1 last */
         reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
-        if (pdata->phy.advertising & ADVERTISED_Pause)
+        if (advertising & ADVERTISED_Pause)
                 reg |= 0x400;
         else
                 reg &= ~0x400;
 
-        if (pdata->phy.advertising & ADVERTISED_Asym_Pause)
+        if (advertising & ADVERTISED_Asym_Pause)
                 reg |= 0x800;
         else
                 reg &= ~0x800;
@@ -941,6 +1019,7 @@ static void xgbe_an_init(struct xgbe_prv_data *pdata)
         pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
         switch (pdata->an_mode) {
         case XGBE_AN_MODE_CL73:
+        case XGBE_AN_MODE_CL73_REDRV:
                 xgbe_an73_init(pdata);
                 break;
         case XGBE_AN_MODE_CL37:
@@ -967,6 +1046,8 @@ static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
 static const char *xgbe_phy_speed_string(int speed)
 {
         switch (speed) {
+        case SPEED_100:
+                return "100Mbps";
         case SPEED_1000:
                 return "1Gbps";
         case SPEED_2500:
@@ -1052,6 +1133,10 @@ static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
         case XGBE_MODE_KX_1000:
         case XGBE_MODE_KX_2500:
         case XGBE_MODE_KR:
+        case XGBE_MODE_SGMII_100:
+        case XGBE_MODE_SGMII_1000:
+        case XGBE_MODE_X:
+        case XGBE_MODE_SFI:
                 break;
         case XGBE_MODE_UNKNOWN:
         default:
@@ -1069,13 +1154,24 @@ static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
 
 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
 {
+        int ret;
+
         set_bit(XGBE_LINK_INIT, &pdata->dev_state);
         pdata->link_check = jiffies;
 
-        if (pdata->phy.autoneg != AUTONEG_ENABLE)
-                return xgbe_phy_config_fixed(pdata);
+        ret = pdata->phy_if.phy_impl.an_config(pdata);
+        if (ret)
+                return ret;
 
-        netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
+        if (pdata->phy.autoneg != AUTONEG_ENABLE) {
+                ret = xgbe_phy_config_fixed(pdata);
+                if (ret || !pdata->kr_redrv)
+                        return ret;
+
+                netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n");
+        } else {
+                netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
+        }
 
         /* Disable auto-negotiation interrupt */
         disable_irq(pdata->an_irq);
@@ -1087,6 +1183,14 @@ static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
                 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
         } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
                 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
+        } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
+                xgbe_set_mode(pdata, XGBE_MODE_SFI);
+        } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
+                xgbe_set_mode(pdata, XGBE_MODE_X);
+        } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
+                xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
+        } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
+                xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
         } else {
                 enable_irq(pdata->an_irq);
                 return -EINVAL;
@@ -1162,13 +1266,19 @@ static void xgbe_phy_status_result(struct xgbe_prv_data *pdata)
                 mode = xgbe_phy_status_aneg(pdata);
 
         switch (mode) {
+        case XGBE_MODE_SGMII_100:
+                pdata->phy.speed = SPEED_100;
+                break;
+        case XGBE_MODE_X:
         case XGBE_MODE_KX_1000:
+        case XGBE_MODE_SGMII_1000:
                 pdata->phy.speed = SPEED_1000;
                 break;
         case XGBE_MODE_KX_2500:
                 pdata->phy.speed = SPEED_2500;
                 break;
         case XGBE_MODE_KR:
+        case XGBE_MODE_SFI:
                 pdata->phy.speed = SPEED_10000;
                 break;
         case XGBE_MODE_UNKNOWN:
@@ -1184,6 +1294,7 @@ static void xgbe_phy_status_result(struct xgbe_prv_data *pdata)
 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
 {
         unsigned int link_aneg;
+        int an_restart;
 
         if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
                 netif_carrier_off(pdata->netdev);
@@ -1194,7 +1305,13 @@ static void xgbe_phy_status(struct xgbe_prv_data *pdata)
 
         link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
 
-        pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata);
+        pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
+                                                             &an_restart);
+        if (an_restart) {
+                xgbe_phy_config_aneg(pdata);
+                return;
+        }
+
         if (pdata->phy.link) {
                 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
                         xgbe_check_link_timeout(pdata);
@@ -1237,7 +1354,8 @@ static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
         /* Disable auto-negotiation */
         xgbe_an_disable_all(pdata);
 
-        devm_free_irq(pdata->dev, pdata->an_irq, pdata);
+        if (pdata->dev_irq != pdata->an_irq)
+                devm_free_irq(pdata->dev, pdata->an_irq, pdata);
 
         pdata->phy_if.phy_impl.stop(pdata);
 
@@ -1258,12 +1376,15 @@ static int xgbe_phy_start(struct xgbe_prv_data *pdata)
         if (ret)
                 return ret;
 
-        ret = devm_request_irq(pdata->dev, pdata->an_irq,
-                               xgbe_an_isr, 0, pdata->an_name,
-                               pdata);
-        if (ret) {
-                netdev_err(netdev, "phy irq request failed\n");
-                goto err_stop;
+        /* If we have a separate AN irq, enable it */
+        if (pdata->dev_irq != pdata->an_irq) {
+                ret = devm_request_irq(pdata->dev, pdata->an_irq,
+                                       xgbe_an_isr, 0, pdata->an_name,
+                                       pdata);
+                if (ret) {
+                        netdev_err(netdev, "phy irq request failed\n");
+                        goto err_stop;
+                }
         }
 
         /* Set initial mode - call the mode setting routines
@@ -1275,6 +1396,14 @@ static int xgbe_phy_start(struct xgbe_prv_data *pdata)
                 xgbe_kx_2500_mode(pdata);
         } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
                 xgbe_kx_1000_mode(pdata);
+        } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
+                xgbe_sfi_mode(pdata);
+        } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
+                xgbe_x_mode(pdata);
+        } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
+                xgbe_sgmii_1000_mode(pdata);
+        } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
+                xgbe_sgmii_100_mode(pdata);
         } else {
                 ret = -EINVAL;
                 goto err_irq;
@@ -1289,7 +1418,8 @@ static int xgbe_phy_start(struct xgbe_prv_data *pdata)
         return xgbe_phy_config_aneg(pdata);
 
 err_irq:
-        devm_free_irq(pdata->dev, pdata->an_irq, pdata);
+        if (pdata->dev_irq != pdata->an_irq)
+                devm_free_irq(pdata->dev, pdata->an_irq, pdata);
 
 err_stop:
         pdata->phy_if.phy_impl.stop(pdata);
@@ -1357,10 +1487,16 @@ static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
 {
         if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full)
                 return SPEED_10000;
+        else if (pdata->phy.advertising & ADVERTISED_10000baseT_Full)
+                return SPEED_10000;
         else if (pdata->phy.advertising & ADVERTISED_2500baseX_Full)
                 return SPEED_2500;
         else if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full)
                 return SPEED_1000;
+        else if (pdata->phy.advertising & ADVERTISED_1000baseT_Full)
+                return SPEED_1000;
+        else if (pdata->phy.advertising & ADVERTISED_100baseT_Full)
+                return SPEED_100;
 
         return SPEED_UNKNOWN;
 }
@@ -1442,4 +1578,6 @@ void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
         phy_if->phy_config_aneg = xgbe_phy_config_aneg;
 
         phy_if->phy_valid_speed = xgbe_phy_valid_speed;
+
+        phy_if->an_isr          = xgbe_an_combined_isr;
 }
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
new file mode 100644
index 000000000000..e76b7f65b805
--- /dev/null
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
@@ -0,0 +1,529 @@
+/*
+ * AMD 10Gb Ethernet driver
+ *
+ * This file is available to you under your choice of the following two
+ * licenses:
+ *
+ * License 1: GPLv2
+ *
+ * Copyright (c) 2016 Advanced Micro Devices, Inc.
+ *
+ * This file is free software; you may copy, redistribute and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * License 2: Modified BSD
+ *
+ * Copyright (c) 2016 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/pci.h>
+#include <linux/log2.h>
+
+#include "xgbe.h"
+#include "xgbe-common.h"
+
+static int xgbe_config_msi(struct xgbe_prv_data *pdata)
+{
+        unsigned int msi_count;
+        unsigned int i, j;
+        int ret;
+
+        msi_count = XGBE_MSIX_BASE_COUNT;
+        msi_count += max(pdata->rx_ring_count,
+                         pdata->tx_ring_count);
+        msi_count = roundup_pow_of_two(msi_count);
+
+        ret = pci_enable_msi_exact(pdata->pcidev, msi_count);
+        if (ret < 0) {
+                dev_info(pdata->dev, "MSI request for %u interrupts failed\n",
+                         msi_count);
+
+                ret = pci_enable_msi(pdata->pcidev);
+                if (ret < 0) {
+                        dev_info(pdata->dev, "MSI enablement failed\n");
+                        return ret;
+                }
+
+                msi_count = 1;
+        }
+
+        pdata->irq_count = msi_count;
+
+        pdata->dev_irq = pdata->pcidev->irq;
+
+        if (msi_count > 1) {
+                pdata->ecc_irq = pdata->pcidev->irq + 1;
+                pdata->i2c_irq = pdata->pcidev->irq + 2;
+                pdata->an_irq = pdata->pcidev->irq + 3;
+
+                for (i = XGBE_MSIX_BASE_COUNT, j = 0;
+                     (i < msi_count) && (j < XGBE_MAX_DMA_CHANNELS);
+                     i++, j++)
+                        pdata->channel_irq[j] = pdata->pcidev->irq + i;
+                pdata->channel_irq_count = j;
+
+                pdata->per_channel_irq = 1;
+                pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
+        } else {
+                pdata->ecc_irq = pdata->pcidev->irq;
+                pdata->i2c_irq = pdata->pcidev->irq;
+                pdata->an_irq = pdata->pcidev->irq;
+        }
+
+        if (netif_msg_probe(pdata))
+                dev_dbg(pdata->dev, "MSI interrupts enabled\n");
+
+        return 0;
+}
+
+static int xgbe_config_msix(struct xgbe_prv_data *pdata)
+{
+        unsigned int msix_count;
+        unsigned int i, j;
+        int ret;
+
+        msix_count = XGBE_MSIX_BASE_COUNT;
+        msix_count += max(pdata->rx_ring_count,
+                          pdata->tx_ring_count);
+
+        pdata->msix_entries = devm_kcalloc(pdata->dev, msix_count,
+                                           sizeof(struct msix_entry),
+                                           GFP_KERNEL);
+        if (!pdata->msix_entries)
+                return -ENOMEM;
+
+        for (i = 0; i < msix_count; i++)
+                pdata->msix_entries[i].entry = i;
+
+        ret = pci_enable_msix_range(pdata->pcidev, pdata->msix_entries,
+                                    XGBE_MSIX_MIN_COUNT, msix_count);
+        if (ret < 0) {
+                dev_info(pdata->dev, "MSI-X enablement failed\n");
+                devm_kfree(pdata->dev, pdata->msix_entries);
+                pdata->msix_entries = NULL;
+                return ret;
+        }
+
+        pdata->irq_count = ret;
+
+        pdata->dev_irq = pdata->msix_entries[0].vector;
+        pdata->ecc_irq = pdata->msix_entries[1].vector;
+        pdata->i2c_irq = pdata->msix_entries[2].vector;
+        pdata->an_irq = pdata->msix_entries[3].vector;
+
+        for (i = XGBE_MSIX_BASE_COUNT, j = 0; i < ret; i++, j++)
+                pdata->channel_irq[j] = pdata->msix_entries[i].vector;
+        pdata->channel_irq_count = j;
+
+        pdata->per_channel_irq = 1;
+        pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
+
+        if (netif_msg_probe(pdata))
+                dev_dbg(pdata->dev, "MSI-X interrupts enabled\n");
+
+        return 0;
+}
+
+static int xgbe_config_irqs(struct xgbe_prv_data *pdata)
+{
+        int ret;
+
+        ret = xgbe_config_msix(pdata);
+        if (!ret)
+                goto out;
+
+        ret = xgbe_config_msi(pdata);
+        if (!ret)
+                goto out;
+
+        pdata->irq_count = 1;
+        pdata->irq_shared = 1;
+
+        pdata->dev_irq = pdata->pcidev->irq;
+        pdata->ecc_irq = pdata->pcidev->irq;
+        pdata->i2c_irq = pdata->pcidev->irq;
+        pdata->an_irq = pdata->pcidev->irq;
+
+out:
+        if (netif_msg_probe(pdata)) {
+                unsigned int i;
+
+                dev_dbg(pdata->dev, " dev irq=%d\n", pdata->dev_irq);
+                dev_dbg(pdata->dev, " ecc irq=%d\n", pdata->ecc_irq);
+                dev_dbg(pdata->dev, " i2c irq=%d\n", pdata->i2c_irq);
+                dev_dbg(pdata->dev, "  an irq=%d\n", pdata->an_irq);
+                for (i = 0; i < pdata->channel_irq_count; i++)
+                        dev_dbg(pdata->dev, " dma%u irq=%d\n",
+                                i, pdata->channel_irq[i]);
+        }
+
+        return 0;
+}
+
+static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+        struct xgbe_prv_data *pdata;
+        struct device *dev = &pdev->dev;
+        void __iomem * const *iomap_table;
+        unsigned int ma_lo, ma_hi;
+        unsigned int reg;
+        int bar_mask;
+        int ret;
+
+        pdata = xgbe_alloc_pdata(dev);
+        if (IS_ERR(pdata)) {
+                ret = PTR_ERR(pdata);
+                goto err_alloc;
+        }
+
+        pdata->pcidev = pdev;
+        pci_set_drvdata(pdev, pdata);
+
+        /* Get the version data */
+        pdata->vdata = (struct xgbe_version_data *)id->driver_data;
+
+        ret = pcim_enable_device(pdev);
+        if (ret) {
+                dev_err(dev, "pcim_enable_device failed\n");
+                goto err_pci_enable;
+        }
+
+        /* Obtain the mmio areas for the device */
+        bar_mask = pci_select_bars(pdev, IORESOURCE_MEM);
+        ret = pcim_iomap_regions(pdev, bar_mask, XGBE_DRV_NAME);
+        if (ret) {
+                dev_err(dev, "pcim_iomap_regions failed\n");
+                goto err_pci_enable;
+        }
+
+        iomap_table = pcim_iomap_table(pdev);
+        if (!iomap_table) {
+                dev_err(dev, "pcim_iomap_table failed\n");
+                ret = -ENOMEM;
+                goto err_pci_enable;
+        }
+
+        pdata->xgmac_regs = iomap_table[XGBE_XGMAC_BAR];
+        if (!pdata->xgmac_regs) {
+                dev_err(dev, "xgmac ioremap failed\n");
+                ret = -ENOMEM;
+                goto err_pci_enable;
+        }
+        pdata->xprop_regs = pdata->xgmac_regs + XGBE_MAC_PROP_OFFSET;
+        pdata->xi2c_regs = pdata->xgmac_regs + XGBE_I2C_CTRL_OFFSET;
+        if (netif_msg_probe(pdata)) {
+                dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs);
+                dev_dbg(dev, "xprop_regs = %p\n", pdata->xprop_regs);
+                dev_dbg(dev, "xi2c_regs  = %p\n", pdata->xi2c_regs);
+        }
+
+        pdata->xpcs_regs = iomap_table[XGBE_XPCS_BAR];
+        if (!pdata->xpcs_regs) {
+                dev_err(dev, "xpcs ioremap failed\n");
+                ret = -ENOMEM;
+                goto err_pci_enable;
+        }
+        if (netif_msg_probe(pdata))
+                dev_dbg(dev, "xpcs_regs  = %p\n", pdata->xpcs_regs);
+
+        /* Configure the PCS indirect addressing support */
+        reg = XPCS32_IOREAD(pdata, PCS_V2_WINDOW_DEF);
+        pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
+        pdata->xpcs_window <<= 6;
+        pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
+        pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
+        pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
+        if (netif_msg_probe(pdata)) {
+                dev_dbg(dev, "xpcs window      = %#010x\n",
+                        pdata->xpcs_window);
+                dev_dbg(dev, "xpcs window size = %#010x\n",
+                        pdata->xpcs_window_size);
+                dev_dbg(dev, "xpcs window mask = %#010x\n",
+                        pdata->xpcs_window_mask);
+        }
+
+        pci_set_master(pdev);
+
+        /* Enable all interrupts in the hardware */
+        XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
+
+        /* Retrieve the MAC address */
+        ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
+        ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
+        pdata->mac_addr[0] = ma_lo & 0xff;
+        pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
+        pdata->mac_addr[2] = (ma_lo >> 16) & 0xff;
+        pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
+        pdata->mac_addr[4] = ma_hi & 0xff;
+        pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
+        if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID) ||
+            !is_valid_ether_addr(pdata->mac_addr)) {
+                dev_err(dev, "invalid mac address\n");
+                ret = -EINVAL;
+                goto err_pci_enable;
+        }
+
+        /* Clock settings */
+        pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
+        pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
+
+        /* Set the DMA coherency values */
+        pdata->coherent = 1;
+        pdata->axdomain = XGBE_DMA_OS_AXDOMAIN;
+        pdata->arcache = XGBE_DMA_OS_ARCACHE;
+        pdata->awcache = XGBE_DMA_OS_AWCACHE;
+
+        /* Set the maximum channels and queues */
+        reg = XP_IOREAD(pdata, XP_PROP_1);
+        pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);
+        pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);
+        pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);
+        pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);
+        if (netif_msg_probe(pdata)) {
+                dev_dbg(dev, "max tx/rx channel count = %u/%u\n",
+                        pdata->tx_max_channel_count,
+                        pdata->tx_max_channel_count);
+                dev_dbg(dev, "max tx/rx hw queue count = %u/%u\n",
+                        pdata->tx_max_q_count, pdata->rx_max_q_count);
+        }
+
+        /* Set the hardware channel and queue counts */
+        xgbe_set_counts(pdata);
+
+        /* Set the maximum fifo amounts */
+        reg = XP_IOREAD(pdata, XP_PROP_2);
+        pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);
+        pdata->tx_max_fifo_size *= 16384;
+        pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
+                                      pdata->vdata->tx_max_fifo_size);
+        pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);
+        pdata->rx_max_fifo_size *= 16384;
+        pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
+                                      pdata->vdata->rx_max_fifo_size);
+        if (netif_msg_probe(pdata))
+                dev_dbg(dev, "max tx/rx max fifo size = %u/%u\n",
+                        pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
+
+        /* Configure interrupt support */
+        ret = xgbe_config_irqs(pdata);
+        if (ret)
+                goto err_pci_enable;
+
+        /* Configure the netdev resource */
+        ret = xgbe_config_netdev(pdata);
+        if (ret)
+                goto err_pci_enable;
+
+        netdev_notice(pdata->netdev, "net device enabled\n");
+
+        return 0;
+
+err_pci_enable:
+        xgbe_free_pdata(pdata);
+
+err_alloc:
+        dev_notice(dev, "net device not enabled\n");
+
+        return ret;
+}
+
+static void xgbe_pci_remove(struct pci_dev *pdev)
+{
+        struct xgbe_prv_data *pdata = pci_get_drvdata(pdev);
+
+        xgbe_deconfig_netdev(pdata);
+
+        xgbe_free_pdata(pdata);
+}
+
+#ifdef CONFIG_PM
+static int xgbe_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+        struct xgbe_prv_data *pdata = pci_get_drvdata(pdev);
+        struct net_device *netdev = pdata->netdev;
+        int ret = 0;
+
+        if (netif_running(netdev))
+                ret = xgbe_powerdown(netdev, XGMAC_DRIVER_CONTEXT);
+
+        pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
+        pdata->lpm_ctrl |= MDIO_CTRL1_LPOWER;
+        XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
+
+        return ret;
+}
+
+static int xgbe_pci_resume(struct pci_dev *pdev)
+{
+        struct xgbe_prv_data *pdata = pci_get_drvdata(pdev);
+        struct net_device *netdev = pdata->netdev;
+        int ret = 0;
+
+        pdata->lpm_ctrl &= ~MDIO_CTRL1_LPOWER;
+        XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
+
+        if (netif_running(netdev)) {
+                ret = xgbe_powerup(netdev, XGMAC_DRIVER_CONTEXT);
+
+                /* Schedule a restart in case the link or phy state changed
+                 * while we were powered down.
+                 */
+                schedule_work(&pdata->restart_work);
+        }
+
+        return ret;
+}
+#endif /* CONFIG_PM */
+
+static const struct xgbe_version_data xgbe_v2a = {
+        .init_function_ptrs_phy_impl    = xgbe_init_function_ptrs_phy_v2,
+        .xpcs_access                    = XGBE_XPCS_ACCESS_V2,
+        .mmc_64bit                      = 1,
+        .tx_max_fifo_size               = 229376,
+        .rx_max_fifo_size               = 229376,
+        .tx_tstamp_workaround           = 1,
+        .ecc_support                    = 1,
+        .i2c_support                    = 1,
+};
+
+static const struct xgbe_version_data xgbe_v2b = {
+        .init_function_ptrs_phy_impl    = xgbe_init_function_ptrs_phy_v2,
+        .xpcs_access                    = XGBE_XPCS_ACCESS_V2,
+        .mmc_64bit                      = 1,
+        .tx_max_fifo_size               = 65536,
+        .rx_max_fifo_size               = 65536,
+        .tx_tstamp_workaround           = 1,
+        .ecc_support                    = 1,
+        .i2c_support                    = 1,
+};
+
+static const struct pci_device_id xgbe_pci_table[] = {
+        { PCI_VDEVICE(AMD, 0x1458),
+          .driver_data = (kernel_ulong_t)&xgbe_v2a },
+        { PCI_VDEVICE(AMD, 0x1459),
+          .driver_data = (kernel_ulong_t)&xgbe_v2b },
+        /* Last entry must be zero */
+        { 0, }
+};
+MODULE_DEVICE_TABLE(pci, xgbe_pci_table);
+
+static struct pci_driver xgbe_driver = {
+        .name = XGBE_DRV_NAME,
+        .id_table = xgbe_pci_table,
+        .probe = xgbe_pci_probe,
+        .remove = xgbe_pci_remove,
+#ifdef CONFIG_PM
+        .suspend = xgbe_pci_suspend,
+        .resume = xgbe_pci_resume,
+#endif
+};
+
+int xgbe_pci_init(void)
+{
+        return pci_register_driver(&xgbe_driver);
+}
+
+void xgbe_pci_exit(void)
+{
+        pci_unregister_driver(&xgbe_driver);
+}
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c
index 9c913a06efcc..c75edcac5e0a 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c
@@ -295,6 +295,17 @@ static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
         return mode;
 }
 
+static unsigned int xgbe_phy_an_advertising(struct xgbe_prv_data *pdata)
+{
+        return pdata->phy.advertising;
+}
+
+static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
+{
+        /* Nothing uniquely required for an configuration */
+        return 0;
+}
+
 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
 {
         return XGBE_AN_MODE_CL73;
@@ -607,10 +618,12 @@ static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
         }
 }
 
-static int xgbe_phy_link_status(struct xgbe_prv_data *pdata)
+static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
 {
         unsigned int reg;
 
+        *an_restart = 0;
+
         /* Link status is latched low, so read once to clear
          * and then read again to get current state
          */
@@ -821,6 +834,10 @@ void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *phy_if)
 
         phy_impl->an_mode               = xgbe_phy_an_mode;
 
+        phy_impl->an_config             = xgbe_phy_an_config;
+
+        phy_impl->an_advertising        = xgbe_phy_an_advertising;
+
         phy_impl->an_outcome            = xgbe_phy_an_outcome;
 
         phy_impl->kr_training_pre       = xgbe_phy_kr_training_pre;
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
new file mode 100644
index 000000000000..4ba43328d99e
--- /dev/null
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
@@ -0,0 +1,3083 @@
+/*
+ * AMD 10Gb Ethernet driver
+ *
+ * This file is available to you under your choice of the following two
+ * licenses:
+ *
+ * License 1: GPLv2
+ *
+ * Copyright (c) 2016 Advanced Micro Devices, Inc.
+ *
+ * This file is free software; you may copy, redistribute and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * License 2: Modified BSD
+ *
+ * Copyright (c) 2016 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/kmod.h>
+#include <linux/mdio.h>
+#include <linux/phy.h>
+
+#include "xgbe.h"
+#include "xgbe-common.h"
+
+#define XGBE_PHY_PORT_SPEED_100         BIT(0)
+#define XGBE_PHY_PORT_SPEED_1000        BIT(1)
+#define XGBE_PHY_PORT_SPEED_2500        BIT(2)
+#define XGBE_PHY_PORT_SPEED_10000       BIT(3)
+
+#define XGBE_MUTEX_RELEASE              0x80000000
+
+#define XGBE_SFP_DIRECT                 7
+
+/* I2C target addresses */
+#define XGBE_SFP_SERIAL_ID_ADDRESS      0x50
+#define XGBE_SFP_DIAG_INFO_ADDRESS      0x51
+#define XGBE_SFP_PHY_ADDRESS            0x56
+#define XGBE_GPIO_ADDRESS_PCA9555       0x20
+
+/* SFP sideband signal indicators */
+#define XGBE_GPIO_NO_TX_FAULT           BIT(0)
+#define XGBE_GPIO_NO_RATE_SELECT        BIT(1)
+#define XGBE_GPIO_NO_MOD_ABSENT         BIT(2)
+#define XGBE_GPIO_NO_RX_LOS             BIT(3)
+
+/* Rate-change complete wait/retry count */
+#define XGBE_RATECHANGE_COUNT           500
+
+enum xgbe_port_mode {
+        XGBE_PORT_MODE_RSVD = 0,
+        XGBE_PORT_MODE_BACKPLANE,
+        XGBE_PORT_MODE_BACKPLANE_2500,
+        XGBE_PORT_MODE_1000BASE_T,
+        XGBE_PORT_MODE_1000BASE_X,
+        XGBE_PORT_MODE_NBASE_T,
+        XGBE_PORT_MODE_10GBASE_T,
+        XGBE_PORT_MODE_10GBASE_R,
+        XGBE_PORT_MODE_SFP,
+        XGBE_PORT_MODE_MAX,
+};
+
+enum xgbe_conn_type {
+        XGBE_CONN_TYPE_NONE = 0,
+        XGBE_CONN_TYPE_SFP,
+        XGBE_CONN_TYPE_MDIO,
+        XGBE_CONN_TYPE_BACKPLANE,
+        XGBE_CONN_TYPE_MAX,
+};
+
+/* SFP/SFP+ related definitions */
+enum xgbe_sfp_comm {
+        XGBE_SFP_COMM_DIRECT = 0,
+        XGBE_SFP_COMM_PCA9545,
+};
+
+enum xgbe_sfp_cable {
+        XGBE_SFP_CABLE_UNKNOWN = 0,
+        XGBE_SFP_CABLE_ACTIVE,
+        XGBE_SFP_CABLE_PASSIVE,
+};
+
+enum xgbe_sfp_base {
+        XGBE_SFP_BASE_UNKNOWN = 0,
+        XGBE_SFP_BASE_1000_T,
+        XGBE_SFP_BASE_1000_SX,
+        XGBE_SFP_BASE_1000_LX,
+        XGBE_SFP_BASE_1000_CX,
+        XGBE_SFP_BASE_10000_SR,
+        XGBE_SFP_BASE_10000_LR,
+        XGBE_SFP_BASE_10000_LRM,
+        XGBE_SFP_BASE_10000_ER,
+        XGBE_SFP_BASE_10000_CR,
+};
+
+enum xgbe_sfp_speed {
+        XGBE_SFP_SPEED_UNKNOWN = 0,
+        XGBE_SFP_SPEED_100_1000,
+        XGBE_SFP_SPEED_1000,
+        XGBE_SFP_SPEED_10000,
+};
+
+/* SFP Serial ID Base ID values relative to an offset of 0 */
+#define XGBE_SFP_BASE_ID                        0
+#define XGBE_SFP_ID_SFP                         0x03
+
+#define XGBE_SFP_BASE_EXT_ID                    1
+#define XGBE_SFP_EXT_ID_SFP                     0x04
+
+#define XGBE_SFP_BASE_10GBE_CC                  3
+#define XGBE_SFP_BASE_10GBE_CC_SR               BIT(4)
+#define XGBE_SFP_BASE_10GBE_CC_LR               BIT(5)
+#define XGBE_SFP_BASE_10GBE_CC_LRM              BIT(6)
+#define XGBE_SFP_BASE_10GBE_CC_ER               BIT(7)
+
+#define XGBE_SFP_BASE_1GBE_CC                   6
+#define XGBE_SFP_BASE_1GBE_CC_SX                BIT(0)
+#define XGBE_SFP_BASE_1GBE_CC_LX                BIT(1)
+#define XGBE_SFP_BASE_1GBE_CC_CX                BIT(2)
+#define XGBE_SFP_BASE_1GBE_CC_T                 BIT(3)
+
+#define XGBE_SFP_BASE_CABLE                     8
+#define XGBE_SFP_BASE_CABLE_PASSIVE             BIT(2)
+#define XGBE_SFP_BASE_CABLE_ACTIVE              BIT(3)
+
+#define XGBE_SFP_BASE_BR                        12
+#define XGBE_SFP_BASE_BR_1GBE_MIN               0x0a
+#define XGBE_SFP_BASE_BR_1GBE_MAX               0x0d
+#define XGBE_SFP_BASE_BR_10GBE_MIN              0x64
+#define XGBE_SFP_BASE_BR_10GBE_MAX              0x68
+
+#define XGBE_SFP_BASE_CU_CABLE_LEN              18
+
+#define XGBE_SFP_BASE_VENDOR_NAME               20
+#define XGBE_SFP_BASE_VENDOR_NAME_LEN           16
+#define XGBE_SFP_BASE_VENDOR_PN                 40
+#define XGBE_SFP_BASE_VENDOR_PN_LEN             16
+#define XGBE_SFP_BASE_VENDOR_REV                56
+#define XGBE_SFP_BASE_VENDOR_REV_LEN            4
+
+#define XGBE_SFP_BASE_CC                        63
+
+/* SFP Serial ID Extended ID values relative to an offset of 64 */
+#define XGBE_SFP_BASE_VENDOR_SN                 4
+#define XGBE_SFP_BASE_VENDOR_SN_LEN             16
+
+#define XGBE_SFP_EXTD_DIAG                      28
+#define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE          BIT(2)
+
+#define XGBE_SFP_EXTD_SFF_8472                  30
+
+#define XGBE_SFP_EXTD_CC                        31
+
+struct xgbe_sfp_eeprom {
+        u8 base[64];
+        u8 extd[32];
+        u8 vendor[32];
+};
+
+#define XGBE_BEL_FUSE_VENDOR    "BEL-FUSE        "
+#define XGBE_BEL_FUSE_PARTNO    "1GBT-SFP06      "
+
+struct xgbe_sfp_ascii {
+        union {
+                char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
+                char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
+                char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
+                char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
+        } u;
+};
+
+/* MDIO PHY reset types */
+enum xgbe_mdio_reset {
+        XGBE_MDIO_RESET_NONE = 0,
+        XGBE_MDIO_RESET_I2C_GPIO,
+        XGBE_MDIO_RESET_INT_GPIO,
+        XGBE_MDIO_RESET_MAX,
+};
+
+/* Re-driver related definitions */
+enum xgbe_phy_redrv_if {
+        XGBE_PHY_REDRV_IF_MDIO = 0,
+        XGBE_PHY_REDRV_IF_I2C,
+        XGBE_PHY_REDRV_IF_MAX,
+};
+
+enum xgbe_phy_redrv_model {
+        XGBE_PHY_REDRV_MODEL_4223 = 0,
+        XGBE_PHY_REDRV_MODEL_4227,
+        XGBE_PHY_REDRV_MODEL_MAX,
+};
+
+enum xgbe_phy_redrv_mode {
+        XGBE_PHY_REDRV_MODE_CX = 5,
+        XGBE_PHY_REDRV_MODE_SR = 9,
+};
+
+#define XGBE_PHY_REDRV_MODE_REG 0x12b0
+
+/* PHY related configuration information */
+struct xgbe_phy_data {
+        enum xgbe_port_mode port_mode;
+
+        unsigned int port_id;
+
+        unsigned int port_speeds;
+
+        enum xgbe_conn_type conn_type;
+
+        enum xgbe_mode cur_mode;
+        enum xgbe_mode start_mode;
+
+        unsigned int rrc_count;
+
+        unsigned int mdio_addr;
+
+        unsigned int comm_owned;
+
+        /* SFP Support */
+        enum xgbe_sfp_comm sfp_comm;
+        unsigned int sfp_mux_address;
+        unsigned int sfp_mux_channel;
+
+        unsigned int sfp_gpio_address;
+        unsigned int sfp_gpio_mask;
+        unsigned int sfp_gpio_rx_los;
+        unsigned int sfp_gpio_tx_fault;
+        unsigned int sfp_gpio_mod_absent;
+        unsigned int sfp_gpio_rate_select;
+
+        unsigned int sfp_rx_los;
+        unsigned int sfp_tx_fault;
+        unsigned int sfp_mod_absent;
+        unsigned int sfp_diags;
+        unsigned int sfp_changed;
+        unsigned int sfp_phy_avail;
+        unsigned int sfp_cable_len;
+        enum xgbe_sfp_base sfp_base;
+        enum xgbe_sfp_cable sfp_cable;
+        enum xgbe_sfp_speed sfp_speed;
+        struct xgbe_sfp_eeprom sfp_eeprom;
+
+        /* External PHY support */
+        enum xgbe_mdio_mode phydev_mode;
+        struct mii_bus *mii;
+        struct phy_device *phydev;
+        enum xgbe_mdio_reset mdio_reset;
+        unsigned int mdio_reset_addr;
+        unsigned int mdio_reset_gpio;
+
+        /* Re-driver support */
+        unsigned int redrv;
+        unsigned int redrv_if;
+        unsigned int redrv_addr;
+        unsigned int redrv_lane;
+        unsigned int redrv_model;
+};
+
+/* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
+static DEFINE_MUTEX(xgbe_phy_comm_lock);
+
+static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
+
+static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
+                             struct xgbe_i2c_op *i2c_op)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        /* Be sure we own the bus */
+        if (WARN_ON(!phy_data->comm_owned))
+                return -EIO;
+
+        return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
+}
+
+static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
+                                unsigned int val)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        struct xgbe_i2c_op i2c_op;
+        __be16 *redrv_val;
+        u8 redrv_data[5], csum;
+        unsigned int i, retry;
+        int ret;
+
+        /* High byte of register contains read/write indicator */
+        redrv_data[0] = ((reg >> 8) & 0xff) << 1;
+        redrv_data[1] = reg & 0xff;
+        redrv_val = (__be16 *)&redrv_data[2];
+        *redrv_val = cpu_to_be16(val);
+
+        /* Calculate 1 byte checksum */
+        csum = 0;
+        for (i = 0; i < 4; i++) {
+                csum += redrv_data[i];
+                if (redrv_data[i] > csum)
+                        csum++;
+        }
+        redrv_data[4] = ~csum;
+
+        retry = 1;
+again1:
+        i2c_op.cmd = XGBE_I2C_CMD_WRITE;
+        i2c_op.target = phy_data->redrv_addr;
+        i2c_op.len = sizeof(redrv_data);
+        i2c_op.buf = redrv_data;
+        ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
+        if (ret) {
+                if ((ret == -EAGAIN) && retry--)
+                        goto again1;
+
+                return ret;
+        }
+
+        retry = 1;
+again2:
+        i2c_op.cmd = XGBE_I2C_CMD_READ;
+        i2c_op.target = phy_data->redrv_addr;
+        i2c_op.len = 1;
+        i2c_op.buf = redrv_data;
+        ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
+        if (ret) {
+                if ((ret == -EAGAIN) && retry--)
+                        goto again2;
+
+                return ret;
+        }
+
+        if (redrv_data[0] != 0xff) {
+                netif_dbg(pdata, drv, pdata->netdev,
+                          "Redriver write checksum error\n");
+                ret = -EIO;
+        }
+
+        return ret;
+}
+
+static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
+                              void *val, unsigned int val_len)
+{
+        struct xgbe_i2c_op i2c_op;
+        int retry, ret;
+
+        retry = 1;
+again:
+        /* Write the specfied register */
+        i2c_op.cmd = XGBE_I2C_CMD_WRITE;
+        i2c_op.target = target;
+        i2c_op.len = val_len;
+        i2c_op.buf = val;
+        ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
+        if ((ret == -EAGAIN) && retry--)
+                goto again;
+
+        return ret;
+}
+
+static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
+                             void *reg, unsigned int reg_len,
+                             void *val, unsigned int val_len)
+{
+        struct xgbe_i2c_op i2c_op;
+        int retry, ret;
+
+        retry = 1;
+again1:
+        /* Set the specified register to read */
+        i2c_op.cmd = XGBE_I2C_CMD_WRITE;
+        i2c_op.target = target;
+        i2c_op.len = reg_len;
+        i2c_op.buf = reg;
+        ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
+        if (ret) {
+                if ((ret == -EAGAIN) && retry--)
+                        goto again1;
+
+                return ret;
+        }
+
+        retry = 1;
+again2:
+        /* Read the specfied register */
+        i2c_op.cmd = XGBE_I2C_CMD_READ;
+        i2c_op.target = target;
+        i2c_op.len = val_len;
+        i2c_op.buf = val;
+        ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
+        if ((ret == -EAGAIN) && retry--)
+                goto again2;
+
+        return ret;
+}
+
+static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        struct xgbe_i2c_op i2c_op;
+        u8 mux_channel;
+
+        if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
+                return 0;
+
+        /* Select no mux channels */
+        mux_channel = 0;
+        i2c_op.cmd = XGBE_I2C_CMD_WRITE;
+        i2c_op.target = phy_data->sfp_mux_address;
+        i2c_op.len = sizeof(mux_channel);
+        i2c_op.buf = &mux_channel;
+
+        return xgbe_phy_i2c_xfer(pdata, &i2c_op);
+}
+
+static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        struct xgbe_i2c_op i2c_op;
+        u8 mux_channel;
+
+        if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
+                return 0;
+
+        /* Select desired mux channel */
+        mux_channel = 1 << phy_data->sfp_mux_channel;
+        i2c_op.cmd = XGBE_I2C_CMD_WRITE;
+        i2c_op.target = phy_data->sfp_mux_address;
+        i2c_op.len = sizeof(mux_channel);
+        i2c_op.buf = &mux_channel;
+
+        return xgbe_phy_i2c_xfer(pdata, &i2c_op);
+}
+
+static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        phy_data->comm_owned = 0;
+
+        mutex_unlock(&xgbe_phy_comm_lock);
+}
+
+static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned long timeout;
+        unsigned int mutex_id;
+
+        if (phy_data->comm_owned)
+                return 0;
+
+        /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
+         * the driver needs to take the software mutex and then the hardware
+         * mutexes before being able to use the busses.
+         */
+        mutex_lock(&xgbe_phy_comm_lock);
+
+        /* Clear the mutexes */
+        XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
+        XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
+
+        /* Mutex formats are the same for I2C and MDIO/GPIO */
+        mutex_id = 0;
+        XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
+        XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
+
+        timeout = jiffies + (5 * HZ);
+        while (time_before(jiffies, timeout)) {
+                /* Must be all zeroes in order to obtain the mutex */
+                if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
+                    XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
+                        usleep_range(100, 200);
+                        continue;
+                }
+
+                /* Obtain the mutex */
+                XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
+                XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
+
+                phy_data->comm_owned = 1;
+                return 0;
+        }
+
+        mutex_unlock(&xgbe_phy_comm_lock);
+
+        netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
+
+        return -ETIMEDOUT;
+}
+
+static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
+                                   int reg, u16 val)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        if (reg & MII_ADDR_C45) {
+                if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
+                        return -ENOTSUPP;
+        } else {
+                if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
+                        return -ENOTSUPP;
+        }
+
+        return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
+}
+
+static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
+{
+        __be16 *mii_val;
+        u8 mii_data[3];
+        int ret;
+
+        ret = xgbe_phy_sfp_get_mux(pdata);
+        if (ret)
+                return ret;
+
+        mii_data[0] = reg & 0xff;
+        mii_val = (__be16 *)&mii_data[1];
+        *mii_val = cpu_to_be16(val);
+
+        ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
+                                 mii_data, sizeof(mii_data));
+
+        xgbe_phy_sfp_put_mux(pdata);
+
+        return ret;
+}
+
+static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
+{
+        struct xgbe_prv_data *pdata = mii->priv;
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        int ret;
+
+        ret = xgbe_phy_get_comm_ownership(pdata);
+        if (ret)
+                return ret;
+
+        if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
+                ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
+        else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
+                ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
+        else
+                ret = -ENOTSUPP;
+
+        xgbe_phy_put_comm_ownership(pdata);
+
+        return ret;
+}
+
+static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
+                                  int reg)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        if (reg & MII_ADDR_C45) {
+                if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
+                        return -ENOTSUPP;
+        } else {
+                if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
+                        return -ENOTSUPP;
+        }
+
+        return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
+}
+
+static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
+{
+        __be16 mii_val;
+        u8 mii_reg;
+        int ret;
+
+        ret = xgbe_phy_sfp_get_mux(pdata);
+        if (ret)
+                return ret;
+
+        mii_reg = reg;
+        ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
+                                &mii_reg, sizeof(mii_reg),
+                                &mii_val, sizeof(mii_val));
+        if (!ret)
+                ret = be16_to_cpu(mii_val);
+
+        xgbe_phy_sfp_put_mux(pdata);
+
+        return ret;
+}
+
+static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
+{
+        struct xgbe_prv_data *pdata = mii->priv;
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        int ret;
+
+        ret = xgbe_phy_get_comm_ownership(pdata);
+        if (ret)
+                return ret;
+
+        if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
+                ret = xgbe_phy_i2c_mii_read(pdata, reg);
+        else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
+                ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
+        else
+                ret = -ENOTSUPP;
+
+        xgbe_phy_put_comm_ownership(pdata);
+
+        return ret;
+}
+
+static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        if (phy_data->sfp_mod_absent) {
+                pdata->phy.speed = SPEED_UNKNOWN;
+                pdata->phy.duplex = DUPLEX_UNKNOWN;
+                pdata->phy.autoneg = AUTONEG_ENABLE;
+                pdata->phy.advertising = pdata->phy.supported;
+        }
+
+        pdata->phy.advertising &= ~ADVERTISED_Autoneg;
+        pdata->phy.advertising &= ~ADVERTISED_TP;
+        pdata->phy.advertising &= ~ADVERTISED_FIBRE;
+        pdata->phy.advertising &= ~ADVERTISED_100baseT_Full;
+        pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full;
+        pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full;
+        pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC;
+
+        switch (phy_data->sfp_base) {
+        case XGBE_SFP_BASE_1000_T:
+        case XGBE_SFP_BASE_1000_SX:
+        case XGBE_SFP_BASE_1000_LX:
+        case XGBE_SFP_BASE_1000_CX:
+                pdata->phy.speed = SPEED_UNKNOWN;
+                pdata->phy.duplex = DUPLEX_UNKNOWN;
+                pdata->phy.autoneg = AUTONEG_ENABLE;
+                pdata->phy.advertising |= ADVERTISED_Autoneg;
+                break;
+        case XGBE_SFP_BASE_10000_SR:
+        case XGBE_SFP_BASE_10000_LR:
+        case XGBE_SFP_BASE_10000_LRM:
+        case XGBE_SFP_BASE_10000_ER:
+        case XGBE_SFP_BASE_10000_CR:
+        default:
+                pdata->phy.speed = SPEED_10000;
+                pdata->phy.duplex = DUPLEX_FULL;
+                pdata->phy.autoneg = AUTONEG_DISABLE;
+                break;
+        }
+
+        switch (phy_data->sfp_base) {
+        case XGBE_SFP_BASE_1000_T:
+        case XGBE_SFP_BASE_1000_CX:
+        case XGBE_SFP_BASE_10000_CR:
+                pdata->phy.advertising |= ADVERTISED_TP;
+                break;
+        default:
+                pdata->phy.advertising |= ADVERTISED_FIBRE;
+        }
+
+        switch (phy_data->sfp_speed) {
+        case XGBE_SFP_SPEED_100_1000:
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
+                        pdata->phy.advertising |= ADVERTISED_100baseT_Full;
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
+                        pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
+                break;
+        case XGBE_SFP_SPEED_1000:
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
+                        pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
+                break;
+        case XGBE_SFP_SPEED_10000:
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
+                        pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
+                break;
+        default:
+                /* Choose the fastest supported speed */
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
+                        pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
+                else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
+                        pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
+                else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
+                        pdata->phy.advertising |= ADVERTISED_100baseT_Full;
+        }
+}
+
+static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
+                                  enum xgbe_sfp_speed sfp_speed)
+{
+        u8 *sfp_base, min, max;
+
+        sfp_base = sfp_eeprom->base;
+
+        switch (sfp_speed) {
+        case XGBE_SFP_SPEED_1000:
+                min = XGBE_SFP_BASE_BR_1GBE_MIN;
+                max = XGBE_SFP_BASE_BR_1GBE_MAX;
+                break;
+        case XGBE_SFP_SPEED_10000:
+                min = XGBE_SFP_BASE_BR_10GBE_MIN;
+                max = XGBE_SFP_BASE_BR_10GBE_MAX;
+                break;
+        default:
+                return false;
+        }
+
+        return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
+                (sfp_base[XGBE_SFP_BASE_BR] <= max));
+}
+
+static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        if (phy_data->phydev) {
+                phy_detach(phy_data->phydev);
+                phy_device_remove(phy_data->phydev);
+                phy_device_free(phy_data->phydev);
+                phy_data->phydev = NULL;
+        }
+}
+
+static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int phy_id = phy_data->phydev->phy_id;
+
+        if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
+                return false;
+
+        /* Enable Base-T AN */
+        phy_write(phy_data->phydev, 0x16, 0x0001);
+        phy_write(phy_data->phydev, 0x00, 0x9140);
+        phy_write(phy_data->phydev, 0x16, 0x0000);
+
+        /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
+        phy_write(phy_data->phydev, 0x1b, 0x9084);
+        phy_write(phy_data->phydev, 0x09, 0x0e00);
+        phy_write(phy_data->phydev, 0x00, 0x8140);
+        phy_write(phy_data->phydev, 0x04, 0x0d01);
+        phy_write(phy_data->phydev, 0x00, 0x9140);
+
+        phy_data->phydev->supported = PHY_GBIT_FEATURES;
+        phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
+        phy_data->phydev->advertising = phy_data->phydev->supported;
+
+        netif_dbg(pdata, drv, pdata->netdev,
+                  "Finisar PHY quirk in place\n");
+
+        return true;
+}
+
+static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
+{
+        if (xgbe_phy_finisar_phy_quirks(pdata))
+                return;
+}
+
+static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        struct phy_device *phydev;
+        int ret;
+
+        /* If we already have a PHY, just return */
+        if (phy_data->phydev)
+                return 0;
+
+        /* Check for the use of an external PHY */
+        if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
+                return 0;
+
+        /* For SFP, only use an external PHY if available */
+        if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
+            !phy_data->sfp_phy_avail)
+                return 0;
+
+        /* Create and connect to the PHY device */
+        phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
+                                (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
+        if (IS_ERR(phydev)) {
+                netdev_err(pdata->netdev, "get_phy_device failed\n");
+                return -ENODEV;
+        }
+        netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
+                  phydev->phy_id);
+
+        /*TODO: If c45, add request_module based on one of the MMD ids? */
+
+        ret = phy_device_register(phydev);
+        if (ret) {
+                netdev_err(pdata->netdev, "phy_device_register failed\n");
+                phy_device_free(phydev);
+                return ret;
+        }
+
+        ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
+                                PHY_INTERFACE_MODE_SGMII);
+        if (ret) {
+                netdev_err(pdata->netdev, "phy_attach_direct failed\n");
+                phy_device_remove(phydev);
+                phy_device_free(phydev);
+                return ret;
+        }
+        phy_data->phydev = phydev;
+
+        xgbe_phy_external_phy_quirks(pdata);
+        phydev->advertising &= pdata->phy.advertising;
+
+        phy_start_aneg(phy_data->phydev);
+
+        return 0;
+}
+
+static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        int ret;
+
+        if (!phy_data->sfp_changed)
+                return;
+
+        phy_data->sfp_phy_avail = 0;
+
+        if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
+                return;
+
+        /* Check access to the PHY by reading CTRL1 */
+        ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
+        if (ret < 0)
+                return;
+
+        /* Successfully accessed the PHY */
+        phy_data->sfp_phy_avail = 1;
+}
+
+static bool xgbe_phy_belfuse_parse_quirks(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
+
+        if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
+                   XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
+                return false;
+
+        if (!memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
+                    XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) {
+                phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
+                phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
+                phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
+                if (phy_data->sfp_changed)
+                        netif_dbg(pdata, drv, pdata->netdev,
+                                  "Bel-Fuse SFP quirk in place\n");
+                return true;
+        }
+
+        return false;
+}
+
+static bool xgbe_phy_sfp_parse_quirks(struct xgbe_prv_data *pdata)
+{
+        if (xgbe_phy_belfuse_parse_quirks(pdata))
+                return true;
+
+        return false;
+}
+
+static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
+        u8 *sfp_base;
+
+        sfp_base = sfp_eeprom->base;
+
+        if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
+                return;
+
+        if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
+                return;
+
+        if (xgbe_phy_sfp_parse_quirks(pdata))
+                return;
+
+        /* Assume ACTIVE cable unless told it is PASSIVE */
+        if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
+                phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
+                phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
+        } else {
+                phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
+        }
+
+        /* Determine the type of SFP */
+        if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
+                phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
+        else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
+                phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
+        else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
+                phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
+        else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
+                phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
+        else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
+                phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
+        else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
+                phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
+        else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
+                phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
+        else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
+                phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
+        else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
+                 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
+                phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
+
+        switch (phy_data->sfp_base) {
+        case XGBE_SFP_BASE_1000_T:
+                phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
+                break;
+        case XGBE_SFP_BASE_1000_SX:
+        case XGBE_SFP_BASE_1000_LX:
+        case XGBE_SFP_BASE_1000_CX:
+                phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
+                break;
+        case XGBE_SFP_BASE_10000_SR:
+        case XGBE_SFP_BASE_10000_LR:
+        case XGBE_SFP_BASE_10000_LRM:
+        case XGBE_SFP_BASE_10000_ER:
+        case XGBE_SFP_BASE_10000_CR:
+                phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
+                break;
+        default:
+                break;
+        }
+}
+
+static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
+                                     struct xgbe_sfp_eeprom *sfp_eeprom)
+{
+        struct xgbe_sfp_ascii sfp_ascii;
+        char *sfp_data = (char *)&sfp_ascii;
+
+        netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
+        memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
+               XGBE_SFP_BASE_VENDOR_NAME_LEN);
+        sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
+        netif_dbg(pdata, drv, pdata->netdev, "  vendor:         %s\n",
+                  sfp_data);
+
+        memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
+               XGBE_SFP_BASE_VENDOR_PN_LEN);
+        sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
+        netif_dbg(pdata, drv, pdata->netdev, "  part number:    %s\n",
+                  sfp_data);
+
+        memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
+               XGBE_SFP_BASE_VENDOR_REV_LEN);
+        sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
+        netif_dbg(pdata, drv, pdata->netdev, "  revision level: %s\n",
+                  sfp_data);
+
+        memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
+               XGBE_SFP_BASE_VENDOR_SN_LEN);
+        sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
+        netif_dbg(pdata, drv, pdata->netdev, "  serial number:  %s\n",
+                  sfp_data);
+}
+
+static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
+{
+        u8 cc;
+
+        for (cc = 0; len; buf++, len--)
+                cc += *buf;
+
+        return (cc == cc_in) ? true : false;
+}
+
+static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        struct xgbe_sfp_eeprom sfp_eeprom;
+        u8 eeprom_addr;
+        int ret;
+
+        ret = xgbe_phy_sfp_get_mux(pdata);
+        if (ret) {
+                netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
+                return ret;
+        }
+
+        /* Read the SFP serial ID eeprom */
+        eeprom_addr = 0;
+        ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
+                                &eeprom_addr, sizeof(eeprom_addr),
+                                &sfp_eeprom, sizeof(sfp_eeprom));
+        if (ret) {
+                netdev_err(pdata->netdev, "I2C error reading SFP EEPROM\n");
+                goto put;
+        }
+
+        /* Validate the contents read */
+        if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
+                                        sfp_eeprom.base,
+                                        sizeof(sfp_eeprom.base) - 1)) {
+                ret = -EINVAL;
+                goto put;
+        }
+
+        if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
+                                        sfp_eeprom.extd,
+                                        sizeof(sfp_eeprom.extd) - 1)) {
+                ret = -EINVAL;
+                goto put;
+        }
+
+        /* Check for an added or changed SFP */
+        if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
+                phy_data->sfp_changed = 1;
+
+                if (netif_msg_drv(pdata))
+                        xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
+
+                memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
+
+                if (sfp_eeprom.extd[XGBE_SFP_EXTD_SFF_8472]) {
+                        u8 diag_type = sfp_eeprom.extd[XGBE_SFP_EXTD_DIAG];
+
+                        if (!(diag_type & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
+                                phy_data->sfp_diags = 1;
+                }
+
+                xgbe_phy_free_phy_device(pdata);
+        } else {
+                phy_data->sfp_changed = 0;
+        }
+
+put:
+        xgbe_phy_sfp_put_mux(pdata);
+
+        return ret;
+}
+
+static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int gpio_input;
+        u8 gpio_reg, gpio_ports[2];
+        int ret;
+
+        /* Read the input port registers */
+        gpio_reg = 0;
+        ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
+                                &gpio_reg, sizeof(gpio_reg),
+                                gpio_ports, sizeof(gpio_ports));
+        if (ret) {
+                netdev_err(pdata->netdev, "I2C error reading SFP GPIOs\n");
+                return;
+        }
+
+        gpio_input = (gpio_ports[1] << 8) | gpio_ports[0];
+
+        if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) {
+                /* No GPIO, just assume the module is present for now */
+                phy_data->sfp_mod_absent = 0;
+        } else {
+                if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent)))
+                        phy_data->sfp_mod_absent = 0;
+        }
+
+        if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) &&
+            (gpio_input & (1 << phy_data->sfp_gpio_rx_los)))
+                phy_data->sfp_rx_los = 1;
+
+        if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) &&
+            (gpio_input & (1 << phy_data->sfp_gpio_tx_fault)))
+                phy_data->sfp_tx_fault = 1;
+}
+
+static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        xgbe_phy_free_phy_device(pdata);
+
+        phy_data->sfp_mod_absent = 1;
+        phy_data->sfp_phy_avail = 0;
+        memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
+}
+
+static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
+{
+        phy_data->sfp_rx_los = 0;
+        phy_data->sfp_tx_fault = 0;
+        phy_data->sfp_mod_absent = 1;
+        phy_data->sfp_diags = 0;
+        phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
+        phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
+        phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
+}
+
+static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        int ret;
+
+        /* Reset the SFP signals and info */
+        xgbe_phy_sfp_reset(phy_data);
+
+        ret = xgbe_phy_get_comm_ownership(pdata);
+        if (ret)
+                return;
+
+        /* Read the SFP signals and check for module presence */
+        xgbe_phy_sfp_signals(pdata);
+        if (phy_data->sfp_mod_absent) {
+                xgbe_phy_sfp_mod_absent(pdata);
+                goto put;
+        }
+
+        ret = xgbe_phy_sfp_read_eeprom(pdata);
+        if (ret) {
+                /* Treat any error as if there isn't an SFP plugged in */
+                xgbe_phy_sfp_reset(phy_data);
+                xgbe_phy_sfp_mod_absent(pdata);
+                goto put;
+        }
+
+        xgbe_phy_sfp_parse_eeprom(pdata);
+
+        xgbe_phy_sfp_external_phy(pdata);
+
+put:
+        xgbe_phy_sfp_phy_settings(pdata);
+
+        xgbe_phy_put_comm_ownership(pdata);
+}
+
+static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        u16 lcl_adv = 0, rmt_adv = 0;
+        u8 fc;
+
+        pdata->phy.tx_pause = 0;
+        pdata->phy.rx_pause = 0;
+
+        if (!phy_data->phydev)
+                return;
+
+        if (phy_data->phydev->advertising & ADVERTISED_Pause)
+                lcl_adv |= ADVERTISE_PAUSE_CAP;
+        if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause)
+                lcl_adv |= ADVERTISE_PAUSE_ASYM;
+
+        if (phy_data->phydev->pause) {
+                pdata->phy.lp_advertising |= ADVERTISED_Pause;
+                rmt_adv |= LPA_PAUSE_CAP;
+        }
+        if (phy_data->phydev->asym_pause) {
+                pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
+                rmt_adv |= LPA_PAUSE_ASYM;
+        }
+
+        fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+        if (fc & FLOW_CTRL_TX)
+                pdata->phy.tx_pause = 1;
+        if (fc & FLOW_CTRL_RX)
+                pdata->phy.rx_pause = 1;
+}
+
+static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
+{
+        enum xgbe_mode mode;
+
+        pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
+        pdata->phy.lp_advertising |= ADVERTISED_TP;
+
+        /* Use external PHY to determine flow control */
+        if (pdata->phy.pause_autoneg)
+                xgbe_phy_phydev_flowctrl(pdata);
+
+        switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
+        case XGBE_SGMII_AN_LINK_SPEED_100:
+                if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
+                        pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full;
+                        mode = XGBE_MODE_SGMII_100;
+                } else {
+                        /* Half-duplex not supported */
+                        pdata->phy.lp_advertising |= ADVERTISED_100baseT_Half;
+                        mode = XGBE_MODE_UNKNOWN;
+                }
+                break;
+        case XGBE_SGMII_AN_LINK_SPEED_1000:
+                if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
+                        pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
+                        mode = XGBE_MODE_SGMII_1000;
+                } else {
+                        /* Half-duplex not supported */
+                        pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half;
+                        mode = XGBE_MODE_UNKNOWN;
+                }
+                break;
+        default:
+                mode = XGBE_MODE_UNKNOWN;
+        }
+
+        return mode;
+}
+
+static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
+{
+        enum xgbe_mode mode;
+        unsigned int ad_reg, lp_reg;
+
+        pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
+        pdata->phy.lp_advertising |= ADVERTISED_FIBRE;
+
+        /* Compare Advertisement and Link Partner register */
+        ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
+        lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
+        if (lp_reg & 0x100)
+                pdata->phy.lp_advertising |= ADVERTISED_Pause;
+        if (lp_reg & 0x80)
+                pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
+
+        if (pdata->phy.pause_autoneg) {
+                /* Set flow control based on auto-negotiation result */
+                pdata->phy.tx_pause = 0;
+                pdata->phy.rx_pause = 0;
+
+                if (ad_reg & lp_reg & 0x100) {
+                        pdata->phy.tx_pause = 1;
+                        pdata->phy.rx_pause = 1;
+                } else if (ad_reg & lp_reg & 0x80) {
+                        if (ad_reg & 0x100)
+                                pdata->phy.rx_pause = 1;
+                        else if (lp_reg & 0x100)
+                                pdata->phy.tx_pause = 1;
+                }
+        }
+
+        if (lp_reg & 0x40)
+                pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half;
+        if (lp_reg & 0x20)
+                pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
+
+        /* Half duplex is not supported */
+        ad_reg &= lp_reg;
+        mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
+
+        return mode;
+}
+
+static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        enum xgbe_mode mode;
+        unsigned int ad_reg, lp_reg;
+
+        pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
+        pdata->phy.lp_advertising |= ADVERTISED_Backplane;
+
+        /* Use external PHY to determine flow control */
+        if (pdata->phy.pause_autoneg)
+                xgbe_phy_phydev_flowctrl(pdata);
+
+        /* Compare Advertisement and Link Partner register 2 */
+        ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
+        lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
+        if (lp_reg & 0x80)
+                pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
+        if (lp_reg & 0x20)
+                pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
+
+        ad_reg &= lp_reg;
+        if (ad_reg & 0x80) {
+                switch (phy_data->port_mode) {
+                case XGBE_PORT_MODE_BACKPLANE:
+                        mode = XGBE_MODE_KR;
+                        break;
+                default:
+                        mode = XGBE_MODE_SFI;
+                        break;
+                }
+        } else if (ad_reg & 0x20) {
+                switch (phy_data->port_mode) {
+                case XGBE_PORT_MODE_BACKPLANE:
+                        mode = XGBE_MODE_KX_1000;
+                        break;
+                case XGBE_PORT_MODE_1000BASE_X:
+                        mode = XGBE_MODE_X;
+                        break;
+                case XGBE_PORT_MODE_SFP:
+                        switch (phy_data->sfp_base) {
+                        case XGBE_SFP_BASE_1000_T:
+                                if (phy_data->phydev &&
+                                    (phy_data->phydev->speed == SPEED_100))
+                                        mode = XGBE_MODE_SGMII_100;
+                                else
+                                        mode = XGBE_MODE_SGMII_1000;
+                                break;
+                        case XGBE_SFP_BASE_1000_SX:
+                        case XGBE_SFP_BASE_1000_LX:
+                        case XGBE_SFP_BASE_1000_CX:
+                        default:
+                                mode = XGBE_MODE_X;
+                                break;
+                        }
+                        break;
+                default:
+                        if (phy_data->phydev &&
+                            (phy_data->phydev->speed == SPEED_100))
+                                mode = XGBE_MODE_SGMII_100;
+                        else
+                                mode = XGBE_MODE_SGMII_1000;
+                        break;
+                }
+        } else {
+                mode = XGBE_MODE_UNKNOWN;
+        }
+
+        /* Compare Advertisement and Link Partner register 3 */
+        ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
+        lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
+        if (lp_reg & 0xc000)
+                pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
+
+        return mode;
+}
+
+static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
+{
+        enum xgbe_mode mode;
+        unsigned int ad_reg, lp_reg;
+
+        pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
+        pdata->phy.lp_advertising |= ADVERTISED_Backplane;
+
+        /* Compare Advertisement and Link Partner register 1 */
+        ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
+        lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
+        if (lp_reg & 0x400)
+                pdata->phy.lp_advertising |= ADVERTISED_Pause;
+        if (lp_reg & 0x800)
+                pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
+
+        if (pdata->phy.pause_autoneg) {
+                /* Set flow control based on auto-negotiation result */
+                pdata->phy.tx_pause = 0;
+                pdata->phy.rx_pause = 0;
+
+                if (ad_reg & lp_reg & 0x400) {
+                        pdata->phy.tx_pause = 1;
+                        pdata->phy.rx_pause = 1;
+                } else if (ad_reg & lp_reg & 0x800) {
+                        if (ad_reg & 0x400)
+                                pdata->phy.rx_pause = 1;
+                        else if (lp_reg & 0x400)
+                                pdata->phy.tx_pause = 1;
+                }
+        }
+
+        /* Compare Advertisement and Link Partner register 2 */
+        ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
+        lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
+        if (lp_reg & 0x80)
+                pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
+        if (lp_reg & 0x20)
+                pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
+
+        ad_reg &= lp_reg;
+        if (ad_reg & 0x80)
+                mode = XGBE_MODE_KR;
+        else if (ad_reg & 0x20)
+                mode = XGBE_MODE_KX_1000;
+        else
+                mode = XGBE_MODE_UNKNOWN;
+
+        /* Compare Advertisement and Link Partner register 3 */
+        ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
+        lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
+        if (lp_reg & 0xc000)
+                pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
+
+        return mode;
+}
+
+static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
+{
+        switch (pdata->an_mode) {
+        case XGBE_AN_MODE_CL73:
+                return xgbe_phy_an73_outcome(pdata);
+        case XGBE_AN_MODE_CL73_REDRV:
+                return xgbe_phy_an73_redrv_outcome(pdata);
+        case XGBE_AN_MODE_CL37:
+                return xgbe_phy_an37_outcome(pdata);
+        case XGBE_AN_MODE_CL37_SGMII:
+                return xgbe_phy_an37_sgmii_outcome(pdata);
+        default:
+                return XGBE_MODE_UNKNOWN;
+        }
+}
+
+static unsigned int xgbe_phy_an_advertising(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int advertising;
+
+        /* Without a re-driver, just return current advertising */
+        if (!phy_data->redrv)
+                return pdata->phy.advertising;
+
+        /* With the KR re-driver we need to advertise a single speed */
+        advertising = pdata->phy.advertising;
+        advertising &= ~ADVERTISED_1000baseKX_Full;
+        advertising &= ~ADVERTISED_10000baseKR_Full;
+
+        switch (phy_data->port_mode) {
+        case XGBE_PORT_MODE_BACKPLANE:
+                advertising |= ADVERTISED_10000baseKR_Full;
+                break;
+        case XGBE_PORT_MODE_BACKPLANE_2500:
+                advertising |= ADVERTISED_1000baseKX_Full;
+                break;
+        case XGBE_PORT_MODE_1000BASE_T:
+        case XGBE_PORT_MODE_1000BASE_X:
+        case XGBE_PORT_MODE_NBASE_T:
+                advertising |= ADVERTISED_1000baseKX_Full;
+                break;
+        case XGBE_PORT_MODE_10GBASE_T:
+                if (phy_data->phydev &&
+                    (phy_data->phydev->speed == SPEED_10000))
+                        advertising |= ADVERTISED_10000baseKR_Full;
+                else
+                        advertising |= ADVERTISED_1000baseKX_Full;
+                break;
+        case XGBE_PORT_MODE_10GBASE_R:
+                advertising |= ADVERTISED_10000baseKR_Full;
+                break;
+        case XGBE_PORT_MODE_SFP:
+                switch (phy_data->sfp_base) {
+                case XGBE_SFP_BASE_1000_T:
+                case XGBE_SFP_BASE_1000_SX:
+                case XGBE_SFP_BASE_1000_LX:
+                case XGBE_SFP_BASE_1000_CX:
+                        advertising |= ADVERTISED_1000baseKX_Full;
+                        break;
+                default:
+                        advertising |= ADVERTISED_10000baseKR_Full;
+                        break;
+                }
+                break;
+        default:
+                advertising |= ADVERTISED_10000baseKR_Full;
+                break;
+        }
+
+        return advertising;
+}
+
+static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        int ret;
+
+        ret = xgbe_phy_find_phy_device(pdata);
+        if (ret)
+                return ret;
+
+        if (!phy_data->phydev)
+                return 0;
+
+        phy_data->phydev->autoneg = pdata->phy.autoneg;
+        phy_data->phydev->advertising = phy_data->phydev->supported &
+                                        pdata->phy.advertising;
+
+        if (pdata->phy.autoneg != AUTONEG_ENABLE) {
+                phy_data->phydev->speed = pdata->phy.speed;
+                phy_data->phydev->duplex = pdata->phy.duplex;
+        }
+
+        ret = phy_start_aneg(phy_data->phydev);
+
+        return ret;
+}
+
+static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
+{
+        switch (phy_data->sfp_base) {
+        case XGBE_SFP_BASE_1000_T:
+                return XGBE_AN_MODE_CL37_SGMII;
+        case XGBE_SFP_BASE_1000_SX:
+        case XGBE_SFP_BASE_1000_LX:
+        case XGBE_SFP_BASE_1000_CX:
+                return XGBE_AN_MODE_CL37;
+        default:
+                return XGBE_AN_MODE_NONE;
+        }
+}
+
+static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        /* A KR re-driver will always require CL73 AN */
+        if (phy_data->redrv)
+                return XGBE_AN_MODE_CL73_REDRV;
+
+        switch (phy_data->port_mode) {
+        case XGBE_PORT_MODE_BACKPLANE:
+                return XGBE_AN_MODE_CL73;
+        case XGBE_PORT_MODE_BACKPLANE_2500:
+                return XGBE_AN_MODE_NONE;
+        case XGBE_PORT_MODE_1000BASE_T:
+                return XGBE_AN_MODE_CL37_SGMII;
+        case XGBE_PORT_MODE_1000BASE_X:
+                return XGBE_AN_MODE_CL37;
+        case XGBE_PORT_MODE_NBASE_T:
+                return XGBE_AN_MODE_CL37_SGMII;
+        case XGBE_PORT_MODE_10GBASE_T:
+                return XGBE_AN_MODE_CL73;
+        case XGBE_PORT_MODE_10GBASE_R:
+                return XGBE_AN_MODE_NONE;
+        case XGBE_PORT_MODE_SFP:
+                return xgbe_phy_an_sfp_mode(phy_data);
+        default:
+                return XGBE_AN_MODE_NONE;
+        }
+}
+
+static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
+                                        enum xgbe_phy_redrv_mode mode)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        u16 redrv_reg, redrv_val;
+
+        redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
+        redrv_val = (u16)mode;
+
+        return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
+                                               redrv_reg, redrv_val);
+}
+
+static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
+                                       enum xgbe_phy_redrv_mode mode)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int redrv_reg;
+        int ret;
+
+        /* Calculate the register to write */
+        redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
+
+        ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
+
+        return ret;
+}
+
+static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        enum xgbe_phy_redrv_mode mode;
+        int ret;
+
+        if (!phy_data->redrv)
+                return;
+
+        mode = XGBE_PHY_REDRV_MODE_CX;
+        if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
+            (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
+            (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
+                mode = XGBE_PHY_REDRV_MODE_SR;
+
+        ret = xgbe_phy_get_comm_ownership(pdata);
+        if (ret)
+                return;
+
+        if (phy_data->redrv_if)
+                xgbe_phy_set_redrv_mode_i2c(pdata, mode);
+        else
+                xgbe_phy_set_redrv_mode_mdio(pdata, mode);
+
+        xgbe_phy_put_comm_ownership(pdata);
+}
+
+static void xgbe_phy_start_ratechange(struct xgbe_prv_data *pdata)
+{
+        if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
+                return;
+
+        /* Log if a previous command did not complete */
+        netif_dbg(pdata, link, pdata->netdev,
+                  "firmware mailbox not ready for command\n");
+}
+
+static void xgbe_phy_complete_ratechange(struct xgbe_prv_data *pdata)
+{
+        unsigned int wait;
+
+        /* Wait for command to complete */
+        wait = XGBE_RATECHANGE_COUNT;
+        while (wait--) {
+                if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
+                        return;
+
+                usleep_range(1000, 2000);
+        }
+
+        netif_dbg(pdata, link, pdata->netdev,
+                  "firmware mailbox command did not complete\n");
+}
+
+static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
+{
+        unsigned int s0;
+
+        xgbe_phy_start_ratechange(pdata);
+
+        /* Receiver Reset Cycle */
+        s0 = 0;
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
+
+        /* Call FW to make the change */
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+        XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+
+        xgbe_phy_complete_ratechange(pdata);
+
+        netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
+}
+
+static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        xgbe_phy_start_ratechange(pdata);
+
+        /* Call FW to make the change */
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+        XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+
+        xgbe_phy_complete_ratechange(pdata);
+
+        phy_data->cur_mode = XGBE_MODE_UNKNOWN;
+
+        netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
+}
+
+static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int s0;
+
+        xgbe_phy_set_redrv_mode(pdata);
+
+        xgbe_phy_start_ratechange(pdata);
+
+        /* 10G/SFI */
+        s0 = 0;
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
+        if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
+                XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
+        } else {
+                if (phy_data->sfp_cable_len <= 1)
+                        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
+                else if (phy_data->sfp_cable_len <= 3)
+                        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
+                else if (phy_data->sfp_cable_len <= 5)
+                        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
+                else
+                        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
+        }
+
+        /* Call FW to make the change */
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+        XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+
+        xgbe_phy_complete_ratechange(pdata);
+
+        phy_data->cur_mode = XGBE_MODE_SFI;
+
+        netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
+}
+
+static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int s0;
+
+        xgbe_phy_set_redrv_mode(pdata);
+
+        xgbe_phy_start_ratechange(pdata);
+
+        /* 1G/X */
+        s0 = 0;
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
+
+        /* Call FW to make the change */
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+        XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+
+        xgbe_phy_complete_ratechange(pdata);
+
+        phy_data->cur_mode = XGBE_MODE_X;
+
+        netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
+}
+
+static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int s0;
+
+        xgbe_phy_set_redrv_mode(pdata);
+
+        xgbe_phy_start_ratechange(pdata);
+
+        /* 1G/SGMII */
+        s0 = 0;
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
+
+        /* Call FW to make the change */
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+        XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+
+        xgbe_phy_complete_ratechange(pdata);
+
+        phy_data->cur_mode = XGBE_MODE_SGMII_1000;
+
+        netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
+}
+
+static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int s0;
+
+        xgbe_phy_set_redrv_mode(pdata);
+
+        xgbe_phy_start_ratechange(pdata);
+
+        /* 1G/SGMII */
+        s0 = 0;
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
+
+        /* Call FW to make the change */
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+        XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+
+        xgbe_phy_complete_ratechange(pdata);
+
+        phy_data->cur_mode = XGBE_MODE_SGMII_100;
+
+        netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
+}
+
+static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int s0;
+
+        xgbe_phy_set_redrv_mode(pdata);
+
+        xgbe_phy_start_ratechange(pdata);
+
+        /* 10G/KR */
+        s0 = 0;
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4);
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
+
+        /* Call FW to make the change */
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+        XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+
+        xgbe_phy_complete_ratechange(pdata);
+
+        phy_data->cur_mode = XGBE_MODE_KR;
+
+        netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
+}
+
+static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int s0;
+
+        xgbe_phy_set_redrv_mode(pdata);
+
+        xgbe_phy_start_ratechange(pdata);
+
+        /* 2.5G/KX */
+        s0 = 0;
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2);
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
+
+        /* Call FW to make the change */
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+        XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+
+        xgbe_phy_complete_ratechange(pdata);
+
+        phy_data->cur_mode = XGBE_MODE_KX_2500;
+
+        netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
+}
+
+static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int s0;
+
+        xgbe_phy_set_redrv_mode(pdata);
+
+        xgbe_phy_start_ratechange(pdata);
+
+        /* 1G/KX */
+        s0 = 0;
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
+        XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
+
+        /* Call FW to make the change */
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+        XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+        XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+
+        xgbe_phy_complete_ratechange(pdata);
+
+        phy_data->cur_mode = XGBE_MODE_KX_1000;
+
+        netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
+}
+
+static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        return phy_data->cur_mode;
+}
+
+static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        /* No switching if not 10GBase-T */
+        if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
+                return xgbe_phy_cur_mode(pdata);
+
+        switch (xgbe_phy_cur_mode(pdata)) {
+        case XGBE_MODE_SGMII_100:
+        case XGBE_MODE_SGMII_1000:
+                return XGBE_MODE_KR;
+        case XGBE_MODE_KR:
+        default:
+                return XGBE_MODE_SGMII_1000;
+        }
+}
+
+static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
+{
+        return XGBE_MODE_KX_2500;
+}
+
+static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
+{
+        /* If we are in KR switch to KX, and vice-versa */
+        switch (xgbe_phy_cur_mode(pdata)) {
+        case XGBE_MODE_KX_1000:
+                return XGBE_MODE_KR;
+        case XGBE_MODE_KR:
+        default:
+                return XGBE_MODE_KX_1000;
+        }
+}
+
+static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        switch (phy_data->port_mode) {
+        case XGBE_PORT_MODE_BACKPLANE:
+                return xgbe_phy_switch_bp_mode(pdata);
+        case XGBE_PORT_MODE_BACKPLANE_2500:
+                return xgbe_phy_switch_bp_2500_mode(pdata);
+        case XGBE_PORT_MODE_1000BASE_T:
+        case XGBE_PORT_MODE_NBASE_T:
+        case XGBE_PORT_MODE_10GBASE_T:
+                return xgbe_phy_switch_baset_mode(pdata);
+        case XGBE_PORT_MODE_1000BASE_X:
+        case XGBE_PORT_MODE_10GBASE_R:
+        case XGBE_PORT_MODE_SFP:
+                /* No switching, so just return current mode */
+                return xgbe_phy_cur_mode(pdata);
+        default:
+                return XGBE_MODE_UNKNOWN;
+        }
+}
+
+static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
+                                              int speed)
+{
+        switch (speed) {
+        case SPEED_1000:
+                return XGBE_MODE_X;
+        case SPEED_10000:
+                return XGBE_MODE_KR;
+        default:
+                return XGBE_MODE_UNKNOWN;
+        }
+}
+
+static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
+                                              int speed)
+{
+        switch (speed) {
+        case SPEED_100:
+                return XGBE_MODE_SGMII_100;
+        case SPEED_1000:
+                return XGBE_MODE_SGMII_1000;
+        case SPEED_10000:
+                return XGBE_MODE_KR;
+        default:
+                return XGBE_MODE_UNKNOWN;
+        }
+}
+
+static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
+                                            int speed)
+{
+        switch (speed) {
+        case SPEED_100:
+                return XGBE_MODE_SGMII_100;
+        case SPEED_1000:
+                if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
+                        return XGBE_MODE_SGMII_1000;
+                else
+                        return XGBE_MODE_X;
+        case SPEED_10000:
+        case SPEED_UNKNOWN:
+                return XGBE_MODE_SFI;
+        default:
+                return XGBE_MODE_UNKNOWN;
+        }
+}
+
+static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
+{
+        switch (speed) {
+        case SPEED_2500:
+                return XGBE_MODE_KX_2500;
+        default:
+                return XGBE_MODE_UNKNOWN;
+        }
+}
+
+static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
+{
+        switch (speed) {
+        case SPEED_1000:
+                return XGBE_MODE_KX_1000;
+        case SPEED_10000:
+                return XGBE_MODE_KR;
+        default:
+                return XGBE_MODE_UNKNOWN;
+        }
+}
+
+static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
+                                        int speed)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        switch (phy_data->port_mode) {
+        case XGBE_PORT_MODE_BACKPLANE:
+                return xgbe_phy_get_bp_mode(speed);
+        case XGBE_PORT_MODE_BACKPLANE_2500:
+                return xgbe_phy_get_bp_2500_mode(speed);
+        case XGBE_PORT_MODE_1000BASE_T:
+        case XGBE_PORT_MODE_NBASE_T:
+        case XGBE_PORT_MODE_10GBASE_T:
+                return xgbe_phy_get_baset_mode(phy_data, speed);
+        case XGBE_PORT_MODE_1000BASE_X:
+        case XGBE_PORT_MODE_10GBASE_R:
+                return xgbe_phy_get_basex_mode(phy_data, speed);
+        case XGBE_PORT_MODE_SFP:
+                return xgbe_phy_get_sfp_mode(phy_data, speed);
+        default:
+                return XGBE_MODE_UNKNOWN;
+        }
+}
+
+static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
+{
+        switch (mode) {
+        case XGBE_MODE_KX_1000:
+                xgbe_phy_kx_1000_mode(pdata);
+                break;
+        case XGBE_MODE_KX_2500:
+                xgbe_phy_kx_2500_mode(pdata);
+                break;
+        case XGBE_MODE_KR:
+                xgbe_phy_kr_mode(pdata);
+                break;
+        case XGBE_MODE_SGMII_100:
+                xgbe_phy_sgmii_100_mode(pdata);
+                break;
+        case XGBE_MODE_SGMII_1000:
+                xgbe_phy_sgmii_1000_mode(pdata);
+                break;
+        case XGBE_MODE_X:
+                xgbe_phy_x_mode(pdata);
+                break;
+        case XGBE_MODE_SFI:
+                xgbe_phy_sfi_mode(pdata);
+                break;
+        default:
+                break;
+        }
+}
+
+static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
+                                enum xgbe_mode mode, u32 advert)
+{
+        if (pdata->phy.autoneg == AUTONEG_ENABLE) {
+                if (pdata->phy.advertising & advert)
+                        return true;
+        } else {
+                enum xgbe_mode cur_mode;
+
+                cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
+                if (cur_mode == mode)
+                        return true;
+        }
+
+        return false;
+}
+
+static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
+                                    enum xgbe_mode mode)
+{
+        switch (mode) {
+        case XGBE_MODE_X:
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_1000baseT_Full);
+        case XGBE_MODE_KR:
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_10000baseT_Full);
+        default:
+                return false;
+        }
+}
+
+static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
+                                    enum xgbe_mode mode)
+{
+        switch (mode) {
+        case XGBE_MODE_SGMII_100:
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_100baseT_Full);
+        case XGBE_MODE_SGMII_1000:
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_1000baseT_Full);
+        case XGBE_MODE_KR:
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_10000baseT_Full);
+        default:
+                return false;
+        }
+}
+
+static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
+                                  enum xgbe_mode mode)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        switch (mode) {
+        case XGBE_MODE_X:
+                if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
+                        return false;
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_1000baseT_Full);
+        case XGBE_MODE_SGMII_100:
+                if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
+                        return false;
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_100baseT_Full);
+        case XGBE_MODE_SGMII_1000:
+                if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
+                        return false;
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_1000baseT_Full);
+        case XGBE_MODE_SFI:
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_10000baseT_Full);
+        default:
+                return false;
+        }
+}
+
+static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
+                                      enum xgbe_mode mode)
+{
+        switch (mode) {
+        case XGBE_MODE_KX_2500:
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_2500baseX_Full);
+        default:
+                return false;
+        }
+}
+
+static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
+                                 enum xgbe_mode mode)
+{
+        switch (mode) {
+        case XGBE_MODE_KX_1000:
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_1000baseKX_Full);
+        case XGBE_MODE_KR:
+                return xgbe_phy_check_mode(pdata, mode,
+                                           ADVERTISED_10000baseKR_Full);
+        default:
+                return false;
+        }
+}
+
+static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        switch (phy_data->port_mode) {
+        case XGBE_PORT_MODE_BACKPLANE:
+                return xgbe_phy_use_bp_mode(pdata, mode);
+        case XGBE_PORT_MODE_BACKPLANE_2500:
+                return xgbe_phy_use_bp_2500_mode(pdata, mode);
+        case XGBE_PORT_MODE_1000BASE_T:
+        case XGBE_PORT_MODE_NBASE_T:
+        case XGBE_PORT_MODE_10GBASE_T:
+                return xgbe_phy_use_baset_mode(pdata, mode);
+        case XGBE_PORT_MODE_1000BASE_X:
+        case XGBE_PORT_MODE_10GBASE_R:
+                return xgbe_phy_use_basex_mode(pdata, mode);
+        case XGBE_PORT_MODE_SFP:
+                return xgbe_phy_use_sfp_mode(pdata, mode);
+        default:
+                return false;
+        }
+}
+
+static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
+                                            int speed)
+{
+        switch (speed) {
+        case SPEED_1000:
+                return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
+        case SPEED_10000:
+                return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
+        default:
+                return false;
+        }
+}
+
+static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
+                                            int speed)
+{
+        switch (speed) {
+        case SPEED_100:
+        case SPEED_1000:
+                return true;
+        case SPEED_10000:
+                return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
+        default:
+                return false;
+        }
+}
+
+static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
+                                          int speed)
+{
+        switch (speed) {
+        case SPEED_100:
+                return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
+        case SPEED_1000:
+                return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
+                        (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
+        case SPEED_10000:
+                return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
+        default:
+                return false;
+        }
+}
+
+static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
+{
+        switch (speed) {
+        case SPEED_2500:
+                return true;
+        default:
+                return false;
+        }
+}
+
+static bool xgbe_phy_valid_speed_bp_mode(int speed)
+{
+        switch (speed) {
+        case SPEED_1000:
+        case SPEED_10000:
+                return true;
+        default:
+                return false;
+        }
+}
+
+static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        switch (phy_data->port_mode) {
+        case XGBE_PORT_MODE_BACKPLANE:
+                return xgbe_phy_valid_speed_bp_mode(speed);
+        case XGBE_PORT_MODE_BACKPLANE_2500:
+                return xgbe_phy_valid_speed_bp_2500_mode(speed);
+        case XGBE_PORT_MODE_1000BASE_T:
+        case XGBE_PORT_MODE_NBASE_T:
+        case XGBE_PORT_MODE_10GBASE_T:
+                return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
+        case XGBE_PORT_MODE_1000BASE_X:
+        case XGBE_PORT_MODE_10GBASE_R:
+                return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
+        case XGBE_PORT_MODE_SFP:
+                return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
+        default:
+                return false;
+        }
+}
+
+static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int ret, reg;
+
+        *an_restart = 0;
+
+        if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
+                /* Check SFP signals */
+                xgbe_phy_sfp_detect(pdata);
+
+                if (phy_data->sfp_changed) {
+                        *an_restart = 1;
+                        return 0;
+                }
+
+                if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
+                        return 0;
+        }
+
+        if (phy_data->phydev) {
+                /* Check external PHY */
+                ret = phy_read_status(phy_data->phydev);
+                if (ret < 0)
+                        return 0;
+
+                if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
+                    !phy_aneg_done(phy_data->phydev))
+                        return 0;
+
+                if (!phy_data->phydev->link)
+                        return 0;
+        }
+
+        /* Link status is latched low, so read once to clear
+         * and then read again to get current state
+         */
+        reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
+        reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
+        if (reg & MDIO_STAT1_LSTATUS)
+                return 1;
+
+        /* No link, attempt a receiver reset cycle */
+        if (phy_data->rrc_count++) {
+                phy_data->rrc_count = 0;
+                xgbe_phy_rrc(pdata);
+        }
+
+        return 0;
+}
+
+static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int reg;
+
+        reg = XP_IOREAD(pdata, XP_PROP_3);
+
+        phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
+                                     XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
+
+        phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
+
+        phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
+                                                GPIO_RX_LOS);
+        phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
+                                                  GPIO_TX_FAULT);
+        phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
+                                                    GPIO_MOD_ABS);
+        phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
+                                                     GPIO_RATE_SELECT);
+
+        if (netif_msg_probe(pdata)) {
+                dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
+                        phy_data->sfp_gpio_address);
+                dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
+                        phy_data->sfp_gpio_mask);
+                dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
+                        phy_data->sfp_gpio_rx_los);
+                dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
+                        phy_data->sfp_gpio_tx_fault);
+                dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
+                        phy_data->sfp_gpio_mod_absent);
+                dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
+                        phy_data->sfp_gpio_rate_select);
+        }
+}
+
+static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int reg, mux_addr_hi, mux_addr_lo;
+
+        reg = XP_IOREAD(pdata, XP_PROP_4);
+
+        mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
+        mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
+        if (mux_addr_lo == XGBE_SFP_DIRECT)
+                return;
+
+        phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
+        phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
+        phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
+
+        if (netif_msg_probe(pdata)) {
+                dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
+                        phy_data->sfp_mux_address);
+                dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
+                        phy_data->sfp_mux_channel);
+        }
+}
+
+static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
+{
+        xgbe_phy_sfp_comm_setup(pdata);
+        xgbe_phy_sfp_gpio_setup(pdata);
+}
+
+static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int ret;
+
+        ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
+        if (ret)
+                return ret;
+
+        ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
+
+        return ret;
+}
+
+static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        u8 gpio_reg, gpio_ports[2], gpio_data[3];
+        int ret;
+
+        /* Read the output port registers */
+        gpio_reg = 2;
+        ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
+                                &gpio_reg, sizeof(gpio_reg),
+                                gpio_ports, sizeof(gpio_ports));
+        if (ret)
+                return ret;
+
+        /* Prepare to write the GPIO data */
+        gpio_data[0] = 2;
+        gpio_data[1] = gpio_ports[0];
+        gpio_data[2] = gpio_ports[1];
+
+        /* Set the GPIO pin */
+        if (phy_data->mdio_reset_gpio < 8)
+                gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
+        else
+                gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
+
+        /* Write the output port registers */
+        ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
+                                 gpio_data, sizeof(gpio_data));
+        if (ret)
+                return ret;
+
+        /* Clear the GPIO pin */
+        if (phy_data->mdio_reset_gpio < 8)
+                gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
+        else
+                gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
+
+        /* Write the output port registers */
+        ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
+                                 gpio_data, sizeof(gpio_data));
+
+        return ret;
+}
+
+static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        int ret;
+
+        if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
+                return 0;
+
+        ret = xgbe_phy_get_comm_ownership(pdata);
+        if (ret)
+                return ret;
+
+        if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
+                ret = xgbe_phy_i2c_mdio_reset(pdata);
+        else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
+                ret = xgbe_phy_int_mdio_reset(pdata);
+
+        xgbe_phy_put_comm_ownership(pdata);
+
+        return ret;
+}
+
+static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
+{
+        if (!phy_data->redrv)
+                return false;
+
+        if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
+                return true;
+
+        switch (phy_data->redrv_model) {
+        case XGBE_PHY_REDRV_MODEL_4223:
+                if (phy_data->redrv_lane > 3)
+                        return true;
+                break;
+        case XGBE_PHY_REDRV_MODEL_4227:
+                if (phy_data->redrv_lane > 1)
+                        return true;
+                break;
+        default:
+                return true;
+        }
+
+        return false;
+}
+
+static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        unsigned int reg;
+
+        if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
+                return 0;
+
+        reg = XP_IOREAD(pdata, XP_PROP_3);
+        phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
+        switch (phy_data->mdio_reset) {
+        case XGBE_MDIO_RESET_NONE:
+        case XGBE_MDIO_RESET_I2C_GPIO:
+        case XGBE_MDIO_RESET_INT_GPIO:
+                break;
+        default:
+                dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
+                        phy_data->mdio_reset);
+                return -EINVAL;
+        }
+
+        if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
+                phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
+                                            XP_GET_BITS(reg, XP_PROP_3,
+                                                        MDIO_RESET_I2C_ADDR);
+                phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
+                                                        MDIO_RESET_I2C_GPIO);
+        } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
+                phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
+                                                        MDIO_RESET_INT_GPIO);
+        }
+
+        return 0;
+}
+
+static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        switch (phy_data->port_mode) {
+        case XGBE_PORT_MODE_BACKPLANE:
+                if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
+                    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
+                        return false;
+                break;
+        case XGBE_PORT_MODE_BACKPLANE_2500:
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
+                        return false;
+                break;
+        case XGBE_PORT_MODE_1000BASE_T:
+                if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
+                    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
+                        return false;
+                break;
+        case XGBE_PORT_MODE_1000BASE_X:
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
+                        return false;
+                break;
+        case XGBE_PORT_MODE_NBASE_T:
+                if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
+                    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
+                    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
+                        return false;
+                break;
+        case XGBE_PORT_MODE_10GBASE_T:
+                if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
+                    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
+                    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
+                        return false;
+                break;
+        case XGBE_PORT_MODE_10GBASE_R:
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
+                        return false;
+                break;
+        case XGBE_PORT_MODE_SFP:
+                if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
+                    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
+                    (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
+                        return false;
+                break;
+        default:
+                break;
+        }
+
+        return true;
+}
+
+static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        switch (phy_data->port_mode) {
+        case XGBE_PORT_MODE_BACKPLANE:
+        case XGBE_PORT_MODE_BACKPLANE_2500:
+                if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
+                        return false;
+                break;
+        case XGBE_PORT_MODE_1000BASE_T:
+        case XGBE_PORT_MODE_1000BASE_X:
+        case XGBE_PORT_MODE_NBASE_T:
+        case XGBE_PORT_MODE_10GBASE_T:
+        case XGBE_PORT_MODE_10GBASE_R:
+                if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
+                        return false;
+                break;
+        case XGBE_PORT_MODE_SFP:
+                if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
+                        return false;
+                break;
+        default:
+                break;
+        }
+
+        return true;
+}
+
+static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
+{
+        unsigned int reg;
+
+        reg = XP_IOREAD(pdata, XP_PROP_0);
+        if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
+                return false;
+        if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
+                return false;
+
+        return true;
+}
+
+static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        /* If we have an external PHY, free it */
+        xgbe_phy_free_phy_device(pdata);
+
+        /* Reset SFP data */
+        xgbe_phy_sfp_reset(phy_data);
+        xgbe_phy_sfp_mod_absent(pdata);
+
+        /* Power off the PHY */
+        xgbe_phy_power_off(pdata);
+
+        /* Stop the I2C controller */
+        pdata->i2c_if.i2c_stop(pdata);
+}
+
+static int xgbe_phy_start(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        int ret;
+
+        /* Start the I2C controller */
+        ret = pdata->i2c_if.i2c_start(pdata);
+        if (ret)
+                return ret;
+
+        /* Start in highest supported mode */
+        xgbe_phy_set_mode(pdata, phy_data->start_mode);
+
+        /* After starting the I2C controller, we can check for an SFP */
+        switch (phy_data->port_mode) {
+        case XGBE_PORT_MODE_SFP:
+                xgbe_phy_sfp_detect(pdata);
+                break;
+        default:
+                break;
+        }
+
+        /* If we have an external PHY, start it */
+        ret = xgbe_phy_find_phy_device(pdata);
+        if (ret)
+                goto err_i2c;
+
+        return 0;
+
+err_i2c:
+        pdata->i2c_if.i2c_stop(pdata);
+
+        return ret;
+}
+
+static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+        enum xgbe_mode cur_mode;
+        int ret;
+
+        /* Reset by power cycling the PHY */
+        cur_mode = phy_data->cur_mode;
+        xgbe_phy_power_off(pdata);
+        xgbe_phy_set_mode(pdata, cur_mode);
+
+        if (!phy_data->phydev)
+                return 0;
+
+        /* Reset the external PHY */
+        ret = xgbe_phy_mdio_reset(pdata);
+        if (ret)
+                return ret;
+
+        return phy_init_hw(phy_data->phydev);
+}
+
+static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data = pdata->phy_data;
+
+        /* Unregister for driving external PHYs */
+        mdiobus_unregister(phy_data->mii);
+}
+
+static int xgbe_phy_init(struct xgbe_prv_data *pdata)
+{
+        struct xgbe_phy_data *phy_data;
+        struct mii_bus *mii;
+        unsigned int reg;
+        int ret;
+
+        /* Check if enabled */
+        if (!xgbe_phy_port_enabled(pdata)) {
+                dev_info(pdata->dev, "device is not enabled\n");
+                return -ENODEV;
+        }
+
+        /* Initialize the I2C controller */
+        ret = pdata->i2c_if.i2c_init(pdata);
+        if (ret)
+                return ret;
+
+        phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
+        if (!phy_data)
+                return -ENOMEM;
+        pdata->phy_data = phy_data;
+
+        reg = XP_IOREAD(pdata, XP_PROP_0);
+        phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
+        phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
+        phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
+        phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
+        phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
+        if (netif_msg_probe(pdata)) {
+                dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
+                dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
+                dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
+                dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
+                dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
+        }
+
+        reg = XP_IOREAD(pdata, XP_PROP_4);
+        phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);
+        phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);
+        phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);
+        phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);
+        phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);
+        if (phy_data->redrv && netif_msg_probe(pdata)) {
+                dev_dbg(pdata->dev, "redrv present\n");
+                dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
+                dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
+                dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
+                dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
+        }
+
+        /* Validate the connection requested */
+        if (xgbe_phy_conn_type_mismatch(pdata)) {
+                dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
+                        phy_data->port_mode, phy_data->conn_type);
+        }
+
+        /* Validate the mode requested */
+        if (xgbe_phy_port_mode_mismatch(pdata)) {
+                dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
+                        phy_data->port_mode, phy_data->port_speeds);
+                return -EINVAL;
+        }
+
+        /* Check for and validate MDIO reset support */
+        ret = xgbe_phy_mdio_reset_setup(pdata);
+        if (ret)
+                return ret;
+
+        /* Validate the re-driver information */
+        if (xgbe_phy_redrv_error(phy_data)) {
+                dev_err(pdata->dev, "phy re-driver settings error\n");
+                return -EINVAL;
+        }
+        pdata->kr_redrv = phy_data->redrv;
+
+        /* Indicate current mode is unknown */
+        phy_data->cur_mode = XGBE_MODE_UNKNOWN;
+
+        /* Initialize supported features */
+        pdata->phy.supported = 0;
+
+        switch (phy_data->port_mode) {
+        /* Backplane support */
+        case XGBE_PORT_MODE_BACKPLANE:
+                pdata->phy.supported |= SUPPORTED_Autoneg;
+                pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
+                pdata->phy.supported |= SUPPORTED_Backplane;
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
+                        pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
+                        phy_data->start_mode = XGBE_MODE_KX_1000;
+                }
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
+                        pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
+                        if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
+                                pdata->phy.supported |=
+                                        SUPPORTED_10000baseR_FEC;
+                        phy_data->start_mode = XGBE_MODE_KR;
+                }
+
+                phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
+                break;
+        case XGBE_PORT_MODE_BACKPLANE_2500:
+                pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
+                pdata->phy.supported |= SUPPORTED_Backplane;
+                pdata->phy.supported |= SUPPORTED_2500baseX_Full;
+                phy_data->start_mode = XGBE_MODE_KX_2500;
+
+                phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
+                break;
+
+        /* MDIO 1GBase-T support */
+        case XGBE_PORT_MODE_1000BASE_T:
+                pdata->phy.supported |= SUPPORTED_Autoneg;
+                pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
+                pdata->phy.supported |= SUPPORTED_TP;
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
+                        pdata->phy.supported |= SUPPORTED_100baseT_Full;
+                        phy_data->start_mode = XGBE_MODE_SGMII_100;
+                }
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
+                        pdata->phy.supported |= SUPPORTED_1000baseT_Full;
+                        phy_data->start_mode = XGBE_MODE_SGMII_1000;
+                }
+
+                phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
+                break;
+
+        /* MDIO Base-X support */
+        case XGBE_PORT_MODE_1000BASE_X:
+                pdata->phy.supported |= SUPPORTED_Autoneg;
+                pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
+                pdata->phy.supported |= SUPPORTED_FIBRE;
+                pdata->phy.supported |= SUPPORTED_1000baseT_Full;
+                phy_data->start_mode = XGBE_MODE_X;
+
+                phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
+                break;
+
+        /* MDIO NBase-T support */
+        case XGBE_PORT_MODE_NBASE_T:
+                pdata->phy.supported |= SUPPORTED_Autoneg;
+                pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
+                pdata->phy.supported |= SUPPORTED_TP;
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
+                        pdata->phy.supported |= SUPPORTED_100baseT_Full;
+                        phy_data->start_mode = XGBE_MODE_SGMII_100;
+                }
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
+                        pdata->phy.supported |= SUPPORTED_1000baseT_Full;
+                        phy_data->start_mode = XGBE_MODE_SGMII_1000;
+                }
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
+                        pdata->phy.supported |= SUPPORTED_2500baseX_Full;
+                        phy_data->start_mode = XGBE_MODE_KX_2500;
+                }
+
+                phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
+                break;
+
+        /* 10GBase-T support */
+        case XGBE_PORT_MODE_10GBASE_T:
+                pdata->phy.supported |= SUPPORTED_Autoneg;
+                pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
+                pdata->phy.supported |= SUPPORTED_TP;
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
+                        pdata->phy.supported |= SUPPORTED_100baseT_Full;
+                        phy_data->start_mode = XGBE_MODE_SGMII_100;
+                }
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
+                        pdata->phy.supported |= SUPPORTED_1000baseT_Full;
+                        phy_data->start_mode = XGBE_MODE_SGMII_1000;
+                }
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
+                        pdata->phy.supported |= SUPPORTED_10000baseT_Full;
+                        phy_data->start_mode = XGBE_MODE_KR;
+                }
+
+                phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
+                break;
+
+        /* 10GBase-R support */
+        case XGBE_PORT_MODE_10GBASE_R:
+                pdata->phy.supported |= SUPPORTED_Autoneg;
+                pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
+                pdata->phy.supported |= SUPPORTED_TP;
+                pdata->phy.supported |= SUPPORTED_10000baseT_Full;
+                if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
+                        pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
+                phy_data->start_mode = XGBE_MODE_SFI;
+
+                phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
+                break;
+
+        /* SFP support */
+        case XGBE_PORT_MODE_SFP:
+                pdata->phy.supported |= SUPPORTED_Autoneg;
+                pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
+                pdata->phy.supported |= SUPPORTED_TP;
+                pdata->phy.supported |= SUPPORTED_FIBRE;
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
+                        pdata->phy.supported |= SUPPORTED_100baseT_Full;
+                        phy_data->start_mode = XGBE_MODE_SGMII_100;
+                }
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
+                        pdata->phy.supported |= SUPPORTED_1000baseT_Full;
+                        phy_data->start_mode = XGBE_MODE_SGMII_1000;
+                }
+                if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
+                        pdata->phy.supported |= SUPPORTED_10000baseT_Full;
+                        phy_data->start_mode = XGBE_MODE_SFI;
+                        if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
+                                pdata->phy.supported |=
+                                        SUPPORTED_10000baseR_FEC;
+                }
+
+                phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
+
+                xgbe_phy_sfp_setup(pdata);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (netif_msg_probe(pdata))
+                dev_dbg(pdata->dev, "phy supported=%#x\n",
+                        pdata->phy.supported);
+
+        if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
+            (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
+                ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
+                                                    phy_data->phydev_mode);
+                if (ret) {
+                        dev_err(pdata->dev,
+                                "mdio port/clause not compatible (%d/%u)\n",
+                                phy_data->mdio_addr, phy_data->phydev_mode);
+                        return -EINVAL;
+                }
+        }
+
+        if (phy_data->redrv && !phy_data->redrv_if) {
+                ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
+                                                    XGBE_MDIO_MODE_CL22);
+                if (ret) {
+                        dev_err(pdata->dev,
+                                "redriver mdio port not compatible (%u)\n",
+                                phy_data->redrv_addr);
+                        return -EINVAL;
+                }
+        }
+
+        /* Register for driving external PHYs */
+        mii = devm_mdiobus_alloc(pdata->dev);
+        if (!mii) {
+                dev_err(pdata->dev, "mdiobus_alloc failed\n");
+                return -ENOMEM;
+        }
+
+        mii->priv = pdata;
+        mii->name = "amd-xgbe-mii";
+        mii->read = xgbe_phy_mii_read;
+        mii->write = xgbe_phy_mii_write;
+        mii->parent = pdata->dev;
+        mii->phy_mask = ~0;
+        snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
+        ret = mdiobus_register(mii);
+        if (ret) {
+                dev_err(pdata->dev, "mdiobus_register failed\n");
+                return ret;
+        }
+        phy_data->mii = mii;
+
+        return 0;
+}
+
+void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
+{
+        struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
+
+        phy_impl->init                  = xgbe_phy_init;
+        phy_impl->exit                  = xgbe_phy_exit;
+
+        phy_impl->reset                 = xgbe_phy_reset;
+        phy_impl->start                 = xgbe_phy_start;
+        phy_impl->stop                  = xgbe_phy_stop;
+
+        phy_impl->link_status           = xgbe_phy_link_status;
+
+        phy_impl->valid_speed           = xgbe_phy_valid_speed;
+
+        phy_impl->use_mode              = xgbe_phy_use_mode;
+        phy_impl->set_mode              = xgbe_phy_set_mode;
+        phy_impl->get_mode              = xgbe_phy_get_mode;
+        phy_impl->switch_mode           = xgbe_phy_switch_mode;
+        phy_impl->cur_mode              = xgbe_phy_cur_mode;
+
+        phy_impl->an_mode               = xgbe_phy_an_mode;
+
+        phy_impl->an_config             = xgbe_phy_an_config;
+
+        phy_impl->an_advertising        = xgbe_phy_an_advertising;
+
+        phy_impl->an_outcome            = xgbe_phy_an_outcome;
+}
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-platform.c b/drivers/net/ethernet/amd/xgbe/xgbe-platform.c
index 0edbcd523f8f..8c530dccb447 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-platform.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-platform.c
@@ -426,8 +426,10 @@ static int xgbe_platform_probe(struct platform_device *pdev)
         pdata->phy_mode = PHY_INTERFACE_MODE_XGMII;
 
         /* Check for per channel interrupt support */
-        if (device_property_present(dev, XGBE_DMA_IRQS_PROPERTY))
+        if (device_property_present(dev, XGBE_DMA_IRQS_PROPERTY)) {
                 pdata->per_channel_irq = 1;
+                pdata->channel_irq_mode = XGBE_IRQ_MODE_EDGE;
+        }
 
         /* Obtain device settings unique to ACPI/OF */
         if (pdata->use_acpi)
@@ -462,6 +464,9 @@ static int xgbe_platform_probe(struct platform_device *pdev)
         /* Set the hardware channel and queue counts */
         xgbe_set_counts(pdata);
 
+        /* Always have XGMAC and XPCS (auto-negotiation) interrupts */
+        pdata->irq_count = 2;
+
         /* Get the device interrupt */
         ret = platform_get_irq(pdev, 0);
         if (ret < 0) {
@@ -485,6 +490,10 @@ static int xgbe_platform_probe(struct platform_device *pdev)
 
                         pdata->channel_irq[i] = ret;
                 }
+
+                pdata->channel_irq_count = max;
+
+                pdata->irq_count += max;
         }
 
         /* Get the auto-negotiation interrupt */
@@ -581,6 +590,7 @@ static const struct xgbe_version_data xgbe_v1 = {
         .xpcs_access                    = XGBE_XPCS_ACCESS_V1,
         .tx_max_fifo_size               = 81920,
         .rx_max_fifo_size               = 81920,
+        .tx_tstamp_workaround           = 1,
 };
 
 #ifdef CONFIG_ACPI
@@ -608,7 +618,7 @@ static SIMPLE_DEV_PM_OPS(xgbe_platform_pm_ops,
 
 static struct platform_driver xgbe_driver = {
         .driver = {
-                .name = "amd-xgbe",
+                .name = XGBE_DRV_NAME,
 #ifdef CONFIG_ACPI
                 .acpi_match_table = xgbe_acpi_match,
 #endif
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index 0779247057fb..f52a9bd05bac 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -127,6 +127,7 @@
 #include <linux/timecounter.h>
 #include <linux/net_tstamp.h>
 #include <net/dcbnl.h>
+#include <linux/completion.h>
 
 #define XGBE_DRV_NAME           "amd-xgbe"
 #define XGBE_DRV_VERSION        "1.0.3"
@@ -171,6 +172,10 @@
 #define XGBE_DMA_SYS_ARCACHE    0x0
 #define XGBE_DMA_SYS_AWCACHE    0x0
 
+/* DMA channel interrupt modes */
+#define XGBE_IRQ_MODE_EDGE      0
+#define XGBE_IRQ_MODE_LEVEL     1
+
 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
 
 #define XGMAC_MIN_PACKET        60
@@ -200,6 +205,20 @@
 #define XGBE_ACPI_DMA_FREQ      "amd,dma-freq"
 #define XGBE_ACPI_PTP_FREQ      "amd,ptp-freq"
 
+/* PCI BAR mapping */
+#define XGBE_XGMAC_BAR          0
+#define XGBE_XPCS_BAR           1
+#define XGBE_MAC_PROP_OFFSET    0x1d000
+#define XGBE_I2C_CTRL_OFFSET    0x1e000
+
+/* PCI MSIx support */
+#define XGBE_MSIX_BASE_COUNT    4
+#define XGBE_MSIX_MIN_COUNT     (XGBE_MSIX_BASE_COUNT + 1)
+
+/* PCI clock frequencies */
+#define XGBE_V2_DMA_CLOCK_FREQ  500000000       /* 500 MHz */
+#define XGBE_V2_PTP_CLOCK_FREQ  125000000       /* 125 MHz */
+
 /* Timestamp support - values based on 50MHz PTP clock
  *   50MHz => 20 nsec
  */
@@ -267,6 +286,12 @@
 #define XGBE_SGMII_AN_LINK_SPEED_1000   0x08
 #define XGBE_SGMII_AN_LINK_DUPLEX       BIT(4)
 
+/* ECC correctable error notification window (seconds) */
+#define XGBE_ECC_LIMIT                  60
+
+/* MDIO port types */
+#define XGMAC_MAX_C22_PORT              3
+
 struct xgbe_prv_data;
 
 struct xgbe_packet_data {
@@ -443,6 +468,7 @@ enum xgbe_state {
         XGBE_DOWN,
         XGBE_LINK_INIT,
         XGBE_LINK_ERR,
+        XGBE_STOPPED,
 };
 
 enum xgbe_int {
@@ -462,6 +488,12 @@ enum xgbe_int_state {
         XGMAC_INT_STATE_RESTORE,
 };
 
+enum xgbe_ecc_sec {
+        XGBE_ECC_SEC_TX,
+        XGBE_ECC_SEC_RX,
+        XGBE_ECC_SEC_DESC,
+};
+
 enum xgbe_speed {
         XGBE_SPEED_1000 = 0,
         XGBE_SPEED_2500,
@@ -476,6 +508,7 @@ enum xgbe_xpcs_access {
 
 enum xgbe_an_mode {
         XGBE_AN_MODE_CL73 = 0,
+        XGBE_AN_MODE_CL73_REDRV,
         XGBE_AN_MODE_CL37,
         XGBE_AN_MODE_CL37_SGMII,
         XGBE_AN_MODE_NONE,
@@ -501,6 +534,10 @@ enum xgbe_mode {
         XGBE_MODE_KX_1000 = 0,
         XGBE_MODE_KX_2500,
         XGBE_MODE_KR,
+        XGBE_MODE_X,
+        XGBE_MODE_SGMII_100,
+        XGBE_MODE_SGMII_1000,
+        XGBE_MODE_SFI,
         XGBE_MODE_UNKNOWN,
 };
 
@@ -509,6 +546,12 @@ enum xgbe_speedset {
         XGBE_SPEEDSET_2500_10000,
 };
 
+enum xgbe_mdio_mode {
+        XGBE_MDIO_MODE_NONE = 0,
+        XGBE_MDIO_MODE_CL22,
+        XGBE_MDIO_MODE_CL45,
+};
+
 struct xgbe_phy {
         u32 supported;
         u32 advertising;
@@ -527,6 +570,43 @@ struct xgbe_phy {
         int rx_pause;
 };
 
+enum xgbe_i2c_cmd {
+        XGBE_I2C_CMD_READ = 0,
+        XGBE_I2C_CMD_WRITE,
+};
+
+struct xgbe_i2c_op {
+        enum xgbe_i2c_cmd cmd;
+
+        unsigned int target;
+
+        void *buf;
+        unsigned int len;
+};
+
+struct xgbe_i2c_op_state {
+        struct xgbe_i2c_op *op;
+
+        unsigned int tx_len;
+        unsigned char *tx_buf;
+
+        unsigned int rx_len;
+        unsigned char *rx_buf;
+
+        unsigned int tx_abort_source;
+
+        int ret;
+};
+
+struct xgbe_i2c {
+        unsigned int started;
+        unsigned int max_speed_mode;
+        unsigned int rx_fifo_size;
+        unsigned int tx_fifo_size;
+
+        struct xgbe_i2c_op_state op_state;
+};
+
 struct xgbe_mmc_stats {
         /* Tx Stats */
         u64 txoctetcount_gb;
@@ -599,6 +679,14 @@ struct xgbe_hw_if {
         void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
         int (*set_speed)(struct xgbe_prv_data *, int);
 
+        int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int,
+                                enum xgbe_mdio_mode);
+        int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int);
+        int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, u16);
+
+        int (*set_gpio)(struct xgbe_prv_data *, unsigned int);
+        int (*clr_gpio)(struct xgbe_prv_data *, unsigned int);
+
         void (*enable_tx)(struct xgbe_prv_data *);
         void (*disable_tx)(struct xgbe_prv_data *);
         void (*enable_rx)(struct xgbe_prv_data *);
@@ -676,6 +764,10 @@ struct xgbe_hw_if {
         int (*disable_rss)(struct xgbe_prv_data *);
         int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
         int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
+
+        /* For ECC */
+        void (*disable_ecc_ded)(struct xgbe_prv_data *);
+        void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec);
 };
 
 /* This structure represents implementation specific routines for an
@@ -694,7 +786,7 @@ struct xgbe_phy_impl_if {
         void (*stop)(struct xgbe_prv_data *);
 
         /* Return the link status */
-        int (*link_status)(struct xgbe_prv_data *);
+        int (*link_status)(struct xgbe_prv_data *, int *);
 
         /* Indicate if a particular speed is valid */
         bool (*valid_speed)(struct xgbe_prv_data *, int);
@@ -713,6 +805,12 @@ struct xgbe_phy_impl_if {
         /* Retrieve current auto-negotiation mode */
         enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);
 
+        /* Configure auto-negotiation settings */
+        int (*an_config)(struct xgbe_prv_data *);
+
+        /* Set/override auto-negotiation advertisement settings */
+        unsigned int (*an_advertising)(struct xgbe_prv_data *);
+
         /* Process results of auto-negotiation */
         enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);
 
@@ -738,10 +836,28 @@ struct xgbe_phy_if {
         /* For PHY settings validation */
         bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
 
+        /* For single interrupt support */
+        irqreturn_t (*an_isr)(int, struct xgbe_prv_data *);
+
         /* PHY implementation specific services */
         struct xgbe_phy_impl_if phy_impl;
 };
 
+struct xgbe_i2c_if {
+        /* For initial I2C setup */
+        int (*i2c_init)(struct xgbe_prv_data *);
+
+        /* For I2C support when setting device up/down */
+        int (*i2c_start)(struct xgbe_prv_data *);
+        void (*i2c_stop)(struct xgbe_prv_data *);
+
+        /* For performing I2C operations */
+        int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *);
+
+        /* For single interrupt support */
+        irqreturn_t (*i2c_isr)(int, struct xgbe_prv_data *);
+};
+
 struct xgbe_desc_if {
         int (*alloc_ring_resources)(struct xgbe_prv_data *);
         void (*free_ring_resources)(struct xgbe_prv_data *);
@@ -805,10 +921,14 @@ struct xgbe_version_data {
         unsigned int mmc_64bit;
         unsigned int tx_max_fifo_size;
         unsigned int rx_max_fifo_size;
+        unsigned int tx_tstamp_workaround;
+        unsigned int ecc_support;
+        unsigned int i2c_support;
 };
 
 struct xgbe_prv_data {
         struct net_device *netdev;
+        struct pci_dev *pcidev;
         struct platform_device *platdev;
         struct acpi_device *adev;
         struct device *dev;
@@ -827,6 +947,8 @@ struct xgbe_prv_data {
         void __iomem *rxtx_regs;        /* SerDes Rx/Tx CSRs */
         void __iomem *sir0_regs;        /* SerDes integration registers (1/2) */
         void __iomem *sir1_regs;        /* SerDes integration registers (2/2) */
+        void __iomem *xprop_regs;       /* XGBE property registers */
+        void __iomem *xi2c_regs;        /* XGBE I2C CSRs */
 
         /* Overall device lock */
         spinlock_t lock;
@@ -843,13 +965,39 @@ struct xgbe_prv_data {
         /* Flags representing xgbe_state */
         unsigned long dev_state;
 
+        /* ECC support */
+        unsigned long tx_sec_period;
+        unsigned long tx_ded_period;
+        unsigned long rx_sec_period;
+        unsigned long rx_ded_period;
+        unsigned long desc_sec_period;
+        unsigned long desc_ded_period;
+
+        unsigned int tx_sec_count;
+        unsigned int tx_ded_count;
+        unsigned int rx_sec_count;
+        unsigned int rx_ded_count;
+        unsigned int desc_ded_count;
+        unsigned int desc_sec_count;
+
+        struct msix_entry *msix_entries;
         int dev_irq;
-        unsigned int per_channel_irq;
+        int ecc_irq;
+        int i2c_irq;
         int channel_irq[XGBE_MAX_DMA_CHANNELS];
 
+        unsigned int per_channel_irq;
+        unsigned int irq_shared;
+        unsigned int irq_count;
+        unsigned int channel_irq_count;
+        unsigned int channel_irq_mode;
+
+        char ecc_name[IFNAMSIZ + 32];
+
         struct xgbe_hw_if hw_if;
         struct xgbe_phy_if phy_if;
         struct xgbe_desc_if desc_if;
+        struct xgbe_i2c_if i2c_if;
 
         /* AXI DMA settings */
         unsigned int coherent;
@@ -957,8 +1105,9 @@ struct xgbe_prv_data {
         /* Hardware features of the device */
         struct xgbe_hw_features hw_feat;
 
-        /* Device restart work structure */
+        /* Device work structures */
         struct work_struct restart_work;
+        struct work_struct stopdev_work;
 
         /* Keeps track of power mode */
         unsigned int power_down;
@@ -977,6 +1126,9 @@ struct xgbe_prv_data {
         struct xgbe_phy phy;
         int mdio_mmd;
         unsigned long link_check;
+        struct completion mdio_complete;
+
+        unsigned int kr_redrv;
 
         char an_name[IFNAMSIZ + 32];
         struct workqueue_struct *an_workqueue;
@@ -999,6 +1151,12 @@ struct xgbe_prv_data {
         unsigned long an_start;
         enum xgbe_an_mode an_mode;
 
+        /* I2C support */
+        struct xgbe_i2c i2c;
+        struct mutex i2c_mutex;
+        struct completion i2c_complete;
+        char i2c_name[IFNAMSIZ + 32];
+
         unsigned int lpm_ctrl;          /* CTRL1 for resume */
 
 #ifdef CONFIG_DEBUG_FS
@@ -1008,6 +1166,10 @@ struct xgbe_prv_data {
 
         unsigned int debugfs_xpcs_mmd;
         unsigned int debugfs_xpcs_reg;
+
+        unsigned int debugfs_xprop_reg;
+
+        unsigned int debugfs_xi2c_reg;
 #endif
 };
 
@@ -1020,11 +1182,20 @@ void xgbe_deconfig_netdev(struct xgbe_prv_data *);
 
 int xgbe_platform_init(void);
 void xgbe_platform_exit(void);
+#ifdef CONFIG_PCI
+int xgbe_pci_init(void);
+void xgbe_pci_exit(void);
+#else
+static inline int xgbe_pci_init(void) { return 0; }
+static inline void xgbe_pci_exit(void) { }
+#endif
 
 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
+void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *);
 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
+void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *);
 const struct net_device_ops *xgbe_get_netdev_ops(void);
 const struct ethtool_ops *xgbe_get_ethtool_ops(void);
 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 2f94c60d4939..e6dd222fddb1 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -143,13 +143,14 @@ static int phy_config_interrupt(struct phy_device *phydev, u32 interrupts)
  * Returns > 0 on success or < 0 on error. 0 means that auto-negotiation
  * is still pending.
  */
-static inline int phy_aneg_done(struct phy_device *phydev)
+int phy_aneg_done(struct phy_device *phydev)
 {
         if (phydev->drv->aneg_done)
                 return phydev->drv->aneg_done(phydev);
 
         return genphy_aneg_done(phydev);
 }
+EXPORT_SYMBOL(phy_aneg_done);
 
 /* A structure for mapping a particular speed and duplex
  * combination to a particular SUPPORTED and ADVERTISED value
diff --git a/include/linux/phy.h b/include/linux/phy.h
index e7e1fd382564..9880d73a2c3d 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -786,6 +786,7 @@ void phy_detach(struct phy_device *phydev);
 void phy_start(struct phy_device *phydev);
 void phy_stop(struct phy_device *phydev);
 int phy_start_aneg(struct phy_device *phydev);
+int phy_aneg_done(struct phy_device *phydev);
 
 int phy_stop_interrupts(struct phy_device *phydev);