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authorTsahee Zidenberg <tsahee@annapurnalabs.com>2015-03-12 07:53:12 -0400
committerArnd Bergmann <arnd@arndb.de>2015-03-16 10:34:53 -0400
commit841990b6b3e2cfc0b51a5efb4c2fed6693cfafee (patch)
treeee2d7369df13b623e2a8bf62cc15dc791e8e9d8a
parent05e6d23296ee46f4d25e9eec78141d45f2703410 (diff)
ARM: dts: Alpine platform devicetree
This patch introduces devicetree for the Alpine platform, and for a development board based on the same platform. Signed-off-by: Barak Wasserstrom <barak@annapurnalabs.com> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/alpine-db.dts35
-rw-r--r--arch/arm/boot/dts/alpine.dtsi141
3 files changed, 178 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 491a3c1d4875..4e1b3873d809 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,5 +1,7 @@
1ifeq ($(CONFIG_OF),y) 1ifeq ($(CONFIG_OF),y)
2 2
3dtb-$(CONFIG_ARCH_ALPINE) += \
4 alpine_db.dtb
3dtb-$(CONFIG_MACH_ASM9260) += \ 5dtb-$(CONFIG_MACH_ASM9260) += \
4 alphascale-asm9260-devkit.dtb 6 alphascale-asm9260-devkit.dtb
5# Keep at91 dtb files sorted alphabetically for each SoC 7# Keep at91 dtb files sorted alphabetically for each SoC
diff --git a/arch/arm/boot/dts/alpine-db.dts b/arch/arm/boot/dts/alpine-db.dts
new file mode 100644
index 000000000000..dfb5a0802273
--- /dev/null
+++ b/arch/arm/boot/dts/alpine-db.dts
@@ -0,0 +1,35 @@
1/*
2 * Copyright 2015 Annapurna Labs Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * Alternatively, redistribution and use in source and binary forms, with or
9 * without modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * * Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in
17 * the documentation and/or other materials provided with the
18 * distribution.
19 *
20 * This program is distributed in the hope it will be useful, but WITHOUT
21 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
23 * more details.
24 *
25 */
26
27/dts-v1/;
28
29#include "alpine.dtsi"
30
31/ {
32 model = "Annapurna Labs Alpine Dev Board";
33 /* no need for anything outside SOC */
34};
35
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
new file mode 100644
index 000000000000..519f58cc9761
--- /dev/null
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -0,0 +1,141 @@
1/*
2 * Copyright 2015 Annapurna Labs Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * Alternatively, redistribution and use in source and binary forms, with or
9 * without modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * * Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in
17 * the documentation and/or other materials provided with the
18 * distribution.
19 *
20 * This program is distributed in the hope it will be useful, but WITHOUT
21 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
23 * more details.
24 *
25 */
26
27#include <dt-bindings/interrupt-controller/arm-gic.h>
28#include "skeleton64.dtsi"
29
30/ {
31 /* SOC compatibility */
32 compatible = "al,alpine";
33
34 /* CPU Configuration */
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 enable-method = "al,alpine-smp";
39
40 cpu@0 {
41 compatible = "arm,cortex-a15";
42 device_type = "cpu";
43 reg = <0>;
44 clock-frequency = <0>; /* Filled by loader */
45 };
46
47 cpu@1 {
48 compatible = "arm,cortex-a15";
49 device_type = "cpu";
50 reg = <1>;
51 clock-frequency = <0>; /* Filled by loader */
52 };
53
54 cpu@2 {
55 compatible = "arm,cortex-a15";
56 device_type = "cpu";
57 reg = <2>;
58 clock-frequency = <0>; /* Filled by loader */
59 };
60
61 cpu@3 {
62 compatible = "arm,cortex-a15";
63 device_type = "cpu";
64 reg = <3>;
65 clock-frequency = <0>; /* Filled by loader */
66 };
67 };
68
69 soc {
70 #address-cells = <2>;
71 #size-cells = <2>;
72 compatible = "simple-bus";
73 interrupt-parent = <&gic>;
74 ranges;
75
76 arch-timer {
77 compatible = "arm,cortex-a15-timer",
78 "arm,armv7-timer";
79 interrupts =
80 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
84 clock-frequency = <0>; /* Filled by loader */
85 };
86
87 /* Interrupt Controller */
88 gic: gic@fb001000 {
89 compatible = "arm,cortex-a15-gic";
90 #interrupt-cells = <3>;
91 #size-cells = <0>;
92 #address-cells = <0>;
93 interrupt-controller;
94 reg = <0x0 0xfb001000 0x0 0x1000>,
95 <0x0 0xfb002000 0x0 0x2000>,
96 <0x0 0xfb004000 0x0 0x1000>,
97 <0x0 0xfb006000 0x0 0x2000>;
98 interrupts =
99 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
100 };
101
102 /* CPU Resume registers */
103 cpu-resume@fbff5ec0 {
104 compatible = "al,alpine-cpu-resume";
105 reg = <0x0 0xfbff5ec0 0x0 0x30>;
106 };
107
108 /* North Bridge Service Registers */
109 sysfabric-service@fb070000 {
110 compatible = "al,alpine-sysfabric-service", "syscon";
111 reg = <0x0 0xfb070000 0x0 0x10000>;
112 };
113
114 /* Performance Monitor Unit */
115 pmu {
116 compatible = "arm,cortex-a15-pmu";
117 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
121 };
122
123 uart0:uart@fd883000 {
124 compatible = "ns16550a";
125 reg = <0x0 0xfd883000 0x0 0x1000>;
126 clock-frequency = <0>; /* Filled by loader */
127 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
128 reg-shift = <2>;
129 reg-io-width = <4>;
130 };
131
132 uart1:uart@0xfd884000 {
133 compatible = "ns16550a";
134 reg = <0x0 0xfd884000 0x0 0x1000>;
135 clock-frequency = <0>; /* Filled by loader */
136 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
137 reg-shift = <2>;
138 reg-io-width = <4>;
139 };
140 };
141};
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