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authorBen Hutchings <ben.hutchings@codethink.co.uk>2017-05-09 13:00:43 -0400
committerDan Williams <dan.j.williams@intel.com>2017-05-09 13:09:26 -0400
commit8376efd31d3d7c44bd05be337adde023cc531fa1 (patch)
treea058fa06362f801e82408c20f5d681b7dfcc8a54
parentcf1e22891bee39f50e058bee0827086fd75a8717 (diff)
x86, pmem: Fix cache flushing for iovec write < 8 bytes
Commit 11e63f6d920d added cache flushing for unaligned writes from an iovec, covering the first and last cache line of a >= 8 byte write and the first cache line of a < 8 byte write. But an unaligned write of 2-7 bytes can still cover two cache lines, so make sure we flush both in that case. Cc: <stable@vger.kernel.org> Fixes: 11e63f6d920d ("x86, pmem: fix broken __copy_user_nocache ...") Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
-rw-r--r--arch/x86/include/asm/pmem.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/asm/pmem.h b/arch/x86/include/asm/pmem.h
index d5a22bac9988..0ff8fe71b255 100644
--- a/arch/x86/include/asm/pmem.h
+++ b/arch/x86/include/asm/pmem.h
@@ -98,7 +98,7 @@ static inline size_t arch_copy_from_iter_pmem(void *addr, size_t bytes,
98 98
99 if (bytes < 8) { 99 if (bytes < 8) {
100 if (!IS_ALIGNED(dest, 4) || (bytes != 4)) 100 if (!IS_ALIGNED(dest, 4) || (bytes != 4))
101 arch_wb_cache_pmem(addr, 1); 101 arch_wb_cache_pmem(addr, bytes);
102 } else { 102 } else {
103 if (!IS_ALIGNED(dest, 8)) { 103 if (!IS_ALIGNED(dest, 8)) {
104 dest = ALIGN(dest, boot_cpu_data.x86_clflush_size); 104 dest = ALIGN(dest, boot_cpu_data.x86_clflush_size);