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authorLudovic Barre <ludovic.barre@st.com>2019-03-27 05:05:31 -0400
committerUlf Hansson <ulf.hansson@linaro.org>2019-04-15 05:55:54 -0400
commit8372f9d0ef0b9276439f4ff35dc4263bcddf1408 (patch)
treed0dc6de3460cc9071211771a5630dbda14bd9d3a
parent5db1e1fc7cab400e991eed32131cecd03a5e03db (diff)
mmc: mmci: stm32: define get_dctrl_cfg
This patch defines get_dctrl_cfg callback for sdmmc variant. sdmmc variant has specific stm32 transfer modes. sdmmc data transfer mode selection could be: -Block data transfer ending on block count. -SDIO multibyte data transfer. -MMC Stream data transfer (not used). -Block data transfer ending with STOP_TRANSMISSION command. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-rw-r--r--drivers/mmc/host/mmci.h5
-rw-r--r--drivers/mmc/host/mmci_stm32_sdmmc.c18
2 files changed, 23 insertions, 0 deletions
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 35c91d0059b9..82e9f94e3a16 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -131,6 +131,11 @@
131/* Control register extensions in the Qualcomm versions */ 131/* Control register extensions in the Qualcomm versions */
132#define MCI_DPSM_QCOM_DATA_PEND BIT(17) 132#define MCI_DPSM_QCOM_DATA_PEND BIT(17)
133#define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20) 133#define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
134/* Control register extensions in STM32 versions */
135#define MCI_DPSM_STM32_MODE_BLOCK (0 << 2)
136#define MCI_DPSM_STM32_MODE_SDIO (1 << 2)
137#define MCI_DPSM_STM32_MODE_STREAM (2 << 2)
138#define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2)
134 139
135#define MMCIDATACNT 0x030 140#define MMCIDATACNT 0x030
136#define MMCISTATUS 0x034 141#define MMCISTATUS 0x034
diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c
index cfbfc6f1048f..8e83ae6920ae 100644
--- a/drivers/mmc/host/mmci_stm32_sdmmc.c
+++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
@@ -265,10 +265,28 @@ static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
265 } 265 }
266} 266}
267 267
268static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
269{
270 u32 datactrl;
271
272 datactrl = mmci_dctrl_blksz(host);
273
274 if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
275 host->data->blocks == 1)
276 datactrl |= MCI_DPSM_STM32_MODE_SDIO;
277 else if (host->data->stop && !host->mrq->sbc)
278 datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP;
279 else
280 datactrl |= MCI_DPSM_STM32_MODE_BLOCK;
281
282 return datactrl;
283}
284
268static struct mmci_host_ops sdmmc_variant_ops = { 285static struct mmci_host_ops sdmmc_variant_ops = {
269 .validate_data = sdmmc_idma_validate_data, 286 .validate_data = sdmmc_idma_validate_data,
270 .prep_data = sdmmc_idma_prep_data, 287 .prep_data = sdmmc_idma_prep_data,
271 .unprep_data = sdmmc_idma_unprep_data, 288 .unprep_data = sdmmc_idma_unprep_data,
289 .get_datactrl_cfg = sdmmc_get_dctrl_cfg,
272 .dma_setup = sdmmc_idma_setup, 290 .dma_setup = sdmmc_idma_setup,
273 .dma_start = sdmmc_idma_start, 291 .dma_start = sdmmc_idma_start,
274 .dma_finalize = sdmmc_idma_finalize, 292 .dma_finalize = sdmmc_idma_finalize,